An ldmos device and a method of manufacturing the same
By setting a composite structure of metal field plate and oxide passivation layer in LDMOS device, the problem of poor stability in high temperature reverse bias test is solved, and the device achieves high stability and applicability to large-scale production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGZHOU ZENGXIN TECH CO LTD
- Filing Date
- 2026-03-11
- Publication Date
- 2026-06-12
AI Technical Summary
In high-temperature reverse bias tests, LDMOS devices suffer from poor stability due to the inability of the passivation layer to shield surface ionic charges.
A composite structure of a metal field plate and an oxide passivation layer is formed on the surface of the dielectric layer. The metal field plate is unoxidized aluminum, and the oxide passivation layer is aluminum oxide. The layer thickness is controlled by ion implantation process to form an equipotential shielding surface charge distribution and provide protection.
It improves the stability of LDMOS devices in high-temperature reverse bias testing, reduces environmental contamination, enhances interface passivation, and is suitable for mass production.
Smart Images
Figure CN122205901A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to an LDMOS device and its fabrication method. Background Technology
[0002] High-voltage power devices are widely used in products such as power management, switching conversion, and LED drivers. LDMOS is widely used as a high-voltage power device because its drift region design can withstand high voltages (such as 700V). To ensure proper chip operation, LDMOS must be evaluated through a High Temperature Reverse Bias (HTRB) test before integration. However, under the high temperature and high pressure stress of the HTRB test, the device passivation layer cannot shield the surface ionic charge, resulting in a lower breakdown voltage and poor stability of the device during the HTRB test. Summary of the Invention
[0003] The technical problem solved by this invention is to provide an LDMOS device and its fabrication method, which improves the stability of the device in HTRB testing by setting a metal field plate and an oxide passivation layer.
[0004] To solve the above-mentioned technical problems, the present invention provides a method for fabricating an LDMOS device, comprising: providing a substrate, wherein an LDMOS device structure is provided within and on the substrate, and a dielectric layer and a conductive layer are provided on the surface of the substrate and the surface of the LDMOS device structure, wherein the conductive layer is located within the dielectric layer and connected to the LDMOS device structure; forming a metal layer on the surface of the dielectric layer; and oxidizing the metal layer to form a metal field plate located on the surface of the dielectric layer and an oxide passivation layer located on the surface of the metal field plate, wherein the thickness of the oxide passivation layer is less than or equal to the thickness of the metal field plate.
[0005] Optionally, the thickness of the oxide passivation layer is 30% to 50% of the total thickness of the metal field plate and the oxide passivation layer.
[0006] Optionally, the total thickness of the metal field plate and the oxide passivation layer is 1 μm to 3 μm.
[0007] Optionally, the material of the metal field plate includes aluminum.
[0008] Optionally, the oxidation treatment process includes an ion implantation process, wherein the implanted ions in the ion implantation process are oxygen ions, and the implantation dose in the ion implantation process is 1e14cm. -2 ~5e14cm -2 .
[0009] Optionally, the LDMOS device structure includes: a first well region located within the substrate; a field oxide structure located within and on the surface of the first well region; a second well region located within the first well region; a drain region located within the first well region, with the second well region and the drain region respectively located on opposite sides of the field oxide structure; a source region located within the second well region; a gate structure located on the surface of the first well region and the surface of the second well region between the source region and the field oxide structure, and extending to a portion of the surface of the field oxide structure; and a body region located within the second well region, with the body region and the gate structure respectively located on opposite sides of the source region, and the body region contacting the source region.
[0010] Optionally, it may also include etching the metal field plate, the oxide passivation layer, and the dielectric layer to form an opening that exposes the conductive layer.
[0011] Accordingly, the present invention also provides an LDMOS device, comprising: a substrate having an LDMOS device structure within and on the substrate, the substrate surface and the LDMOS device structure surface having a dielectric layer and a conductive layer, the conductive layer being located within the dielectric layer and connected to the LDMOS device structure; a metal field plate located on the surface of the dielectric layer; and an oxide passivation layer located on the surface of the metal field plate, the thickness of the oxide passivation layer being less than or equal to the thickness of the metal field plate.
[0012] Optionally, the total thickness of the metal field plate and the oxide passivation layer is 1 μm to 3 μm, the thickness of the oxide passivation layer is 30% to 50% of the total thickness of the metal field plate and the oxide passivation layer, and the material of the metal field plate includes aluminum.
[0013] Optionally, the LDMOS device structure includes: a first well region located within the substrate; a field oxide structure located within and on the surface of the first well region; a second well region located within the first well region; a drain region located within the first well region, with the second well region and the drain region respectively located on opposite sides of the field oxide structure; a source region located within the second well region; a gate structure located on the surface of the first well region and the surface of the second well region between the source region and the field oxide structure, and extending to a portion of the surface of the field oxide structure; and a body region located within the second well region, with the body region and the gate structure respectively located on opposite sides of the source region, and the body region contacting the source region.
[0014] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The present invention provides a method for fabricating an LDMOS device, comprising a substrate having an LDMOS device structure within and on the substrate to define the main structure of the device. Since the substrate surface and the LDMOS device structure surface have a dielectric layer and a conductive layer, with the conductive layer located within the dielectric layer and connected to the LDMOS device structure, the dielectric layer provides electrical isolation between the device and the external environment. A metal layer is formed on the surface of the dielectric layer, and the metal layer is oxidized to form a metal field plate on the surface of the dielectric layer and an oxide passivation layer on the surface of the metal field plate. Therefore, a composite structure consisting of an unoxidized metal field plate and an oxidized oxide passivation layer is formed on the surface of the dielectric layer. In the composite structure, the unoxidized metal field plate has an equipotential form, effectively shielding the PN structure from surface charge redistribution caused by the application of reverse bias during HTRB testing, thus improving the stability of the LDMOS during HTRB testing. Simultaneously, the oxidized oxide passivation layer acts as a passivation layer to protect the device from external environmental factors such as moisture, ion contamination, and mechanical stress. Since the thickness of the oxide passivation layer is less than or equal to the thickness of the metal field plate, the passivation layer can be thick enough to withstand external environmental factors while the metal field plate is formed at an equipotential state. Simultaneously, by oxidizing the metal layer, a composite structure consisting of an unoxidized metal field plate and an oxidized oxide passivation layer is simultaneously formed. This preparation method is simple, efficient, and suitable for large-scale production.
[0015] Furthermore, since the material of the metal field plate includes aluminum, the unoxidized metal field plate in the composite structure is aluminum, and the oxidized oxide passivation layer is aluminum oxide. Because aluminum oxide has a high dielectric constant (ε... r (≈9.3) Excellent impurity resistance reduces environmental contamination of the interface and lowers the interface state density. Furthermore, due to the unique negative fixed charge characteristics of aluminum oxide, the oxide passivation layer provides excellent surface passivation. Under the protection of the oxide passivation layer, the unoxidized aluminum metal acts as a metal field plate, shielding the influence of surface ionic charges on the device's electric field distribution, further improving the device's stability during HTRB testing.
[0016] The LDMOS device provided by the technical solution of the present invention is prepared by the above-mentioned LDMOS device preparation method, and therefore also has the technical effects of the above-mentioned LDMOS device preparation method, which will not be repeated here. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the structure of an LDMOS device; Figures 2 to 6 This is a schematic diagram of the structure of each step in the fabrication method of the LDMOS device according to an embodiment of the present invention.
[0018] Explanation of reference numerals in the attached figures: 10. Passivation layer; 100. Substrate; 210, First well region; 220, Field oxygen structure; 230, Second well region; 240, Drain region; 250, Source region; 260, Gate structure; 270, Body region; 300, dielectric layer; 400, conductive layer; 410, opening; 500, metal layer; 510, metal field plate; 520, oxide passivation layer. Detailed Implementation
[0019] As described in the background section, improving the stability of LDMOS in HTRB testing is a technical problem that needs to be solved, which will be explained in detail below.
[0020] Figure 1 This is a schematic diagram of an LDMOS device. It should be noted that... Figure 1 This explanation addresses the issue of poor stability of LDMOS in HTRB testing due to the passivation layer; therefore, irrelevant details are omitted.
[0021] Please refer to Figure 1 In LDMOS devices, the passivation layer 10 is typically made of silicon nitride. Before HTRB testing, the ions remaining on the chip surface from the silicon nitride are initially uniformly distributed and in a neutral state. For example... Figure 1 As shown, when the HTRB provides a reverse bias voltage to the PN junction, the surface charge of the chip will redistribute according to the existing electric field, forming regions with excessive positive and negative charges. This localized charge accumulation will disrupt the charge balance of the device, thereby affecting its electrical performance. Furthermore, contaminants such as sodium ions in the passivation layer 10 also have a critical impact on device performance. During the HTRB testing of LDMOS, the passivation layer 10, composed of silicon nitride, cannot shield the influence of surface ionic charges on the device's field distribution, which can cause premature breakdown of the device surface.
[0022] To address the aforementioned technical problems, the present invention provides an LDMOS device and its fabrication method, which improves the stability of the device in HTRB testing by setting a metal field plate 510 and an oxide passivation layer 520.
[0023] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0024] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.
[0025] Figures 2 to 6 This is a schematic diagram of the structure of each step in the fabrication method of the LDMOS device according to an embodiment of the present invention.
[0026] Please refer to Figure 2 Substrate 100 is provided.
[0027] In this embodiment, the conductivity type of the substrate 100 can be P-type.
[0028] Specifically, the material of the substrate 100 may include silicon. The size of the substrate 100 may be 6 inches, 8 inches, 12 inches, etc., and there is no limitation thereto.
[0029] Please refer to Figure 3 The substrate 100 has an LDMOS device structure inside and on the substrate 100, and the surface of the substrate 100 and the surface of the LDMOS device structure have a dielectric layer 300 and a conductive layer 400.
[0030] The conductive layer 400 is located within the dielectric layer 300 and is connected to the LDMOS device structure.
[0031] Specifically, the dielectric layer material can include silicon dioxide.
[0032] In this embodiment, the LDMOS device structure may include: a first well region 210, a field oxygen structure 220, a second well region 230, a drain region 240, a source region 250, a gate structure 260, and a body region 270.
[0033] Specifically, the first well region 210 is located within the substrate 100.
[0034] Specifically, the field oxygen structure 220 is located within the first well region 210 and on the surface of the first well region 210.
[0035] Specifically, the second well region 230 is located within the first well region 210.
[0036] Specifically, the drain region 240 is located within the first well region 210, and the second well region 230 and the drain region 240 are located on both sides of the field oxygen structure 220, respectively. Specifically, source region 250 is located within the second well region 230.
[0037] In this embodiment, the conductivity type of the source region 250 and the drain region 240 is opposite to that of the substrate 100.
[0038] Specifically, the conductivity type of the source region 250 and the drain region 240 can be N-type.
[0039] Specifically, the gate structure 260 is located on the surface of the first well region 210 and the surface of the second well region 230 between the source region 250 and the field oxygen structure 220, and extends to a portion of the surface of the field oxygen structure 220.
[0040] Specifically, the body region 270 is located within the second well region 230, and the body region 270 and the gate structure 260 are located on opposite sides of the source region 250, and the body region 270 is in contact with the source region 250.
[0041] In this embodiment, the conductivity type of the second well region 230 and the body region 270 is the same as that of the substrate 100.
[0042] Specifically, the conductivity type of the second well region 230 and the body region 270 can be P-type.
[0043] In this embodiment, the conductive layer 400 is in contact with the drain region 240, the source region 250, the gate structure 260, and the body region 270, respectively.
[0044] Please refer to Figure 4 A metal layer 500 is formed on the surface of the dielectric layer 300.
[0045] In this embodiment, the thickness of the metal layer 500 is 1μm to 3μm.
[0046] In this embodiment, the material of the metal layer 500 can be aluminum.
[0047] Specifically, the method for forming the metal layer 500 may include: depositing aluminum on the surface of the dielectric layer 300 using a physical vapor deposition (PVD) process and a DC sputtering method.
[0048] Please refer to Figure 5 The metal layer 500 is oxidized to form a metal field plate 510 on the surface of the dielectric layer 300 and an oxide passivation layer 520 on the surface of the metal field plate 510.
[0049] The thickness of the oxide passivation layer 520 is less than or equal to the thickness of the metal field plate 510.
[0050] In this embodiment, the oxidation process may include an ion implantation process.
[0051] Specifically, the implanted ion in the ion implantation process is oxygen ion, and the implantation dose is 1e14cm. -2 ~5e14cm -2 .
[0052] In this embodiment, the thickness of the oxide passivation layer 520 is 30% to 50% of the total thickness of the metal field plate 510 and the oxide passivation layer 520.
[0053] In this embodiment, the total thickness of the metal field plate 510 and the oxide passivation layer 520 is 1 μm to 3 μm.
[0054] In this embodiment, the material of the metal field plate 510 may include aluminum.
[0055] In this embodiment, the material of the oxide passivation layer 520 may include aluminum oxide.
[0056] In this embodiment, a metal field plate 510 and an oxide passivation layer 520 are formed simultaneously by ion implantation. The thickness of the oxide passivation layer 520 is set to 30% to 50% of the total thickness of the metal field plate 510 and the oxide passivation layer 520. Therefore, it is possible to avoid device damage caused by excessive penetration of the metal layer by ion implantation, while retaining the isopotential form of aluminum metal, thereby improving the stability of the device in HTRB testing.
[0057] In this embodiment, the metal field plate 510 is made of aluminum, and the oxide passivation layer 520 is made of aluminum oxide. Aluminum oxide has a high dielectric constant (ε). rWith a density of approximately 9.3 and excellent impurity resistance, it reduces environmental contamination of the interface and lowers the interface state density. Simultaneously, due to the unique negative fixed charge characteristics of alumina, the oxide passivation layer 520 provides excellent surface passivation. Under the protection of the oxide passivation layer 520, the unoxidized aluminum metal, acting as a metal field plate 510, can shield the influence of surface ionic charges on the device's electric field distribution, improving the device's stability during HTRB testing.
[0058] Please refer to Figure 6 The metal field plate 510, oxide passivation layer 520 and dielectric layer 300 are etched to form an opening 410 that exposes the conductive layer 400.
[0059] Specifically, the method for forming the opening 410 may include: forming a patterned mask on the surface of the oxide passivation layer 520, using the patterned mask as a mask to etch the metal field plate 510, the oxide passivation layer 520 and the dielectric layer 300 until the conductive layer 400 is exposed, and then removing the patterned mask.
[0060] In this embodiment, an LDMOS device structure is provided within and on the substrate 100 to define the main structure of the device. Since the surfaces of the substrate 100 and the LDMOS device structure have a dielectric layer 300 and a conductive layer 400, with the conductive layer 400 located within the dielectric layer 300 and connected to the LDMOS device structure, the dielectric layer 300 can achieve electrical isolation between the device and the external environment. A metal layer 500 is formed on the surface of the dielectric layer 300, and the metal layer 500 is oxidized to form a metal field plate 510 on the surface of the dielectric layer 300 and an oxide passivation layer 520 on the surface of the metal field plate 510. Therefore, a composite structure consisting of an unoxidized metal field plate 510 and an oxidized oxide passivation layer 520 is formed on the surface of the dielectric layer 300. In the composite structure, the unoxidized metal field plate 510 has an equipotential form, which can effectively shield the surface charge redistribution caused by the application of reverse bias voltage to the PN structure during HTRB testing, improving the stability of the LDMOS during HTRB testing. Meanwhile, the oxidized oxide passivation layer 520 acts as a passivation layer to protect the device from external environmental factors such as moisture, ion contamination, and mechanical stress. Since the thickness of the oxide passivation layer 520 is less than or equal to the thickness of the metal field plate 510, the passivation layer thickness is sufficient to withstand external environmental factors while the metal field plate 510 is formed at an equipotential state. Simultaneously, by oxidizing the metal layer 500, a composite structure consisting of an unoxidized metal field plate 510 and an oxidized oxide passivation layer 520 is simultaneously formed. This fabrication method is simple, efficient, and suitable for large-scale production.
[0061] Accordingly, this invention also provides an LDMOS device fabricated based on the above-described LDMOS device fabrication method.
[0062] Please continue to refer to this. Figure 5 An LDMOS device may include a substrate 100, a metal field plate 510, and an oxide passivation layer 520.
[0063] Specifically, the substrate 100 has an LDMOS device structure inside and on the substrate 100, and the surface of the substrate 100 and the surface of the LDMOS device structure have a dielectric layer 300 and a conductive layer 400. The conductive layer 400 is located inside the dielectric layer 300 and is connected to the LDMOS device structure.
[0064] Specifically, the metal field plate 510 is located on the surface of the dielectric layer 300.
[0065] Specifically, the oxide passivation layer 520 is located on the surface of the metal field plate 510, and the thickness of the oxide passivation layer 520 is less than or equal to the thickness of the metal field plate 510.
[0066] In this embodiment, the total thickness of the metal field plate 510 and the oxide passivation layer 520 is 1 μm to 3 μm.
[0067] In this embodiment, the thickness of the oxide passivation layer 520 is 30% to 50% of the total thickness of the metal field plate 510 and the oxide passivation layer 520.
[0068] In this embodiment, the material of the metal field plate 510 may include aluminum.
[0069] In this embodiment, the LDMOS device structure may include: a first well region 210, a field oxygen structure 220, a second well region 230, a drain region 240, a source region 250, a gate structure 260, and a body region 270.
[0070] Specifically, the first well region 210 is located within the substrate 100.
[0071] Specifically, the field oxygen structure 220 is located within the first well region 210 and on the surface of the first well region 210.
[0072] Specifically, the second well region 230 is located within the first well region 210.
[0073] Specifically, the drain region 240 is located within the first well region 210, and the second well region 230 and the drain region 240 are located on both sides of the field oxygen structure 220, respectively. Specifically, source region 250 is located within the second well region 230.
[0074] Specifically, the gate structure 260 is located on the surface of the first well region 210 and the surface of the second well region 230 between the source region 250 and the field oxygen structure 220, and extends to a portion of the surface of the field oxygen structure 220.
[0075] Specifically, the body region 270 is located within the second well region 230, and the body region 270 and the gate structure 260 are located on opposite sides of the source region 250, and the body region 270 is in contact with the source region 250.
[0076] Specifically, the materials, formation process, working principle, specific implementation method and beneficial effects of the LDMOS device in the embodiments of the present invention can be found in the preparation method of the LDMOS device in the embodiments of the present invention, and will not be repeated here.
[0077] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for fabricating an LDMOS device, characterized in that, include: A substrate is provided, wherein an LDMOS device structure is provided within and on the substrate, and a dielectric layer and a conductive layer are provided on the surface of the substrate and the surface of the LDMOS device structure, wherein the conductive layer is located within the dielectric layer and is connected to the LDMOS device structure; A metal layer is formed on the surface of the dielectric layer; The metal layer is oxidized to form a metal field plate on the surface of the dielectric layer and an oxide passivation layer on the surface of the metal field plate, wherein the thickness of the oxide passivation layer is less than or equal to the thickness of the metal field plate.
2. The preparation method according to claim 1, characterized in that, The thickness of the oxide passivation layer is 30% to 50% of the total thickness of the metal field plate and the oxide passivation layer.
3. The preparation method according to claim 2, characterized in that, The total thickness of the metal field plate and the oxide passivation layer is 1 μm to 3 μm.
4. The preparation method according to claim 1, characterized in that, The material of the metal field plate includes aluminum.
5. The preparation method according to claim 1, characterized in that, The oxidation treatment process includes an ion implantation process, wherein the implanted ions are oxygen ions, and the implantation dose is 1e14cm. -2 ~5e14cm -2 .
6. The preparation method according to claim 1, characterized in that, The LDMOS device structure includes: The first well region is located within the substrate; A field oxygen structure is located within the first well region and on the surface of the first well region; The second well region is located within the first well region; The drain region is located within the first well region, and the second well region and the drain region are located on opposite sides of the field oxygen structure, respectively. The source region is located within the second well region; A gate structure is located on the surface of a first well region and a second well region between the source region and the field oxygen structure, and extends to a portion of the surface of the field oxygen structure. The body region is located within the second well region, and the body region and the gate structure are located on opposite sides of the source region, with the body region in contact with the source region.
7. The preparation method according to claim 1, characterized in that, Also includes: The metal field plate, the oxide passivation layer, and the dielectric layer are etched to form an opening that exposes the conductive layer.
8. An LDMOS device, characterized in that, include: A substrate having an LDMOS device structure inside and on the substrate, the substrate surface and the LDMOS device structure surface having a dielectric layer and a conductive layer, the conductive layer being located within the dielectric layer and connected to the LDMOS device structure; A metal field plate is located on the surface of the dielectric layer; An oxide passivation layer is located on the surface of the metal field plate, and the thickness of the oxide passivation layer is less than the thickness of the metal field plate.
9. The LDMOS device as described in claim 8, characterized in that, The total thickness of the metal field plate and the oxide passivation layer is 1 μm to 3 μm, and the thickness of the oxide passivation layer is 30% to 50% of the total thickness of the metal field plate and the oxide passivation layer. The material of the metal field plate includes aluminum.
10. The LDMOS device as described in claim 8, characterized in that, The LDMOS device structure includes: The first well region is located within the substrate; A field oxygen structure is located within the first well region and on the surface of the first well region; The second well region is located within the first well region; The drain region is located within the first well region, and the second well region and the drain region are located on opposite sides of the field oxygen structure, respectively. The source region is located within the second well region; A gate structure is located on the surface of a first well region and a second well region between the source region and the field oxygen structure, and extends to a portion of the surface of the field oxygen structure. The body region is located within the second well region, and the body region and the gate structure are located on opposite sides of the source region, with the body region in contact with the source region.