Gallium nitride high electron mobility transistor and method of making the same

Abstract

The application discloses a gallium nitride high electron mobility transistor and a preparation method thereof. The gallium nitride high electron mobility transistor comprises a substrate, a channel layer and a barrier layer arranged in sequence along a direction away from the substrate, a gate electrode arranged on a side of the barrier layer away from the substrate, a passivation layer covering the gate electrode and the barrier layer and comprising a plurality of passivation sub-layers arranged in sequence along a direction away from the gate electrode and an etching stop layer arranged between two adjacent passivation sub-layers, and a groove arranged on a side of the passivation layer away from the substrate, wherein the groove comprises a plurality of accommodation spaces distributed in the first direction, the depths of the plurality of accommodation spaces gradually increase so that the bottom surface of the groove is in a stepped shape, and the bottom of each accommodation space is provided with an etching stop layer; and a field plate conformally covers the bottom surface of the groove, and the field plate is in an integral structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to gallium nitride high electron mobility transistors and their fabrication methods. Background Technology

[0002] Due to their high electron mobility, high breakdown voltage, and high frequency characteristics, high electron mobility transistors (HEMTs) are widely used in fields such as radio frequency communication and power electronics.

[0003] However, existing high electron mobility transistors (HEMTs) still need improvement. Summary of the Invention

[0004] The purpose of this application is to provide a gallium nitride high electron mobility transistor and a method for fabricating the same.

[0005] This application discloses a gallium nitride high electron mobility transistor, comprising: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; A passivation layer covers the gate electrode and the barrier layer, and includes a plurality of passivation sub-layers arranged sequentially along a direction away from the gate electrode and an etch stop layer located between two adjacent passivation sub-layers; The first ohmic contact electrode and the second ohmic contact electrode are disposed on opposite sides of the gate electrode in a first direction; A groove is provided on the side of the passivation layer facing away from the substrate, and is located on the side of the first ohmic contact electrode near the gate electrode in the first direction. The groove includes a plurality of accommodating spaces distributed in the first direction. The depth of the plurality of accommodating spaces gradually increases so that the bottom surface of the groove is stepped. An etch stop layer is provided at the bottom of each accommodating space. The field plate conformally covers the bottom surface of the groove, and the field plate is an integral structure.

[0006] In some alternative implementations, the depth difference between any two adjacent accommodating spaces is the same.

[0007] In some alternative embodiments, the width of each of the accommodating spaces is the same in the first direction; or for any two adjacent accommodating spaces with different depths, the width of the accommodating space with greater depth in the first direction is less than the width of the accommodating space with less depth in the first direction.

[0008] In some alternative implementations, the depth of the plurality of accommodating spaces gradually increases along the direction from the first ohmic contact electrode to the gate electrode.

[0009] In some alternative embodiments, the material of the etch stop layer includes aluminum nitride.

[0010] In some alternative implementations, the number of etch stop layers is greater than or equal to 2, and the number of passivation sublayers is greater than or equal to 3.

[0011] In some alternative embodiments, the field plate extends the groove on at least one side in the first direction and covers a portion of the top surface of the passivation layer.

[0012] In some alternative embodiments, the top surface of the passivation layer includes a stepped structure, and the field plate extends from the groove on the side away from the first ohmic contact electrode in the first direction and covers the stepped structure.

[0013] In some alternative embodiments, the orthogonal projection of the field plate onto the substrate covers a portion of the orthogonal projection of the gate electrode onto the substrate.

[0014] In some alternative implementations, the field plate is made of titanium nitride.

[0015] In some alternative implementations, the thickness of the field plate conformally covering the bottom surface of the groove is the same at all points.

[0016] In some alternative embodiments, the gate electrode and the field plate are both strip-shaped when projected onto the substrate, and they extend in the same direction.

[0017] In some alternative embodiments, the gallium nitride high electron mobility transistor further includes: An insulating layer covers the passivation layer and the field plate; The field plate contact hole penetrates the insulating layer, and the portion of the field plate located in the accommodating space with the greatest depth among the plurality of accommodating spaces is exposed through the field plate contact hole; The first wiring layer is disposed on the side of the insulating layer away from the substrate and is connected to the field plate through the field plate contact hole.

[0018] In some alternative implementations, the first wiring layer includes: Two first conductive blocks, one of which is disposed on top of the first ohmic contact electrode, and the other of which is disposed on top of the second ohmic contact electrode. The third conductive block is connected to the field plate through the contact hole of the field plate; The connecting part connects the third conductive block and the first conductive block disposed on top of the second ohmic contact electrode.

[0019] In some alternative embodiments, the orthographic projection of the groove on the substrate lies between the orthographic projection of the gate electrode on the substrate and the orthographic projection of the first ohmic contact electrode on the substrate.

[0020] This application also discloses a method for fabricating a gallium nitride high electron mobility transistor, including: Provide substrate; A channel layer and a barrier layer are formed sequentially along a direction away from the substrate; A gate electrode and a passivation layer covering the gate electrode are formed on the side of the barrier layer away from the substrate. The passivation layer includes a plurality of passivation sub-layers arranged sequentially along the direction away from the gate electrode and an etch stop layer located between two adjacent passivation sub-layers. A groove is formed on the side of the passivation layer facing away from the substrate. The groove includes a plurality of accommodating spaces distributed in a first direction. The depth of the plurality of accommodating spaces gradually increases so that the bottom surface of the groove is stepped. An etching stop layer is provided at the bottom of each accommodating space. A conformal field plate is formed covering the bottom surface of the groove, and the field plate is an integral structure.

[0021] In some alternative embodiments, the step of forming a groove on the side of the passivation layer opposite to the substrate includes: Multiple accommodating spaces are sequentially formed to form the groove, and each accommodating space is formed by a single photolithography process.

[0022] In some alternative implementations, the step of forming the deeper accommodating space precedes the step of forming the shallower accommodating space.

[0023] In some alternative embodiments, in the depth direction of the groove, the groove includes a plurality of receiving spaces distributed sequentially; for any two adjacent receiving spaces, the receiving space away from the substrate extends from the receiving space close to the substrate on one side in the first direction, and an etching stop layer is provided at the bottom of the extended portion; The step of forming a groove on the side of the passivation layer opposite to the substrate includes: Multiple receiving spaces are formed sequentially to create the groove.

[0024] In some alternative embodiments, for any two adjacent containment spaces, the formation step of the containment space farther from the substrate precedes the formation step of the containment space closer to the substrate.

[0025] In some alternative implementations, it also includes: An insulating layer is formed covering the passivation layer and the field plate; A field plate contact hole is formed that penetrates the insulating layer, and the portion of the field plate located in the accommodating space with the greatest depth among the plurality of accommodating spaces is exposed through the field plate contact hole; A first wiring layer is formed on the side of the insulating layer away from the substrate, and the first wiring layer is connected to the field plate through the field plate contact hole.

[0026] In some alternative implementations, it also includes: Two first electrode vias are formed simultaneously with the field plate contact holes. Each first electrode via penetrates the insulating layer and the passivation layer. In a direction facing the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. A first ohmic contact electrode, a second ohmic contact electrode, and a second conductive structure are formed simultaneously. The first ohmic contact electrode fills one of the first electrode vias, the second ohmic contact electrode fills another of the first electrode vias, and the second conductive structure fills the field plate contact hole and contacts the field plate.

[0027] In some alternative embodiments, the field plate extends the groove on at least one side in the first direction and covers a portion of the top surface of the passivation layer.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0030] Figure 1 This is a schematic diagram showing the passivation layer after it has been formed in the method for fabricating the gallium nitride high electron mobility transistor of this application.

[0031] Figure 2A This is a schematic diagram showing the formation of a groove in the fabrication method of the gallium nitride high electron mobility transistor of this application.

[0032] Figure 2B for Figure 2A Enlarged schematic diagram of the central groove.

[0033] Figure 2C , Figure 2D as well as Figure 2E This is a schematic diagram of the groove formation process.

[0034] Figure 3 This is a schematic diagram of the field plate after it has been formed in the method for fabricating the gallium nitride high electron mobility transistor of this application.

[0035] Figure 4 This is a schematic diagram showing the formation of field plate contact holes in the method for fabricating the gallium nitride high electron mobility transistor of this application.

[0036] Figure 5 This is a schematic diagram of the gallium nitride high electron mobility transistor fabrication method of this application after the formation of the first wiring layer.

[0037] Figure 6 and Figure 7 This is a schematic diagram of an ohmic contact electrode, a first conductive structure, or a second conductive structure.

[0038] Figure 8 This is a top view of the gallium nitride high electron mobility transistor of this application.

[0039] Reference numerals: 1. Ohmic contact electrode; 101. First conductive layer; 102. Second conductive layer; 103. Third conductive layer; 104. Fourth conductive layer; 105. First ohmic contact electrode; 106. Second ohmic contact electrode; 2. First conductive structure; 3. First wiring layer; 301. First conductive block; 302. Second conductive block; 303. Third conductive block; 4. Passivation layer; 401. Passivation sublayer; 402. Etch stop layer; 5. Substrate; 6. Channel layer; 7. Barrier layer; 8. Gate electrode; 801. Semiconductor part; 802. Metal part; 9. Groove; 901. Accommodation space; 902. Reception space; 10. Insulating layer; 11. First electrode via; 12. Second electrode via; 13. Field plate contact hole; 14. Second conductive structure; 15. Field plate; 16. Connecting part; 17. Step structure; X, First direction. Detailed Implementation

[0040] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0041] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0042] This application provides a method for fabricating a gallium nitride (GaN) high electron mobility transistor. The method for fabricating this GaN high electron mobility transistor may include: Step S10, as follows Figure 1 As shown, substrate 5 is provided; Step S20: Form a channel layer 6 and a barrier layer 7 sequentially arranged along a direction away from the substrate 5; Step S30: A gate electrode 8 and a passivation layer 4 covering the gate electrode 8 are formed on the side of the barrier layer 7 away from the substrate 5. Step S40, as Figure 5 As shown, two ohmic contact electrodes 1 are formed, and the two ohmic contact electrodes 1 are disposed on opposite sides of the gate electrode 8 in the first direction X.

[0043] This application also provides a gallium nitride high electron mobility transistor. This gallium nitride high electron mobility transistor can be fabricated using the method described above. The gallium nitride high electron mobility transistor may include: a substrate 5; a channel layer 6 and a barrier layer 7 sequentially disposed along a direction away from the substrate 5; a gate electrode 8 disposed on the side of the barrier layer 7 away from the substrate 5; a passivation layer 4 covering the gate electrode 8 and the barrier layer 7; and two ohmic contact electrodes 1 disposed on opposite sides of the gate electrode 8 in a first direction X.

[0044] The following is a detailed description of each part of the embodiments of this application: like Figure 1 As shown, the substrate 5 can be either a Si substrate 5 or a SiC substrate 5. The Si substrate 5 or SiC substrate 5 has a high thermal conductivity and a matching lattice constant, which can improve the heat dissipation performance of the device and the quality of the heterojunction. In other embodiments, the substrate 5 can also be made of other materials.

[0045] This application utilizes a deposition process to grow a GaN layer on substrate 5 to form a channel layer 6. It should be noted that, prior to forming the channel layer 6, a GaN buffer layer can be formed first, followed by the formation of the channel layer 6 on the GaN buffer layer. The function of the channel layer 6 is to provide a high-mobility two-dimensional electron gas (2DEG) channel. This application can also grow an AlGaN layer on the channel layer 6 to form a barrier layer 7. This barrier layer 7 forms a heterojunction with the channel layer 6, inducing 2DEG through a polarization effect.

[0046] The barrier layer 7 and the channel layer 6 can also be selected from other different nitrogen-based semiconductor materials. Exemplary materials for the channel layer 6 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride, aluminum nitride, and indium nitride. Exemplary materials for the barrier layer 7 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride, aluminum nitride, indium nitride, and aluminum gallium nitride. Exemplary materials for the channel layer 6 and the barrier layer 7 may be selected such that the barrier layer 7 has a larger band gap (i.e., bandgap width) than the channel layer 6 to form a heterojunction. For example, when the channel layer 6 is an undoped gallium nitride layer (with a band gap of approximately 3.4 eV), the barrier layer 7 may be selected as an aluminum gallium nitride layer (with a band gap of approximately 4.0 eV). A triangular potential well is generated at the interface between the channel layer 6 and the barrier layer 7, allowing electrons to accumulate in the triangular potential well, thereby creating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.

[0047] This application can form a gate electrode 8 using a deposition process. The gate electrode 8 can be strip-shaped, and its extension direction can be parallel to the substrate 5. Along the direction away from the substrate 5, the gate electrode 8 can include a stacked semiconductor portion 801 and a metal portion 802. The material of the semiconductor portion 801 can include p-type gallium nitride. Along the direction away from the substrate 5, the passivation layer 4 can include a plurality of passivation sub-layers 401 sequentially disposed. This application can form the passivation sub-layers 401 by depositing oxides (e.g., silicon oxide) or nitrides (e.g., silicon nitride) using a deposition process. The materials of different passivation sub-layers 401 can be the same, or they can be different. The passivation layer 4 also includes an etch stop layer 402 located between two adjacent passivation sub-layers 401. An etch stop layer 402 is provided between any two adjacent passivation sub-layers 401. The number of etch stop layers 402 is greater than or equal to 2, for example, 2, 4, 7, 8, etc. The number of passivation sub-layers 401 is greater than or equal to 3, for example, 3, 5, 8, 9, etc. Among the multiple passivation sub-layers 401, the passivation sub-layer 401 closest to the substrate 5 conforms to the gate electrode 8 and the barrier layer 7. An etch stop layer 402 located on the side of the passivation sub-layer 401 away from the substrate 5 conforms to the passivation sub-layer 401, and an etch stop layer 402 located on the side of the etch stop layer 402 away from the substrate 5 conforms to the etch stop layer 402. The thickness of the passivation sub-layer 401 is greater than the thickness of the etch stop layer 402. In another embodiment, the orthographic projection of each etch stop layer 402 onto the substrate 5 lies between the orthographic projection of the gate electrode 8 onto the substrate 5 and the orthographic projection of the first ohmic contact electrode 105 onto the substrate 5. The etch rate of the etch stop layer 402 is less than the etch rate of the passivation sub-layer 401. The material of the etch stop layer 402 may include aluminum, such as aluminum nitride. The etch stop layer 402 can be formed by a deposition process.

[0048] like Figure 5 As shown, the two ohmic contact electrodes 1 include a first ohmic contact electrode 105 and a second ohmic contact electrode 106. The two ohmic contact electrodes 1 are disposed on opposite sides of the gate electrode 8 in a first direction X (see...). Figure 8 , Figure 5 for Figure 8 (A cross-sectional view along the AA direction). This first direction X can be perpendicular or substantially perpendicular to the extension direction of the orthographic projection of the gate electrode 8 onto the substrate 5. One of the first ohmic contact electrode 105 and the second ohmic contact electrode 106 is the source and the other is the drain. For example, the first ohmic contact electrode 105 is the drain and the second ohmic contact electrode 106 is the source.

[0049] like Figure 3 and Figure 5 As shown, this application also includes at least one field plate 15. The field plate 15 can be a source field plate 15, a drain field plate 15, or a gate field plate 15, etc. This application also includes a recess 9 (see...). Figure 2A The groove 9 is located on the side of the passivation layer 4 facing away from the substrate 5, that is, the opening end of the groove 9 is located on the surface of the passivation layer 4 facing away from the substrate 5. The groove 9 is located on the side of the first ohmic contact electrode 105 near the gate electrode 8 in the first direction X. For example, in the first direction X, the orthographic projection of the groove 9 on the substrate 5 is located between the orthographic projection of the gate electrode 8 on the substrate 5 and the orthographic projection of the first ohmic contact electrode 105 on the substrate 5. The field plate 15 conformally covers the bottom surface of the groove 9. The field plate 15 is a one-piece structure, that is, the field plate 15 is integrally formed and continuously disposed. The field plate 15 can be formed by a deposition process. Since the field plate 15 is a one-piece structure, it can be fabricated using a single mask, simplifying the process. The thickness of the field plate 15 conformally covering the bottom surface of the groove 9 is the same at all points, that is, the field plate 15 has a uniform thickness. The material of the field plate 15 may include titanium nitride, etc. The field plate 15 extends a groove 9 on at least one side in the first direction X and covers a portion of the top surface of the passivation layer 4. For example, the top surface of the passivation layer 4 includes a stepped structure 17 (see...). Figure 2A The stepped structure 17 is generated by the conformal coverage of multiple passivation sublayers 401. The field plate 15 extends from the side away from the first ohmic contact electrode 105 in the first direction X, and covers the stepped structure 17. The orthographic projections of the gate electrode 8 and the field plate 15 on the substrate 5 are both strip-shaped and extend in the same direction. In addition, taking the first ohmic contact electrode 105 as the drain and the second ohmic contact electrode 106 as the source as an example, the electric field is strong near the drain side of the gate electrode 8 and weak near the source side of the gate electrode 8. In this application, the orthographic projection of the field plate 15 (connected to the source) on the substrate 5 is also configured to cover part of the orthographic projection of the gate electrode 8 on the substrate 5. With this configuration, the electric field near the drain side of the gate electrode 8 can be reduced, thereby achieving electric field modulation.

[0050] like Figure 2A and Figure 2B As shown, the groove 9 includes a plurality of accommodating spaces 901 distributed along the first direction X. Two adjacent accommodating spaces 901 are connected, and the plurality of accommodating spaces 901 together constitute the groove space within the groove 9. The orthographic projection of each accommodating space 901 onto the substrate 5 is strip-shaped and perpendicular to the first direction X. Along the first direction X, the depth of the plurality of accommodating spaces 901 gradually increases to make the bottom surface of the groove 9 stepped. In one embodiment, along the direction away from the first ohmic contact electrode 105 (i.e., the direction in which the first ohmic contact electrode 105 points to the gate electrode 8), the depth of the plurality of accommodating spaces 901 ( Figure 2B The depth of the plurality of accommodating spaces 901 gradually increases along the direction close to the first ohmic contact electrode 105 (i.e., the direction in which the gate electrode 8 points to the first ohmic contact electrode 105). Furthermore, the difference in depth between any two adjacent accommodating spaces 901 is the same. In the first direction X, the width (h) of each accommodating space 901 is... Figure 2B The etch stop layer 402 is provided at the bottom of each of the two adjacent accommodating spaces 901 with different depths. The accommodating space 901 with the greater depth has a width in the first direction X that is smaller than the accommodating space 901 with the less depth in the first direction X.

[0051] This disclosure allows for the formation of a groove 9 on the side of the passivation layer 4 facing away from the substrate 5 using photolithography, and multiple accommodating spaces 901 can be formed sequentially. Each accommodating space 901 is formed through a single photolithography process; that is, different accommodating spaces 901 are formed through different photolithography processes. For example, if the groove 9 includes n (n greater than or equal to 2) accommodating spaces 901, n accommodating spaces 901 require n photolithography processes to form. Due to the presence of the etch stop layer 402, precise etching can be achieved when etching to form the accommodating spaces 901. Specifically, for the accommodating spaces 901 that penetrate the etch stop layer 402, during the etching process, the passivation sublayer 401 can be etched using a first etching medium, and the etch stop layer 402 can be etched using a second etching medium. The first and second etching media are different. The first etching medium may include one or more of carbon tetrafluoride and trifluoromethane. The second etching medium may include boron trichloride. The step of forming the deeper accommodating space 901 is before the step of forming the shallower accommodating space 901, or the step of forming the deeper accommodating space 901 is after the step of forming the shallower accommodating space 901.

[0052] In addition, such as Figure 2EAs shown, in the depth direction of the groove 9, the groove 9 includes a plurality of sequentially distributed receiving spaces 902. For any two adjacent receiving spaces 902, the receiving space 902 away from the substrate 5 extends outward from the receiving space 902 close to the substrate 5 on the side of the first direction X, and an etching stop layer 402 is provided at the bottom of the extended portion. Further, along the direction away from the substrate 5, the width of the plurality of receiving spaces 902 gradually increases in the first direction X, and the plurality of receiving spaces 902 can be aligned or approximately aligned on one side in the first direction X, while the plurality of receiving spaces 902 are sequentially staggered on the other side in the first direction X. The steps of forming the groove 9 may include: as follows Figure 2C , Figure 2D as well as Figure 2E As shown, multiple accommodating spaces 902 are formed sequentially to form a groove 9. Each accommodating space 902 is formed by a single photolithography process. Furthermore, for any two adjacent accommodating spaces 902, the formation step of the accommodating space 902 farther from the substrate 5 precedes the formation step of the accommodating space 902 closer to the substrate 5.

[0053] like Figure 4 and Figure 5 As shown, this application also includes an insulating layer 10 and a first wiring layer 3. The insulating layer 10 covers the passivation layer 4 and the field plate 15. The insulating layer 10 can be formed by depositing an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride) using a deposition process. This application also includes at least one field plate contact hole 13. The field plate contact hole 13 penetrates the insulating layer 10 and exposes the field plate 15. Taking one field plate contact hole 13 as an example, the portion of the field plate 15 located in the largest of the plurality of accommodating spaces 901 is exposed through the field plate contact hole 13, that is, the orthographic projection of the field plate contact hole 13 on the substrate 5 coincides with the orthographic projection of the largest accommodating space 901 on the substrate 5. The field plate contact hole 13 can be formed by an etching process. In a direction away from the substrate 5 and perpendicular to the substrate 5, the cross-sectional area of ​​the field plate contact hole 13 parallel to the substrate 5 gradually increases. The first wiring layer 3 can be disposed on the side of the insulating layer 10 away from the substrate 5, and covers the field plate contact hole 13, and is connected to the field plate 15 through the field plate contact hole 13. The first wiring layer 3 is also a metallized interconnect layer. The metallized interconnect layer connects all the sources or drains of multiple unit transistors together through the wiring arrangement, and spreads the current more evenly from the pads (such as source pads or drain pads) to the entire device working area.

[0054] This application also includes two first electrode vias 11. The aforementioned first ohmic contact electrode 105 fills one first electrode via 11, and the second ohmic contact electrode 106 fills the other first electrode via 11. The bottom of the ohmic contact electrode 1 is in direct contact with the bottom of the first electrode via 11. The aforementioned first wiring layer 3 covers the two first electrode vias 11 and is in direct contact with the two ohmic electrodes. The first wiring layer 3 is in direct contact with the top of the first electrode via 11. The two ohmic contact electrodes 1 can be formed by a deposition process. In the first direction X, the two first electrode vias 11 are disposed on opposite sides of the gate electrode 8, the opening of each first electrode via 11 is located on the surface of the insulating layer 10 away from the substrate 5, and each first electrode via 11 penetrates the insulating layer 10 and the passivation layer 4. In the direction toward and perpendicular to the substrate 5, the bottom of the first electrode via 11 extends at least into the barrier layer 7. Furthermore, the bottom of the first electrode via 11 may extend to the interface between the barrier layer 7 and the channel layer 6. The bottom of the first electrode via 11 can also extend into the channel layer 6. In this case, the bottom of the ohmic contact electrode 1 disposed in the first electrode via 11 forms a large area of ​​ohmic contact with the channel layer 6 and the barrier layer 7, which is more conducive to the transmission of 2DEG. This can effectively reduce the difficulty of depositing the ohmic contact electrode 1 in the first electrode via 11. That is to say, when the bottom of the first electrode via 11 extends directly into the channel layer 6, even if the hole depth of the first electrode via 11 is large and the bottom hole diameter is small, it is not easy to fill or the material used to prepare the ohmic contact electrode 1 has poor properties and is not easy to deposit to the bottom of the first electrode via 11, resulting in poor deposition quality of the bottom of the ohmic contact electrode 1, the bottom of the ohmic contact electrode 1 can still form a good ohmic contact with the channel layer 6 and the barrier layer 7.

[0055] This application can use dry etching to form two first electrode vias 11. The aforementioned first electrode vias 11 are fabricated using the same mask; that is, this application uses one mask during the dry etching process to form the first electrode vias 11. In related technologies, the formation of the connecting via and the ohmic contact electrode 1 uses two masks. Because the first electrode vias 11 are fabricated using the same mask, the sidewalls of the first electrode vias 11 are continuously formed from the bottom to the opening (top) of the first electrode via 11; that is, the sidewalls of the first electrode via 11 are continuously fabricated using a single etching process. Furthermore, during the formation of the two first electrode vias 11, this application can also simultaneously form the field plate contact hole 13; that is, the field plate contact hole 13 and the first electrode vias 11 are formed using the same mask in a simultaneous etching process. In this application, the first electrode via 11 extends directly from the top of the passivation layer 4 into the barrier layer 7, so that the top of the ohmic contact electrode 1 formed in the two first electrode vias 11 directly contacts the first wiring layer 3, and the bottom of the ohmic contact electrode 1 extends into the barrier layer 7. This eliminates the need to use an additional mask to fabricate the source and drain, simplifying the process and reducing costs.

[0056] In one implementation, such as Figure 4 and Figure 5 As shown, in a direction away from and perpendicular to the substrate 5, the cross-sectional area of ​​the first electrode via 11 parallel to the substrate 5 gradually increases. For example, in the first direction X, the first electrode via 11 includes two opposing sidewalls, each sidewall being inclined, and the distance between the two sidewalls gradually increases along the direction away from the substrate 5, which is more conducive to forming an ohmic contact electrode 1 with good filling quality. In another embodiment, in a direction away from and perpendicular to the substrate 5, the cross-sectional area of ​​at least a portion of the first electrode via 11 monotonically increases, monotonically decreases, or remains unchanged, that is, the distance between the two sidewalls of at least a portion of the first electrode via 11 monotonically increases, monotonically decreases, or remains unchanged. One of the two first electrode vias 11 is used to define the source region, and the other is used to define the drain region.

[0057] Furthermore, during the formation of the two first electrode vias 11, this application can simultaneously form a second electrode via 12, that is, the second electrode via 12 and the first electrode via 11 are formed using the same mask in a synchronous etching process. The orthographic projection of the second electrode via 12 onto the substrate 5 can be strip-shaped, and its extension direction is perpendicular to the first direction X. The depth of the second electrode via 12 is less than the depth of the first electrode via 11. The opening of the second electrode via 12 is located on the surface of the insulating layer 10 away from the substrate 5. The second electrode via 12 penetrates the insulating layer 10 and the portion of the passivation layer 4 located above the gate electrode 8 to expose the gate electrode 8, and the orthographic projection of the bottom of the second electrode via 12 onto the substrate 5 is located within the orthographic projection area of ​​the gate electrode 8 onto the substrate 5. The bottom of the second electrode via 12 can extend to the top surface of the gate electrode 8. Furthermore, in the first direction X, the top width of the second electrode via 12 can be smaller than the top width of the first electrode via 11, meaning the width of the first electrode via 11 is larger. This configuration reduces the aspect ratio of the deeper first electrode via 11. Two ohmic contact electrodes 1 fill the two first electrode vias 11 in a one-to-one correspondence. Along the direction away from the substrate 5, the ohmic contact electrode 1 includes multiple conductive layers stacked together. For example... Figure 6 and Figure 7As shown, the stacked conductive layers include a first conductive layer 101 and a second conductive layer 102. The second conductive layer 102 is located on the side of the first conductive layer 101 away from the substrate 5. The resistivity of the first conductive layer 101 is lower than that of the second conductive layer 102. For example, the material of the first conductive layer 101 may be aluminum, and the material of the second conductive layer 102 may be tungsten. This arrangement can reduce the ohmic contact resistance and improve the via filling performance of the ohmic contact electrode 1 (tungsten has good filling performance). The surface of the second conductive layer 102 away from the substrate 5 is coplanar with the surface of the insulating layer 10 away from the substrate 5. The stacked conductive layers also include a third conductive layer 103 located between the first conductive layer 101 and the second conductive layer 102. The material of the third conductive layer 103 may include titanium nitride. The stacked conductive layers also include a fourth conductive layer 104. The material of the fourth conductive layer 104 may include at least one of titanium and titanium nitride. A portion of the fourth conductive layer 104 directly contacts the bottom of the first electrode via 11, while another portion of the fourth conductive layer 104 extends from the bottom of the first electrode via 11 to its opening and contacts the first wiring layer 3, surrounding the remaining conductive layers. The outer surface of the fourth conductive layer 104 surrounding the remaining conductive layers forms the outer surface of the ohmic contact electrode 1. This fourth conductive layer 104 can conformally cover the first electrode via 11. In a direction away from and perpendicular to the substrate 5, the cross-sectional area of ​​the ohmic contact electrode 1 gradually increases. Furthermore, the top surface of the first conductive layer 101 is located on the side of the top surface of the barrier layer 7 away from the substrate 5. This arrangement can better increase the ohmic contact area between the first conductive layer 101 and the channel layer 6 and the barrier layer 7.

[0058] The gallium nitride high electron mobility transistor of this application may further include a first conductive structure 2. The first conductive structure 2 fills a second electrode via 12, and a first wiring layer 3 covers the second electrode via 12 and is connected to the first conductive structure 2. The gallium nitride high electron mobility transistor of this application may further include at least one second conductive structure 14. Each second conductive structure 14 fills a corresponding field plate contact hole 13. The ohmic contact electrode 1, the first conductive structure 2, and the second conductive structure 14 are made of the same material. For example, along the direction away from the substrate 5, the ohmic contact electrode 1, the second conductive structure 14, and the first conductive structure 2 each include a plurality of stacked conductive layers. The plurality of conductive layers of the ohmic contact electrode 1 are disposed in the same layer as the plurality of conductive layers of the first conductive structure 2, and the plurality of conductive layers of the ohmic contact electrode 1 are disposed in the same layer as the plurality of conductive layers of the second conductive structure 14. In the direction away from the substrate 5 and perpendicular to the substrate 5, the cross-sectional area of ​​the first conductive structure 2 gradually increases, and the cross-sectional area of ​​the second conductive structure 14 gradually increases. The ohmic contact electrode 1, the first conductive structure 2, and the second conductive structure 14 can be formed simultaneously.

[0059] The first wiring layer 3 can be formed by a deposition process. The first wiring layer 3 can be in direct contact with the second conductive layer 102, and the material of the first wiring layer 3 is different from that of the second conductive layer 102. For example, if the material of the second conductive layer 102 includes tungsten, the material of the first wiring layer 3 can include at least one of aluminum and copper. The resistivity of the first wiring layer 3 is less than that of the second conductive layer 102. The first wiring layer 3 includes a plurality of first conductive blocks 301, each first conductive block 301 covering a first electrode via 11 and connected to the top of an ohmic contact electrode 1; that is, the first conductive block 301 is formed directly on the top of the ohmic contact electrode 1. The first wiring layer 3 is in direct contact with the top of the first electrode via 11, meaning that the first wiring layer 3 seals the opening of the first electrode via 11. The first wiring layer 3 also covers the second electrode via 12 and the field plate contact hole 13. Specifically, the first wiring layer 3 covering the second electrode via 12 is in contact with the first conductive structure 2, and the first wiring layer 3 covering the field plate contact hole 13 is in contact with the second conductive structure 14. For example, the first wiring layer 3 further includes a second conductive block 302 and a third conductive block 303. The second conductive block 302 is in contact with the first conductive structure 2, and the third conductive block 303 is in contact with the second conductive structure 14. In a second direction parallel to the substrate 5 and perpendicular to the first direction X, the length of the first wiring layer 3 covering the second electrode via 12 (i.e., the second conductive block 302) is different from the length of the first wiring layer 3 covering the first electrode via 11 (i.e., the first conductive block 301). For example, the length of the first wiring layer 3 covering the second electrode via 12 is greater than the length of the first wiring layer 3 covering the first electrode via 11. The first wiring layer 3 of this application also includes a connecting portion 16 (see...). Figure 8 Taking the second ohmic contact electrode 106 as the source electrode and the field plate 15 as the source field plate as an example, the connecting part 16 connects the third conductive block 303 and the first conductive block 301 disposed on the top of the second ohmic contact electrode 106.

[0060] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A gallium nitride high electron mobility transistor, characterized in that, include: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; A passivation layer covers the gate electrode and the barrier layer, and includes a plurality of passivation sub-layers arranged sequentially along a direction away from the gate electrode and an etch stop layer located between two adjacent passivation sub-layers; The first ohmic contact electrode and the second ohmic contact electrode are disposed on opposite sides of the gate electrode in a first direction; A groove is provided on the side of the passivation layer facing away from the substrate, and is located on the side of the first ohmic contact electrode near the gate electrode in the first direction. The groove includes a plurality of accommodating spaces distributed in the first direction. The depth of the plurality of accommodating spaces gradually increases so that the bottom surface of the groove is stepped. An etch stop layer is provided at the bottom of each accommodating space. The field plate conformally covers the bottom surface of the groove, and the field plate is an integral structure.

2. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The difference in depth between any two adjacent accommodating spaces is the same.

3. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, In the first direction, the width of each of the accommodating spaces is the same; or For any two adjacent accommodating spaces with different depths, the accommodating space with the larger depth has a width in the first direction that is smaller than the accommodating space with the smaller depth in the first direction.

4. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The depth of the plurality of accommodating spaces gradually increases along the direction from the first ohmic contact electrode to the gate electrode.

5. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The material of the etching stop layer includes aluminum nitride.

6. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The number of etch stop layers is greater than or equal to 2, and the number of passivation sublayers is greater than or equal to 3.

7. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The field plate extends the groove on at least one side in the first direction and covers a portion of the top surface of the passivation layer.

8. The gallium nitride high electron mobility transistor according to claim 7, characterized in that, The top surface of the passivation layer includes a stepped structure, and the field plate extends from the groove on the side away from the first ohmic contact electrode in the first direction and covers the stepped structure.

9. The gallium nitride high electron mobility transistor according to claim 7, characterized in that, The orthogonal projection of the field plate onto the substrate covers a portion of the orthogonal projection of the gate electrode onto the substrate.

10. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The field plate is made of titanium nitride.

11. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The thickness of the field plate is the same at all points where it conformally covers the bottom surface of the groove.

12. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The gate electrode and the field plate both have a strip-shaped orthographic projection on the substrate, and they extend in the same direction.

13. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, Also includes: An insulating layer covers the passivation layer and the field plate; The field plate contact hole penetrates the insulating layer, and the portion of the field plate located in the accommodating space with the greatest depth among the plurality of accommodating spaces is exposed through the field plate contact hole; The first wiring layer is disposed on the side of the insulating layer away from the substrate and is connected to the field plate through the field plate contact hole.

14. The gallium nitride high electron mobility transistor according to claim 13, characterized in that, The first wiring layer includes: Two first conductive blocks, one of which is disposed on top of the first ohmic contact electrode, and the other of which is disposed on top of the second ohmic contact electrode. The third conductive block is connected to the field plate through the contact hole of the field plate; The connecting part connects the third conductive block and the first conductive block disposed on top of the second ohmic contact electrode.

15. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The orthographic projection of the groove on the substrate lies between the orthographic projection of the gate electrode on the substrate and the orthographic projection of the first ohmic contact electrode on the substrate.

16. A method for fabricating a gallium nitride high electron mobility transistor, characterized in that, include: Provide substrate; A channel layer and a barrier layer are formed sequentially along a direction away from the substrate; A gate electrode and a passivation layer covering the gate electrode are formed on the side of the barrier layer away from the substrate. The passivation layer includes a plurality of passivation sub-layers arranged sequentially along the direction away from the gate electrode and an etch stop layer located between two adjacent passivation sub-layers. A groove is formed on the side of the passivation layer facing away from the substrate. The groove includes a plurality of accommodating spaces distributed in a first direction. The depth of the plurality of accommodating spaces gradually increases so that the bottom surface of the groove is stepped. An etching stop layer is provided at the bottom of each accommodating space. A conformal field plate is formed covering the bottom surface of the groove, and the field plate is an integral structure.

17. The method for fabricating a gallium nitride high electron mobility transistor according to claim 16, characterized in that, The step of forming a groove on the side of the passivation layer opposite to the substrate includes: Multiple accommodating spaces are sequentially formed to form the groove, and each accommodating space is formed by a single photolithography process.

18. The method for fabricating a gallium nitride high electron mobility transistor according to claim 17, characterized in that, The step of forming the deeper accommodating space precedes the step of forming the shallower accommodating space.

19. The method for fabricating a gallium nitride high electron mobility transistor according to claim 16, characterized in that, In the depth direction of the groove, the groove includes a plurality of receiving spaces distributed sequentially; for any two adjacent receiving spaces, the receiving space away from the substrate extends from the receiving space close to the substrate on the side in the first direction, and an etching stop layer is provided at the bottom of the extended portion; The step of forming a groove on the side of the passivation layer opposite to the substrate includes: Multiple receiving spaces are formed sequentially to create the groove.

20. The method for fabricating a gallium nitride high electron mobility transistor according to claim 19, characterized in that, For any two adjacent containment spaces, the formation step of the containment space farther from the substrate precedes the formation step of the containment space closer to the substrate.

21. The method for fabricating a gallium nitride high electron mobility transistor according to claim 16, characterized in that, Also includes: An insulating layer is formed covering the passivation layer and the field plate; A field plate contact hole is formed that penetrates the insulating layer, and the portion of the field plate located in the accommodating space with the greatest depth among the plurality of accommodating spaces is exposed through the field plate contact hole; A first wiring layer is formed on the side of the insulating layer away from the substrate, and the first wiring layer is connected to the field plate through the field plate contact hole.

22. The method for fabricating a gallium nitride high electron mobility transistor according to claim 21, characterized in that, Also includes: Two first electrode vias are formed simultaneously with the field plate contact holes. Each first electrode via penetrates the insulating layer and the passivation layer. In a direction facing the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. A first ohmic contact electrode, a second ohmic contact electrode, and a second conductive structure are formed simultaneously. The first ohmic contact electrode fills one of the first electrode vias, the second ohmic contact electrode fills another of the first electrode vias, and the second conductive structure fills the field plate contact hole and contacts the field plate.

23. The method for fabricating a gallium nitride high electron mobility transistor according to claim 16, characterized in that, The field plate extends the groove on at least one side in the first direction and covers a portion of the top surface of the passivation layer.

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