A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductor. The semiconductor device comprises a substrate of a first conductive type, a recess is arranged in the substrate; a buried layer of a second conductive type, the buried layer is arranged at least on the bottom wall and the side wall of the recess; an epitaxial layer of the second conductive type, the epitaxial layer is arranged on the buried layer and the substrate, and the doping concentration of the epitaxial layer is less than the doping concentration of the buried layer; a well region of the first conductive type, the well region is arranged at least in the part of the epitaxial layer on the recess; a gate structure, the gate structure is arranged on the epitaxial layer and covers part of the well region; a source electrode of the second conductive type, the source electrode is arranged in the well region on one side of the gate structure; and a drain electrode of the second conductive type, the drain electrode is arranged in the epitaxial layer on both sides of the gate structure, and the drain electrode is connected with the buried layer; and an isolation structure, the isolation structure is arranged at least in the epitaxial layer between the drain electrode and the source electrode. Through the semiconductor device and the manufacturing method thereof, the hot carrier injection effect can be weakened, and the reliability of the semiconductor device can be improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a semiconductor device and its fabrication method. Background Technology

[0002] The hot carrier injection effect refers to the phenomenon where, under the influence of a high electric field inside a device, carriers gain energy and their effective temperature is higher than the equilibrium lattice temperature. The trajectory of these carriers changes, and they are injected into the medium along a direction perpendicular to the surface of the dielectric (such as an oxide layer). For example, they may be captured by trapped charges in the oxide layer. The captured charges will exist in the dielectric layer and affect the movement of normal carriers in the semiconductor. This effect is irreversible, causing problems such as a decrease in the on-resistance of the device and a shift in the threshold voltage. It may also cause an increase in substrate current and gate current, affecting the normal operation of the circuit.

[0003] In existing high-voltage metal-oxide-semiconductor transistors (HVMOS), such as Figure 1 As shown, an HVMOS typically includes a substrate 10, a gate 11, a source terminal 12, a drain terminal 13, and a substrate terminal 14. The source terminal 12 and the drain terminal 13 are respectively disposed in the drift regions (N-) on both sides of the gate 11, and a shallow trench isolation structure 15 is provided between the source terminal 12 and the drain terminal 13. The carriers at the source terminal 12 gain sufficient kinetic energy under the acceleration of a strong electric field, inducing interface state generation and oxide layer damage near the drain terminal 13. Furthermore, the drift region near the drain terminal 13 bears most of the voltage, with extremely high electric field strength, resulting in severe hot carrier injection effect, ultimately causing the HVMOS to deviate electrically and compromise its reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same. The semiconductor device and method provided by this invention can reduce the hot carrier injection effect, improve the reliability of the semiconductor device, and at the same time, avoid excessive heat at the drain, thereby improving the durability of the device.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor device, comprising: A substrate of a first conductivity type, wherein a groove is provided in the substrate; A second type of conductive buried layer is provided at least on the bottom wall and side wall of the groove; An epitaxial layer of a second conductivity type is disposed on the buried layer and the substrate, wherein the doping concentration of the epitaxial layer is less than the doping concentration of the buried layer; A well region of a first conductivity type is disposed at least within a portion of the epitaxial layer on the groove; A gate structure is disposed on the epitaxial layer and covers a portion of the well region; A source of the second conductivity type is disposed within the well region on one side of the gate structure; and A drain of the second conductivity type is disposed in the epitaxial layer on both sides of the gate structure, and the drain is connected to the buried layer; An isolation structure is provided at least within the epitaxial layer between the drain and the source.

[0006] In one embodiment of the present invention, the doping type of the drain electrode is the same as the doping type of the buried layer, and the doping concentration of the drain electrode is the same as the doping concentration of the buried layer.

[0007] In one embodiment of the present invention, the isolation structure is located at the bottom of the epitaxial layer and at a predetermined distance from the buried layer; and / or, the doping depth of the well region is less than or equal to the depth of the isolation structure.

[0008] In one embodiment of the present invention, the doping concentration of the well region is greater than the doping concentration of the epitaxial layer, and the doping concentration of the source is greater than the doping concentration of the well region.

[0009] In one embodiment of the present invention, the semiconductor device further includes a body region, which is disposed at least in the epitaxial layer on the side of the gate structure away from the well region, and the isolation structure is disposed on both sides of the body region.

[0010] In one embodiment of the present invention, the doping type of the body region is opposite to that of the epitaxial layer, and the doping concentration of the body region is greater than that of the epitaxial layer.

[0011] In one embodiment of the present invention, a body terminal is provided in the body region, and the doping type of the body terminal is the same as that of the body region; the doping concentration of the body terminal is greater than that of the body region, and the doping depth of the body terminal is equal to that of the drain electrode.

[0012] In one embodiment of the present invention, the drain is disposed in the epitaxial layer on the side of the source away from the body region and in the epitaxial layer on the side of the body region away from the source, and an isolation structure is provided between the drain, the source, and the body region.

[0013] The present invention also provides a method for fabricating a semiconductor device, comprising: A substrate of a first conductivity type is provided, and a groove is formed in the substrate; At least a second type of conductive buried layer is formed on the bottom wall and side wall of the groove; An epitaxial layer of a second conductivity type is formed on the buried layer and the substrate, wherein the doping concentration of the epitaxial layer is less than that of the buried layer; An isolation structure is formed at least within the epitaxial layer; A well region of a first conductivity type is formed within at least a portion of the epitaxial layer on the groove; A gate structure is formed on the epitaxial layer, the gate structure covering a portion of the well region; A source of a second conductivity type is formed within the well region on one side of the gate structure; and A drain of a second conductivity type is formed in the epitaxial layer on both sides of the gate structure, and the drain is connected to the buried layer; and the isolation structure is provided in the epitaxial layer between the drain and the source.

[0014] In one embodiment of the present invention, the method for fabricating the buried layer and the epitaxial layer includes: A patterned photoresist layer is formed on the substrate, and the substrate is etched using the patterned photoresist layer as a mask to form the groove; Remove the patterned photoresist layer and form the buried layer at least on the bottom and sidewalls of the groove by ion implantation; An epitaxial layer is formed on the buried layer and the substrate; A sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is planarized; and Planarize the sacrificial layer and the epitaxial layer.

[0015] In summary, this invention provides a semiconductor device and its fabrication method. By improving the structure and fabrication method of the semiconductor device, the unexpected technical effect of this application is that it can suppress the lateral movement of the source-drain current, eliminate the impact of electrons on the gate dielectric layer, and weaken the hot carrier injection effect, thereby improving the reliability of the semiconductor device. Simultaneously, the heat distribution of the semiconductor device is uniformly distributed within the space surrounded by the drain and buried layer, preventing excessive heat at the drain and improving device durability.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of HVMOS in the prior art.

[0019] Figure 2 This is a plan view of a semiconductor device according to an embodiment of the present invention.

[0020] Figure 3 For along Figure 2 A schematic diagram of a patterned photoresist layer formed on a substrate along the AA direction.

[0021] Figure 4 For along Figure 2 A schematic diagram showing the grooves formed on the substrate along the AA direction.

[0022] Figure 5 For along Figure 2 A schematic diagram of the AA direction forming a buried layer on the sidewalls and bottom wall of the groove and on the substrate.

[0023] Figure 6 For along Figure 2 A schematic diagram of an epitaxial layer formed on a buried layer in the AA direction.

[0024] Figure 7 For along Figure 2 A schematic diagram of the sacrificial layer formed on the epitaxial layer in the AA direction.

[0025] Figure 8 For along Figure 2 The intention of planarizing the epitaxial layer in the AA direction.

[0026] Figure 9 For along Figure 2 This is a schematic diagram showing the formation of a pad oxide layer, a pad nitride layer, and a photoresist layer on the epitaxial layer along the AA direction.

[0027] Figure 10 For along Figure 2 A schematic diagram of the isolation structure formed in the AA direction.

[0028] Figure 11 For along Figure 2 A schematic diagram of the AA direction in the formation of the trap region and the body region.

[0029] Figure 12 For along Figure 2 A schematic diagram showing the formation of the gate dielectric layer and gate material along the AA direction.

[0030] Figure 13 For along Figure 2 A schematic diagram of the gate structure formed in the AA direction.

[0031] Figure 14 For along Figure 2 A schematic diagram showing the formation of the source, drain, and body terminals along the AA direction.

[0032] Figure 15 For along Figure 2 A schematic diagram of a semiconductor device in the AA direction.

[0033] Figure 16 for Figure 1 The semiconductor device shown is a semiconductor process simulation and a simulation diagram from a device simulation tool.

[0034] Figure 17 for Figure 15 The semiconductor device shown is a semiconductor process simulation and a simulation diagram from a device simulation tool.

[0035] Label Explanation: 10. Substrate; 11. Gate; 12. Source terminal; 13. Drain terminal; 14. Substrate end; 15. Shallow trench isolation structure; 100. Substrate; 120. Buried layer; 130. Epitaxial layer; 140. Sacrificial layer; 150. Isolation structure; 160. Well region; 170. Body region; 180. Gate dielectric layer; 191. Gate material layer; 192. First photoresist layer; 190. Gate structure; 210. Source; 220. Drain; 230. Body end; 240. Sidewall structure; 250. Metal silicide layer; 101. High voltage well region; 102. Patterned photoresist layer; 103. Trench; 104. Pad oxide layer; 105. Pad nitride layer; 106. Photoresist layer. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0038] In the description of this specification, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this solution and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] Please see Figure 2 , Figure 11 and Figure 12As shown, the present invention provides a semiconductor device including a substrate 100, a buried layer 120, an epitaxial layer 130, a well region 160, a gate structure 190, a source 210, a drain 220, and an isolation structure 150. The substrate 100 has a recess, and the buried layer is disposed at least on the bottom and sidewalls of the recess. The substrate 100 and the well region 160 are of a first conductivity type, while the buried layer 120, the epitaxial layer 130, the source 210, and the drain 220 are of a second conductivity type, with the first and second conductivity types being opposite. The buried layer 120 is disposed on the bottom wall and side wall of the trench and on the surface of part of the substrate 100. The epitaxial layer 130 is disposed on the buried layer 120 and the substrate 100, and the doping concentration of the epitaxial layer 130 is less than that of the buried layer 120. The well region 160 is disposed at least in part of the epitaxial layer 130 on the trench. The gate structure 190 is disposed on the epitaxial layer 130 and covers part of the well region 160. The source 210 is disposed in the well region 160 on one side of the gate structure 190. The drain 220 is disposed in the epitaxial layer 130 on both sides of the gate structure 190 and is connected to the buried layer 120. The isolation structure 150 is disposed at least in the epitaxial layer 130 between the drain 220 and the source 210. By connecting the drain to the buried layer, when the semiconductor device is working, the lateral current movement from the source to the drain is suppressed by the blocking of the isolation structure, the attraction of the buried layer, and the isolation of the PN junction formed by the epitaxial layer and the well region. The current is pulled to the buried layer at the bottom of the epitaxial layer and then moves to the drain through the buried layer. This eliminates the impact of electrons on the gate dielectric layer, weakens the hot carrier injection effect, and improves the reliability of the semiconductor device.

[0040] Please see Figure 3 As shown, in one embodiment of the present invention, a substrate 100 is first provided. The substrate 100 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other III / V compound semiconductor materials. It also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanide-on-insulator, and germanium-on-insulator. In this embodiment, the substrate 100 is, for example, a silicon wafer substrate of a first conductivity type. A high-voltage well region 101 is formed on the substrate 100, and the high-voltage well region 101 is, for example, of a first conductivity type, such as P-type. In other embodiments, the types of the substrate 100 and the high-voltage well region 101 are selected according to the semiconductor device being fabricated.

[0041] Please see Figures 3 to 4As shown, in one embodiment of the present invention, a patterned photoresist layer 102 is formed on a substrate 100, exposing a portion of the substrate 100 at a central location for the location of a groove 103. Using the patterned photoresist layer 102 as a mask, etching is performed to remove the exposed portion of the substrate 100 to form the groove 103. The depth of the groove 103 is, for example, 1000 nm to 1500 nm. In this embodiment, for example, dry etching is used to form the groove 103. After etching, the patterned photoresist layer 102 is removed.

[0042] Please see Figures 4 to 5 As shown, in one embodiment of the present invention, after forming the groove 103, a buried layer 120 of a second conductivity type is formed at least on the surface of the substrate 100 exposed by the groove 103. For example, the buried layer is formed on the bottom wall and sidewalls of the groove 103, and on the substrate 100 on both sides of the groove 103. The buried layer 120 is formed, for example, within the high-voltage well region 101. In this embodiment, the buried layer 120 is formed, for example, by ion implantation. The implanted dopant ions are, for example, N-type ions such as phosphorus (P) or arsenic (As), and the doping concentration of the buried layer 120 is greater than the doping concentration of the high-voltage well region 101. The doping depth of the buried layer 120 is, for example, 30 nm to 40 nm, that is, the thickness of the buried layer 120 is, for example, 30 nm to 40 nm. By ion implantation, a buried layer 120 of uniform thickness is formed on a portion of the surface of the substrate 100 and on the surfaces of the bottom wall and sidewalls of the groove 103, improving the quality of the buried layer 120. In other embodiments, the buried layer 120 can also be formed by thermal diffusion or other methods. By etching the substrate to form grooves to expose the interior of the substrate, it is easier to prepare the buried layer, control the doping depth and concentration of the buried layer, and simplify the fabrication process.

[0043] Please see Figures 5 to 6As shown, in one embodiment of the present invention, after forming the buried layer 120, an epitaxial layer 130 is formed on the buried layer 120 and the substrate 100. The epitaxial layer 130 has a second conductivity type, and the doping concentration of the epitaxial layer 130 is, for example, less than the doping concentration of the buried layer 120, to provide voltage resistance and electron transfer. In this embodiment, the epitaxial layer 130 is formed, for example, by selective epitaxial growth. Specifically, the epitaxial growth gas source is, for example, one or a mixture of several of silane (SiH4), trichlorosilane (SiHCl3), silicon tetrachloride (SiCl4), or dichlorodihydrosilane (DCS), and for example, dichlorodihydrosilane. The epitaxial growth temperature is, for example, 900°C to 1100°C. During the formation process, a doping source, such as phosphine (PH3) or arsine (AsH3), is simultaneously introduced to form an epitaxial layer 130 of the second conductivity type. The doping concentration of the epitaxial layer 130 is controlled by controlling the amount of doping source introduced. In this embodiment, deposition is stopped after the epitaxial layer 130 in the groove 103 protrudes from the surface of the substrate 100.

[0044] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after forming the epitaxial layer 130, a sacrificial layer 140 is formed on the epitaxial layer. In this embodiment, the sacrificial layer 140 is, for example, a silicon oxide layer. The sacrificial layer 140 can be formed, for example, by a method such as high aspect ratio chemical vapor deposition (HARP-CVD). After depositing the silicon oxide layer, a planarization process such as chemical mechanical polishing (CMP) is used to remove part of the silicon oxide layer, making the surface of the silicon oxide layer flush, thus obtaining a sacrificial layer 140 with a smooth surface. In this embodiment, the thickness of the epitaxial layer 130 at the bottom of the groove 103 is a, and the thickness of the sacrificial layer 140 is b, wherein the value of a ranges, for example, from 1200nm to 1800nm, and the value of b ranges, for example, from 500nm to 1000nm.

[0045] Please see Figures 7 to 8 As shown, in one embodiment of the present invention, after the sacrificial layer 140 is formed, the sacrificial layer 140 and the epitaxial layer 130 are removed by a planarization process such as chemical mechanical polishing to form a flat epitaxial layer 130. In this embodiment, after planarization, the thickness of the epitaxial layer 130 at the bottom of the groove 103 is c, and the value of c is, for example, 1100nm~1600nm, that is, the epitaxial layer 130 covers the entire surface of the substrate 100. By forming a flat sacrificial layer 140 and then performing planarization on the epitaxial layer, a flat epitaxial layer 130 can be obtained, and the epitaxial layer 130 is less damaged in the planarization process, resulting in a high-quality epitaxial layer 130.

[0046] Please see Figures 8 to 9 As shown, in one embodiment of the present invention, after planarizing the epitaxial layer 130, a pad oxide layer 104 is formed on the epitaxial layer 130. The pad oxide layer 104 serves as a buffer layer to improve the stress between the epitaxial layer 130 and the subsequently formed pad nitride layer 105. The pad oxide layer 104 is, for example, a dense silicon oxide material, and the pad oxide layer 104 can be formed by any one of the following methods: dry oxygen oxidation, wet oxygen oxidation, or in-situ steam generation (ISSG). In this embodiment, the pad oxide layer 104 is formed, for example, by dry oxygen oxidation. Specifically, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced. The surface of the substrate 100 reacts with the oxygen at a high temperature to generate a dense pad oxide layer 104, and the generated pad oxide layer 104 has good quality. The pad oxide layer 104 is, for example, silicon oxide, and the thickness of the pad oxide layer 104 is, for example, 10 nm to 40 nm.

[0047] Please see Figure 9 As shown, in one embodiment of the present invention, a pad nitride layer 105 is formed on the pad oxide layer 104. The pad nitride layer 105 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. In this embodiment, the pad nitride layer 105 is, for example, silicon nitride, and can be formed, for example, by a method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the pad nitride layer 105 is, for example, 50 nm to 80 nm. By providing the pad nitride layer 105, the substrate 100 can be protected from the effects of planarization processes such as chemical mechanical polishing involved in the fabrication of the isolation structure 150. Furthermore, the pad nitride layer 105 can serve as a mask during the subsequent formation of the isolation structure, protecting the epitaxial layer 130 outside the isolation structure from damage when etching the epitaxial layer 130.

[0048] Please see Figures 9 to 10As shown, in one embodiment of the present invention, after forming the pad nitride layer 105, a photoresist layer 106 is formed on the pad nitride layer 105 to define the position of the isolation structure 150. Using the photoresist layer 106 as a mask, etching is performed to remove the pad nitride layer 105, pad oxide layer 104, part of the epitaxial layer 130, or the epitaxial layer 130 and part of the substrate 100 exposed by the photoresist layer 106, to form a trench. In this embodiment, for example, dry etching is used to form the trench (not shown in the figure). After etching, the epitaxial layer 130 is removed. Then, an insulating medium is deposited in the trench until the insulating medium in the trench protrudes from the surface of the pad nitride layer 105. The present invention does not limit the deposition method of the insulating medium. For example, high-density plasma chemical vapor deposition (HDP-CVD) or high aspect ratio chemical vapor deposition can be used to form a high-quality insulating medium. In this embodiment, the insulating medium is, for example, silicon oxide. In other embodiments, the insulating medium may be other insulating materials suitable for isolation.

[0049] Please see Figure 10 As shown, in one embodiment of the present invention, after depositing the insulating dielectric, the insulating dielectric is planarized, for example, using CMP to planarize the insulating dielectric. For example, grinding removes part of the insulating dielectric and part of the pad nitride layer 105, and then removing the pad nitride layer 105 to obtain the isolation structure 150. The present invention does not limit the method of removing the pad nitride layer 105, for example, dry etching, wet etching, or a combination of dry etching and wet etching can be used for removal. In this embodiment, for example, thermal phosphoric acid is used to remove the pad nitride layer 105 to form the isolation structure 150, wherein, on both sides of the semiconductor device, the formed isolation structure 150 extends from the surface of the epitaxial layer 130 into the high-voltage well region 101 to isolate adjacent semiconductor devices. An isolation structure 150 formed within a semiconductor device is located within an epitaxial layer 130, and the isolation structure 150 is at the bottom of the epitaxial layer 130, at a predetermined distance from the buried layer 120. That is, the depth of the isolation structure 150 formed within the semiconductor device is less than the thickness of the epitaxial layer 130 on the groove, so as to achieve high-precision electrical isolation and improve device reliability.

[0050] Please see Figures 10 to 11As shown, in one embodiment of the present invention, after forming the isolation structure 150, a well region 160 and a body region 170 with a first conductivity type are formed side-by-side within the epitaxial layer 130. Specifically, a first patterned photoresist layer (not shown) is formed on the pad oxide layer 104 and the isolation structure 150 to locate the position of the well region 160. Using the first patterned photoresist layer as a mask and the pad oxide layer 104 as an ion implantation buffer layer, ion implantation is performed to form the well region 160 at least within a portion of the epitaxial layer 130 on the groove. In this embodiment, the doped ions implanted in the well region 160 are, for example, p-type ions such as boron (B) or gallium (Ga), and the doping concentration of the well region 160 is greater than the doping concentration of the epitaxial layer 130, while the doping depth of the well region 160 is less than or equal to the depth of the isolation structure 150. After forming the well region 160, the first patterned photoresist layer is removed by ashing or wet etching. A second patterned photoresist layer (not shown) is formed on the substrate 100 and the isolation structure 150 to locate the body region 170. Using the second patterned photoresist layer as a mask and the pad oxide layer 104 as an ion implantation buffer layer, ion implantation is performed to form the body region 170. In this embodiment, the doped ions implanted in the body region 170 are, for example, p-type ions such as boron or gallium. That is, the doping type of the body region 170 is opposite to the doping type of the epitaxial layer 130, and the doping concentration of the body region 170 is greater than that of the epitaxial layer 130 but less than that of the well region 160, to prevent abrupt junctions between the subsequently formed body end and the epitaxial layer 130. Abrupt junctions reduce the breakdown voltage of the device. The doping depth of the body region 170 is, for example, greater than or equal to the doping depth of the isolation structure 150. After forming the body region 170, the second patterned photoresist layer is removed by ashing or wet etching. The formation order of the well region 160 and the body region 170 is not specifically limited. By retaining the pad oxide layer 104 formed during the formation of the isolation structure 150, damage to the substrate 100 during ion implantation is reduced.

[0051] Please see Figure 11 As shown, in one embodiment of the present invention, three mutually spaced isolation structures 150 are provided within the epitaxial layer 130 on the groove. A well region 160 is provided within the epitaxial layer 130 between two adjacent isolation structures 150, with one side of the well region 160 being adjacent to the isolation structure 150 and the other side being spaced apart from the isolation structure 150. A body region 170 is provided within the epitaxial layer 130 between two adjacent isolation structures 150 and is isolated from the well region 160 by the isolation structure 150. The body region 170 is adjacent to the isolation structures on both sides to form a body end.

[0052] Please see Figures 11 to 12As shown, in one embodiment of the present invention, after forming the well region 160 and the body region 170, the pad oxide layer 104 is removed, for example by dilute hydrofluoric acid. During the removal process, a portion of the isolation structure 150 is simultaneously removed. The isolation structure 150 is flush with the surfaces of the epitaxial layers 130 on both sides. A gate dielectric layer 180 is formed on the epitaxial layer 130 and the isolation structure 150. The gate dielectric layer 180 is, for example, a silicon oxide layer, and is formed by deposition methods such as chemical vapor deposition, physical vapor deposition (PVD), or atomic layer deposition (ALD). The thickness of the gate dielectric layer 180 is, for example, 8 nm to 50 nm. A gate material layer 191 is formed on the gate dielectric layer 180, and the gate material layer 191 is, for example, a polysilicon layer. In this embodiment, the gate material layer 191 is prepared by methods such as chemical vapor deposition, and the thickness of the gate material layer 191 is, for example, 50 nm to 200 nm. A first photoresist layer 192 is formed on the gate material layer 191 to position the gate structure.

[0053] Please see Figures 12 to 13 As shown, in one embodiment of the present invention, using the first photoresist layer 192 as a mask and the gate dielectric layer 180 as an etch stop layer, the gate material layer 191 is etched, for example, by a dry etching process, a wet etching process, or a combination of dry and wet etching processes, and the remaining gate material layer 191 is defined as the gate structure 190. The gate structure 190 is disposed on the epitaxial layer 130 and covers a portion of the isolation structure 150 and a portion of the well region 160 on the side of the body region 170 near the well region 160.

[0054] Please see Figures 13 to 14As shown, in one embodiment of the present invention, after forming the gate structure 190, a source 210 is formed in the well region 160, a drain 220 is formed in the epitaxial layer 130, and a bulk 230 is formed in the body region 170. In this embodiment, the source 210 and the drain 220 are formed in the same ion implantation process. Specifically, a patterned photoresist layer (not shown) is re-formed on the gate dielectric layer 180. The patterned photoresist layer exposes the well region 160 on one side of the gate structure 190 to locate the source 210, and also exposes a portion of the epitaxial layer 130 outside the well region 160 and the body region 170 to locate the drain 220. Using the patterned photoresist layer as a mask and the gate dielectric layer 180 as an ion implantation buffer layer, ion implantation is performed to form the source 210 and the drain 220. The doping type of the source 210 and the drain 220 is the same as that of the epitaxial layer 130. In this embodiment, the doped ions of the source 210 and drain 220 are, for example, N-type ions such as phosphorus or arsenic, and the doping concentration of the source 210 and drain 220 is greater than the doping concentration of the well region 160, and the doping concentration of the source 210 and drain 220 is equal to the doping concentration of the buried layer 120. The source 210 is located within the well region 160 on one side of the gate structure 190, and the doping depth of the source 210 is less than the doping depth of the well region 160. The source 210 partially overlaps with the gate structure 190. The drain 220 is located within the epitaxial layers 130 on both sides of the gate structure 190. The drain 220 is disposed within the epitaxial layers 130 on the side of the source 210 away from the body region 170 and on the side of the body region 170 away from the source 210. An isolation structure 150 is provided between the drain 220, the source 210, and the body region 170. The drain 220 is in contact with the isolation structure 150 at the edge of the semiconductor device. The doping depth of the drain 220 is equal to the thickness of the epitaxial layer 130 on the buried layer 120 outside the trench, thus connecting the drain 220 to the buried layer 120. After forming the source 210 and drain 220, the patterned photoresist layer is removed by ashing or wet etching. In other embodiments, the source 210 and drain 220 can also be fabricated in steps; this application does not impose specific limitations.

[0055] Please see Figure 14As shown, in one embodiment of the present invention, after forming the source 210 and drain 220, a body terminal 230 is formed within the body region 170. Specifically, a patterned photoresist layer (not shown) is re-formed on the gate dielectric layer 180, exposing the surface of the body region 170 to locate the position of the body terminal 230. Using the patterned photoresist layer as a mask and the gate dielectric layer 180 as an ion implantation buffer layer, ion implantation is performed to form the body terminal 230. The doping type of the body terminal 230 is the same as that of the body region 170. In this embodiment, the doped ions of the body terminal 230 are, for example, p-type ions such as boron or gallium, and the doping concentration of the body terminal 230 is greater than that of the body region 170. The doping depth of the body terminal 230 is, for example, the same as that of the drain 220. The body terminal 230 is in contact with the isolation structures 150 on both sides. This application does not limit the fabrication steps of the source 210, drain 220 and body 230. Other fabrication steps may be used in other embodiments, and this application does not impose specific limitations.

[0056] Please see Figures 14 to 15 As shown, in one embodiment of the present invention, after forming the body end 230, sidewall structures 240 are formed on both sides of the gate structure 190. The sidewall structures 240 are, for example, a stacked structure, or include, for example, stacked silicon oxide-silicon nitride-silicon oxide-silicon nitride layers, thereby improving the stability of the sidewall structures 240. In other embodiments, the sidewall structures 240 are, for example, other stacked structures. By setting the sidewall structures 240 as a stacked structure, the stability of the gate structure is improved. During the formation of the sidewall structures 240, for example, the gate dielectric layer 180 in areas other than the gate structure 190 and the sidewall structures 240 is removed simultaneously. Next, a metal layer (not shown in the figure) is formed on the gate structure 190, the source 210, the drain 220, and the body terminal 230 outside the gate structure 190. Through heat treatment, the metal reacts with the exposed silicon to form a metal silicide layer 250 on the gate structure 190, the source 210, the drain 220, and the body terminal 230 outside the gate structure 190. This layer is used to improve the contact resistance of the conductive plugs subsequently formed on the source and drain. After the metal silicide layer 250 is formed, the conductive plugs and metal wiring layers are fabricated, which will not be described in detail here.

[0057] Please see Figure 15As shown, in one embodiment of the present invention, by forming a lower-elongated buried layer 120 and connecting the buried layer 120 to the drain 220, when the semiconductor device is working, under the obstruction of the isolation structure 150, the attraction of the buried layer 120, and the isolation of the PN junction formed by the epitaxial layer 130 and the well region 160, the current movement from the lateral source 210 to the drain 220 is suppressed. The current is pulled to the buried layer 120 at the bottom of the epitaxial layer 130, and then moves to the drain 220 through the buried layer 120. This eliminates the impact of electrons on the gate dielectric layer 180, weakens the hot carrier injection effect, and improves the reliability of the semiconductor device.

[0058] Please see Figures 16 to 17 As shown, in one embodiment of the present invention, respectively for Figure 1 and Figure 15 The semiconductor device shown was simulated using semiconductor process simulation and device simulation tools (Technology Computer Aided Design, TCAD). Figure 1 In conventional semiconductor devices, the electric field of the gate dielectric layer is strong near the drain, enhancing the hot carrier injection effect. The semiconductor device obtained in this application has a more uniform electric field distribution, optimizing the heat distribution during device operation. Furthermore, the peak electric field near the drain is weakened, preventing a large peak electric field from appearing at the channel. This signifies a reduction in the hot carrier injection effect. This structure protects the thin gate dielectric layer, improving device reliability. Simulation results also show… Figure 1 The substrate current (I) of the semiconductor device shown sub The value is 1.58 × 10 -2 A, obtained in this application Figure 15 The substrate current of the semiconductor device shown is 1.957 × 10⁻⁶. -6 A. The substrate current is reduced by nearly four orders of magnitude, the hot carrier injection effect is reduced, and the device reliability is greatly improved. The heat distribution of the semiconductor device is uniformly distributed inside the drain and buried layer, which will not cause excessive heat at the drain and improve the device durability.

[0059] In summary, this invention provides a semiconductor device and its fabrication method. By improving the structure and fabrication method of the semiconductor device, the unexpected technical effect of this application is that it can suppress the lateral movement of the source-drain current, eliminate the impact of electrons on the gate dielectric layer, and weaken the hot carrier injection effect, thereby improving the reliability of the semiconductor device. Simultaneously, the heat distribution of the semiconductor device is uniformly distributed within the space surrounded by the drain and buried layer, preventing excessive heat at the drain and improving device durability.

[0060] The above description of the embodiments shown in this invention (including the content set forth in the abstract of the specification) is not intended to be an exhaustive enumeration or to limit the invention to the precise forms disclosed herein. Although specific embodiments and examples of the invention have been described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the invention, as will be recognized and understood by those skilled in the art. As indicated, these modifications can be made to the invention in accordance with the above description of the embodiments described herein, and such modifications will be within the spirit and scope of the invention.

[0061] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by specific combinations of the above-described technical features. It should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application. Except for the technical features described in the specification, the remaining technical features are known to those skilled in the art. To highlight the innovative features of this invention, the remaining technical features will not be described further here.

Claims

1. A semiconductor device, characterized in that, include: A substrate of a first conductivity type, wherein a groove is provided in the substrate; A second type of conductive buried layer is provided at least on the bottom wall and side wall of the groove; An epitaxial layer of a second conductivity type is disposed on the buried layer and the substrate, wherein the doping concentration of the epitaxial layer is less than the doping concentration of the buried layer; A well region of a first conductivity type is disposed at least within a portion of the epitaxial layer on the groove; A gate structure is disposed on the epitaxial layer and covers a portion of the well region; A source of the second conductivity type is disposed in the well region on one side of the gate structure; as well as A drain of the second conductivity type is disposed in the epitaxial layer on both sides of the gate structure, and the drain is connected to the buried layer; An isolation structure is disposed at least within the epitaxial layer between the drain and the source, wherein the isolation structure is located at the bottom of the epitaxial layer at a predetermined distance from the buried layer, and the doping depth of the well region is less than or equal to the depth of the isolation structure.

2. The semiconductor device according to claim 1, characterized in that, The doping type of the drain electrode is the same as that of the buried layer, and the doping concentration of the drain electrode is the same as that of the buried layer.

3. The semiconductor device according to claim 1, characterized in that, The doping concentration of the well region is greater than that of the epitaxial layer, and the doping concentration of the source is greater than that of the well region.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a body region, which is disposed at least in the epitaxial layer on the side of the gate structure away from the well region, and the isolation structure is disposed on both sides of the body region.

5. The semiconductor device according to claim 4, characterized in that, The doping type of the body region is opposite to that of the epitaxial layer, and the doping concentration of the body region is greater than that of the epitaxial layer.

6. The semiconductor device according to claim 4, characterized in that, A body terminal is provided within the body region, and the doping type of the body terminal is the same as that of the body region; the doping concentration of the body terminal is greater than that of the body region, and the doping depth of the body terminal is equal to that of the drain electrode.

7. The semiconductor device according to claim 4, characterized in that, The drain is disposed in the epitaxial layer on the side of the source away from the body region and in the epitaxial layer on the side of the body region away from the source. An isolation structure is provided between the drain, the source, and the body region.

8. A method for fabricating a semiconductor device, characterized in that, include: A substrate of a first conductivity type is provided, and a groove is formed in the substrate; At least a second type of conductive buried layer is formed on the bottom wall and side wall of the groove; An epitaxial layer of a second conductivity type is formed on the buried layer and the substrate, wherein the doping concentration of the epitaxial layer is less than that of the buried layer; An isolation structure is formed at least within the epitaxial layer; A well region of a first conductivity type is formed within at least a portion of the epitaxial layer on the groove; A gate structure is formed on the epitaxial layer, the gate structure covering a portion of the well region; A source of a second conductivity type is formed in the well region on one side of the gate structure; as well as A drain of a second conductivity type is formed in the epitaxial layer on both sides of the gate structure, and the drain is connected to the buried layer; and the isolation structure is provided in the epitaxial layer between the drain and the source. The isolation structure is located at the bottom of the epitaxial layer, at a predetermined distance from the buried layer, and the doping depth of the well region is less than or equal to the depth of the isolation structure.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The method for fabricating the buried layer and the epitaxial layer includes: A patterned photoresist layer is formed on the substrate, and the substrate is etched using the patterned photoresist layer as a mask to form the groove; Remove the patterned photoresist layer and form the buried layer at least on the bottom and sidewalls of the groove by ion implantation; An epitaxial layer is formed on the buried layer and the substrate; A sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is planarized; and Planarize the sacrificial layer and the epitaxial layer.

Images