Hybrid transistor device and method of making the same

Abstract

This application belongs to the field of power semiconductor technology, specifically relating to a hybrid transistor device and its fabrication method. The hybrid transistor device includes a silicon carbide semiconductor substrate configured to withstand a blocking voltage in the device off state and provide a vertical current path when the device is forward-biased; a shielding layer with a conductivity type opposite to that of the silicon carbide semiconductor substrate; at least one gallium nitride heterostructure configured to form a conductive channel; at least one floating conductive structure configured to provide a vertical transport path for electrons to be injected from the gallium nitride heterostructure into the silicon carbide semiconductor substrate when the device is forward-biased; at least one gate structure and at least one source structure. This application effectively manages the electric field distribution at the SiC / GaN heterostructure interface in a monolithic integrated structure, while achieving high withstand voltage, low on-resistance, and high reliability.

Description

Technical Field

[0001] This application belongs to the field of power semiconductor technology, specifically relating to a hybrid transistor device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) and gallium nitride (GaN), as wide-bandgap semiconductor materials, are widely used in power devices. However, while single silicon carbide MOSFET devices have high voltage withstand capability, they also suffer from relatively high on-resistance; while single gallium nitride HEMT devices have extremely low on-resistance and extremely high switching speed, they also suffer from poor high-voltage reliability.

[0003] To combine the advantages of both, a proposed technology integrates SiC and GaN, specifically by directly epitaxially growing a GaN channel layer on a SiC substrate to form a simple HEMT structure. However, this approach lacks an integrated electric field management structure within the device, leading to severe electric field concentration at the AlGaN / GaN heterojunction during high-voltage shutdown. This results in a device breakdown voltage far below the theoretical breakdown voltage of SiC, leading to poor reliability.

[0004] Therefore, how to effectively manage the electric field distribution at the SiC and GaN heterojunction interface in a monolithic integrated structure, while achieving high withstand voltage, low on-resistance, and high reliability, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a hybrid transistor device and its fabrication method. Through the synergistic operation of a silicon carbide semiconductor substrate, a shielding layer, a gallium nitride heterostructure, and a floating conductive structure, this application effectively manages the electric field distribution at the SiC and GaN heterostructure interface in a monolithic integrated structure, while achieving high withstand voltage, low on-resistance, and high reliability.

[0006] In a first aspect, this application provides a hybrid transistor device, comprising: a silicon carbide semiconductor substrate configured to withstand a blocking voltage in a device off state and provide a vertical current path in a device forward conduction state; a shielding layer disposed on the silicon carbide semiconductor substrate, wherein the shielding layer has a conductivity type opposite to that of the silicon carbide semiconductor substrate; at least one gallium nitride heterostructure disposed on the silicon carbide semiconductor substrate, such that the shielding layer is located between the silicon carbide semiconductor substrate and the gallium nitride heterostructure; the gallium nitride heterostructure is configured to form a conductive channel; and at least one floating conductive structure disposed on the silicon carbide semiconductor substrate. The device is situated on a conductor substrate and electrically connected to the at least one gallium nitride heterostructure; the floating conductive structure is configured to provide a vertical transport path for electrons to be injected from the gallium nitride heterostructure into the silicon carbide semiconductor substrate when the device is forward-biased; at least one gate structure is disposed on the gallium nitride heterostructure; at least one source structure is disposed on the shielding layer and electrically connected to the shielding layer; wherein the shielding layer is configured to form a depletion layer together with the silicon carbide semiconductor substrate when the device is off, and to shield the electric field coupling between the silicon carbide semiconductor substrate and the gallium nitride heterostructure.

[0007] Secondly, this application provides a method for fabricating a hybrid transistor device, the method comprising: providing an N+ type silicon carbide substrate; epitaxially growing an N-type silicon carbide buffer layer on the N+ type silicon carbide substrate; forming a composite withstand voltage layer on the N-type silicon carbide buffer layer; forming at least one P-type silicon carbide shielding region and at least one N+ type silicon carbide source region within the composite withstand voltage layer; epitaxially growing a gallium nitride channel layer and an aluminum gallium nitride barrier layer on the P-type silicon carbide shielding region; forming a P-type gallium nitride gate layer on the aluminum gallium nitride barrier layer; and forming an interlayer dielectric layer covering the P-type gallium nitride gate. A portion of the electrode layer, the aluminum gallium nitride barrier layer, and the composite withstand voltage layer are formed; the interlayer dielectric layer is etched to form contact holes exposing the P-type silicon carbide shielding region, the P-type gallium nitride gate layer, and the N+ type silicon carbide source region; a metal layer is formed in the contact holes and on the interlayer dielectric layer, and the metal layer is patterned to form a metal source electrode located on the P-type silicon carbide shielding region, a metal gate electrode located on the P-type gallium nitride gate layer, and a metal floating electrode located on the N+ type silicon carbide source region, respectively; a metal drain electrode is formed on the back side of the N+ type silicon carbide substrate.

[0008] The technical solution provided in this application has at least the following beneficial effects:

[0009] (1) This application utilizes a silicon carbide semiconductor substrate to withstand the blocking voltage, uses a gallium nitride heterostructure to form a high-mobility conductive channel, and forms a depletion layer together with the silicon carbide semiconductor substrate in the off state through a shielding layer to withstand the high voltage. Thus, the high critical breakdown field strength of silicon carbide material and the high mobility of two-dimensional electron gas of gallium nitride material are synergistically utilized in the same device, solving the problems of high on-resistance of single SiC MOSFET and insufficient voltage withstand capability of single GaN HEMT, and achieving both high voltage blocking capability and extremely low on-resistance.

[0010] (2) In this application, a shielding layer is disposed between the silicon carbide semiconductor substrate and the gallium nitride heterostructure, and the source structure is electrically connected to the shielding layer. In the off state, the shielding layer not only forms a depletion layer together with the silicon carbide semiconductor substrate, but also physically isolates the electric field coupling between the gate and the drain, significantly reducing the Miller capacitance (Cgd). At the same time, the shielding layer transfers the high electric field peak from the fragile AlGaN / GaN heterostructure interface to the robust silicon carbide drift region, avoiding electric field concentration at the heterostructure interface. As a result, the switching speed of the device is greatly improved, the switching loss is significantly reduced, and the breakdown voltage and long-term reliability are fundamentally improved, solving the problems of easy breakdown and poor reliability of the heterostructure interface in the existing simple epitaxial stacking scheme.

[0011] (3) By introducing a floating conductive structure, this application achieves efficient vertical injection of electrons from the transverse two-dimensional electron gas channel to the longitudinal silicon carbide drift region, solving the bottleneck problem of electron transport between heterogeneous material interfaces. This structure does not require external bias, does not increase static power consumption, and is compatible with existing processes, further reducing the on-resistance of the device and improving forward conduction characteristics.

[0012] (4) This application integrates a silicon carbide semiconductor substrate, a shielding layer, a gallium nitride heterostructure, a floating conductive structure, a gate structure, a source structure, and a drain structure into a single chip to form a vertically conductive hybrid transistor device. This monolithic integration scheme eliminates the parasitic inductance, additional packaging area, and interconnection losses caused by parallel or external series connection of discrete devices, and eliminates the need for external clamping circuits or complex gate drive auxiliary networks. As a result, the size, weight, and design complexity of the power system are significantly reduced, while the power density and system reliability are improved, solving the problems of large parasitic parameters, low integration density, and complex peripheral circuits in existing hybrid integration schemes. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0014] Figure 1 The diagram shown is a structural schematic of the first hybrid transistor device provided in the embodiments of this application.

[0015] Figure 2 The diagram shown is a structural schematic of a second hybrid transistor device provided in an embodiment of this application.

[0016] Figure 3 The diagram shown is a structural schematic of the third hybrid transistor device provided in the embodiments of this application.

[0017] Figure 4 The diagram shown is a structural schematic of the fourth hybrid transistor device provided in the embodiments of this application.

[0018] Figure 5 The diagram shown is a structural schematic of the fifth hybrid transistor device provided in the embodiments of this application.

[0019] Figure 6 The diagram shown is a structural schematic of the sixth hybrid transistor device provided in the embodiments of this application.

[0020] Figure 7 The diagram shown is a flowchart illustrating the fabrication method of the first hybrid transistor device provided in this application embodiment.

[0021] Figure 8 The diagram shown is a flowchart illustrating a second method for fabricating a hybrid transistor device according to an embodiment of this application.

[0022] Explanation of reference numerals in the attached figures: 100. Hybrid transistor device; 110. Silicon carbide semiconductor substrate; 120. Shielding layer; 130. Gallium nitride heterostructure; 140. Gate structure; 150. Source structure; 160. Floating conductive structure; 170. Interlayer dielectric layer; 111. Metal drain; 112. N+ type silicon carbide substrate; 113. N- type silicon carbide buffer layer; 114. N- type silicon carbide drift region; 115. N+ type source region; 131. Gallium nitride channel layer; 132. Aluminum gallium nitride barrier layer; 141. P-type gallium nitride gate layer; 142. Metal gate; 151. First contact hole; 152. Metal source; 161. Second contact hole; 162. Metal floating electrode; 116. Composite withstand voltage layer; 1161. P-type vertical conductive region; 1162. N-type vertical conductive region; 1163. P-type embedded blocking region; 1164. N-type charge storage layer; 1165. N-type auxiliary layer; 1166. Barrier modulation layer. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0024] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0025] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0026] Silicon carbide (SiC) and gallium nitride (GaN), as wide-bandgap semiconductor materials, are widely used in power devices. However, power devices made from a single material all have inherent technical bottlenecks: (1) Bottlenecks of single SiC MOSFET: SiC material has high breakdown field strength and high thermal conductivity, but the channel mobility of SiC MOSFET is relatively low, which means that the on-resistance per unit area (Rds(on)×A) still has room for optimization. In addition, the reverse recovery charge (Qrr) of the body diode of traditional SiC MOSFET is large, which will bring significant switching losses and electromagnetic interference (EMI) problems under hard switching conditions.

[0027] (2) Bottlenecks of single GaN HEMTs: GaN materials have extremely high two-dimensional electron gas (2DEG) mobility, enabling extremely low on-resistance and extremely high switching speeds. However, GaN high electron mobility transistors (HEMTs) are inherently depletion-mode (normally on) devices, and achieving enhancement-mode (normally off) operation and a stable threshold voltage (Vth) has always been a technical challenge. At the same time, GaN devices lack a good body diode, have high reverse conduction voltage drop, and their high-voltage reliability still needs further improvement.

[0028] To overcome the performance limitations of single materials, related technologies have attempted to integrate SiC and GaN. However, the inventors of this application have discovered that existing solutions all suffer from the following problems: Option 1: Parallel connection of discrete components: A SiC MOSFET is connected in parallel with an external SiC or GaN Schottky diode inside the module. While this option can utilize the fast reverse recovery characteristics of the Schottky diode, it introduces additional package parasitic inductance, occupies a larger chip area, and cannot achieve optimal performance at high frequencies.

[0029] Option 2: Simple Epitaxial Stacking: GaN material is epitaxially grown on a SiC substrate to form a simple HEMT structure. This option does not integrate an electric field management structure inside the device, resulting in severe electric field concentration at the AlGaN / GaN heterojunction under high voltage. The device breakdown voltage is far lower than the theoretical value, leading to poor long-term reliability.

[0030] Option 3, P-GaN gate HEMT: Some GaN devices introduce a P-type GaN (P-GaN) gate to achieve enhancement-mode operation, but the AlGaN / GaN heterostructure underneath still faces the problem of electric field peak under high voltage, and lacks the pinch-off design of the JFET region (junction field-effect transistor region) in SiC MOSFET, resulting in unsatisfactory turn-off characteristics.

[0031] To address the problems in the aforementioned related technologies, the inventors of this application have developed a hybrid transistor device. The core of this device lies in the monolithic integration of a silicon carbide (SiC) semiconductor substrate and a gallium nitride (GaN)-based heterogeneous component, with a shielding layer placed between them. This achieves high withstand voltage, low on-resistance, and excellent switching characteristics. Specific embodiments include the following: Figure 1 The diagram shown is a structural schematic of the first hybrid transistor device 100 provided in an embodiment of this application; as shown Figure 1 As shown, the hybrid transistor device 100 of this embodiment includes a silicon carbide semiconductor substrate 110, a shielding layer 120, at least one gallium nitride heterostructure 130, at least one floating conductive structure 160, at least one gate structure 140 and at least one source structure 150.

[0032] In this embodiment, the silicon carbide semiconductor substrate 110 is configured to withstand a blocking voltage in the device off state and provide a vertical current path when the device is forward-biased. Specifically, the silicon carbide semiconductor substrate 110 includes at least one N-type silicon carbide drift region and a metal drain. Because silicon carbide has an extremely high critical breakdown field strength, when the hybrid transistor device 100 (hereinafter referred to as the device) is in the off state (i.e., the gate voltage is below the threshold voltage and a high voltage is applied to the drain), the drift region can withstand the high voltage applied from the drain, and the depletion layer expands within the drift region, thereby blocking the current. Simultaneously, when the device is forward-biased, electrons are injected from the source through the channel into the drift region and flow vertically towards the bottom drain, forming a low-resistance vertical current path. The high thermal conductivity of silicon carbide also facilitates device heat dissipation and improves high-temperature reliability.

[0033] In this embodiment, the shielding layer 120 is disposed on the upper surface of the silicon carbide semiconductor substrate 110, and its conductivity type is opposite to that of the silicon carbide semiconductor substrate 110. For example, when the silicon carbide semiconductor substrate 110 is N-type, the shielding layer 120 is P-type.

[0034] Furthermore, the shielding layer 120 is configured to form a depletion layer together with the silicon carbide semiconductor substrate 110 in the device off state, and to shield the electric field coupling between the silicon carbide semiconductor substrate 110 and the gallium nitride heterostructure 130. Specifically, in the off state, the shielding layer 120 forms a reverse-biased PN junction with the underlying silicon carbide drift region. The depletion layer mainly extends within the drift region, bearing most of the blocking voltage. More importantly, the shielding layer 120 acts as an electric field buffer layer, transferring the high electric field peak point from the gallium nitride heterostructure interface to the interior of the silicon carbide drift region, thereby achieving electric field management of the heterostructure interface, protecting the heterostructure from high electric field damage, and significantly improving the device's breakdown voltage and long-term reliability.

[0035] Furthermore, since the shielding layer 120 is located between the gate and the drain and is electrically connected to the source, it plays an electrostatic shielding role, which greatly reduces the capacitive coupling between the gate and the drain, that is, reduces the Miller capacitance (Cgd), thereby enabling the device to achieve faster switching speed and lower switching losses.

[0036] like Figure 1As shown, in this embodiment, the gallium nitride heterostructure 130 is disposed on a silicon carbide semiconductor substrate 110, and its position is such that the shielding layer 120 is located between the silicon carbide semiconductor substrate 110 and the gallium nitride heterostructure 130; the gallium nitride heterostructure 130 is configured to form a conductive channel. Typically, the gallium nitride heterostructure 130 includes a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer. Due to the different band gaps of the two materials, a high-concentration two-dimensional electron gas (2DEG) is formed at the interface. This 2DEG has extremely high electron mobility, providing the device with extremely low on-resistance. When a positive voltage is applied to the gate, the 2DEG channel turns on, and electrons can be transported laterally rapidly; when the gate voltage is below the threshold voltage, the channel is depleted, and the device turns off. The lateral conductivity of this component complements the vertical breakdown voltage of the silicon carbide substrate, achieving an ideal combination of high breakdown voltage and low resistance.

[0037] In this embodiment, the floating conductive structure 160 is disposed on the silicon carbide semiconductor substrate 110 and electrically connected to the gallium nitride heterostructure 130. One floating conductive structure 160 corresponds to one gallium nitride heterostructure 130. Specifically, the floating conductive structure 160 forms an ohmic contact with the aluminum gallium nitride barrier layer or gallium nitride channel layer in the gallium nitride heterostructure 130. Simultaneously, the floating conductive structure 160 is also electrically connected to the heavily doped source region (i.e., the N+ type source region) inside the silicon carbide semiconductor substrate 110. The floating conductive structure 160 is not connected to any fixed potential (not grounded, not connected to power or signal lines); its potential is determined by the potential of the semiconductor layers it contacts, and it does not output or receive control signals externally.

[0038] The floating conductive structure 160 is configured to provide a vertical transport path for electrons from the gallium nitride heterostructure 130 into the silicon carbide semiconductor substrate 110 when the device is forward-biased. The specific operating principle will be explained in detail in the operating principle section below.

[0039] like Figure 1 As shown, in this embodiment, the gate structure 140 is disposed on the gallium nitride heterostructure 130 and is mainly used to control the conduction and cutoff of the conductive channel in the gallium nitride heterostructure 130. When the gate voltage applied to the gate structure 140 is higher than the threshold voltage, the channel is turned on; when it is lower than the threshold voltage, the channel is turned off.

[0040] like Figure 1As shown, in this embodiment, the source structure 150 is disposed on top of the shielding layer 120 and electrically connected to the shielding layer 120. The source structure 150 serves as the main current output terminal of the device; during forward conduction, electrons enter the 2DEG channel of the gallium nitride heterostructure 130 from the source structure 150. The electrical connection between the source structure 150 and the shielding layer 120 fixes the shielding layer 120 to the source potential (typically ground potential), thereby enabling it to effectively absorb the gate electric field lines and reduce Miller capacitance.

[0041] It is worth noting that the descriptions of at least one gallium nitride heterostructure 130, at least one floating conductive structure 160, at least one gate structure 140, and at least one source structure 150 in this embodiment refer to the fact that the hybrid transistor device 100 may include one or more corresponding components and structures. Specifically: (1) When it contains one: such as Figure 2 As shown, the device has a single conductive unit. A gallium nitride heterostructure 130 is disposed above the shielding layer 120, with a gate structure 140 correspondingly disposed above this component. A source structure 150 is disposed above the shielding layer 120, and a floating conductive structure 160 is disposed on one side of the gallium nitride heterostructure 130, connecting this component to the silicon carbide source region below. This single-unit structure is suitable for low-current applications or as a basic device unit.

[0042] (2) When it contains two: such as Figure 1 As shown, the device can have symmetrical dual-conducting units. For example, two symmetrical gallium nitride heterostructures 130 are disposed above the shielding layer 120, each with a gate structure 140 disposed above it, and the two gate structures 140 are electrically connected to each other. The two gallium nitride heterostructures 130 share a source structure 150. A floating conductive structure 160 is disposed on the outside of each gallium nitride heterostructure 130, which injects electrons from the corresponding component into its respective source region. The two floating conductive structures 160 are independent of each other and are not connected to an external potential. This dual-unit structure can improve current handling capability without significantly increasing the chip area, and the symmetrical layout is conducive to uniform electric field distribution.

[0043] Similarly, depending on the actual current level and layout requirements, it can be expanded into more units. These units share the same silicon carbide semiconductor substrate 110 and shielding layer 120. The shielding layer 120 can be composed of multiple shielding areas, each shielding area corresponding to a source structure 150, two gallium nitride heterostructures 130, and two floating conductive structures 160. At the same time, each source structure 150 needs to be electrically connected to each other, and each gate structure 140 also needs to be electrically connected to each other. Examples will not be given here.

[0044] The specific working principle of the hybrid transistor device 100 in this embodiment is as follows: (1) In the on-state: A forward bias voltage higher than the threshold voltage is applied to the gate structure 140, and the two-dimensional electron gas channel in the gallium nitride heterostructure 130 is opened. Electrons enter the 2DEG channel from the source structure 150 and are transported rapidly in the lateral direction. When the electrons reach the contact area between the gallium nitride heterostructure 130 and the floating conductive structure 160, since the floating conductive structure 160 is a low-resistance metal or conductive material and is not connected to any fixed potential, the electrons can be smoothly injected into the N+ type source region in the silicon carbide semiconductor substrate 110 through the floating conductive structure 160. This source region and the drift region of the silicon carbide semiconductor substrate 110 form a low-resistance path, and the electrons are then injected vertically downward into the drift region, eventually flowing to the drain at the bottom. In this process, the silicon carbide substrate provides high withstand voltage support, the gallium nitride channel provides a low-resistance path, and the floating conductive structure, as a key bridge for vertical electron injection, jointly achieves low conduction loss.

[0045] (2) In the off state: the gate voltage is lower than the threshold voltage, and the 2DEG channel is depleted. At the same time, a high voltage is applied to the drain, and the PN junction formed by the shielding layer 120 and the silicon carbide drift region is reverse biased. The depletion layer expands within the drift region to withstand the voltage. The shielding layer 120 also transfers the high electric field peak from the heterostructure interface to the silicon carbide body, protecting the gallium nitride heterostructure 130, and isolating the gate and drain electric fields, reducing Miller capacitance, thereby achieving high withstand voltage, low switching loss and high reliability.

[0046] It is worth noting that without the floating conductive structure 160, direct injection of electrons from the gallium nitride heterostructure 130 (lateral channel) into the silicon carbide semiconductor substrate 110 (vertical drift region) would face significant potential barriers and interface defects, resulting in low injection efficiency and increased on-resistance. The floating conductive structure 160, acting as a low-resistance springboard, effectively bridges the electron transport between the two different semiconductor materials (gallium nitride and silicon carbide), ensuring a smooth vertical current path and thus fully leveraging the advantages of the low resistance of the gallium nitride channel and the high voltage withstand capability of the silicon carbide substrate.

[0047] In summary, the hybrid transistor device 100 provided in this application has at least the following beneficial effects: (1) This application utilizes a silicon carbide semiconductor substrate 110 to withstand the blocking voltage, and a gallium nitride heterostructure 130 to form a high-mobility conductive channel. In the off state, the shielding layer 120 and the silicon carbide semiconductor substrate 110 together form a depletion layer to withstand the high voltage. Thus, the high critical breakdown field strength of silicon carbide and the high mobility of two-dimensional electron gas of gallium nitride are synergistically utilized in the same device, solving the problems of high on-resistance of single SiC MOSFET and insufficient voltage withstand capability of single GaN HEMT, and achieving both high voltage blocking capability and extremely low on-resistance.

[0048] (2) In this application, a shielding layer 120 is disposed between the silicon carbide semiconductor substrate 110 and the gallium nitride heterostructure 130, and the source structure 150 is electrically connected to the shielding layer 120. In the off state, the shielding layer 120 not only forms a depletion layer together with the silicon carbide semiconductor substrate 110, but also physically isolates the electric field coupling between the gate and the drain, significantly reducing the Miller capacitance (Cgd). At the same time, the shielding layer 120 transfers the high electric field peak from the fragile AlGaN / GaN heterostructure interface to the robust silicon carbide drift region, avoiding electric field concentration at the heterostructure interface. As a result, the switching speed of the device is greatly improved, the switching loss is significantly reduced, and the breakdown voltage and long-term reliability are fundamentally improved, solving the problems of easy breakdown and poor reliability of the heterostructure interface in the existing simple epitaxial stacking scheme.

[0049] (3) By introducing a floating conductive structure 160, this application achieves efficient vertical injection of electrons from the transverse two-dimensional electron gas channel to the longitudinal silicon carbide drift region, solving the bottleneck problem of electron transport between heterogeneous material interfaces. This structure does not require external bias, does not increase static power consumption, and is compatible with existing processes, further reducing the on-resistance of the device and improving forward conduction characteristics.

[0050] (4) This application integrates a silicon carbide semiconductor substrate 110, a shielding layer 120, a gallium nitride heterostructure 130, a floating conductive structure 160, a gate structure 140, a source structure 150, and a drain structure into a single chip to form a vertically conductive hybrid transistor device 100. This monolithic integration scheme eliminates the parasitic inductance, additional packaging area, and interconnection losses caused by parallel or external series connection of discrete devices, and eliminates the need for external clamping circuits or complex gate drive auxiliary networks. As a result, the size, weight, and design complexity of the power system are significantly reduced, while the power density and system reliability are improved, solving the problems of large parasitic parameters, low integration density, and complex peripheral circuits in existing hybrid integration schemes.

[0051] Figure 3 The diagram shown is a structural schematic of the third hybrid transistor device 100 provided in an embodiment of this application; as shown Figure 3 As shown, this embodiment further defines the specific layered structure of the silicon carbide semiconductor substrate 110, which, from bottom to top, includes: a metal drain 111, an N+ type silicon carbide substrate 112, an N- type silicon carbide buffer layer 113, and an N- type silicon carbide drift region 114. At least one N+ type source region 115 is embedded within the N- type silicon carbide drift region 114, and the upper surface of the N+ type source region 115 is flush with the upper surface of the N- type silicon carbide drift region 114. Specifically: (1) The metal drain 111 is disposed at the bottom of the entire silicon carbide semiconductor substrate 110, and is usually made of a highly conductive metal (such as a nickel / silver stack, a titanium / nickel / silver stack, or aluminum). The metal drain 111 forms an ohmic contact with the N+ type silicon carbide substrate 112 above it, serving as the main current outlet of the device. When the device is forward-biased, electrons flow vertically from the top source through the drift region to the substrate and are eventually collected by the metal drain 111; when the device is off, the metal drain 111 withstands the high voltage applied by the external circuit.

[0052] (2) The N+ type silicon carbide substrate 112 is located above the metal drain 111 and has an extremely high doping concentration (typically greater than 1×10¹). 9 The purpose of high doping is to reduce substrate resistance and decrease ohmic losses in the vertical current path; at the same time, the N+ substrate provides a high-quality crystallographic substrate for subsequent epitaxial growth. Since the substrate does not participate in voltage blocking, its thickness can be relatively thin (e.g., 100–500 micrometers) to reduce the overall thermal resistance of the device.

[0053] (3) An N-type silicon carbide buffer layer 113 is disposed on an N+ type silicon carbide substrate 112, and its doping concentration is between that of the N+ silicon carbide substrate and the N- drift region above it (typically 1×10¹). 7 ~1×10¹ 8 The main functions of the buffer layer are: ① to prevent crystal defects in the N+ substrate from extending upwards into the drift region, thereby ensuring the crystal quality of the drift region and improving breakdown voltage and reliability; ② to serve as a transition layer for doping concentration, mitigating the abrupt change from a highly doped substrate to a lightly doped drift region and optimizing the electric field distribution. The thickness of the buffer layer is typically 0.5–2 micrometers.

[0054] (4) The N-type silicon carbide drift region 114 is disposed on the N-type silicon carbide buffer layer 113 and is the core region of the device that withstands the blocking voltage. The drift region is lightly doped (typically 1×10¹). 4 ~1×10¹ 6 This is because, according to the PN junction depletion theory, the lower the doping concentration, the larger the depletion layer thickness, and the higher the voltage it can withstand. The thickness of the drift region is designed according to the target voltage rating. For example, 5 to 10 micrometers can be selected for 600V devices, 10 to 20 micrometers can be selected for 1200V devices, and a thicker drift region is required for higher voltages (such as above 3.3kV).

[0055] In the device off state, the PN junction formed by the shielding layer 120 and the N-drift region is reverse biased, and the depletion layer mainly extends into the N-drift region. Due to the light doping of the N-drift region, the depletion layer can be extended to a large thickness, thereby withstanding voltages of hundreds to thousands of volts. At the same time, the wide bandgap of the drift region gives it an extremely high critical breakdown field strength (approximately 10 times that of silicon). Therefore, at the same breakdown voltage level, the thickness of the silicon carbide drift region is only one-tenth that of the silicon drift region, which is beneficial for reducing device size and on-resistance.

[0056] (5) The N+ source region 115 is embedded within the N-type silicon carbide drift region 114, located at the upper part of the drift region near the surface. The N+ source region 115 has an extremely high doping concentration (typically greater than 1×10¹). 9 Its function is to provide a low-barrier, low-resistance entry point for electrons to be injected from the gallium nitride heterostructure 130 into the drift region. Due to the concentration gradient formed between the N+ source region and the N- drift region, the injected electrons can be quickly collected by the drift region and transported vertically downwards.

[0057] The upper surface of the N+ source region is flush with the upper surface of the N-silicon carbide drift region. The purpose is that in subsequent processes, the floating conductive structure 160 can simultaneously contact the N+ source region and the gallium nitride heterostructure 130 above through the contact hole to form a flat interface and avoid problems such as poor step coverage or increased contact resistance. Among them, one N+ source region 115 is matched with one floating conductive structure 160.

[0058] like Figure 3 As shown, the shielding layer 120 in this embodiment includes a P-type silicon carbide shielding region, and the shielding layer 120 is embedded within an N-type silicon carbide drift region, forming a PN junction between the shielding layer 120 and the silicon carbide drift region. Specifically, the P-type silicon carbide shielding region is formed on the upper part of the drift region by ion implantation (such as aluminum ion implantation), and its lower and side surfaces are surrounded by the N-type silicon carbide drift region, with only the upper surface exposed. In addition, since the P-type silicon carbide shielding region and the N-type drift region have opposite doping types, they naturally form a PN junction upon contact. This PN junction is reverse biased in the device off state, and the depletion layer mainly extends into the lightly doped N-type drift region, thereby withstanding high voltage. At the same time, the presence of the PN junction attracts the high electric field peak from the interface of the fragile gallium nitride heterostructure 130 above to the interior of the silicon carbide drift region, protecting the heterostructure from electric field damage.

[0059] Therefore, the PN junction formed by the shielding layer 120 and the drift region not only participates in voltage blocking, but also optimizes the electric field distribution inside the device, thereby improving the breakdown voltage and long-term reliability.

[0060] like Figure 3As shown, the gallium nitride heterostructure 130 of this embodiment includes a gallium nitride channel layer 131 and an aluminum gallium nitride barrier layer 132. The gallium nitride channel layer 131 is at least partially disposed above the shielding layer 120, that is, the bottom of the gallium nitride channel layer 131 can partially cover the shielding layer 120 and partially cover the silicon carbide drift region, while the aluminum gallium nitride barrier layer 132 is disposed above the gallium nitride channel layer 131.

[0061] It should be noted that due to the difference in bandgap between gallium nitride (GaN) and aluminum gallium nitride (AlGaN), a high-concentration two-dimensional electron gas (2DEG) spontaneously forms at their interface. This 2DEG conductive channel is located in an extremely thin layer of the GaN channel layer 131 near the interface. The 2DEG has extremely high electron mobility (typically exceeding 1500–2000 cm² / V·s), providing a lateral conductive path with extremely low resistance for the device. When a positive voltage is applied to the gate, the 2DEG channel turns on, allowing electrons to be rapidly transported laterally from the source structure 150 to the floating conductive structure 160 region; when the gate voltage is below the threshold voltage, the 2DEG channel is depleted, and the device turns off. Therefore, the GaN heterostructure 130 of this embodiment fully utilizes the high mobility of GaN material, ensuring low losses when the device is turned on.

[0062] like Figure 3 As shown, the gate structure 140 of this embodiment includes a P-type gallium nitride gate layer 141 and a metal gate 142, wherein the P-type gallium nitride gate layer 141 is disposed on the aluminum gallium nitride barrier layer 132.

[0063] Specifically, the p-type gallium nitride gate layer 141 is formed by selective epitaxial growth or re-growth processes, and its doping type is p-type (e.g., magnesium doping), with a doping concentration typically of 1×10¹. 9 ~1×10² 0 The p-type gallium nitride gate layer 141 forms a PN junction with the underlying aluminum gallium nitride barrier layer 132 and gallium nitride channel layer 131. At zero gate voltage or negative gate voltage, the depletion region of this PN junction extends downward, depleting the two-dimensional electron gas channel and keeping the device in a normally off state (enhancement mode). When a sufficiently high positive voltage is applied to the gate, the depletion region shrinks, the two-dimensional electron gas recovers, and the channel turns on.

[0064] A metal gate 142 is disposed on top of the p-type gallium nitride gate layer 141, typically using a nickel / gold (Ni / Au) stack to form a metal system with good ohmic contact with the p-type gallium nitride gate layer 141. The metal gate 142 is used to apply an external driving voltage, control the potential of the p-type gallium nitride gate layer 141, and thus control the opening and closing of the underlying channel. Through the combination of the p-type GaN gate layer and the metal gate 142, this device can achieve stable enhancement-mode operation without external clamping circuitry, improving system safety and driving simplicity.

[0065] like Figure 3 As shown, the source structure 150 of this embodiment includes a first contact hole 151 and a metal source 152. Specifically, the first contact hole 151 is disposed on the shielding layer 120, and the first contact hole 151 is also in contact with the gallium nitride heterostructure 130. That is, the sidewall of the contact hole is in contact with the sidewall of the gallium nitride channel layer 131 and the aluminum gallium nitride barrier layer 132, ensuring that the source structure 150 can simultaneously electrically connect the shielding layer 120 and the gallium nitride heterostructure 130.

[0066] A metal source 152 is disposed above the first contact hole 151, forming an ohmic contact with the shielding layer 120 through the first contact hole 151, thereby fixing the potential of the shielding layer 120 to the source potential (typically ground potential). Simultaneously, since the first contact hole 151 also contacts the gallium nitride heterostructure 130, the metal source 152 also provides an entrance for electrons to enter the two-dimensional electron gas channel of the gallium nitride heterostructure 130 from the external circuit. In this embodiment, the source structure 150 achieves the functions of fixing the potential of the shielding layer 120 (reducing Miller capacitance) and receiving external current. The placement of the first contact hole 151 ensures a low-resistance connection, which is beneficial for improving device switching speed and reducing conduction losses.

[0067] like Figure 3 As shown, the floating conductive structure 160 of this embodiment includes a second contact hole 161 and a metal floating electrode 162. Specifically, the second contact hole 161 is disposed on the N+ type source region in the silicon carbide semiconductor substrate 110. The second contact hole 161 also contacts the gallium nitride heterostructure 130, that is, the sidewall of the contact hole contacts the sidewall of the gallium nitride channel layer 131 and the aluminum gallium nitride barrier layer 132, thereby establishing an electrical connection between the floating conductive structure 160 and the gallium nitride heterostructure 130.

[0068] A floating metal electrode 162 is disposed above the second contact hole 161. Unlike the source structure 150, the floating metal electrode 162 is not connected to any external potential; that is, it is neither grounded nor connected to a power supply or signal line, and is in an electrically floating state. When the device is forward-biased, electrons enter the two-dimensional electron gas channel of the gallium nitride heterostructure 130 from the source, are transported laterally to the region of the second contact hole 161, and are vertically injected into the silicon carbide semiconductor substrate 110 via the floating metal electrode 162 and the N+ type source region, eventually flowing to the drain. Since the floating metal electrode 162 is not connected to any potential, its potential is determined by the semiconductor layer it contacts, and it does not interfere with the channel potential distribution, while providing a low-resistance vertical transport path for electrons. The floating conductive structure 160 of this embodiment achieves efficient injection of electrons from the gallium nitride heterostructure 130 to the silicon carbide semiconductor substrate 110, solves the bottleneck problem of electron transport at the heterostructure interface, and requires no additional control signal, thus not increasing static power consumption.

[0069] like Figure 3 As shown, the hybrid transistor device 100 of this embodiment further includes an interlayer dielectric layer 170. The interlayer dielectric layer 170 is disposed between the gate structure 140 and the source structure 150 and is configured to electrically isolate the gate structure 140 and the source structure 150. Specifically, the dielectric layer covers the top and sidewalls of the metal gate 142 and a portion of the surface of the gallium nitride heterostructure 130.

[0070] The main functions of the interlayer dielectric layer 170 in this embodiment are: ① to prevent short circuits between the gate and the source, ensuring the independence of the gate control signal; ② to reduce the parasitic capacitance between the gate and the source, improving the switching speed; ③ to provide planarization support in subsequent metal interconnect processes, preventing accidental contact between different electrodes.

[0071] By setting the interlayer dielectric layer 170, the gate structure 140 and the source structure 150 of this device achieve reliable electrical isolation, avoiding device failure caused by leakage current or short circuit, and improving the yield and long-term reliability of the device.

[0072] The working principle of the hybrid transistor device 100 provided in this embodiment is explained below: (1) In the on state: When a forward bias voltage higher than the threshold voltage is applied to the gate structure 140 (the P-type gallium nitride gate layer 141 and the metal gate 142 above it), the two-dimensional electron gas conductive channel below the P-type gallium nitride gate layer 141 is reopened. Electrons enter the gallium nitride heterostructure 130 (the two-dimensional electron gas conductive channel formed between the gallium nitride channel layer 131 and the aluminum gallium nitride barrier layer 132) from the metal source 152 (through the first contact hole 151) and are transported at high speed laterally. When the electrons reach the floating conductive structure 160 (the second contact hole 161 and the metal floating electrode 162), since the metal floating electrode 162 is not connected to any potential, it acts as a low-resistance jumper, and the electrons are successfully injected into the N+ type source region 115 in the silicon carbide semiconductor substrate 110 through the second contact hole 161. Subsequently, electrons diffuse from the N+ source region 115 and flow vertically into the N- type silicon carbide drift region 114, passing sequentially through the N-type silicon carbide buffer layer 113 and the N+ type silicon carbide substrate 112, finally reaching the metal drain 111. The high mobility of the gallium nitride heterostructure 130 ensures extremely low on-resistance, while the layered structure of the silicon carbide semiconductor substrate 110 ensures low resistance and breakdown voltage of the vertical current path.

[0073] (2) In the off state: When the gate voltage is lower than the threshold voltage and a high voltage is applied to the drain, the P-type gallium nitride gate layer 141 depletes the two-dimensional electron gas conductive channel below, cutting off the current path. At the same time, the P-type silicon carbide shielding region embedded in the N-type silicon carbide drift region 114 forms a reverse-biased PN junction with the N-type silicon carbide drift region 114. The depletion layer mainly extends within the lightly doped N-type drift region and withstands high voltage. The P-type silicon carbide shielding region also plays an electric field shielding role: it transfers the high electric field peak point from the heterogeneous interface between the fragile aluminum gallium nitride barrier layer 132 and the gallium nitride channel layer 131 to the more robust silicon carbide drift region, thereby greatly improving the breakdown voltage and long-term reliability of the device. In addition, the interlayer dielectric layer 170 ensures electrical isolation between the gate structure 140 and the source structure 150 to avoid leakage.

[0074] (3) Switching Transient: During the switching process, the P-type silicon carbide shielding region electrically connected to the source structure 150 (first contact hole 151 and metal source 152) not only manages the static electric field but also serves as a dynamic electric field shielding layer 120. Since the shielding region is fixed at the source potential through the first contact hole 151, it effectively isolates the electric field coupling between the gate and drain, significantly reducing the gate-drain capacitance (Miller capacitance Cgd). At the same time, the floating conductive structure 160 does not participate in the potential fluctuations during the switching transient and does not affect the shielding effect. The reduced Miller capacitance allows the device to switch at a faster speed, significantly reducing switching losses. The buffer layer and substrate in the silicon carbide semiconductor substrate 110 further optimize the dynamic response of the vertical current path.

[0075] In summary, this application achieves a balance of high withstand voltage, low on-resistance, low switching loss, and high reliability through the coordinated operation of the silicon carbide semiconductor substrate 110, the P-type silicon carbide shielding layer 120, the gallium nitride heterostructure 130, the gate structure 140, the source structure 150, the floating conductive structure 160, the interlayer dielectric layer 170, and the metal drain 111.

[0076] The inventors of this application have discovered through research that, Figure 3 In the hybrid transistor device structure shown, the silicon carbide semiconductor substrate 110 employs a single N-type silicon carbide drift region 114. Although this structure can achieve high breakdown voltage by utilizing the high critical breakdown field strength of silicon carbide material, and obtain good conduction characteristics with the cooperation of the shielding layer 120 and the floating conductive structure 160, leakage current still exists in the off state, such as surface leakage current, heterojunction tunneling leakage current, gate edge leakage current, and off-state tail current.

[0077] To address the aforementioned leakage current problem, this application provides another embodiment of a silicon carbide semiconductor substrate. For example... Figure 4 , Figure 5 and Figure 6 As shown, this embodiment is similar to Figure 3 The difference shown is that the original N-type silicon carbide drift region 114 is replaced with a composite withstand layer 116. This composite withstand layer 116 is configured to provide a vertical current path when the device is forward-biased and to withstand blocking voltage and leakage current when the device is off.

[0078] In this embodiment, the silicon carbide semiconductor substrate 110 includes, from bottom to top: a metal drain 111, an N+ type silicon carbide substrate 112, an N-type silicon carbide buffer layer 113, a composite withstand voltage layer 116, and at least one N+ type source region 115 embedded in the composite withstand voltage layer 116. The upper surface of the N+ type source region 115 is flush with the upper surface of the composite withstand voltage layer 116 to facilitate the contact and planarization of the subsequent floating conductive structure 160.

[0079] The working principle of the composite pressure-resistant layer 116 in this embodiment is as follows: (1) During forward conduction, the vertical conductive channels inside the composite withstand layer 116 provide a low-resistance path for electrons, ensuring that the device obtains extremely low on-resistance. At the same time, the charge storage or auxiliary layer inside the composite withstand layer 116 can enhance conductivity modulation and further reduce conduction loss.

[0080] (2) In the off state, the composite withstand voltage layer 116 actively or passively blocks multiple leakage current paths through its internal PN junction structure, buried blocking region, auxiliary extraction layer or barrier control layer, etc.: for example, suppressing leakage from the top of the drift region to the surface, blocking tunneling current at the heterogeneous interface, clearing the majority carriers remaining in the drift region, etc., thereby significantly reducing the off-state leakage current and improving the withstand voltage stability of the device.

[0081] This embodiment replaces the single N-type silicon carbide drift region 114 with a composite withstand voltage layer 116, which, while maintaining the advantages of the original device, further reduces the off-state leakage current, improves the breakdown voltage and high-temperature reliability of the device, and improves the trade-off relationship between on-resistance and withstand voltage, enabling the hybrid transistor device to better meet the needs of high-frequency, high-voltage, and high-power-density applications.

[0082] Figure 4 The diagram shown is a structural schematic of the fourth hybrid transistor device 100 provided in an embodiment of this application; as follows: Figure 4 As shown, this embodiment provides one implementation of the composite withstand voltage layer 116, which includes a conductive layer (composed of alternating N-type vertical conductive regions 1162 and P-type vertical conductive regions 1161), at least one P-type buried blocking region 1163, and an N-type charge storage layer 1164.

[0083] Specifically, a conductive layer is disposed on top of an N-type silicon carbide buffer layer 113. This conductive layer is composed of alternating N-type vertical conductive regions 1162 and P-type vertical conductive regions 1161. At the top of each N-type vertical conductive region 1162, a P-type embedded blocking region 1163 is embedded. This P-type embedded blocking region 1163 completely covers the entire top surface of the corresponding N-type vertical conductive region 1162, has the same width as the N-type vertical conductive region 1162, and its upper surface is flush with the upper surface of the conductive layer. In other words, on the upper surface of the conductive layer, the original positions of the N-type vertical conductive regions 1162 are completely replaced by P-type embedded blocking regions 1163, resulting in the upper surface of the conductive layer being alternately composed of P-type embedded blocking regions 1163 and P-type vertical conductive regions 1161, with no exposed N-type vertical conductive regions 1162. An N-type charge storage layer 1164 is covered above the conductive layer and all P-type buried blocking regions 1163, and the doping concentration of this layer is higher than that of the N-type vertical conductive regions 1162.

[0084] In this embodiment, both the shielding layer 120 and the N+ type source region 115 are formed within the N-type charge storage layer 1164. Specifically, a P-type silicon carbide shielding region is provided in the middle of the N-type charge storage layer 1164, and N+ type source regions 115 are provided on both sides thereon, with the upper surfaces of both being flush with the upper surface of the N-type charge storage layer 1164.

[0085] The working principle of this embodiment is as follows: (1) In the on-state: Electrons are laterally transported from the source through the channel below the gate, vertically injected into the N+ type source region 115 through the floating conductive structure 160, and then enter the N-type charge storage layer 1164. Due to the high doping concentration of the N-type charge storage layer 1164, the conductivity modulation effect is significant, and electrons rapidly enter the N-type vertical conductive region 1162 in the conductive layer, and finally flow to the metal drain 111 through the N-type silicon carbide buffer layer 113 and the N+ type silicon carbide substrate 112. The presence of the N-type charge storage layer 1164 reduces the injection barrier and the on-resistance.

[0086] (2) In the off state: First, the P-type buried blocking region 1163 forms a PN junction with the lower N-type vertical conductive region 1162. When reverse biased, the depletion layer extends downward, completely sealing the leakage path from the top of the N-pillar to the surface (including surface leakage and vertical leakage). At the same time, a depletion region is also formed between the P-type buried blocking region 1163 and the adjacent P-type vertical conductive region 1161 and N-type charge storage layer 1164, further suppressing lateral leakage. Second, the N-type charge storage layer 1164 forms an additional PN junction with the lower P-type buried blocking region 1163 and P-type vertical conductive region 1161, which helps to expand the depletion layer and improve the withstand voltage. In addition, the upper P-type silicon carbide shielding region still performs its original electric field shielding and Miller capacitance reduction functions.

[0087] With the above structure, this embodiment retains the advantage of low on-resistance of the superjunction, while completely blocking the leakage channel at the top of the N-type vertical conductive region 1162 by using the P-type buried blocking region 1163, and improving carrier injection and electric field distribution by using the N-type charge storage layer 1164.

[0088] Figure 5 The diagram shown is a structural schematic of the fifth hybrid transistor device 100 provided in this application embodiment; as follows: Figure 5 As shown, this embodiment provides another implementation of the composite withstand voltage layer 116, which includes an N-type auxiliary layer 1165 and a conductive layer (composed of alternating N-type vertical conductive regions 1162 and P-type vertical conductive regions 1161).

[0089] Specifically, the N-type auxiliary layer 1165 is disposed above the N-type silicon carbide buffer layer 113, and is a continuous N-type doped layer. Its doping concentration is between that of the N-type silicon carbide buffer layer 113 and the N-type vertical conductive region 1162 in the subsequent conductive layer (e.g., 1×10¹). 5 ~1×10¹ 7 cm - ³). A conductive layer is disposed on top of the N-type auxiliary layer 1165. This conductive layer consists of alternating N-type vertical conductive regions 1162 and P-type vertical conductive regions 1161. The upper surface of the conductive layer is the upper surface of the composite withstand voltage layer 116. In this embodiment, the shielding layer 120 and the N+ type source region 115 are both embedded in the upper region of the conductive layer: the middle is a P-type silicon carbide shielding region (which can span the N-type and P-type vertical conductive regions), and the two sides are N+ type source regions 115 (embedded on the top of the N-type vertical conductive regions 1162 on the left and right sides respectively), and the upper surfaces of both are flush with the upper surface of the conductive layer. The N-type auxiliary layer 1165 is not connected to any external potential and is in a floating or grounded state.

[0090] The working principle of this embodiment is as follows: (1) In the on-state: Electrons enter the N+ type source region 115 from the source electrode, and then flow downwards into the N-type vertical conductive region 1162. Since there is no potential barrier between the N-type auxiliary layer 1165 and the N-type vertical conductive region 1162 (both are N-type), electrons can flow smoothly through the N-type auxiliary layer 1165, the N-type silicon carbide buffer layer 113, and the N+ type silicon carbide substrate 112 to the metal drain electrode 111. The doping concentration of the N-type auxiliary layer 1165 is optimized and will not significantly increase the on-resistance.

[0091] (2) In the off state: When the gate is turned off and a high voltage is applied to the drain, the N-type vertical conductive region 1162 and the P-type vertical conductive region 1161 in the conductive layer form a depletion layer, and the electrons in the N-pillar are gradually cleared. However, in conventional superjunctions, the removal of residual electrons is slow. In this embodiment, since the N-type auxiliary layer 1165 is located at the bottom of the N-pillar and has a low doping concentration, under reverse bias conditions, an electric field gradient is formed between the bottom of the N-pillar and the auxiliary layer, which causes the residual electrons in the N-pillar to be collected into the N-type auxiliary layer 1165 and guided to the drain along the path of auxiliary layer → buffer layer → substrate → drain, thereby accelerating the depletion process of the conductive layer and significantly reducing the tail current and off-state leakage current.

[0092] Therefore, without increasing the complexity of the process, this embodiment solves the problem of residual carrier tailing during high-speed switching by introducing a simple N-type auxiliary layer 1165, thereby reducing switching losses and improving the switching frequency and efficiency of the device.

[0093] Figure 6 The diagram shown is a structural schematic of the sixth hybrid transistor device 100 provided in this application embodiment; as follows: Figure 6 As shown, this embodiment provides another implementation of the composite withstand voltage layer 116, which includes a conductive layer (composed of alternating N-type vertical conductive regions 1162 and P-type vertical conductive regions 1161) and a barrier modulation layer 1166.

[0094] Specifically, in this embodiment, the conductive layer is disposed on top of the N-type silicon carbide buffer layer 113. This conductive layer is composed of alternating N-type vertical conductive regions 1162 and P-type vertical conductive regions 1161. The upper surface of the conductive layer is the upper surface of the composite withstand voltage layer 116. A P-type silicon carbide shielding region and an N+ type source region 115 are embedded in the upper part of the conductive layer. A barrier control layer 1166 is disposed on the upper surface of the conductive layer. This barrier control layer 1166 is an ultrathin amorphous aluminum nitride (AlN) layer with a thickness of 1–5 nm. A gallium nitride heterostructure 130 (gallium nitride channel layer 131 and aluminum gallium nitride barrier layer 132) is then disposed on top of the barrier control layer 1166.

[0095] It should be noted that although the barrier control layer 1166 covers the P-type silicon carbide shielding region 120 and the N+ type source region 115, the etching process will penetrate the barrier control layer 1166 during the subsequent fabrication of contact holes, exposing the shielding region or source region below, and then fill it with metal to form an ohmic contact. Therefore, the presence of the barrier control layer 1166 does not affect the electrical connection function between the source and the floating conductive structure.

[0096] The working principle of this embodiment is as follows: (1) Tunneling leakage current blocking: Ultrathin amorphous AlN has a wide bandgap (about 6.2 eV) and a high barrier, which can effectively increase the height and width of the tunneling barrier at the SiC / GaN heterostructure. In the device off state, the high voltage leads to the enhancement of the electric field at the interface, but the AlN layer prevents electrons from tunneling from the SiC conduction band through the defect state to the GaN side, thereby significantly reducing the leakage current at the heterostructure interface.

[0097] (2) Atomic diffusion barrier: During the high-temperature process of MOCVD epitaxial growth of GaN layers (typically 1000-1100℃), the AlN layer, as a dense diffusion barrier layer, can effectively prevent Ga atoms from diffusing into the SiC conductive layer. This protects the doping distribution of the N-type vertical conductive region 1162 and the P-type vertical conductive region 1161 in the conductive layer from being disrupted, maintains the charge balance of the superjunction, and ensures the breakdown voltage and conduction performance of the device.

[0098] (3) Impact on original functions: Since the thickness of the ultrathin AlN layer is only 1 to 5 nm, electrons can pass through the layer through tunneling or thermal emission during forward conduction, without significantly increasing the on-resistance. At the same time, as mentioned above, the contact hole etching process ensures that the ohmic contact between the source and the floating conductive structure is not affected, so the functions of the P-type silicon carbide shielding region and the N+ type source region 115 are normal.

[0099] This embodiment solves two long-standing and interrelated technical problems—tunneling leakage current at heterogeneous interfaces and high-temperature epitaxial atomic diffusion—by using an ultrathin AlN barrier control layer 1166, significantly improving the reliability and process stability of the device.

[0100] Figure 7 The diagram shown is a schematic flowchart of a method for fabricating a first hybrid transistor device according to an embodiment of this application; as shown Figure 7 As shown, applied to the above Figure 3 The method for fabricating the hybrid transistor device 100 shown specifically includes the following steps: Step S110: Provide an N+ type silicon carbide substrate 112.

[0101] Specifically, an N+ type silicon carbide substrate 112 is selected. This substrate has a high doping concentration (typically greater than 1 × 10¹). 9 This provides a substrate for subsequent epitaxial growth and serves as a low-resistivity layer for the vertical current path. The preferred crystal form of the substrate is 4H-SiC or 6H-SiC, and the thickness can be selected according to mechanical strength requirements (e.g., 350 micrometers).

[0102] Step S120: An N-type silicon carbide buffer layer 113 and an N-type silicon carbide drift region 114 are epitaxially grown sequentially on an N+ type silicon carbide substrate 112.

[0103] It should be noted that an N-type silicon carbide buffer layer 113 and an N-type silicon carbide drift region 114 are sequentially epitaxially grown on an N+ type silicon carbide substrate 112 using chemical vapor deposition; specifically: (1) N-type silicon carbide buffer layer 113: the doping concentration is between that of the N+ substrate and the drift region (e.g., 1×10¹). 7 ~1×10¹ 8 The thickness is about 0.5 to 2 micrometers; its function is to block the upward extension of substrate defects and to serve as a doping transition layer to optimize the electric field distribution.

[0104] (2) N-type silicon carbide drift region 114: lightly doped (e.g., 1×10¹) 4 ~1×10¹ 6 The thickness is designed according to the target withstand voltage level (e.g., 5-10 micrometers for 600V devices, 10-20 micrometers for 1200V devices). This drift region is the core area where the device withstands the blocking voltage.

[0105] The epitaxial growth temperature is typically 1500–1650℃, and the pressure is 100–300 mbar.

[0106] Step S130: At least one P-type silicon carbide shielding region and at least one N+ type silicon carbide source region are formed in the N-type silicon carbide drift region 114 by ion implantation.

[0107] It should be noted that this embodiment employs an ion implantation process to form a P-type silicon carbide shielding region and an N+ type silicon carbide source region within the N-type silicon carbide drift region 114; specifically: (1) Formation of a P-type silicon carbide shielding region: Using a P-type shielding mask, aluminum (Al) ion implantation is performed in the central region of the drift region surface. The implantation energy is 200–500 keV, and the dose is 1×10¹³–1×10¹³. 5 This process induces P-type doping in the implanted region. High-temperature annealing (approximately 1600–1800 °C) then activates the doped atoms, forming a P-type silicon carbide shielding region. This shielding region is embedded within the drift region, with its lower and side surfaces surrounded by N-drift regions, and only its upper surface exposed.

[0108] (2) Formation of N+ type silicon carbide source region: Using an N+ mask, nitrogen (N) or phosphorus (P) ions are implanted on both sides of the drift region surface (i.e., the lateral outer side of the shielding region), with an implantation energy of 50-150 keV and a dose greater than 1×10¹. 5 This forms a highly doped N+ type silicon carbide source region. After annealing, the upper surface of the source region is basically flush with the upper surface of the drift region.

[0109] Step S140: Epitaxially grow gallium nitride channel layer 131 and aluminum gallium nitride barrier layer 132 on the P-type silicon carbide shielding region.

[0110] It should be noted that a gallium nitride channel layer 131 and an aluminum gallium nitride barrier layer 132 are epitaxially grown on the p-type silicon carbide shielding region and the partially exposed drift region using metal-organic chemical vapor deposition; specifically: (1) Gallium nitride channel layer 131: growth temperature 1000~1100℃, thickness 50~500nm.

[0111] (2) Aluminum gallium nitride barrier layer 132: Continues to grow on gallium nitride channel layer 131, with Al composition of 15% to 30% and thickness of 10 to 30 nm.

[0112] Due to the difference in bandgap between gallium nitride (GaN) and aluminum gallium nitride (AlGaN), a high-mobility two-dimensional electron gas (2DEG) conductive channel naturally forms at their interface. This growth process can be selective epitaxy (growing only above the shielded area) or non-selective epitaxy (growing all over the area and then etching away the excess).

[0113] Step S150: Form a P-type gallium nitride gate layer 141 on the aluminum gallium nitride barrier layer 132.

[0114] Specifically, a p-type gallium nitride gate layer 141 was formed on the surface of the aluminum gallium nitride barrier layer 132 using MOCVD or molecular beam epitaxy (MBE). Growth conditions: magnesium doping (Mg), doping concentration 1×10¹ 9 ~1×10² 0 The thickness is 50–200 nm. Subsequently, magnesium doping is activated by annealing in a nitrogen atmosphere (800–950 °C) to form a p-type gallium nitride gate layer 141. This gate layer is located above the aluminum gallium nitride barrier layer 132 and is used to deplete the underlying two-dimensional electron gas at zero gate voltage to achieve enhancement-mode operation.

[0115] Step S160: Form an interlayer dielectric layer 170, covering a portion of the P-type gallium nitride gate layer 141, the aluminum gallium nitride barrier layer 132, and the N-type silicon carbide drift region 114.

[0116] Specifically, plasma-enhanced chemical vapor deposition (PECVD) was used to deposit an interlayer dielectric layer of 170. The dielectric material was either silicon dioxide (SiO2) or silicon nitride (SiN). x The dielectric layer has a thickness of 200–500 nm. It covers the top and sidewalls of the P-type gallium nitride gate layer 141, the surface of the aluminum gallium nitride barrier layer 132, and the exposed area of ​​the N-type silicon carbide drift region 114 (including above the N+ source region), for electrical isolation between subsequent electrodes.

[0117] Step S170: Etch the interlayer dielectric layer 170 to form contact holes that expose the P-type silicon carbide shielding region, the P-type gallium nitride gate layer 141, and the N+ type silicon carbide source region.

[0118] It should be noted that contact holes are etched in the interlayer dielectric layer 170 using photolithography and dry etching processes. Specifically: (1) A first contact hole 151 is etched above the P-type silicon carbide shielding area. The contact hole penetrates the dielectric layer to expose the upper surface of the shielding area, while its sidewall exposes a portion of the gallium nitride heterostructure 130 (i.e., the side of the gallium nitride channel layer 131 or the aluminum gallium nitride barrier layer 132).

[0119] (2) Etch gate contact holes above the P-type gallium nitride gate layer 141 to expose the upper surface of the gate layer.

[0120] (3) The second contact hole 161 is etched above the N+ type silicon carbide source region to expose the upper surface of the source region, while its sidewalls also expose part of the gallium nitride heterostructure 130.

[0121] The etching gas can be fluorine-based gases such as CF4 and SF6, and the etching time needs to be precisely controlled to ensure that there is no residual medium at the bottom of the hole.

[0122] Step S180: A metal layer is formed in the contact hole and on the interlayer dielectric layer 170, and the metal layer is patterned to form a metal source 152 located on the P-type silicon carbide shielding region, a metal gate 142 located on the P-type gallium nitride gate layer 141, and a metal floating electrode 162 located on the N+ type silicon carbide source region, respectively.

[0123] Specifically, a metal layer is deposited within the contact holes and on the interlayer dielectric layer 170 using sputtering or electron beam evaporation. The metal material can be aluminum (Al), titanium / aluminum (Ti / Al) stack, or nickel / gold (Ni / Au), with a thickness of 1–3 micrometers. The metal layer is then patterned using photolithography and etching. (1) A metal pattern located on the P-type silicon carbide shielding area forms a metal source 152 (which is in contact with the sidewall of the gallium nitride heterostructure 130 at the same time).

[0124] (2) A metal pattern on the P-type gallium nitride gate layer 141 forms a metal gate 142.

[0125] (3) A metal pattern located on the N+ type silicon carbide source region forms a metal floating electrode 162. This electrode is not connected to any external potential (i.e., it is not grounded, not connected to a power supply or signal line), and is in an electrically floating state.

[0126] Step S190: Form a metal drain 111 on the back side of the N+ type silicon carbide substrate 112.

[0127] Specifically, the wafer is flipped, and the back side of the N+ type silicon carbide substrate 112 is thinned (optionally, to 100–200 micrometers to reduce thermal resistance). A back-side metal layer, such as a nickel / silver (Ni / Ag) or titanium / nickel / silver (Ti / Ni / Ag) stack, is then deposited with a thickness of approximately 0.5–2 micrometers. An ohmic contact is formed as the metal drain 111 by rapid thermal annealing (RTA, temperature 800–1000°C).

[0128] In summary, this application has the following beneficial effects: (1) This application utilizes the high critical breakdown field strength and high thermal conductivity of silicon carbide semiconductor substrate 110 to achieve high withstand voltage and high reliability, and utilizes the two-dimensional electron gas channel of gallium nitride heterostructure 130 to achieve extremely low on-resistance, overcoming the defects of high on-resistance of single SiC MOSFET and insufficient withstand voltage of single GaN HEMT, and truly realizing the ideal combination of "high voltage + low resistance".

[0129] (2) Enhanced operation is achieved through the P-type gallium nitride gate layer 141, resulting in a stable and high threshold voltage and improving the system's anti-interference capability. The P-type silicon carbide shielding layer 120, which is embedded in the silicon carbide drift region and electrically connected to the source, physically isolates the gate and drain, significantly reducing Miller capacitance (Cgd) and achieving ultra-fast switching speed and low switching loss. At the same time, the shielding layer 120 transfers the high electric field peak from the fragile heterogeneous interface to the robust silicon carbide drift region, optimizing the electric field distribution and improving the breakdown voltage and avalanche tolerance.

[0130] (3) When the hybrid transistor device 100 of this application is reverse-conducting, the current mainly relies on the majority carrier (electron) for transmission. There is no minority carrier injection and storage effect of bipolar devices. Theoretically, the reverse recovery charge Qrr≈0, which is particularly suitable for bridge circuits.

[0131] (4) The monolithic integrated solution eliminates the parasitic inductance and area waste caused by parallel or external series connection of discrete devices, greatly improving power density; excellent switching characteristics and low loss simplify gate drive circuit and heat dissipation design, reducing the total system cost.

[0132] Figure 8 The diagram shown is a schematic flowchart of a second hybrid transistor device fabrication method provided in this application embodiment; as follows: Figure 8 As shown, the specific steps include: Step S210: Provide an N+ type silicon carbide substrate; Step S220: Epitaxially grow an N-type silicon carbide buffer layer on the N+ type silicon carbide substrate; Step S230: Form a composite pressure-resistant layer on the N-type silicon carbide buffer layer; Step S240: Form at least one P-type silicon carbide shielding region and at least one N+ type silicon carbide source region within the composite pressure-resistant layer; Step S250: Epitaxially grow a gallium nitride channel layer and an aluminum gallium nitride barrier layer on the p-type silicon carbide shielding region; Step S260: Form a P-type gallium nitride gate layer on the aluminum gallium nitride barrier layer; Step S270: Form an interlayer dielectric layer covering a portion of the P-type gallium nitride gate layer, the aluminum gallium nitride barrier layer, and the composite withstand voltage layer; Step S280: Etch the interlayer dielectric layer to form contact holes that expose the P-type silicon carbide shielding region, the P-type gallium nitride gate layer, and the N+ type silicon carbide source region; Step S290: Form a metal layer in the contact hole and on the interlayer dielectric layer, and pattern the metal layer to form a metal source electrode on the P-type silicon carbide shielding region, a metal gate electrode on the P-type gallium nitride gate layer, and a metal floating electrode on the N+ type silicon carbide source region, respectively. Step S300: Form a metal drain on the back side of the N+ type silicon carbide substrate.

[0133] It should be noted that, Figure 8 The preparation method shown is the same as Figure 7 The only difference is: Figure 7 In step S230, the formation of an N-type silicon carbide drift region on the N-type silicon carbide buffer layer is replaced by the formation of a composite withstand voltage layer, and correspondingly, a P-type silicon carbide shielding region and an N+ type silicon carbide source region are formed within the composite withstand voltage layer. Specifically, step S230, forming a composite withstand voltage layer on the N-type silicon carbide buffer layer, can be implemented in the following three different ways: (1) An epitaxial conductive layer is grown on an N-type silicon carbide buffer layer, the conductive layer being composed of alternating N-type vertical conductive regions and P-type vertical conductive regions; a P-type buried blocking region is formed by aluminum ion implantation in the top region of each N-type vertical conductive region, so that the P-type buried blocking region completely covers the top of the N-type vertical conductive region and its upper surface is flush with the upper surface of the conductive layer; an N-type charge storage layer is epitaxially grown on the conductive layer and the P-type buried blocking region; in subsequent steps, the P-type silicon carbide shielding region and the N+ type silicon carbide source region are both formed in the N-type charge storage layer.

[0134] (2) An N-type auxiliary layer (a continuous N-type doped layer with a doping concentration between the buffer layer and the N-type vertical conductive region of the subsequent conductive layer) is epitaxially grown on the N-type silicon carbide buffer layer; a conductive layer is epitaxially grown on the N-type auxiliary layer, which is composed of alternating N-type vertical conductive regions and P-type vertical conductive regions; in the subsequent step S240, the P-type silicon carbide shielding region and the N+ type silicon carbide source region are both embedded in the upper region of the conductive layer by ion implantation (the shielding region is located in the middle, and the source region is located on the top of the N-type vertical conductive regions on both sides), and the upper surface is flush with the upper surface of the conductive layer.

[0135] (3) An epitaxial conductive layer is grown on the N-type silicon carbide buffer layer. This conductive layer consists of alternating N-type and P-type vertical conductive regions. An ultrathin amorphous aluminum nitride (AlN) barrier control layer with a thickness of 1–5 nm is deposited on the entire upper surface of the conductive layer. In step S240, the P-type silicon carbide shielding region and the N+ type silicon carbide source region are embedded in the upper region of the conductive layer by ion implantation (the shielding region is located in the middle, and the source region is located on both sides), and the upper surface is flush with the upper surface of the conductive layer. It should be noted that when etching the contact holes (step S280) laterally, the etching process will penetrate the barrier control layer, so that the metal source electrode and the metal floating electrode can form ohmic contact with the shielding region and the source region.

[0136] Therefore, this application provides a monolithically integrated hybrid transistor device 100 that combines high withstand voltage, low on-resistance, low off-state leakage current, low switching loss, high reliability, and zero reverse recovery characteristics. It is particularly suitable for high-end power electronic systems with extreme requirements for efficiency, power density, and reliability, including but not limited to: main drive inverters for new energy vehicles, on-board chargers (OBC) and DC-DC converters (DCDC), power modules for data center servers, grid-connected inverters for renewable energy (photovoltaic, wind power), and solid-state transformers in smart grids.

[0137] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0138] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0139] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A hybrid transistor device, characterized by, The hybrid transistor device includes: The silicon carbide semiconductor substrate is configured to withstand blocking voltage in the device off state and provide a vertical current path when the device is forward conducting. A shielding layer is disposed on the silicon carbide semiconductor substrate, and the conductivity type of the shielding layer is opposite to that of the silicon carbide semiconductor substrate; At least one gallium nitride heterostructure is disposed on the silicon carbide semiconductor substrate, such that the shielding layer is located between the silicon carbide semiconductor substrate and the gallium nitride heterostructure; the gallium nitride heterostructure is configured to form a conductive channel; At least one floating conductive structure is disposed on the silicon carbide semiconductor substrate and electrically connected to the at least one gallium nitride heterostructure; the floating conductive structure is configured to provide a vertical transport path for electrons to be injected from the gallium nitride heterostructure into the silicon carbide semiconductor substrate when the device is forward-biased. At least one gate structure, said gate structure being disposed on the gallium nitride heterostructure; At least one source structure is disposed on the shielding layer and electrically connected to the shielding layer; The shielding layer is configured to form a depletion layer together with the silicon carbide semiconductor substrate in the device off state, and to shield the electric field coupling between the silicon carbide semiconductor substrate and the gallium nitride heterostructure. The silicon carbide semiconductor substrate includes: Metal drain electrode; An N+ type silicon carbide substrate is disposed on the metal drain electrode; An N-type silicon carbide buffer layer is disposed on the N+ type silicon carbide substrate; A composite withstand voltage layer is disposed on the N-type silicon carbide buffer layer and is configured to: provide a vertical current path when the device is forward conducting and withstand blocking voltage and blocking leakage current when the device is off. At least one N+ type source region is embedded in the composite pressure-resistant layer, and the upper surface of the N+ type source region is flush with the upper surface of the composite pressure-resistant layer.

2. The hybrid transistor device of claim 1, wherein, The composite pressure-resistant layer includes: A conductive layer is disposed on the N-type silicon carbide buffer layer, the conductive layer comprising alternating N-type vertical conductive regions and P-type vertical conductive regions; At least one P-type embedded blocking region is provided, wherein the P-type embedded blocking region is embedded in the top region of the N-type vertical conductive region, and the upper surface of the P-type embedded blocking region is flush with the upper surface of the conductive layer. An N-type charge storage layer covers the conductive layer and the at least one P-type buried blocking region; The shielding layer and the N+ type source region are both formed within the N-type charge storage layer.

3. The hybrid transistor device according to claim 1, characterized in that, The composite pressure-resistant layer includes: An N-type auxiliary layer is disposed on top of the N-type silicon carbide buffer layer; A conductive layer is disposed on the N-type auxiliary layer, the conductive layer comprising alternating N-type vertical conductive regions and P-type vertical conductive regions; The N-type auxiliary layer is configured to collect electrons remaining in the conductive layer when the device is off and guide the electrons to the drain electrode.

4. The hybrid transistor device according to claim 1, characterized in that, The composite pressure-resistant layer includes: A conductive layer is disposed on the N-type silicon carbide buffer layer, the conductive layer comprising alternating N-type vertical conductive regions and P-type vertical conductive regions; A barrier control layer is disposed between the conductive layer and the gallium nitride heterostructure; the barrier control layer is configured to: block the tunneling leakage current between the conductive layer and the gallium nitride heterostructure, and block atomic diffusion into the conductive layer during the epitaxial growth of the gallium nitride heterostructure.

5. A method for fabricating a hybrid transistor device, characterized in that, The method of fabrication, applied to the hybrid transistor device according to any one of claims 1-4, comprises: Provide N+ type silicon carbide substrate; An N-type silicon carbide buffer layer is epitaxially grown on the N+ type silicon carbide substrate; A composite pressure-resistant layer is formed on the N-type silicon carbide buffer layer; At least one P-type silicon carbide shielding region and at least one N+ type silicon carbide source region are formed within the composite pressure-resistant layer; A gallium nitride channel layer and an aluminum gallium nitride barrier layer are epitaxially grown on the P-type silicon carbide shielding region; A P-type gallium nitride gate layer is formed on the aluminum gallium nitride barrier layer; An interlayer dielectric layer is formed, covering a portion of the P-type gallium nitride gate layer, the aluminum gallium nitride barrier layer, and the composite withstand voltage layer; The interlayer dielectric layer is etched to form contact holes that expose the P-type silicon carbide shielding region, the P-type gallium nitride gate layer, and the N+ type silicon carbide source region; A metal layer is formed inside the contact hole and on the interlayer dielectric layer, and the metal layer is patterned to form a metal source electrode located on the P-type silicon carbide shielding region, a metal gate electrode located on the P-type gallium nitride gate layer, and a metal floating electrode located on the N+ type silicon carbide source region, respectively. A metal drain is formed on the back side of the N+ type silicon carbide substrate.

6. The preparation method according to claim 5, characterized in that, Forming the composite pressure-resistant layer on the N-type silicon carbide buffer layer includes: A conductive layer is formed on the N-type silicon carbide buffer layer, the conductive layer comprising alternating N-type vertical conductive regions and P-type vertical conductive regions; A P-type buried blocking region is formed at the top of each N-type vertical conductive region by ion implantation, so that the upper surface of the P-type buried blocking region is flush with the upper surface of the conductive layer; An N-type charge storage layer is epitaxially grown on the conductive layer and the P-type buried blocking region.

7. The preparation method according to claim 6, characterized in that, Forming the composite pressure-resistant layer on the N-type silicon carbide buffer layer includes: An N-type auxiliary layer is epitaxially grown on the N-type silicon carbide buffer layer; A conductive layer is formed on the N-type auxiliary layer, the conductive layer comprising alternating N-type vertical conductive regions and P-type vertical conductive regions.

8. The preparation method according to claim 5, characterized in that, Forming the composite pressure-resistant layer on the N-type silicon carbide buffer layer includes: A conductive layer is formed on the N-type silicon carbide buffer layer, the conductive layer comprising alternating N-type vertical conductive regions and P-type vertical conductive regions; A barrier control layer is deposited on the conductive layer, wherein the barrier control layer is an ultrathin amorphous aluminum nitride layer.

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