A parameter design method of a battery string

Abstract

The application relates to the technical field of photovoltaic modules, in particular to a parameter design method of a cell string. The cell string comprises solar cells arranged in sequence along a first direction and conductive interconnection belts connected in series on the solar cells; each solar cell comprises a silicon substrate, a back light surface of the silicon substrate is provided with two kinds of doped layers with different polarities and arranged alternately and spaced apart along a second direction, a metal electrode and a conductive interconnection belt are sequentially arranged on each doped layer; along the second direction, the shortest distance D between each conductive interconnection belt and the adjacent doped layer with different polarities satisfies the formula: D >= M / (beta*alpha*DeltaT), wherein beta is a gap design safety factor, M is the distance between two adjacent welding spots on the conductive interconnection belt, alpha is the thermal expansion coefficient of the conductive interconnection belt, and DeltaT is the temperature change value of the conductive interconnection belt under extreme working conditions. When D satisfies the above formula, the problem of electric leakage or short circuit caused by the movement of the conductive interconnection belt to the doped layer with different polarity can be avoided.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic module technology, and in particular to a method for designing the parameters of a battery string. Background Technology

[0002] Current developments in photovoltaic module technology primarily focus on increasing module power and reducing costs, exploring how to improve power while lowering costs simultaneously. Back-contact cells, with their unique electrode layout, concentrate the positive and negative grid lines on the back of the cell, avoiding optical losses caused by front electrode shading in traditional cell structures, thus significantly improving module power.

[0003] Back-contact photovoltaic modules include solar cells and conductive interconnects. The back surface of the solar cells has alternating P-type and N-type doped layers, with metal electrodes and conductive interconnects sequentially arranged on each doped layer. Existing technologies, when designing back-contact solar cells, only consider the insulation between the conductive interconnects and the opposite-polarity grid lines. This is achieved by using methods such as creating a disconnect region or insulating blocks between the conductive interconnects and the opposite-polarity grid lines to prevent short circuits.

[0004] However, the current design approach does not take into account the insulation problem between the conductive interconnect and the heteropolar doped layer, which can lead to leakage or short circuit problems when the conductive interconnect comes into contact with the heteropolar doped layer due to expansion and displacement during use. Summary of the Invention

[0005] The purpose of this invention is to provide a parameter design method for battery strings to solve at least one of the above-mentioned technical problems in the prior art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A method for designing parameters of a battery string, the battery string comprising a plurality of solar cells arranged sequentially along a first direction and a plurality of conductive interconnect strips extending along the first direction and respectively connected in series to the plurality of solar cells; Each of the solar cells includes a silicon substrate, and the back surface of the silicon substrate is provided with two doped layers of different polarities arranged alternately along a second direction. Each doped layer is provided with a metal electrode and the conductive interconnection band in sequence, and the second direction intersects the first direction. Along the second direction, the shortest spacing D between each conductive interconnect band and the adjacent, oppositely polar doped layer satisfies the formula:

[0007] In the formula, β is the safety factor for gap design, M is the distance between two adjacent solder joints on a single conductive interconnect strip, α is the coefficient of thermal expansion of the conductive interconnect strip, and ΔT is the difference between the highest and lowest temperatures of the conductive interconnect strip under extreme operating conditions.

[0008] During the use of photovoltaic modules, the temperature of the conductive interconnect strip often fluctuates significantly throughout the day due to the combined effects of ambient temperature and Joule heating. This causes the conductive interconnect strip to expand and shift due to thermal expansion and contraction. Particularly in the section between two solder joints of the conductive interconnect strip, because the two ends are fixed by welding and cannot extend freely, the middle of this section will bulge in an approximately arc shape towards either side of the conductive interconnect strip (in reality, probabilistically towards either side). This makes it easy for this part to shift onto adjacent, oppositely polar doped layers, leading to leakage or short circuit problems. Based on this issue, this application uses the small arch height calculation formula... (In the formula, S is the arc length of the protrusion between the two weld points, and h is the arch height) and ( This refers to the thermal expansion elongation of the portion between the two solder joints. The formula for calculating h is fitted. Theoretically, if D is greater than h, the conductive interconnect will not move onto the doped layer of the opposite polarity. Of course, in actual use, the conductive interconnect expands not only along its length but also laterally. Since the conductive interconnect is very narrow, the lateral expansion is much smaller than h. Therefore, the lateral expansion can be ignored, provided that a safety factor has already been included in the formula.

[0009] As mentioned above, when D satisfies the above formula, it can avoid the problem of leakage or short circuit caused by the conductive interconnect band moving to the doped layer of opposite polarity.

[0010] In some embodiments, the conductive interconnect strip may be a solder strip, a metal wire, or a metal foil.

[0011] In some embodiments: the value of β in the formula is: 2.5≤β≤30; And / or, the value of M in the formula is: 0.5mm≤M≤10mm; And / or, the value of α in the formula is: 15E-6 / °C≤α≤25E-6 / °C; And / or, the value of ΔT in the formula is: 20°C≤ΔT≤70°C.

[0012] The specific values ​​of β, M, α, and ΔT can be selected from the above-mentioned preferred ranges. The above ranges are merely preferred examples and are not strictly limited.

[0013] In some embodiments, D also satisfies the formula:

[0014] In the formula, L is the length of the solar cell along the second direction, and N is the total number of metal electrodes in a single solar cell.

[0015] If the value of D is too large, the locations where charge carriers are generated cannot be effectively collected, which will seriously affect the output power of the module. This application ensures the ability of the metal electrode to collect charge carriers by limiting the upper limit value of D, thereby avoiding power loss in the module.

[0016] In some embodiments, the value of L in the formula is: 125mm≤L≤220mm; In the formula, N takes the value of 20≤N≤120.

[0017] The specific values ​​of L and N can be selected from the above-mentioned preferred range. The above range values ​​are only preferred examples and are not strict limitations.

[0018] In some embodiments, D also satisfies the formula:

[0019] In the formula, γ is the electrical insulation design safety factor, 2.5≤γ≤30, U is the reverse breakdown voltage of the bypass channel of the solar cell, 3V≤U≤6V, and E is the dielectric strength of the encapsulation material of the photovoltaic module, 15kV / mm≤E≤50kV / mm.

[0020] The above technical solution limits the distance between the highest point of the protruding part of the conductive interconnect and the heteropolar doped layer. This distance needs to be greater than the thickness of the encapsulation material when it is broken down by the reverse electrode, so as to ensure the insulation between the conductive interconnect and the heteropolar doped layer.

[0021] In some embodiments, 0.05mm ≤ D ≤ 1mm.

[0022] The specific value of D can be selected from the above-mentioned optimal range. The above range values ​​are obtained by substituting commonly used parameters of the solar cell, and are not strictly limited.

[0023] In some embodiments, among the three doped layers that are sequentially adjacent along the second direction, the absolute value of the difference between the conductive interconnect band on the middle doped layer and the shortest spacing D between the other two doped layers is greater than or equal to 0 and less than or equal to 0.04 mm.

[0024] For a conductive interconnect with heteropolar doped layers on both sides, the shortest spacing D between the two adjacent heteropolar doped layers is equal to that of the conductive interconnect, with an allowable error range of 0 to 0.04 mm.

[0025] In some embodiments, in each solar cell, the gap between two adjacent doped layers forms an isolation region, the width of which is 30µm to 50µm.

[0026] The width of the isolation zone can be selected from the above-mentioned preferred range. The above range values ​​are preferred examples and are not strictly limited.

[0027] In some embodiments, the cross-sectional profile of the conductive interconnect strip is at least one of a circle, an oval, a waist-shaped shape, an ellipse, and a semi-circle.

[0028] The cross-section of the conductive interconnect strip is restricted to at least one of the following: circular, oval, waist-shaped, elliptical, and semi-circular. This makes the side of the conductive interconnect strip away from the solar cell an arc surface. This facilitates the flow of encapsulation material along the surface of the conductive interconnect strip to both sides of the conductive interconnect strip during the module lamination process, thereby ensuring that both sides of the conductive interconnect strip are completely filled with encapsulation material.

[0029] This application also provides a photovoltaic module, which includes the battery string described in any of the above claims.

[0030] The photovoltaic module provided in this application, by introducing the above formula in the early stage of design, can avoid leakage or short circuit problems caused by the conductive interconnect band moving onto the doped layer of opposite polarity, thereby improving the long-term reliability of the photovoltaic module and filling the technical gap in the industry that does not take into account the insulation problem between the conductive interconnect band and the doped layer of opposite polarity. Attached Figure Description

[0031] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the battery string structure provided in an embodiment of the present invention; Figure 2 A schematic diagram of the silicon substrate, doped layer, and metal electrode provided in an embodiment of the present invention; Figure 3 A schematic diagram of the silicon substrate, doped layer, metal electrode, and conductive interconnect band provided in an embodiment of the present invention; Figure 4 This is a schematic diagram showing the position of the conductive interconnect strip and the adjacent heteropolar doped region before and after thermal expansion and deformation, as provided in an embodiment of the present invention.

[0033] icon: 1-Solar cell; 11-Silicon substrate; 12-First doped layer; 13-Second doped layer; 14-Isolation region; 15-Metal electrode; 151-Bucket line; 152-Collector line; 153-Pad array; 2-Conductive interconnect strip. Detailed Implementation

[0034] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] It should be noted that in the description of this invention, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0036] It should be noted that in the description of this invention, the terms "connection" and "installation" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or a connection through an intermediate medium; they can refer to a mechanical connection or an electrical connection. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] Existing technologies, when designing back-contact solar cells, only consider the insulation between the conductive interconnect strip and the opposite-polarity grid lines. For example, they use methods such as setting disconnect regions or insulating blocks between the conductive interconnect strip and the opposite-polarity grid lines to prevent short circuits. However, during the use of photovoltaic modules, even with these structures, leakage and short circuits are still unavoidable.

[0038] The applicant's research revealed that conductive interconnects frequently shift due to thermal expansion. For example, during daytime operation, certain areas of the conductive interconnect may shift slightly to the left or right as the temperature rises, only to return to their original position at night when the temperature drops. This shift may cause the conductive interconnect to come into contact with the heteropolar doped layer, resulting in leakage or short circuits. This phenomenon cannot be avoided by increasing the spacing between the conductive interconnect and the heteropolar gate (i.e., reducing the gate length). Therefore, no matter how much the spacing between the conductive interconnect and the heteropolar gate is increased, leakage and short circuits remain unavoidable.

[0039] Based on the problems existing in the prior art, the first aspect of this application provides a battery string, referring to... Figures 1 to 4 The battery string includes several solar cells 1 arranged sequentially along a first direction and several conductive interconnecting strips 2 extending along the first direction and connected in series to the solar cells. Each solar cell 1 includes a silicon substrate 11, and the back surface of the silicon substrate 11 is provided with two doped layers of different polarities arranged alternately along a second direction. Each doped layer is provided with a metal electrode 15 and a conductive interconnecting strip 2 in sequence. The second direction intersects the first direction. Along the second direction, the shortest distance D between each conductive interconnecting strip 2 and the adjacent doped layer of opposite polarity satisfies the formula:

[0040] In the formula, β is the safety factor for gap design, M is the distance between two adjacent solder joints on a single conductive interconnect strip 2, α is the thermal expansion coefficient of the conductive interconnect strip 2, and ΔT is the difference between the highest and lowest temperatures of the conductive interconnect strip 2 under extreme operating conditions.

[0041] Specifically, each solar cell 1 includes a first doped layer 12 and a second doped layer 13. The first doped layer 12 and the second doped layer 13 have different polarities; for example, the first doped layer 12 is N-type doped and the second doped layer 13 is P-type doped, or vice versa. The first doped layer 12 and the second doped layer 13 are alternately arranged along a second direction on the back surface of the silicon substrate 11, and the gap between two adjacent doped layers forms an isolation region 14. A metal electrode 15 is provided on the upper layer of each doped layer.

[0042] The metal electrode 15 includes a bus electrode and a collector grid line 152. The bus electrode includes a bus grid line 151 and a pad array 153, or, the bus electrode only includes the pad array 153 and does not include the bus grid line 151 (i.e., a gridless cell). The bus electrode extends along a first direction. The collector grid line 152 extends along a second direction and is spaced apart along the first direction on one or both sides of the bus electrode, used to collect charge carriers. The pad array 153 consists of multiple pads arranged along the first direction, and conductive interconnects 2 are soldered onto the corresponding pad array 153. M is generally the spacing between two adjacent pads in a row of pad arrays 153; some conductive interconnects 2 are not soldered to some pads during serial soldering, therefore M is not necessarily the spacing between two adjacent pads. M needs to be selected in conjunction with the specific soldering method between the cell and the conductive interconnect 2.

[0043] Reference Figure 4 During the use of photovoltaic modules, the temperature of the conductive interconnect 2 typically fluctuates significantly throughout the day due to the combined effects of ambient temperature and Joule heating. This causes the conductive interconnect 2 to expand and shift due to thermal expansion and contraction. Particularly in the section between the two solder joints of the conductive interconnect 2, since the two ends are fixed by welding and cannot extend freely, the middle part is unrestrained and will probabilistically bulge in an approximately arc shape to either side of the conductive interconnect 2 when heated. This makes it easy for this part to shift onto adjacent, oppositely polar doped layers, leading to leakage or short circuit problems.

[0044] Based on these issues, this application uses the formula for calculating the small arch height. (In the formula, S is the arc length of the protrusion between the two weld points, and h is the arch height) and ( This refers to the thermal expansion elongation of the portion between the two solder joints. The formula for calculating h is fitted. Theoretically, if D is greater than h, the conductive interconnect 2 will not move onto the doped layer of the opposite polarity. Of course, in actual use, the conductive interconnect 2 expands not only along its length but also laterally. Since the conductive interconnect 2 is very narrow, the amount of lateral expansion is much smaller than h. Therefore, the amount of lateral expansion can be ignored, provided that the safety factor has already been included in the formula.

[0045] As can be seen from the preceding text, D satisfies This formula can prevent the conductive interconnect band 2 from moving onto the doped layer of the opposite polarity, which could lead to leakage or short circuit problems.

[0046] In some embodiments, the value of β in the formula is 2.5≤β≤30, for example, any value among 2.5, 4, 5, 8, 10, 15, 20, and 30.

[0047] In some embodiments, the value of M in the formula is: 0.5mm≤M≤10mm, for example, any value among 0.5 mm, 1mm, 2mm, 5mm, 5.6mm, and 10mm.

[0048] In some embodiments, the value of α in the formula is: 15E-6 / °C≤α≤25E-6 / °C, such as any value among 15E-6 / °C, 16E-6 / °C, 18E-6 / °C, 20E-6 / °C, and 55E-6 / °C.

[0049] In some embodiments, the value of ΔT in the formula is: 20°C≤ΔT≤70°C, for example, any value among 20°C, 30°C, 40°C, 50°C, 65°C, and 70°C.

[0050] The specific values ​​of β, M, α, and ΔT can be selected from the above-mentioned preferred ranges. The above ranges are only preferred examples and are not strictly limited. For example, β can also be 40, 50, 60, or higher; the larger β is, the less likely the conductive interconnect band 2 will move onto the heteropolar doped layer; however, a value of 30 for β is already safe enough, and further increasing it will not bring any beneficial effects.

[0051] In some embodiments, D also satisfies the formula:

[0052] In the formula, L is the length of the solar cell 1 along the second direction, and N is the total number of metal electrodes 15 in a single solar cell 1. It is approximately equal to the center-to-center distance between two adjacent conductive interconnects 2.

[0053] If the value of D is too large, the locations where charge carriers are generated cannot be effectively collected, which will seriously affect the output power of the module. This application ensures the charge carrier collection capability of the metal electrode 15 by limiting the upper limit value of D, thereby avoiding module power loss.

[0054] In some embodiments, the value of L in the formula is: 125mm≤L≤220mm, such as any value among 125mm, 166mm, 182mm, 210mm, and 220mm. The value of N in the formula is: 20≤N≤120, such as any value among 20, 30, 40, 80, 100, and 120.

[0055] The specific values ​​of L and N can be selected from the above-mentioned preferred range. The above range values ​​are only preferred examples and are not strict limitations.

[0056] In some embodiments, D also satisfies the formula:

[0057] In the formula, γ is the electrical insulation design safety factor, 2.5≤γ≤30, U is the reverse breakdown voltage of the bypass channel of solar cell 1, 3V≤U≤6V, and E is the dielectric strength of the encapsulation material of the photovoltaic module, 15kV / mm≤E≤50kV / mm.

[0058] The above technical solution limits the spacing between the highest point of the protruding portion of the conductive interconnect and the heteropolar doped layer. This spacing needs to be greater than the thickness of the encapsulation material when it is broken down by the reverse electrode, thus ensuring the insulation between the conductive interconnect 2 and the heteropolar doped layer. γ can also be 40, 50, 60, or higher; however, a value of 30 is already sufficiently safe, and further increasing it will not bring any beneficial effects.

[0059] In some embodiments, 0.05mm ≤ D ≤ 1mm, for example, any value among 0.05mm, 0.1mm, 0.15mm, 0.2mm, 0.3mm, 0.4mm, 0.6mm, 0.8mm, and 1mm. The specific value of D can be selected from the above preferred range. The above range values ​​are obtained by substituting commonly used parameters of solar cells and are not strictly limited.

[0060] In some embodiments, among three sequentially adjacent doped layers along the second direction, the absolute value of the difference between the conductive interconnection band 2 on the middle doped layer and the shortest spacing D between the other two doped layers is greater than or equal to 0 and less than or equal to 0.04 mm.

[0061] For the conductive interconnect 2 with heteropolar doped layers on both sides, the conductive interconnect 2 is equal to the shortest spacing D of the two adjacent heteropolar doped layers, and an error range of 0~0.04mm is allowed. For example, in... Figure 4 In the conductive interconnect 2 shown, the conductive interconnect 2 is disposed on the corresponding first doped layer 12. The shortest distance D between the conductive interconnect 2 and the two adjacent second doped layers 13 is equal, with an allowable error range of 0~0.04mm. For example, the theoretical design value of the shortest distance D between a certain conductive interconnect 2 and the two adjacent opposite polarity doped layers is 0.07mm; due to processing errors, the actual shortest distance D between the conductive interconnect 2 and the two adjacent opposite polarity doped layers is 0.05mm and 0.09mm, respectively, with a processing error of 0.04mm between these two shortest distance D values. It should be noted that the size range of 0.05mm≤D≤1mm is not the theoretical design range, but the actual size range after processing.

[0062] In some embodiments, in each solar cell 1, the gap between two adjacent doped layers forms an isolation region 14, and the width of the isolation region 14 is 30µm to 50µm. The width of the isolation region 14 can be selected from the above-mentioned preferred range. The above range values ​​are preferred examples and are not strictly limited.

[0063] In some embodiments, the cross-sectional profile of the conductive interconnect strip 2 is at least one of a circle, an oval, a waist-shaped shape, an ellipse, and a semicircle. By restricting the cross-section of the conductive interconnect strip 2 to at least one of a circle, an oval, a waist-shaped shape, an ellipse, and a semicircle, the side of the conductive interconnect strip 2 away from the solar cell 1 is an arc surface. This facilitates the flow of encapsulation material along the surface of the conductive interconnect strip 2 to both sides of the conductive interconnect strip 2 during the module lamination process, thereby ensuring that both sides of the conductive interconnect strip 2 are completely filled with encapsulation material.

[0064] A second aspect of this application provides a photovoltaic module comprising the battery string provided in any of the above embodiments.

[0065] The photovoltaic module provided in this application, by introducing the above formula in the early stage of design, can avoid leakage or short circuit problems caused by the conductive interconnect band 2 moving to the opposite polarity doped layer, thereby improving the long-term reliability of the photovoltaic module and filling the technical gap in the industry that does not take into account the insulation problem between the conductive interconnect band 2 and the opposite polarity doped layer.

[0066] Performance Test 1 Ten solar cells 1 with conductive interconnecting strips 2 were selected as test samples. Each test sample consisted of three identical solar cells 1 connected in series by the conductive interconnecting strips 2. The difference between the test samples was the value of D. According to international standards such as IEC 61215, each sample was subjected to thermal cycling (TC) treatment, and then the leakage current of each sample before and after the thermal cycling was measured.

[0067] Test method: The samples were subjected to TC treatment, and the temperature change of conductive interconnect 2 during the TC treatment process was ΔT; the electrical performance of each of the above test samples was tested by IV test (AM1.5G), and the leakage current Irev of the test samples before and after TC treatment was measured.

[0068] The test results are shown in Table 1.

[0069] Table 1

[0070] As shown in Table 1, when D is 0.05 mm or above, the leakage current of the solar cell does not increase significantly after TC cycling. When D is less than 0.05 mm, the conductive interconnect band deforms and comes into contact with the heteropolar doped layer during TC cycling, damaging the surface insulating passivation layer and causing the leakage current of the solar cell to increase significantly.

[0071] Performance Test 2 Eight groups of photovoltaic modules were selected as test samples, with the difference between each group being the value of D. The electrical performance of each group of test samples was tested using IV testing (test conditions 25℃, AM1.5G).

[0072] The test results are shown in Table 2.

[0073] Table 2

[0074] As shown in Table 2, when D exceeds 1 mm (i.e., greater than...), When D does not exceed a certain value, the component power drops significantly. This ensures the carrier collection capability of the gate lines and avoids power loss in the components.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for designing parameters of a battery string, characterized in that, The battery string includes a plurality of solar cells (1) arranged sequentially along a first direction and a plurality of conductive interconnecting strips (2) extending along the first direction and respectively connected in series to the plurality of solar cells (1); each solar cell (1) includes a silicon substrate (11), and the back surface of the silicon substrate (11) is provided with two doped layers of different polarities arranged alternately along a second direction, and each doped layer is provided with a metal electrode (15) and the conductive interconnecting strip (2) in sequence, the second direction intersecting the first direction; The parameter design method for the battery string includes: Along the second direction, the shortest spacing D between each of the conductive interconnects (2) and the adjacent, oppositely polar doped layer satisfies the formula: In the formula: β is the safety factor for gap design, 2.5≤β≤30; M is the distance between two adjacent solder joints on a single conductive interconnect strip (2), 0.5mm≤M≤10mm; α is the coefficient of thermal expansion of the conductive interconnect strip (2), 15E-6 / °C≤α≤25E-6 / °C; ΔT is the difference between the highest and lowest temperature of the conductive interconnect strip (2) under extreme working conditions, 20°C≤ΔT≤70°C.

2. The parameter design method for the battery string according to claim 1, characterized in that, The D also satisfies the formula: In the formula, L is the length of the solar cell (1) along the second direction, and N is the total number of metal electrodes (15) of a single solar cell (1).

3. The parameter design method for the battery string according to claim 2, characterized in that, In the formula, the value of L is: 125mm≤L≤220mm; And / or, the value of N in the formula is: 20≤N≤120.

4. The parameter design method for the battery string according to claim 1, characterized in that, The D also satisfies the formula: In the formula, For electrical insulation design safety factor, 2.5 ≤ ≤30, U is the reverse breakdown voltage of the bypass channel of the solar cell (1), 3V≤U≤6V, E is the dielectric strength of the encapsulation material of the photovoltaic module, 15kV / mm≤E≤50kV / mm.

5. The parameter design method for the battery string according to claim 1, characterized in that, 0.05mm≤D≤1mm.

6. The parameter design method for the battery string according to claim 1, characterized in that, In the three doped layers that are sequentially adjacent along the second direction, the absolute value of the difference between the conductive interconnect band (2) on the middle doped layer and the shortest distance D between the other two doped layers is greater than or equal to 0 and less than or equal to 0.04 mm.

7. The parameter design method for the battery string according to claim 1, characterized in that, In each of the solar cells (1), the gap between two adjacent doped layers forms an isolation region (14), the width of which is 30um to 50um.

8. The parameter design method for the battery string according to claim 1, characterized in that, The cross-sectional profile of the conductive interconnect strip (2) is at least one of the following: circular, oval, waist-shaped, elliptical, and semi-circular.

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