A back contact cell assembly and a method of manufacturing the same

Abstract

The present application relates to the technical field of photovoltaic cells, and particularly relates to a back contact cell module and a preparation method thereof. The preparation method of the back contact cell module comprises the following steps: depositing N zone passivation layer and P zone passivation layer on the back surface of a silicon wafer by using a partitioned passivation deposition process; etching the N zone passivation layer and the P zone passivation layer to form an interdigital PN junction electrode pattern; then performing electrode printing; wherein the interdigital distance of the PN junction is 50-60 mu m, and the electrode width is 20-30 mu m; after the electrode printing, annealing treatment is performed to obtain a cell wafer; the cell wafer is welded with a solder strip by using a hidden main grid series welding process, the exposed bus bar is cancelled, and a hidden interconnection wire is used; full-screen laminated packaging is performed by using a full-screen laminated packaging process to obtain the back contact cell module. The present application is optimized from three aspects of the back contact cell structure, the overall structure of the module and the conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and in particular to a back-contact cell module and its preparation method. Background Technology

[0002] Back-contact (BC) solar modules have the advantages of no main grid on the front and fine grid shading, which maximizes the utilization of incident sunlight and is one of the mainstream technologies for high-efficiency photovoltaic modules. Currently, mass-produced BC solar modules are mainly divided into four major technology paths: IBC (interdigitated back contact), HPBC (hybrid back contact), TBC (TOPCon+BC), and HBC (heterojunction+BC).

[0003] The current mass production of BC battery modules avoids front optical obstruction by arranging the back electrode, improves the passivation effect of the battery by relying on the multi-layer passivation structure, and shortens the carrier transport path by using multi-busbar or busbarless design. Theoretically, it has the potential to approach the theoretical efficiency limit of crystalline silicon batteries. However, due to limitations in mass production process precision, structural design defects and material loss, there is a large gap between the actual mass production efficiency and the theoretical value. Moreover, there are technical bottlenecks in cost, yield and reliability that urgently need to be solved.

[0004] Currently, the large-scale mass production of BC battery modules suffers from several inherent defects, directly hindering the improvement of conversion efficiency and large-scale promotion. These defects are as follows: The structural defects of the battery are as follows: First, the design of the interdigitation distance and electrode width of the PN junction on the back of the existing BC battery is unreasonable, resulting in an excessively long carrier collection path and high surface recombination loss and series resistance loss. Second, the passivation film adopts a one-step co-deposition process, and the passivation layer parameters of the P-region and N-region are designed in a compromise manner, which cannot achieve the optimal passivation effect of the two regions. The uniformity of the tunneling oxide layer is poor, the local leakage rate is high, and the carrier recombination rate is fast. Third, the contact barrier between the metallized electrode and the silicon wafer is high, the adhesion between the silver paste and the silicon wafer is insufficient, the contact resistance is relatively large, and the current transmission loss is significant.

[0005] Overall structural defects in the module: First, there are shortcomings in the cell stringing process. Conventional MBB stringing suffers from issues such as solder ribbons obstructing the back light-receiving area and a high rate of poor soldering. Although OBB stringing does not have main grid obstruction, the bonding force between the copper solder ribbon and the silver grid is poor, resulting in insufficient module reliability. Second, the proportion of ineffective areas inside the module is high. The gaps between cells and the busbar occupy a large area, and these areas cannot participate in photoelectric conversion, reducing the overall effective light-receiving area of ​​the module. Third, the matching degree of the encapsulation layer is poor. Conventional encapsulation films are not well adapted to the back electrodes of BC cells, and electrode displacement and film bubbles are prone to occur during the lamination process, affecting the electrical performance of the module. Fourth, the bifaciality is low. Conventional BC modules have low bifaciality and poor back-side low-light response capability, limiting the actual outdoor power generation.

[0006] Defects in conversion efficiency: Due to the combined effects of the above-mentioned structural and process defects, the conversion efficiency of existing mass-produced BC battery modules has been hindered; in terms of optical loss, the reflectivity of the front antireflection layer is too high, and the utilization rate of incident light is insufficient; in terms of electrical loss, the carrier collection efficiency is low, and the open-circuit voltage and short-circuit current are both lower than the theoretical values; at the same time, the consumption of silver paste is high and the cost remains high.

[0007] Mass production process defects: insufficient laser patterning precision, large etching edge roughness, resulting in severe edge recombination of solar cells; large fluctuations in production yield; and high equipment investment.

[0008] In view of this, the present invention is hereby proposed. Summary of the Invention

[0009] The primary objective of this invention is to provide a method for preparing a back-contact battery module, thereby overcoming the shortcomings of existing mass-produced back-contact battery modules and comprehensively optimizing the back-contact battery structure, the overall module structure, and the conversion efficiency.

[0010] A second objective of the present invention is to provide a back-contact battery assembly.

[0011] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: This invention provides a method for preparing a back-contact battery assembly, comprising the following steps: S1. Texturing the front side of the silicon wafer; S2. An N-region passivation layer and a P-region passivation layer are deposited on the back side of the silicon wafer using a partitioned passivation deposition process. S3. Etch the N-region passivation layer and the P-region passivation layer to form an interdigitated PN junction electrode pattern; then perform electrode printing; wherein the PN junction interdigitation spacing of the interdigitated PN junction electrode pattern is 50~60μm and the electrode width is 20~30μm. S4. After the electrodes are printed, they are annealed to obtain the battery cell. S5. It adopts a hidden busbarless string welding process to weld the solder strip and the battery cell, eliminating the exposed busbar and using invisible interconnecting wires; S6. The back contact battery assembly is obtained by laminating and encapsulating the battery using a full-screen lamination process.

[0012] Furthermore, step S1 includes at least one of the following features (1) to (3); (1) The silicon wafer includes an N-type monocrystalline silicon wafer, wherein the resistivity of the N-type monocrystalline silicon wafer is 1~3 Ω·cm and the oxygen content is ≤1×10 18 atoms / cm 3 ; (2) The flocking process includes: forming a positive pyramidal flocked surface by alkaline flocking, wherein the height of the positive pyramidal flocked surface is 3~5μm; (3) The roughness Ra of the silicon wafer after texturing is ≤0.2μm.

[0013] Further, in step S2, the partitioned passivation deposition process includes: sequentially depositing a first tunneling oxide layer and a phosphorus-doped polysilicon layer in the N region on the back side of the silicon wafer; and sequentially depositing a second tunneling oxide layer and a boron-doped polysilicon layer in the P region on the back side of the silicon wafer. The thickness of the first tunneling oxide layer is 1.2~1.5 nm, the thickness of the phosphorus-doped polycrystalline silicon layer is 15~20 nm, and the phosphorus doping concentration of the phosphorus-doped polycrystalline silicon layer is 1.5 × 10⁻⁶. 20 ~3×10 20 atoms / cm 3 The thickness of the second tunneling oxide layer is 1.0~1.2 nm, the thickness of the boron-doped polysilicon layer is 12~18 nm, and the boron doping concentration of the boron-doped polysilicon layer is 1×10⁻⁶. 20 ~2×10 20 atoms / cm 3 .

[0014] Furthermore, in step S3, femtosecond laser etching is used for etching, with an etching accuracy of ±1μm and an edge roughness of ≤0.5μm.

[0015] Further, in step S3, the electrode printing includes printing on a steel plate using silver paste; the silver paste, by mass percentage, includes: 88%~92% spherical silver powder, 3%~5% nano-silver particles with a particle size of 50~200nm, 2%~3.5% glass powder, and 2.5%~4% organic carrier.

[0016] Further, in step S4, the annealing process includes: holding at 450±5℃ for 8~10 min, then raising the temperature to 550±5℃ and holding for 10~12 min, and then raising the temperature to 650±5℃ and holding for 12~18 min.

[0017] Further, in step S5, the solder strip is a tin-plated copper alloy solder strip with a width of 0.2±0.05mm and a thickness of 0.02~0.04mm; And / or, in step S5, the welding includes infrared welding, wherein the temperature of the infrared welding is 180~200℃ and the pressure is 0.1~0.15MPa.

[0018] Furthermore, in step S6, the welded solar cells are arranged with a gap of 0.08~0.1mm between adjacent solar cells; And / or, in step S6, the encapsulation material of the laminated encapsulation includes tempered glass, POE film, and backplate.

[0019] Further, in step S6, the lamination temperature of the lamination encapsulation is 145~150℃, the lamination pressure is 80~90kPa, and the lamination time is 12~15min.

[0020] The present invention also provides a back contact battery assembly, which is prepared by the back contact battery assembly preparation method described above.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention abandons the traditional one-step passivation film deposition process and adopts a two-step partitioned passivation deposition technology. Passivation layer parameters are set separately for the P-region and N-region, optimizing the thickness and uniformity of the tunneling oxide layer and controlling the local leakage rate to below 0.3%. Simultaneously, the interdigitation distance and electrode width of the back-side PN junction are finely adjusted to shorten the carrier collection path and reduce the surface recombination rate; the metallized electrode formulation and contact structure are optimized to effectively reduce the contact resistance between the electrode and the silicon wafer, improving carrier collection efficiency. Furthermore, the battery edge passivation process is optimized to eliminate edge recombination losses and effectively improve the battery open-circuit voltage.

[0022] 2. This invention adopts a busbar-less hidden stringing structure, eliminating the traditional exposed busbars and hiding the interconnecting wires in the gaps on the back of the cells, maximizing the effective light-receiving area of ​​the module; it optimizes the busbar-less stringing process, improves the solder ribbon material and surface coating, and achieves a high-strength alloyed connection between the copper solder ribbon and the silver grid, eliminating the problems of poor soldering and over-soldering; it adopts a full-screen encapsulation design, reducing the gaps between cells and reducing the proportion of ineffective areas of the module to below 1.2%; it adapts to high-transmittance, low-loss encapsulation materials and optimizes lamination process parameters to improve the module encapsulation yield and reliability; at the same time, it optimizes the back passivation and light transmission design, increasing the module bifaciality to over 80% and enhancing low-light response performance.

[0023] 3. This invention simultaneously reduces optical and electrical losses through structural optimization and process improvement: the front anti-reflection passivation layer structure is optimized to reduce the front reflectivity to below 1.5%, thereby improving the utilization rate of incident light; through partitioned passivation and electrode optimization, the carrier collection efficiency is increased to over 98%, and the series resistance is reduced to below 0.4 mΩ·cm²; the amount of silver paste consumed is reduced, while the cell fill factor is increased, breaking through the current mass production efficiency bottleneck and achieving a module conversion efficiency of ≥25.2%, while taking into account mass production yield and cost control, thus achieving a dual improvement in efficiency and cost-effectiveness. Detailed Implementation

[0024] The technical solution of the present invention will be clearly and completely described below with specific embodiments. However, those skilled in the art will understand that the embodiments described below are some embodiments of the present invention, not all embodiments, and are only used to illustrate the present invention, and should not be regarded as limiting the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall be followed. Where the manufacturers of reagents or instruments are not specified, they are all conventional products that can be purchased commercially.

[0025] In some embodiments of the present invention, a method for preparing a back-contact battery assembly is provided, comprising the following steps: S1. Texturing the front side of the silicon wafer; S2. An N-region passivation layer and a P-region passivation layer are deposited on the back side of the silicon wafer using a partitioned passivation deposition process. S3. Etch the N-region passivation layer and the P-region passivation layer to form an interdigitated PN junction electrode pattern; then perform electrode printing; wherein, the PN junction interdigitation spacing of the interdigitated PN junction electrode pattern is 50~60μm, and the electrode width is 20~30μm. S4. After electrode printing, annealing is performed to obtain the battery cell; S5. It adopts a hidden busbarless string welding process to weld the solder strip and the battery cell, eliminating the exposed busbar and using invisible interconnecting wires; S6. The back contact battery assembly is obtained by laminating and encapsulating the battery using a full-screen lamination process.

[0026] The method for fabricating a back-contact battery module of the present invention includes a two-step process of partition passivation and refined electrode fabrication at the battery end, and a complete process of hidden OBB-less string bonding and full-screen lamination encapsulation at the module end.

[0027] Existing passivation films for back-contact batteries employ a one-step co-deposition process, with compromises in the passivation layer parameters for the P-region and N-region, failing to achieve optimal passivation performance for both regions. This invention abandons the traditional one-step co-deposition process and adopts a two-step, zoned passivation deposition technique, setting passivation layer parameters separately for the P-region and N-region, thus achieving independent optimal passivation performance for each region.

[0028] Existing back-contact batteries typically have a back-junction interdigitation distance of 80-120 μm and an electrode width of 40-60 μm, resulting in an excessively long carrier collection path and high surface recombination and series resistance losses. This invention finely adjusts the back-contact PN junction interdigitation distance to 50-60 μm and the electrode width to 20-30 μm, shortening the carrier collection path and reducing the surface recombination rate.

[0029] Existing back-contact battery module cell stringing processes have shortcomings. Conventional MBB stringing suffers from issues such as solder ribbons obscuring the back-side light-receiving area and a high rate of incomplete or over-soldering connections (approximately 3%–5%). This invention employs a busbar-less, hidden stringing structure, eliminating traditional exposed busbars and concealing the interconnecting wires within the gaps on the back of the cells, maximizing the effective light-receiving area of ​​the module. It also optimizes the busbar-less stringing process, achieving a high-strength alloyed connection between the solder ribbons and the silver grid, thus eliminating incomplete or over-soldering problems.

[0030] This invention employs a full-screen encapsulation design to reduce the gap between battery cells and decrease the proportion of ineffective areas in the module; it maximizes the compression of ineffective areas and improves the overall efficiency of the module.

[0031] In some embodiments of the present invention, in step S1, the silicon wafer includes an N-type monocrystalline silicon wafer, the resistivity of which is 1~3 Ω·cm (e.g., 1 Ω·cm, 2 Ω·cm, or 3 Ω·cm, etc.), and the oxygen content is ≤1×10⁻⁶. 18 atoms / cm 3 It uses N-type high-resistivity, low-oxygen monocrystalline silicon wafers.

[0032] In some embodiments of the present invention, step S1 includes: forming a positive pyramidal pile surface using an alkaline pile method, wherein the height of the positive pyramidal pile surface is 3~5μm (e.g., 3μm, 4μm or 5μm, etc.); and improving the light trapping effect on the front side through the pile process.

[0033] In some embodiments of the present invention, in step S1, the roughness Ra of the silicon wafer after texturing is ≤0.2μm.

[0034] In some embodiments of the present invention, step S2, the partition passivation deposition process includes: sequentially depositing a first tunneling oxide layer and a phosphorus-doped polysilicon layer in the N region on the back side of the silicon wafer, and sequentially depositing a second tunneling oxide layer and a boron-doped polysilicon layer in the P region on the back side of the silicon wafer.

[0035] In some embodiments of the present invention, step S2, the partitioned passivation deposition process, specifically includes the following steps: N-region passivation layer deposition: The first tunneling oxide layer and the phosphorus-doped polycrystalline silicon layer are sequentially deposited on the back side of the silicon wafer using low-pressure chemical vapor deposition (LPCVD); the deposition temperature is 600~620℃, and the uniformity error of the deposited film layer is ≤±0.1nm; Depositing the P-region passivation layer: The N-region passivation layer on the P-region of the back side of the silicon wafer is removed by laser etching (ultrafast laser selective etching), and then a second tunneling oxide layer and a boron-doped polysilicon layer are deposited sequentially on the P-region. The deposition temperature is 600~620℃, and the uniformity error of the deposited film is ≤±0.1nm. Preferably, the first tunneling oxide layer comprises SiO2 with a thickness of 1.2~1.5 nm (e.g., 1.2 nm, 1.3 nm, 1.4 nm, or 1.5 nm, etc.); the phosphorus doping concentration of the phosphorus-doped polycrystalline silicon layer is 1.5 × 10⁻⁶. 20 ~3×10 20 atoms / cm 3 (For example, 1.5 × 10) 20 atoms / cm 3 2×10 20 atoms / cm 3 2.5×10 20 atoms / cm 3 Or 3×10 20 atoms / cm 3 wait); The second tunneling oxide layer comprises SiO2 with a thickness of 1.0~1.2 nm (e.g., 1.0 nm, 1.1 nm, or 1.2 nm, etc.); the boron doping concentration of the boron-doped polycrystalline silicon layer is 1×10⁻⁶. 20 ~2×10 20 atoms / cm 3 (For example, 1×10) 20 atoms / cm 3 1.5×10 20 atoms / cm 3 Or 2×10 20 (atoms / cm, etc.).

[0036] Conventional back-contact batteries employ a one-step co-deposition process for passivation films, with a compromise design for passivation layer parameters in the P and N regions. This approach fails to achieve optimal passivation performance in both regions, resulting in poor uniformity of the tunneling oxide layer, local leakage rates as high as 1.2% to 1.8%, and rapid carrier recombination rates. This invention abandons the traditional one-step co-deposition process and adopts a two-step partitioned passivation deposition technique. It sets passivation layer (tunneling oxide layer and doped polysilicon layer parameters) parameters separately for the P and N regions, enabling independent optimization of passivation performance in the P and N regions. This avoids the compromise design for passivation performance, optimizes the thickness and uniformity of the tunneling oxide layer, reduces carrier recombination losses and local leakage rates, and controls the local leakage rate below 0.3%.

[0037] In some embodiments of the present invention, in step S3, femtosecond laser etching is used for etching, with an etching accuracy of ±1μm and an edge roughness of ≤0.5μm. Pattern optimization of the back electrode is specifically included: back electrode pattern optimization: femtosecond laser etching is used to etch the N-region passivation layer and P-region passivation layer on the back of the silicon wafer. The etching purpose is to create metal contact holes, with an etching accuracy of ±1μm and an edge roughness of ≤0.5μm (to eliminate edge recombination). The PN junction interdigitation distance is 50~60μm (e.g., 50μm, 55μm, or 60μm), and the electrode width is 20~30μm (e.g., 20μm, 25μm, or 30μm).

[0038] The refined patterned design of the back electrode, the femtosecond laser etching process, the PN junction interdigitation spacing of 50~60μm, and the electrode width of 20~30μm work together to shorten the carrier collection path and eliminate edge recombination loss.

[0039] Existing back-contact batteries typically have a back-side PN junction interdigitation distance of 80-120 μm and an electrode width of 40-60 μm, resulting in an excessively long carrier collection path and high surface recombination and series resistance losses. This invention shortens the carrier collection path and reduces the surface recombination rate by finely adjusting the back-side PN junction interdigitation distance and electrode width.

[0040] The existing laser patterning process in the fabrication of back contact batteries has insufficient precision and large roughness at the etched edges, resulting in severe recombination at the battery cell edges. This invention optimizes the battery edge etching process, eliminates edge recombination losses, and improves the battery open-circuit voltage.

[0041] In some embodiments of the present invention, step S3, electrode printing includes printing on a steel plate using silver paste; the silver paste, by mass percentage, comprises: 88%~92% spherical silver powder (e.g., 88%, 90%, or 92%), 3%~5% nano-silver particles with a particle size of 50~200nm (e.g., 3%, 4%, or 5%), 2%~3.5% glass powder (e.g., 2%, 2.5%, 3%, or 3.5%), and 2.5%~4% organic carrier (e.g., 2.5%, 3%, 3.5%, or 4%); preferably, the glass powder comprises PbO-B2O3-SiO2 based glass powder, the organic carrier comprises terpineol and / or ethyl cellulose, and the particle size of the spherical silver powder is >200nm, generally 0.5~5μm. The addition of nano-silver particles and glass powder to the silver paste improves electrode adhesion and conductivity.

[0042] Existing back-contact batteries have a high interface barrier between the metallized electrode and the silicon wafer, insufficient adhesion between the silver paste and the silicon wafer, and relatively high contact resistance, with a series resistance typically ranging from 0.8 to 1.2 mΩ·cm. 2The current transport loss is significant. This invention optimizes the metallized electrode formulation and contact structure to reduce the contact resistance between the electrode and the silicon wafer, thereby improving carrier collection efficiency.

[0043] In some embodiments of the present invention, step S4, the annealing treatment includes: holding at 450±5℃ for 8~10 min, then raising the temperature to 550±5℃ and holding for 10~12 min, then raising the temperature to 650±5℃ and holding for 12~18 min; preferably, the total annealing time is 30~40 min; the annealing treatment is carried out under a mixed gas of nitrogen and oxygen, wherein the volume percentage of oxygen in the mixed gas is 0.1%~1%. A gradient annealing process is used for annealing and activation, with the temperature controlled in segments at 450±5℃, 550±5℃, and 650±5℃, and the total annealing time is 30~40 min, repairing film damage, reducing carrier recombination rate, and achieving a minority carrier lifetime of ≥3ms after annealing.

[0044] In some embodiments of the present invention, step S5, before the hidden gridless stringing process, also includes cell sorting; using non-contact photoelectric testing equipment, the sorting efficiency is ≥6000 cells / h, and cells with efficiency lower than 26.8% and leakage rate exceeding the standard are rejected to ensure the consistency of individual cells.

[0045] In some embodiments of the present invention, in step S5, the solder strip is a tin-plated copper alloy solder strip with a width of 0.2±0.05mm (e.g., 0.2mm) and a thickness of 0.02~0.04mm (e.g., 0.03mm).

[0046] In some embodiments of the present invention, in step S5, the welding includes infrared welding, the temperature of which is 180~200°C (e.g., 180°C, 190°C or 200°C, etc.) and the pressure is 0.1~0.15MPa (e.g., 0.1MPa, 0.13MPa or 0.15MPa, etc.).

[0047] Hidden gridless (OBB) stringing process: tin-plated copper alloy solder strips are used, with a width of 0.2mm and a thickness of 0.03mm. Low-temperature infrared welding is employed, with a welding temperature of 180~200℃ and a welding pressure of 0.1~0.15MPa, achieving seamless bonding between the solder strip and the silver grid, reducing the rate of poor soldering to below 0.2%. Exposed busbars are eliminated, and invisible interconnecting wires are used on the back, embedded inside the POE film, without occupying the light-receiving area. Flat fine wires and segmented dot-matrix interconnects are used, all embedded inside the POE film, running along the cell gaps and densely arranged along the direction of the cell grid.

[0048] The module-side concealed 0BB busbar-free string soldering process employs low-temperature infrared welding and invisible interconnect wire design, eliminating exposed busbars, removing the risk of solder strip obstruction and poor soldering, and improving the effective light-receiving area of ​​the module and welding reliability.

[0049] Existing cell stringing processes have shortcomings. Conventional MBB stringing suffers from issues such as solder ribbon obstructing the back-side light-receiving area and a high rate of incomplete or over-soldering (approximately 3%–5%). While OBB stringing eliminates the main busbar obstruction, the poor bonding strength between the copper solder ribbon and the silver grid results in insufficient module reliability. This invention employs a busbar-less, hidden stringing structure, eliminating traditional exposed busbars and concealing the interconnecting wires within the gaps on the back of the cells, maximizing the effective light-receiving area of ​​the module. The OBB stringing process is optimized by improving the solder ribbon material and surface coating, achieving a high-strength alloyed connection between the copper solder ribbon and the silver grid, thus eliminating incomplete or over-soldering issues.

[0050] In some embodiments of the present invention, in step S6, the welded battery cells are arranged with a gap of 0.08~0.1mm between adjacent battery cells (e.g., 0.08mm, 0.09mm or 0.1mm, etc.); that is, the gap between the cells in the full-screen dense arrangement is 0.08~0.1mm.

[0051] The full-screen lamination encapsulation process uses a narrow gap design of 0.08~0.1mm between cells, combined with highly adaptable POE film and lamination parameters, to maximize the compression of ineffective areas and improve the overall efficiency of the module.

[0052] Existing back-contact battery modules have a high proportion of ineffective areas, with gaps between cells and busbars occupying 7% to 9% of the area. These areas cannot participate in photoelectric conversion, reducing the overall effective light-receiving area of ​​the module. This invention adopts a full-screen encapsulation design, reducing the gap between cells to within 0.1mm and lowering the proportion of ineffective areas to below 1.2%.

[0053] In some embodiments of the present invention, in step S6, the encapsulation material for lamination includes tempered glass, POE film and backplate; the light transmittance of the tempered glass is ≥93.5%, which is high-transmittance tempered glass; the POE film is a low-loss POE film, and the backplate is a high-transmittance backplate.

[0054] In some embodiments of the present invention, in step S6, the lamination temperature of the lamination encapsulation is 145~150°C (e.g., 145°C, 147°C, or 150°C, etc.), the lamination pressure is 80~90 kPa (e.g., 80 kPa, 85 kPa, 90 kPa, etc.), and the lamination time is 12~15 min (e.g., 12 min, 13 min, 14 min, 15 min, etc.).

[0055] Full-screen lamination encapsulation process: High-transmittance tempered glass (transmittance ≥93.5%), POE low-loss encapsulant film and high-transmittance backplane are used as encapsulation materials. The gap between cells (gap between cells in full-screen dense layout) is 0.08~0.1mm, the lamination temperature is 145~150℃, the lamination pressure is 80~90kPa, the lamination time is 12~15min, lamination bubbles and electrode displacement are eliminated, and the proportion of ineffective area of ​​the module is ≤1.2%.

[0056] Existing back-contact battery castings suffer from poor encapsulation layer matching. Conventional encapsulants are not well-suited to the back electrodes of the back-contact battery, leading to electrode displacement and film bubbles during lamination, which negatively impacts module electrical performance. Furthermore, the bifaciality is low, typically only 65%–70% in conventional modules, resulting in poor low-light response and limiting actual outdoor power generation. This invention adapts to high-transmittance, low-loss encapsulation materials, optimizes lamination process parameters, and improves module encapsulation yield and reliability. Simultaneously, it optimizes back-side passivation and light transmission design, increasing the module bifaciality to over 80% and enhancing low-light response performance.

[0057] In some embodiments of the present invention, after lamination and encapsulation, step S6 further includes: installing a lightweight alloy frame and welding a waterproof junction box. The present invention does not strictly limit this step; conventional processes can be used.

[0058] Existing back-contact battery modules have the following performance characteristics: In terms of conversion efficiency, the module efficiency is approximately 24.5%; in terms of optical loss, the reflectivity of the front antireflection layer is relatively high (approximately 3%~4%), resulting in insufficient utilization of incident light; in terms of electrical loss, the carrier collection efficiency is only 92%~94%, and both open-circuit voltage and short-circuit current are lower than theoretical values; in terms of manufacturing process, the consumption of silver paste is high, resulting in high costs, and every 0.1% increase in mass production efficiency requires significant process modification costs, leading to low cost-effectiveness; the laser patterning precision is insufficient, resulting in large etching edge roughness and severe edge recombination of the cells; the production yield fluctuates greatly, and the yield of new production lines needs 3~6 months to stabilize above 90%; equipment investment is high, with laser etching and high-precision printing equipment requiring an investment of over 50 million yuan per GW, about 5 times that of TOPCon modules, making industry promotion difficult. This invention simultaneously reduces optical and electrical losses through structural optimization and process improvement: The optimized front-side anti-reflective passivation layer structure reduces front-side reflectivity to below 1.5%, improving incident light utilization; through partitioned passivation and electrode optimization, carrier collection efficiency is increased to over 98%, and series resistance is reduced to below 0.4 mΩ·cm²; silver paste consumption is reduced while increasing the cell fill factor, breaking through existing mass production efficiency bottlenecks and achieving a module conversion efficiency ≥25.2%, while simultaneously considering mass production yield and cost control, achieving a dual improvement in efficiency and cost-effectiveness. Specific advantages are as follows: Significantly improved conversion efficiency: Through triple optimization of partitioned passivation deposition, refined electrodes, and full-screen lamination encapsulation, the module conversion efficiency can reach over 25.2%, which is 0.7%~1.0% higher than existing mass-produced back-contact battery modules. The single-cell conversion efficiency can reach over 27.2%, approaching the theoretical efficiency limit of crystalline silicon batteries, and the photoelectric conversion performance is significantly improved.

[0059] Significantly reduced electrical losses and improved power generation performance: By optimizing the passivation structure and electrode contact interface, compared with existing mass-produced back-contact battery modules, the series resistance is reduced by more than 50%, the carrier collection efficiency is increased to more than 98%, the open-circuit voltage is increased by 3~5mV, the short-circuit current is increased by 0.1~0.2A, and the fill factor is increased by 2%~3%. At the same time, the temperature coefficient is optimized, resulting in less power decay in high-temperature environments, significantly reduced electrical losses, and better power generation performance. The actual outdoor power generation is much higher than that of conventional back-contact battery modules.

[0060] Reduced production costs and improved cost-effectiveness in mass production: Through refined electrode design and steel plate printing process, paste consumption is ≤8mg / W, reducing silver paste consumption per watt by more than 30%, significantly reducing the cost of precious metal consumables; strong process compatibility, no need to add high-end equipment, only local optimization of existing production lines, reducing equipment investment per GW by more than 20%; mass production yield is improved to 96%~98%, the defect rate is significantly reduced, and the overall production cost is reduced by 0.05~0.08 yuan / W compared with existing back contact battery modules.

[0061] The reliability and adaptability of the modules have been comprehensively enhanced: the low-temperature infrared welding process eliminates the hidden dangers of poor soldering and over-soldering, the bonding strength between the solder strip and the electrode is increased by 40%, the mechanical properties of the modules meet the standards, and the resistance to microcracks and aging is excellent; the bifaciality of the modules has been increased to more than 80%, the low light response capability has been greatly enhanced, and it is suitable for a variety of complex environments; after the lamination process is optimized, the sealing performance and resistance to damp heat of the modules are improved, the service life is extended to more than 30 years, the first year degradation rate is ≤0.8%, and the annual degradation rate is ≤0.3%.

[0062] Maximizing effective light-receiving area and high space utilization: The full-screen design combined with hidden busbars reduces the proportion of ineffective areas of the module to less than 1.2%, which is 6 percentage points less than traditional modules, and significantly increases the effective power generation area for the same size; The module has a clean appearance with no exposed electrodes, making it suitable for high-end scenarios such as residential photovoltaics and building-integrated photovoltaics (BIPV), with a wider range of applications.

[0063] Stable mass production process, suitable for large-scale promotion: The entire process is controllable, the femtosecond laser etching and steel plate printing have high precision, the cell consistency is strong, the new production line can quickly achieve yield ramp-up, and the yield can be stabilized to more than 95% within 1 month. It solves the pain points of slow yield ramp-up and large process fluctuations of traditional back contact battery modules, and is suitable for GW-level mass production.

[0064] The entire process is automated, with key steps equipped with an online detection system to monitor film thickness, etching accuracy, and welding quality in real time, ensuring process stability. Consumables are recyclable, silver paste consumption is low, and there are no harmful waste emissions, meeting green production requirements. Process parameters are compatible with mainstream silicon wafer sizes such as 182mm and 210mm, as well as various module types such as 60-cell, 72-cell, and 78-cell wafers.

[0065] In some embodiments of the present invention, a back-contact battery assembly is also provided, which is prepared using the above-described method for preparing a back-contact battery assembly. The conversion efficiency of the back-contact battery assembly of the present invention is ≥25.2%.

[0066] Example 1 The method for preparing the back contact battery assembly provided in this embodiment includes the following steps: S1. The silicon wafer selected has a size of 182mm, a resistivity of 2Ω·cm, and an oxygen content ≤1×10⁻⁶. 18 atoms / cm 3 N-type single-crystal silicon wafers; the front side of the silicon wafer is texturized using an alkaline method to form a positive pyramid textured surface with a height of 4μm, and the roughness Ra of the texturized silicon wafer is ≤0.2μm; S2. Deposit an N-region passivation layer on the back side of the silicon wafer; the specific steps for depositing the N-region passivation layer are as follows: using a low-pressure chemical vapor deposition (LPCVD) device, sequentially deposit a 1.3 nm thick SiO2 layer and an 18 nm thick phosphorus-doped polycrystalline silicon layer (phosphorus doping concentration of 2 × 10⁻⁶). 20 atoms / cm 3 The deposition temperature was 610℃, and the film uniformity error was ≤±0.1nm; The N-region passivation layer on the P-region location of the silicon wafer is removed by laser etching, and then a P-region passivation layer is deposited on the P-region location. The specific steps for depositing the P-region passivation layer are as follows: using a low-pressure chemical vapor deposition (LPCVD) system, a 1.1 nm thick SiO2 layer and a 15 nm thick boron-doped polycrystalline silicon layer (boron doping concentration of 1.5 × 10⁻⁶) are sequentially deposited on the P-region location. 20 atoms / cm 3 The deposition temperature was 610℃, and the film uniformity error was ≤±0.1nm. S3. Femtosecond laser is used to etch the N-region passivation layer and the P-region passivation layer to form an interdigitated PN junction electrode pattern; the etching accuracy is ±1μm, and the etching edge roughness is ≤0.5μm; the PN junction interdigitation distance of the interdigitated PN junction electrode pattern is 55μm, and the electrode width is 25μm. Then, silver paste is used for steel plate printing. The silver paste, by weight percentage, includes: 90% spherical silver powder, 4% nano-silver particles with a particle size of 50~200nm, 3% glass powder (PbO-B2O3-SiO2 system), and 3% organic carrier (terpineol). S4. After printing on the steel plate, annealing is performed to obtain the electrode sheet. The annealing process includes: holding at 450℃ for 9 minutes, then raising the temperature to 550℃ and holding for 11 minutes, and then raising the temperature to 650℃ and holding for 15 minutes. The annealing process is carried out under a mixture of nitrogen and oxygen, with the oxygen volume accounting for 0.5%. S5. Use non-contact photoelectric testing equipment with a sorting efficiency of ≥6000 pieces / h, and remove battery cells with an efficiency of less than 26.8% and excessive leakage rate. Tin-plated copper alloy solder strips are used, with a width of 0.2mm and a thickness of 0.03mm. Low-temperature infrared welding is employed at a welding temperature of 190℃ and a welding pressure of 0.12MPa to achieve seamless bonding between the solder strips and the silver grid, reducing the rate of poor soldering to below 0.2%. Exposed busbars are eliminated, and invisible interconnecting wires are used on the back. The wires are embedded inside the POE film, without occupying the light-receiving area. Flat fine wires and segmented dot-matrix interconnects are used, all embedded inside the POE film, running along the cell gaps and densely arranged along the direction of the cell main grid. S6. Full-screen lamination encapsulation process is adopted for lamination encapsulation. High-transmittance tempered glass (transmittance ≥93.5%), POE film and backplane are used as encapsulation materials. The gap between the cells is 0.09mm, the lamination temperature is 148℃, the lamination pressure is 85kPa and the lamination time is 14min. After lamination and encapsulation, a lightweight alloy frame is installed, and a waterproof junction box is welded to obtain the back contact battery assembly.

[0067] The back-contact battery module obtained in this embodiment has the following characteristics: single cell efficiency of 27.4%, module efficiency of 25.3%, silver paste consumption of 7.5 mg / W per watt, mass production yield of 97.2%, bifaciality of 82%, and temperature coefficient of -0.26% / ℃.

[0068] Example 2 The method for preparing the back contact battery assembly provided in this embodiment includes the following steps: S1. The silicon wafer selected has a size of 182mm, a resistivity of 1Ω·cm, and an oxygen content ≤1×10⁻⁶. 18 atoms / cm 3 N-type single-crystal silicon wafers; the front side of the silicon wafer is texturized using an alkaline method to form a positive pyramid textured surface with a height of 3μm, and the roughness Ra of the texturized silicon wafer is ≤0.2μm; S2. Deposit an N-region passivation layer on the back side of the silicon wafer; the specific steps for depositing the N-region passivation layer are as follows: using a low-pressure chemical vapor deposition (LPCVD) device, sequentially deposit a 1.2 nm thick SiO2 layer and a 15 nm thick phosphorus-doped polycrystalline silicon layer (phosphorus doping concentration of 1.5 × 10⁻⁶). 20 atoms / cm 3 The deposition temperature is 600℃, and the film uniformity error is ≤±0.1nm; The N-region passivation layer on the P-region location of the silicon wafer is removed by laser etching, and then a P-region passivation layer is deposited on the P-region location. The specific steps for depositing the P-region passivation layer are as follows: using a low-pressure chemical vapor deposition (LPCVD) system, a 1.0 nm thick SiO2 layer and a 12 nm thick boron-doped polycrystalline silicon layer (boron doping concentration of 1×10⁻⁶) are sequentially deposited on the P-region location. 20 atoms / cm 3 The deposition temperature is 600℃, and the film uniformity error is ≤±0.1nm. S3. Femtosecond laser is used to etch the N-region passivation layer and the P-region passivation layer to form an interdigitated PN junction electrode pattern; the etching accuracy is ±1μm and the etching edge roughness is ≤0.5μm; the PN junction interdigitation distance of the interdigitated PN junction electrode pattern is 50μm and the electrode width is 20μm. Then, silver paste is used for steel plate printing. The silver paste, by weight percentage, includes: 88% spherical silver powder, 5% nano-silver particles with a particle size of 50~200nm, 3.5% glass powder (PbO-B2O3-SiO2 system), and 3.5% organic carrier (ethyl cellulose). S4. After printing on the steel plate, annealing is performed to obtain the electrode sheet. The annealing process includes: holding at 450℃ for 8 minutes, then raising the temperature to 550℃ and holding for 10 minutes, and then raising the temperature to 650℃ and holding for 18 minutes. The annealing process is carried out under a mixture of nitrogen and oxygen, with the oxygen volume percentage in the mixture being 0.1%. S5. Use non-contact photoelectric testing equipment with a sorting efficiency of ≥6000 pieces / h, and remove battery cells with an efficiency of less than 26.8% and excessive leakage rate. Tin-plated copper alloy solder strips are used, with a width of 0.2mm and a thickness of 0.03mm. Low-temperature infrared welding is employed at a welding temperature of 180℃ and a welding pressure of 0.1MPa to achieve seamless bonding between the solder strips and the silver grid, reducing the rate of poor soldering to below 0.2%. Exposed busbars are eliminated, and invisible interconnecting wires are used on the back. The wires are embedded inside the POE film, without occupying the light-receiving area. Flat fine wires and segmented dot-matrix interconnects are used, all embedded inside the POE film, running along the cell gaps and densely arranged along the direction of the cell main grid. S6. Full-screen lamination encapsulation process is adopted for lamination encapsulation. High-transmittance tempered glass (transmittance ≥93.5%), POE film and backplane are used as encapsulation materials. The gap between the cells is 0.08mm, the lamination temperature is 145℃, the lamination pressure is 80kPa and the lamination time is 12min. After lamination and encapsulation, a lightweight alloy frame is installed, and a waterproof junction box is welded to obtain the back contact battery assembly.

[0069] Example 3 The method for preparing the back contact battery assembly provided in this embodiment includes the following steps: S1. The silicon wafer selected has a size of 182mm, a resistivity of 3Ω·cm, and an oxygen content of ≤1×10⁻⁶. 18 atoms / cm 3 N-type single-crystal silicon wafers; the front side of the silicon wafer is texturized using an alkaline method to form a positive pyramid textured surface with a height of 5μm, and the roughness Ra of the texturized silicon wafer is ≤0.2μm; S2. Deposit an N-region passivation layer on the back side of the silicon wafer; the specific steps for depositing the N-region passivation layer are as follows: using a low-pressure chemical vapor deposition (LPCVD) device, sequentially deposit a 1.5 nm thick SiO2 layer and a 20 nm thick phosphorus-doped polycrystalline silicon layer (phosphorus doping concentration of 3 × 10⁻⁶). 20 atoms / cm 3 The deposition temperature is 620℃, and the film uniformity error is ≤±0.1nm; The N-region passivation layer on the P-region location of the silicon wafer is removed by laser etching, and then a P-region passivation layer is deposited on the P-region location. The specific steps for depositing the P-region passivation layer are as follows: using a low-pressure chemical vapor deposition (LPCVD) device, a 1.2 nm thick SiO2 layer and an 18 nm thick boron-doped polycrystalline silicon layer (boron doping concentration of 2 × 10⁻⁶) are sequentially deposited on the P-region location. 20 atoms / cm 3 The deposition temperature was 620℃, and the film uniformity error was ≤±0.1nm. S3. Femtosecond laser is used to etch the N-region passivation layer and the P-region passivation layer to form an interdigitated PN junction electrode pattern; the etching accuracy is ±1μm and the etching edge roughness is ≤0.5μm; the PN junction interdigitation distance of the interdigitated PN junction electrode pattern is 60μm and the electrode width is 30μm. Then, silver paste is used for steel plate printing. The silver paste, by weight percentage, includes: 92% spherical silver powder, 3% nano-silver particles with a particle size of 50~200nm, 2% glass powder (PbO-B2O3-SiO2 system), and 3% organic carrier (terpineol). S4. After printing on the steel plate, an annealing process is performed to obtain the electrode sheet. The annealing process includes: holding at 450℃ for 10 minutes, then raising the temperature to 550℃ and holding for 12 minutes, and then raising the temperature to 650℃ and holding for 18 minutes. The annealing process is carried out under a mixture of nitrogen and oxygen, with oxygen accounting for 1% of the volume in the mixture. S5. Use non-contact photoelectric testing equipment with a sorting efficiency of ≥6000 pieces / h, and remove battery cells with an efficiency of less than 26.8% and excessive leakage rate. Tin-plated copper alloy solder strips are used, with a width of 0.2mm and a thickness of 0.03mm. Low-temperature infrared welding is employed at a welding temperature of 200℃ and a welding pressure of 0.15MPa to achieve seamless bonding between the solder strips and the silver grid, reducing the rate of poor soldering to below 0.2%. Exposed busbars are eliminated, and invisible interconnecting wires are used on the back. The wires are embedded inside the POE film, without occupying the light-receiving area. Flat fine wires and segmented dot-matrix interconnects are used, all embedded inside the POE film, running along the gaps between cells and densely arranged along the direction of the main grid of the cell. S6. Full-screen lamination encapsulation process is adopted for lamination encapsulation. High-transmittance tempered glass (transmittance ≥93.5%), POE film and backplane are used as encapsulation materials. The gap between the cells is 0.1mm, the lamination temperature is 150℃, the lamination pressure is 90kPa and the lamination time is 15min. After lamination and encapsulation, a lightweight alloy frame is installed, and a waterproof junction box is welded to obtain the back contact battery assembly.

[0070] Comparative Example 1 The method for preparing the back contact battery assembly provided in this comparative example includes the following steps: S1. Select an N-type monocrystalline silicon wafer with a size of 182mm and a resistivity of 1~5Ω·cm; perform alkaline texturing on the front side of the silicon wafer to form a positive pyramid textured surface with a height of 2~4μm; S2. Using a low-pressure chemical vapor deposition (LPCVD) device, a 1.2 nm thick SiO2 layer and a 16 nm thick polycrystalline silicon layer are sequentially deposited on the back side of the silicon wafer; then phosphorus doping and boron doping are performed to form N-regions and P-regions. S3. Femtosecond laser is used to etch the N-region passivation layer and the P-region passivation layer to form an interdigitated PN junction electrode pattern; the interdigitated PN junction electrode pattern has a PN junction interdigitation distance of 90μm and an electrode width of 50μm; Then, silver paste is used for screen printing. The silver paste, by weight percentage, includes: 95% spherical silver powder, 2% glass powder (PbO-B2O3-SiO2 system), and 3% organic carrier (terpineol). S4. After screen printing, annealing is performed to obtain the electrode sheet; the annealing process includes: holding at 550℃ for 20 minutes under a nitrogen atmosphere; S5. Copper solder strips are used, with a width of 0.5mm and a thickness of 0.05mm. Hot air welding is used at a temperature of 220~240℃ to achieve bonding between the solder strip and the silver grid; it has main grids and fine grids, and exposed busbars; S6. Full-screen lamination encapsulation process is adopted for lamination encapsulation. Tempered glass, EVA film and backplane are used as encapsulation materials. The gap between battery cells is 0.2~0.3mm, the lamination temperature is 140~142℃, the lamination pressure is 75kPa and the lamination time is 15min. After lamination and encapsulation, a lightweight alloy frame is installed, and a waterproof junction box is welded to obtain the back contact battery assembly.

[0071] Test case Seventy-two standard components were prepared using the methods described in Examples 1-3 and Comparative Example 1, respectively. The performance of each component was tested, and the results are shown in Table 1.

[0072] Table 1

[0073] Outdoor practical application: Under standard outdoor lighting conditions (irradiance 1000W / m²) 2 (Ambient temperature 25℃).

[0074] The peak power of the modules in Examples 1-3 of this invention can reach 580-590W, which is 8%-10% higher than that of Comparative Example 1. The advantage of increased power generation is more obvious in low light and high temperature environments, with a power generation gain of 12% in high temperature environment (60℃) and low light environment (irradiance 200W / m²). 2 With a power generation gain of up to 15%, it is fully adaptable to various scenarios such as residential distributed photovoltaic, mountain photovoltaic, and desert photovoltaic.

[0075] Although the present invention has been illustrated and described with specific embodiments, it should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; those skilled in the art should understand that modifications can be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein, without departing from the spirit and scope of the present invention; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention; therefore, this means that all such substitutions and modifications that fall within the scope of the present invention are included in the appended claims.

Claims

1. A method for preparing a back-contact battery assembly, characterized in that, Includes the following steps: S1. Texturing the front side of the silicon wafer; S2. An N-region passivation layer and a P-region passivation layer are deposited on the back side of the silicon wafer using a partitioned passivation deposition process. S3. Etch the N-region passivation layer and the P-region passivation layer to form an interdigitated PN junction electrode pattern; Then, electrode printing is performed; wherein, the PN junction interdigitation distance of the interdigitated PN junction electrode pattern is 50~60μm, and the electrode width is 20~30μm; S4. After the electrodes are printed, they are annealed to obtain the battery cell. S5. It adopts a hidden busbarless string welding process to weld the solder strip and the battery cell, eliminating the exposed busbar and using invisible interconnecting wires; S6. The back contact battery assembly is obtained by laminating and encapsulating the battery using a full-screen lamination process.

2. The method for preparing a back contact battery assembly according to claim 1, characterized in that, Step S1 includes at least one of the following features (1) to (3); (1) The silicon wafer includes an N-type monocrystalline silicon wafer, wherein the resistivity of the N-type monocrystalline silicon wafer is 1~3 Ω·cm and the oxygen content is ≤1×10 18 atoms / cm 3 ; (2) The flocking process includes: forming a positive pyramidal flocked surface by alkaline flocking, wherein the height of the positive pyramidal flocked surface is 3~5μm; (3) The roughness Ra of the silicon wafer after texturing is ≤0.2μm.

3. The method for preparing a back contact battery assembly according to claim 1, characterized in that, In step S2, the partitioned passivation deposition process includes: sequentially depositing a first tunneling oxide layer and a phosphorus-doped polysilicon layer in the N region on the back side of the silicon wafer; and sequentially depositing a second tunneling oxide layer and a boron-doped polysilicon layer in the P region on the back side of the silicon wafer. The thickness of the first tunneling oxide layer is 1.2~1.5 nm, the thickness of the phosphorus-doped polycrystalline silicon layer is 15~20 nm, and the phosphorus doping concentration of the phosphorus-doped polycrystalline silicon layer is 1.5 × 10⁻⁶. 20 ~3×10 20 atoms / cm 3 The thickness of the second tunneling oxide layer is 1.0~1.2 nm, the thickness of the boron-doped polysilicon layer is 12~18 nm, and the boron doping concentration of the boron-doped polysilicon layer is 1×10⁻⁶. 20 ~2×10 20 atoms / cm 3 .

4. The method for preparing a back contact battery assembly according to claim 1, characterized in that, In step S3, femtosecond laser etching is used for etching, with an etching accuracy of ±1μm and an edge roughness of ≤0.5μm.

5. The method for preparing a back contact battery assembly according to claim 1, characterized in that, In step S3, the electrode printing includes printing on a steel plate using silver paste; the silver paste, by mass percentage, includes: 88%~92% spherical silver powder, 3%~5% nano-silver particles with a particle size of 50~200nm, 2%~3.5% glass powder, and 2.5%~4% organic carrier.

6. The method for preparing a back contact battery assembly according to claim 1, characterized in that, In step S4, the annealing process includes: holding at 450±5℃ for 8~10 min, then raising the temperature to 550±5℃ and holding for 10~12 min, and then raising the temperature to 650±5℃ and holding for 12~18 min.

7. The method for preparing a back contact battery assembly according to claim 1, characterized in that, In step S5, the solder strip is a tin-plated copper alloy solder strip with a width of 0.2±0.05mm and a thickness of 0.02~0.04mm; And / or, in step S5, the welding includes infrared welding, wherein the temperature of the infrared welding is 180~200℃ and the pressure is 0.1~0.15MPa.

8. The method for preparing a back contact battery assembly according to claim 1, characterized in that, In step S6, the welded solar cells are arranged with a gap of 0.08~0.1mm between adjacent solar cells; And / or, in step S6, the encapsulation material of the laminated encapsulation includes tempered glass, POE film, and backplate.

9. The method for preparing a back contact battery assembly according to claim 1, characterized in that, In step S6, the lamination temperature of the lamination encapsulation is 145~150℃, the lamination pressure is 80~90kPa, and the lamination time is 12~15min.

10. A back-contact battery assembly, characterized in that, It is prepared by the method of any one of claims 1 to 9 for back contact battery assembly.

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