Semiconductor device, support device, semiconductor substrate and method for treating a surface thereof

Abstract

The application provides a semiconductor device, a supporting device, a semiconductor substrate and a surface treatment method thereof. It relates to the technical field of semiconductor processing technology. The surface treatment method of the semiconductor substrate comprises the following steps: etching a first surface of a semiconductor substrate to obtain a first transition surface under a first temperature field, and forming a first silicon carbide film on a second surface of the semiconductor substrate, the semiconductor substrate comprising silicon atoms and carbon atoms, the temperature of the first surface of the semiconductor substrate being lower than that of the second surface, and the first surface and the second surface being oppositely arranged; etching the first silicon carbide film to obtain a second transition surface under a second temperature field, and forming a second silicon carbide film on the first transition surface, the temperature of the first transition surface of the semiconductor substrate being higher than that of the first silicon carbide film. The surface treatment method of the semiconductor substrate can reduce or not increase the hidden damage layer in the semiconductor substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and in particular to a semiconductor device, a support device, a semiconductor substrate, and a surface treatment method thereof. Background Technology

[0002] With the development of semiconductor technology, silicon substrates can no longer meet the needs of power devices and radio frequency devices. Compared with power devices made on silicon substrates, power devices made on silicon carbide (SiC) substrates are widely favored due to their advantages such as higher frequency and higher power.

[0003] In the fabrication of SiC devices, the surface roughness of the cut SiC substrate is relatively large (ranging from tens of micrometers to tens of nanometers depending on the cutting process), and the uniformity of the substrate surface is also affected by the cutting process. Therefore, before SiC substrate epitaxy, the current mainstream industry choice is Chemical Mechanical Polishing (CMP) to polish the substrate surface to varying degrees. However, this polishing method requires applying pressure to the substrate surface, which can lead to the formation of a poorly crystalline hidden layer within the substrate. Summary of the Invention

[0004] This application provides a semiconductor device, a support device, a semiconductor substrate, and a surface treatment method thereof. The aim is to reduce or eliminate the formation of a hidden defect layer within the semiconductor substrate during surface treatment.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] On one hand, this application provides a surface treatment method for a semiconductor substrate, comprising:

[0007] The first and second surfaces of a semiconductor substrate are processed under a first temperature field to etch a first transition surface on the first surface and form a first silicon carbide film on the second surface. The semiconductor substrate includes silicon atoms and carbon atoms. The temperature of the first surface of the same semiconductor substrate is lower than the temperature of its second surface. The first and second surfaces are arranged in opposite directions.

[0008] The first transition surface and the first silicon carbide film are processed under a second temperature field to etch the first silicon carbide film to obtain the second transition surface, and a second silicon carbide film is formed on the first transition surface. The temperature of the first transition surface on the same semiconductor substrate is higher than the temperature of its first silicon carbide film.

[0009] The surface treatment method for a semiconductor substrate disclosed in this application first etches the first surface of the semiconductor substrate under a first temperature field to obtain a first transition surface. This removes uneven portions or damaged layers on the first surface of the semiconductor substrate, helping to improve the roughness of the first surface and providing better substrate conditions for the subsequent formation of a second silicon carbide film. Then, a first silicon carbide film is formed on the second surface of the semiconductor substrate, which can compensate for the material loss due to the etching of the first surface and also helps to form a more uniform underlying structure. Next, the first silicon carbide film is etched under a second temperature field to obtain a second transition surface. This removes excess growth material from the underlying structure of the semiconductor substrate, maintains the uniformity of the overall thickness, and further improves the surface flatness of the semiconductor substrate. Finally, a second silicon carbide film is formed on the first transition surface, which can fill the depressions left by the etching of the first surface, making the surface flatter and also providing some compensation for the etching of the first silicon carbide film. This application employs alternating etching and silicon carbide film formation. On one hand, this allows for the rearrangement of atoms on the first and second surfaces of the semiconductor substrate, achieving surface reconstruction and gradually reducing surface unevenness and damage. This improves the surface quality and structural performance of the semiconductor substrate, enhancing its planarization effect. On the other hand, because this application uses alternating etching and epitaxial growth, it is a non-contact planarization method compared to polishing, eliminating the pressure applied to the semiconductor substrate. Therefore, it can reduce or eliminate the need for a hidden damage layer on the substrate.

[0010] In one feasible manner, the process conditions of the surface treatment method for the semiconductor substrate include: the working gas pressure of the surface treatment method for the semiconductor substrate is between 0.1 mbar and 100 mbar.

[0011] The surface treatment method for the semiconductor substrate of this application sets the working gas pressure between 0.1 mbar and 100 mbar, thus enabling the process to be carried out in a low-pressure environment. In a low-pressure environment, the vapor pressure of silicon decreases, making it easier for silicon atoms to transform from a solid state to a gaseous state, i.e., to undergo sublimation, thereby detaching from the surface of the semiconductor substrate and being removed in a gaseous state. Therefore, this low-pressure environment promotes the etching of the first surface and the etching of the first silicon carbide film.

[0012] In one feasible manner, the process conditions of the surface treatment method for the semiconductor substrate include at least one of the following:

[0013] The highest temperature in the first temperature field is between 1800℃ and 2100℃;

[0014] The highest temperature in the second temperature field is between 1800℃ and 2100℃;

[0015] The temperature gradient of the first temperature field is between 0.1℃ / mm and 5℃ / mm;

[0016] The temperature gradient of the second temperature field is between 0.1℃ / mm and 5℃ / mm.

[0017] This application establishes a high-temperature environment by setting a first temperature field and / or a second temperature field. This high temperature provides the necessary energy for etching the surface of the semiconductor substrate, making it easier to break the chemical bonds between silicon and carbon atoms on the substrate surface. This allows silicon atoms to sublimate and detach from the first surface. Furthermore, the high-temperature environment accelerates the chemical reaction rate, making the etching of the semiconductor substrate surface faster and more efficient. By setting temperature gradients for the first and second temperature fields, this promotes the movement of gaseous products along the temperature gradient direction, thereby facilitating the removal of silicon and carbon atoms from the semiconductor substrate surface and accelerating the etching rate. Additionally, the temperature gradient enhances the convection and diffusion of gas molecules, thus accelerating the transport of matter.

[0018] In one feasible approach, etching the first surface to obtain a first transition surface includes:

[0019] This causes silicon atoms on the first surface to detach from the first surface, thus obtaining the first sub-transition surface;

[0020] This causes the carbon atoms of the first sub-transition surface to detach from the first sub-transition surface, thus obtaining the first transition surface.

[0021] This application obtains a first transition surface by causing silicon atoms to detach from a first surface to form a first sub-transition surface, and then by causing the carbon atoms remaining on the first sub-transition surface to detach from the first sub-transition surface. The sequential detachment of silicon and carbon atoms from the first surface enables etching of the first surface.

[0022] In one feasible manner, the carbon atoms of the first sub-transition surface are decoupled from the first sub-transition surface, including:

[0023] The reactant gas reacts chemically with the carbon atoms on the first transition surface to generate silicon carbide gaseous products.

[0024] This application removes residual carbon atoms from the first transition surface using a chemical method. By controlling the amount of reactant gas, reaction temperature, and reaction time, as well as the combination of different process environments and the carbon and silicon atom ratios of the semiconductor substrate, the roughness and step width of the first surface etching can be adjusted. This method has high precision and controllability, and can remove a specific amount of carbon atoms more accurately.

[0025] In one feasible manner, the reaction gas that chemically reacts with the carbon atoms of the first sub-transition surface includes at least one of silicon vapor, silane, trichlorosilane, ethoxysilane, or silicon tetrachloride.

[0026] This application enables the production of silicon carbide gaseous products by causing carbon atoms on the first sub-transition surface to chemically react with at least one of the aforementioned reactive gases, thereby facilitating the removal of carbon atoms from the first sub-transition surface.

[0027] In one feasible manner, forming a first silicon carbide film on the second surface includes:

[0028] The silicon carbide vapor products are deposited on the second surface to obtain the first silicon carbide film.

[0029] This application deposits the silicon carbide vapor products generated during the etching of the first surface onto the second surface. On the one hand, this allows the silicon carbide vapor products to detach from the first surface, thus achieving the etching of the first surface. On the other hand, it allows the silicon carbide vapor products generated during etching to be deposited onto the second surface, enabling the reuse of the silicon carbide vapor products, thereby reducing the loss of the semiconductor substrate.

[0030] In one possible implementation, the semiconductor substrate includes a plurality of semiconductor substrates arranged at intervals along a first direction parallel to the thickness direction of the semiconductor substrate.

[0031] Depositing silicon carbide vapor products onto a second surface includes:

[0032] Silicon carbide vapor products from a semiconductor substrate are deposited on a second surface of an adjacent semiconductor substrate.

[0033] This application enables the reuse of silicon carbide vapor products generated from etching the first surface by depositing silicon carbide vapor products from one semiconductor substrate onto the second surface of an adjacent semiconductor substrate. It also enables simultaneous surface treatment of multiple semiconductor substrates, thereby improving the efficiency of surface treatment.

[0034] In one feasible approach, etching the first silicon carbide film to obtain the second transition surface includes:

[0035] This causes silicon atoms in the first silicon carbide film to detach from the first silicon carbide film, thereby obtaining the second sub-transition surface;

[0036] This causes the carbon atoms of the second sub-transition surface to detach from the second sub-transition surface, thus obtaining the second transition surface.

[0037] This application obtains a second transition surface by detaching silicon atoms from a first silicon carbide film, and then detaching the remaining carbon atoms from the second transition surface. The sequential detachment of silicon and carbon atoms from the first silicon carbide film allows for etching of the first silicon carbide film, thereby rearranging the atoms on the surface of the semiconductor substrate and improving its surface quality, making it smoother.

[0038] In one feasible manner, the carbon atoms at the second sub-transition surface detach from the second sub-transition surface, including:

[0039] The reactant gas reacts chemically with the carbon atoms on the second transition surface to generate silicon carbide gaseous products.

[0040] This application removes residual carbon atoms from the second transition surface using a chemical method. By controlling the amount of reactant gas, reaction temperature, and reaction time, as well as the combination of different process environments and the carbon and silicon atom ratios of the semiconductor substrate, the roughness and step width of the first silicon carbide film can be adjusted. This method has high precision and controllability, and can remove a specific amount of carbon atoms more accurately.

[0041] In one feasible manner, the reaction gas that chemically reacts with the carbon atoms of the second transition surface includes at least one of silicon vapor, silane, trichlorosilane, ethoxysilane, or silicon tetrachloride.

[0042] This application enables the production of silicon carbide gaseous products by causing the reaction gas at the second sub-transition surface to chemically react with at least one of the aforementioned reaction gases, thereby facilitating the removal of carbon atoms from the first sub-transition surface.

[0043] In one feasible manner, forming a second silicon carbide film at the first transition surface includes:

[0044] The silicon carbide vapor product is deposited on the first transition surface to obtain a second silicon carbide film.

[0045] This application deposits the silicon carbide vapor products generated during the etching of the first silicon carbide film onto the first transition surface. On the one hand, this allows the silicon carbide vapor products to detach from the first silicon carbide film, thus achieving the etching of the first silicon carbide film. On the other hand, it allows the silicon carbide vapor products generated during etching to be deposited onto the first transition surface, enabling the reuse of the silicon carbide vapor products, thereby reducing the loss of the semiconductor substrate.

[0046] In one possible implementation, the semiconductor substrate includes a plurality of semiconductor substrates arranged at intervals along a first direction parallel to the thickness direction of the semiconductor substrate.

[0047] Depositing silicon carbide vapor products onto the first transition surface includes:

[0048] Silicon carbide vapor products from a semiconductor substrate are deposited on a first transition surface of an adjacent semiconductor substrate.

[0049] This application enables the reuse of silicon carbide vapor products generated from the etching of the first silicon carbide film by depositing silicon carbide vapor products from one semiconductor substrate onto the first transition surface of an adjacent semiconductor substrate, thereby reducing material loss of the silicon carbide substrate. It also allows multiple semiconductor substrates to undergo surface treatment simultaneously, thereby improving the efficiency of surface treatment.

[0050] In one feasible approach, after the first silicon carbide film is formed on the second surface and before the first silicon carbide film is etched to obtain the second transition surface, the method further includes:

[0051] The semiconductor substrate is annealed at a constant temperature.

[0052] This application utilizes annealing to achieve two main benefits: firstly, it rearranges the surface atoms of the semiconductor substrate, thereby improving surface flatness and planarization; secondly, it optimizes the crystal structure of the semiconductor substrate, enhancing its reliability. Furthermore, the annealing process used in this application suppresses silicon atom sublimation, thus reducing material loss while improving planarization.

[0053] In one feasible approach, the annealing temperature is between 1600°C and 2100°C.

[0054] By setting the annealing temperature between 1600°C and 2100°C, this application enables the atoms on the surface of the semiconductor substrate to diffuse and sublimate, while simultaneously facilitating equal amounts of deposition and adsorption. This allows for the reconstruction of the surface atoms of the semiconductor substrate, resulting in further surface planarization.

[0055] On the other hand, this application provides a semiconductor substrate obtained by the above-described surface treatment method for semiconductor substrates.

[0056] Since the semiconductor substrate provided in this application is obtained by the aforementioned surface treatment method, the semiconductor substrate can eliminate or reduce the hidden damage layer, thereby making it less prone to cracking or damage when subjected to external forces or other stresses. Furthermore, it can also eliminate or reduce the impact on the conductivity or other electrical properties of the semiconductor substrate.

[0057] In another aspect, this application also provides a semiconductor device, which includes functional components and the aforementioned semiconductor substrate, with the functional components disposed on the semiconductor substrate.

[0058] Since the semiconductor device includes the aforementioned semiconductor substrate, the semiconductor device can also eliminate or reduce the hidden damage layer, so that the semiconductor substrate is less likely to crack or be damaged when the semiconductor device is subjected to external force or other stress.

[0059] In another aspect, this application provides an electronic device including a circuit board and the aforementioned semiconductor device, wherein the semiconductor device and the circuit board are electrically connected.

[0060] The electronic device provided in this application includes the semiconductor device described above. Therefore, the electronic device provided in this application can also eliminate or reduce the hidden damage layer of the semiconductor substrate, so that the semiconductor substrate is not easily cracked or damaged when subjected to external force or other stress.

[0061] In another aspect, this application provides a support device for supporting a semiconductor substrate. The support device includes at least one support structure, which includes a fixing member and a support member. The fixing member has an annular structure and a first connecting portion; the support member includes a second connecting portion and a support portion connected to the second connecting portion, the second connecting portion being connected to the first connecting portion, and the support portion being used to support the semiconductor substrate; the melting point of the fixing member is greater than or equal to 1800°C, and / or the melting point of the support member is greater than or equal to 1800°C.

[0062] This application sets the melting point of the fastener to be greater than or equal to 1800°C, and / or the melting point of the support to be greater than or equal to 1800°C. In this way, the fastener and / or support can have high high temperature resistance, which can improve the high temperature resistance of the support device and make the support device of this application applicable in high temperature environments.

[0063] In one possible implementation, the support members comprise multiple members, which are arranged at circumferential intervals along the fixing member.

[0064] This application improves the support reliability of the semiconductor substrate by arranging multiple support members at circumferential intervals along the fixing member, so that the multiple support members can cooperate with each other to support the semiconductor substrate.

[0065] In one possible implementation, the second connecting portion includes an insert groove, and the first connecting portion includes a protrusion located within the insert groove, connecting the fixing member and the support member.

[0066] By using the engagement of the protrusion and the embedded groove, this application can connect the first connecting part and the second connecting part together, which is a simple and reliable connection method.

[0067] In one possible implementation, the support portion has a sheet-like structure and extends in a direction away from the second connecting portion; along the direction away from the second connecting portion, the cross-sectional area of ​​the support portion gradually decreases.

[0068] This application minimizes the contact area between the support and the semiconductor substrate by configuring the support portion to extend away from the second connection portion, and by gradually reducing the cross-sectional area of ​​the support portion along the direction away from the second connection portion. When the support device is used in a high-temperature environment, it can reduce local high temperatures caused by heat conduction and improve the uniformity of heat conduction on the semiconductor substrate.

[0069] In one possible implementation, the fastener also has a third connecting portion, with a receiving groove between the third connecting portion and the first connecting portion.

[0070] This application utilizes the structure of the fastener by providing a receiving groove on the fastener, which can be used to place solid materials or other materials. For example, when the support device of this application is applied in the above-mentioned surface treatment method for semiconductor substrates, the receiving groove can be used to place solid materials or other materials for forming reactive gases. Furthermore, the receiving groove is located between the third connecting part and the first connecting part, which can effectively utilize the space of the fastener without interfering with the semiconductor substrate.

[0071] In one possible implementation, the support structure comprises multiple supports stacked together, with a third connection between adjacent supports, and a gas channel between adjacent supports that communicates with the receiving groove.

[0072] This application provides a gas channel for the support device to allow external process gases to enter or exit. By connecting the gas channel with the receiving tank, the solid material in the receiving tank can be vaporized and then introduced through the gas channel to the outer periphery or surface of the semiconductor substrate, thereby facilitating the corresponding process processing of the semiconductor substrate.

[0073] In one possible implementation, in one of two adjacent support structures, the third connecting portion includes a protrusion; in the other of the two adjacent support structures, the third connecting portion includes a groove; the protrusion is located within the groove, connecting the two adjacent support structures.

[0074] By using the cooperation of protrusions and grooves, this application can connect two adjacent third connecting parts together, and the connection method is simple and reliable. Attached Figure Description

[0075] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0076] Figure 2 This is a schematic diagram of the structure of a base station provided in an embodiment of this application;

[0077] Figure 3 This is a schematic diagram of the structure of an active antenna element provided in an embodiment of this application;

[0078] Figure 4 A cross-sectional structural diagram of a normally open HEMT device provided in an embodiment of this application;

[0079] Figure 5 A cross-sectional structural diagram of a normally-off HEMT device provided in an embodiment of this application;

[0080] Figure 6 One of the flowcharts for a surface treatment method for a semiconductor substrate provided in this application embodiment;

[0081] Figure 7 A second flowchart illustrating a surface treatment method for a semiconductor substrate provided in an embodiment of this application;

[0082] Figure 8 A third flowchart illustrating a surface treatment method for a semiconductor substrate provided in this application embodiment;

[0083] Figure 9 This is one of the schematic diagrams illustrating the surface treatment process of a semiconductor substrate provided in an embodiment of this application;

[0084] Figure 10 A second schematic diagram illustrating the process of a surface treatment method for a semiconductor substrate provided in an embodiment of this application;

[0085] Figure 11 A schematic diagram of the surface treatment process of a semiconductor substrate provided in this application embodiment is shown in Figure 3.

[0086] Figure 12 A schematic diagram illustrating an implementation of a first temperature field and / or a second temperature field provided in an embodiment of this application;

[0087] Figure 13 This is a comparison image of the Si surface of a semiconductor substrate before and after surface treatment by a method provided in this application.

[0088] Figure 14 This is a comparison image of the appearance of the C-side of a semiconductor substrate before and after surface treatment by a method provided in this application.

[0089] Figure 15This is a comparison image of the Si surface of another semiconductor substrate before and after surface treatment by a semiconductor substrate surface treatment method provided in the embodiments of this application.

[0090] Figure 16 This is a comparison image of the appearance of the C-side of another semiconductor substrate before and after surface treatment by a semiconductor substrate surface treatment method provided in the embodiments of this application.

[0091] Figure 17 A graph showing the relationship between the etching rate of silicon atoms in a semiconductor substrate and temperature and operating pressure, provided for an embodiment of this application;

[0092] Figure 18 This is a schematic diagram of the structure of multiple semiconductor substrates stacked according to an embodiment of this application;

[0093] Figure 19 A fourth flowchart illustrating a surface treatment method for a semiconductor substrate provided in this application embodiment;

[0094] Figure 20 One of the schematic diagrams of a surface treatment method for a semiconductor substrate provided in an embodiment of this application;

[0095] Figure 21 A second schematic diagram illustrating the processing steps of another surface treatment method for a semiconductor substrate provided in this application embodiment;

[0096] Figure 22 A third schematic diagram of the processing steps of another surface treatment method for a semiconductor substrate provided in this application embodiment;

[0097] Figure 23 One of the structural schematic diagrams of the support device provided in the embodiments of this application;

[0098] Figure 24 A schematic diagram of the structure of the support device provided in the embodiments of this application placed inside the crucible;

[0099] Figure 25 for Figure 24 A magnified view of a section at point A in the middle;

[0100] Figure 26 This is a second schematic diagram of the support device provided in the embodiments of this application.

[0101] Figure label:

[0102] 01 - Electronic device; 11 - Circuit board; 12 - Semiconductor device; 121 - Semiconductor substrate; 1211 - First surface; 1212 - Second surface; 1213 - First transition surface; 1214 - First silicon carbide film; 1215 - Second transition surface; 1216 - Second silicon carbide film;

[0103] 02-Base station; 21-Baseband processing unit; 22-Active antenna unit; 221-Computing unit; 2211-Control unit; 2212-Second transmission unit; 2213-Baseband unit; 2214-Power supply unit; 222-First transmission unit; 2221-RF unit; 2222-Power amplifier; 223-Antenna unit; 224-Power supply;

[0104] 03-Support device; 30-Support structure; 31-Fixing component; 311-First connecting part; 312-Accommodating groove; 313-Third connecting part; 32-Supporting component; 321-Second connecting part; 322-Supporting part; 3221-Supporting end; 33-Gas passage;

[0105] 41-First heater; 42-Second heater; 43-First valve; 44-Second valve; 45-Third valve; 46-Crucible. Detailed Implementation

[0106] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0107] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "one" or similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one.

[0108] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0109] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0110] In the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0111] In the embodiments of this application, directional indications such as "up" and "down," used to explain the structure and movement of different components in this application, are relative. These indications are appropriate when the components are in the positions shown in the figures. However, if the description of the component positions changes, then these directional indications will also change accordingly.

[0112] This application provides an electronic device 01. The electronic device 01 can be, for example, a mobile phone, tablet computer, television, smart wearable products (such as smartwatches and smart bracelets), augmented reality (AR) terminals, virtual reality (VR) terminals, and in-vehicle devices, or other different types of user equipment or terminal devices; it can also be a network device such as a base station 02. This application does not impose any special limitations on the specific type of the electronic device 01.

[0113] like Figure 1 As shown, the electronic device 01 may include a circuit board 11 and a semiconductor device 12. The semiconductor device 12 and the circuit board 11 are electrically connected, and the circuit board 11 is used to connect and support various electronic components to realize the transmission and processing of electrical signals.

[0114] Semiconductor device 12 may include a substrate and functional components, the functional components being disposed on the substrate. Exemplarily, an epitaxial layer may be first fabricated on the substrate, and then the functional components may be fabricated on the epitaxial layer through a series of process steps (e.g., ion implantation, fabrication of a gate, and fabrication of a passivation layer).

[0115] In some embodiments, the substrate can be a silicon carbide (SiC) substrate, thus the semiconductor device 12 is a silicon carbide semiconductor device. The silicon carbide substrate can be a semi-insulating substrate or a conductive substrate. For example, in one possible implementation, the substrate is a semi-insulating substrate. In this case, the silicon carbide semiconductor device can be a radio frequency (RF) device, such as a high electron mobility transistor (HEMT). This RF device can be used as a power amplifier, filter, switch, low-noise amplifier, and duplexer, etc.

[0116] In another possible implementation, the silicon carbide substrate can be a conductive substrate. In this case, the semiconductor device 12 can be a power device, such as a Schottky barrier diode (SBD), a metal-oxide-semiconductor field-effect transistor (MOSFET), or an IGBT.

[0117] Of course, in addition to circuit board 11 and silicon carbide semiconductor devices, electronic device 01 may also include basic components (such as resistors R, capacitors C and inductors L, etc.), sensors, connectors, power supplies, display devices, and other special devices (such as filters, voltage regulators and relays, etc.), etc. This application does not impose any special restrictions here.

[0118] Taking electronic device 01 as an example of base station 02, the structure of electronic device 01 will be explained. Figure 2 As shown, base station 02 includes a baseband unit (BBU) 21 and an active antenna unit (AAU) 22. The baseband unit 21 is primarily responsible for baseband digital signal processing, such as fast Fourier transform (FFT) / inverse fast Fourier transform (IFFT), modulation / demodulation, and channel coding / decoding.

[0119] like Figure 3 As shown, the active antenna element 22 includes a computing unit 221, a first transmission unit 222, and an antenna element 223.

[0120] The computing unit 221 includes a control unit 2211, a second transmission unit 2212, a baseband unit 2213, and a power supply unit 2214. These units are electrically connected to each other. The control unit 2211 is responsible for controlling the radio frequency (RF) signal, the second transmission unit 2212 is responsible for transmitting the RF signal, and the baseband unit 2213 is responsible for converting digital signals to analog signals. The baseband unit 2213 can be, for example, a digital-to-analog converter (DAC), which converts the digital signal output from the baseband processing unit 21 into an analog signal. The power supply unit 2214 is electrically connected to the power supply 224 and supplies power to the control unit 2211, the second transmission unit 2212, and the baseband unit 2213 within the computing unit 221.

[0121] The first transmission unit 222 is responsible for the transmission and amplification of radio frequency (RF) signals. The first transmission unit 222 includes a radio frequency (RF) unit 2221 and a power amplifier (PA) 2222. The RF unit 2221 is used to convert analog signals into low-power RF signals, and the power amplifier 2222 is used to amplify the low-power RF signals and output them to the antenna unit 223.

[0122] Antenna element 223 is responsible for radiating radio frequency signals outwards. For example... Figure 3 As shown, the active antenna unit 22 may include multiple radio frequency units 2221, multiple power amplifiers 2222, and multiple antenna units 223.

[0123] HEMT devices, as a type of semiconductor device 12, are widely used as radio frequency devices or power devices due to their advantages such as high breakdown electric field, high channel electron concentration, high electron mobility, and high temperature stability. Therefore, in some embodiments, when the electronic device 01 is the base station 02 of the above example, the power amplifier 2222 of the electronic device 01 can be an HEMT device.

[0124] It should be understood that when the semiconductor device 12 employs a HEMT device, and the HEMT device is used as a power amplifier 2222 in the electronic device 01, the electronic device 01 provided in this application embodiment is not limited to... Figure 2 and Figure 3 The base station 02 shown, and any electronic device 01 that needs to use power amplifier 2222 to amplify the signal, belong to the application scenarios of the embodiments of this application.

[0125] When semiconductor device 12 is used as power amplifier 2222 and an HEMT device is employed, an example of a HEMT device structure is provided, such as... Figure 4 As shown, a normally open HEMT device includes a substrate, an AlN (aluminum nitride) nucleation layer, a GaN (gallium nitride) buffer layer, an AlN insertion layer, an AlGaN (aluminum gallium nitride) barrier layer, a GaN cap layer, and a source (S), drain (D), and gate (G) disposed on the substrate. Figure 5 As shown, a normally-off HEMT device includes a substrate, an AlN nucleation layer, a GaN buffer layer, an AlN insertion layer, an AlGaN barrier layer, a gate cap layer, and source (S), drain (D), and gate (G) disposed on the substrate. For a normally-on HEMT device, when the gate-source voltage is zero, due to the characteristics of the AlGaN / GaN heterojunction, a two-dimensional electron gas (2DEG) channel exists between the source (S) and drain (D), which keeps the device in a conducting state (normally on) without external voltage. For a normally-off HEMT device, because the gate cap layer can adjust the band structure, electrons directly below the gate cap layer are depleted. Therefore, the 2DEG is in a turned-off state without bias voltage, and the 2DEG cannot flow within the channel layer between the source (S) and drain (D), keeping the HEMT device in a turned-off state.

[0126] The operating principle of HEMT devices is as follows: the source (S) and drain (D) form conductive ohmic contacts with the AlGaN barrier layer, while the gate (G) forms a Schottky contact with the AlGaN barrier layer. The dashed lines in the AlN insertion layer represent the 2DEG generated through polarization in the heterojunction formed by the AlN insertion layer and the AlGaN barrier layer in the HEMT device. The 2DEG is used to efficiently conduct electrons under the influence of an electric field. The source (S) and drain (D) allow the 2DEG to flow within the AlN insertion layer between the source (S) and drain (D) under the influence of an electric field; conduction between the source (S) and drain (D) occurs at the two-dimensional electron gas in the AlN insertion layer. The gate (G) is positioned between the source (S) and drain (D) to allow or impede the passage of the two-dimensional electron gas. The high conductivity of the 2DEG is partly due to the fact that electrons are trapped in a very small region at the interface between the AlN insertion layer and the AlGaN barrier layer, thus greatly increasing electron mobility.

[0127] Silicon carbide semiconductor devices, such as HEMT devices, require silicon carbide substrates. Therefore, the performance of the silicon carbide substrate is crucial for the future development of silicon carbide semiconductor devices. Since the fabrication of silicon carbide semiconductor devices requires the epitaxial growth of an epitaxial layer on the silicon carbide substrate, existing silicon carbide substrates need to be polished before device fabrication to facilitate this growth. However, current methods mostly employ chemical mechanical polishing (CMP) before epitaxy. This method, which applies pressure to the substrate surface, can create a hidden layer with poor crystallinity within the substrate. This results in poor surface properties of the polished substrate, consequently affecting the overall performance of the semiconductor device fabricated later.

[0128] Based on this, this application also provides a surface treatment method for a substrate and a semiconductor substrate 121 obtained by the surface treatment method, wherein the semiconductor substrate 121 is obtained by the surface treatment method of the semiconductor substrate 121. This surface treatment method, through alternating etching and epitaxial growth of the substrate, can achieve contactless polishing of the substrate. Therefore, it can eliminate or reduce the pressure applied to the substrate during polishing, thereby not increasing or decreasing the hidden damage layer within the substrate. The semiconductor substrate 121 prepared in this manner eliminates or reduces the hidden damage layer within the substrate; therefore, its mechanical and electrical properties are not affected or are minimally affected by the hidden damage layer, thus improving the reliability of the semiconductor substrate 121.

[0129] Please refer to Figure 6 As shown, Figure 6 This is a flowchart of a surface treatment method for a semiconductor substrate 121 provided in an embodiment of this application. The surface treatment method for a semiconductor substrate 121 provided in this application includes steps S100-S200.

[0130] S100, the first surface 1211 and the second surface 1212 of the semiconductor substrate 121 are processed under the first temperature field to etch the first surface 1211 to obtain the first transition surface 1213, and to form the first silicon carbide film 1214 on the second surface 1212.

[0131] The semiconductor substrate 121 includes silicon atoms and carbon atoms. The temperature of the first surface 1211 of the same semiconductor substrate 121 is lower than the temperature of the second surface 1212 of the semiconductor substrate 121. The first surface 1211 and the second surface 1212 are arranged opposite to each other.

[0132] In embodiments of this application, the semiconductor substrate 121 comprises silicon atoms and carbon atoms. Exemplarily, the semiconductor substrate 121 may be a silicon carbide substrate. For example, the semiconductor substrate 121 may be the (0001) facet of 4H-SiC. 4H-SiC belongs to the hexagonal crystal system, and its (0001) facet is referred to as the "Si facet".

[0133] The semiconductor substrate 121 has a first surface 1211 and a second surface 1212, wherein the first surface 1211 and the second surface 1212 are arranged opposite to each other, such as... Figure 9 As shown. For example, the first surface 1211 can be the front side of the semiconductor substrate 121, and the second surface 1212 can be the back side of the semiconductor substrate 121; or, the first surface 1211 can be the back side of the semiconductor substrate 121, and the second surface 1212 can be the front side of the semiconductor substrate 121.

[0134] In this embodiment, under the first temperature field, each semiconductor substrate 121 has a first surface 1211 and a second surface 1212, and the temperature of the first surface 1211 of each semiconductor substrate 121 is lower than the temperature of the second surface 1212 of the semiconductor substrate 121.

[0135] For example, if step S100 is performed on the first surface 1211 and the second surface 1212 of a single semiconductor substrate 121, the temperature of the first surface of the semiconductor substrate 121 is lower than the temperature of the second surface 1212 of the semiconductor substrate 121.

[0136] If step S100 involves simultaneously processing the first surfaces 1211 and second surfaces 1212 of multiple semiconductor substrates 121, then the temperature of the first surface of each semiconductor substrate 121 is lower than the temperature of its second surface 1212. The multiple semiconductor substrates 121 may be stacked on top of each other and arranged at intervals. In two adjacent semiconductor substrates 121, the first surface 1211 of one semiconductor substrate 121 is positioned opposite to the second surface of the other semiconductor substrate 121.

[0137] When performing step S100, the semiconductor substrate 121 can be placed in the first temperature field first, and then the first surface 1211 and the second surface 1212 of the semiconductor substrate 121 can be processed.

[0138] In the first temperature field, the temperature of the first surface 1211 of the semiconductor substrate 121 is lower than the temperature of the second surface 1212. That is, in the first temperature field, the first surface 1211 of the semiconductor substrate 121 is in a relatively low temperature region, while the second surface 1212 is in a relatively high temperature region.

[0139] For example, the temperature distribution of the first temperature field can be as follows: along the thickness direction parallel to the semiconductor substrate 121, the temperature of the first temperature field can gradually decrease from the second surface 1212 toward the first surface 1211. In other words, the second surface 1212 is in a relatively high temperature environment of the first temperature field, while the first surface 1211 is in a relatively low temperature environment of the first temperature field.

[0140] In step S100, the first surface 1211 of the semiconductor substrate 121 is processed, which can etch the first surface 1211 to obtain a first transition surface 1213; the second surface 1212 is processed, which can form a first silicon carbide film 1214 on the second surface 1212, such as... Figure 10 As shown. In Figure 10 In the diagram, the thin lines with arrows indicate the direction of temperature change in the first temperature field, with the arrow pointing in the direction of increasing temperature. The broad lines with arrows indicate the direction of atomic motion, for example, in... Figure 10 In the orientation shown, the broad line with arrows above the first transition surface 1213 of the semiconductor substrate 121 indicates that atoms on the first surface 1211 move upward and detach from the semiconductor substrate 121 to form the first transition surface 1213; the broad line with arrows below the first silicon carbide film 1214 of the semiconductor substrate 121 indicates that atoms move upward and attach to the second surface 1212 of the semiconductor substrate 121 to form the first silicon carbide film 1214.

[0141] This application etches the first surface 1211 of the semiconductor substrate 121 under a first temperature field to obtain a first transition surface 1213, which can remove uneven parts or damaged layers on the first surface 1211 of the semiconductor substrate 121, thereby helping to improve the roughness of the first surface 1211 and providing better substrate conditions for the formation of the second silicon carbide film 1216 in the subsequent step S200.

[0142] This application forms a first silicon carbide film 1214 on the second surface 1212 of a semiconductor substrate 121 under a first temperature field. This can compensate for the material loss in the semiconductor substrate 121 due to the etching of the first surface 1211, thereby reducing material loss in the semiconductor substrate 121. At the same time, the formation of the first silicon carbide film 1214 on the second surface 1212 allows the atoms of the second surface 1212 to be rearranged, enabling surface reconstruction of the second surface 1212 of the semiconductor substrate 121 and helping to form a more uniform underlying structure.

[0143] S200: The first transition surface 1213 and the first silicon carbide film 1214 are processed under a second temperature field to etch the first silicon carbide film 1214 to obtain the second transition surface 1215, and a second silicon carbide film 1216 is formed on the first transition surface 1213. The temperature of the first transition surface 1213 on the same semiconductor substrate 121 is higher than the temperature of its first silicon carbide film 1214.

[0144] In this embodiment, when performing step S200, the semiconductor substrate 121 after being processed in step S100 can be placed in the second temperature field first, and then the first transition surface 1213 and the first silicon carbide film 1214 of the semiconductor substrate 121 can be reprocessed.

[0145] In the second temperature field, the temperature of the first transition surface 1213 of the semiconductor substrate 121 is higher than the temperature of the first silicon carbide film 1214. That is, in the second temperature field, the first transition surface 1213 of each semiconductor substrate 121 is in a relatively high temperature region, while the first silicon carbide film 1214 is in a relatively low temperature region.

[0146] For example, the temperature distribution of the second temperature field can be as follows: along the thickness direction parallel to the semiconductor substrate 121, the temperature of the second temperature field can gradually increase from the first silicon carbide film 1214 toward the first transition surface 1213. In other words, the first transition surface 1213 is in a relatively high-temperature environment of the second temperature field, while the first silicon carbide film 1214 is in a relatively low-temperature environment of the second temperature field.

[0147] In step S200, the first silicon carbide film 1214 of the semiconductor substrate 121 is processed to etch a second transition surface 1215; the first transition surface 1213 is processed to form a second silicon carbide film 1216, such as... Figure 11 As shown. In Figure 11 In the diagram, the thin lines with arrows indicate the direction of temperature change in the second temperature field, with the arrows pointing in the direction of increasing temperature. The broad lines with arrows indicate the direction of atomic motion, for example, in... Figure 11In the orientation shown, the broad line with arrows located below the second transition surface 1215 of the semiconductor substrate 121 indicates that the atoms of the first silicon carbide film 1214 move downwards and detach from the semiconductor substrate 121 to form the second transition surface 1215; the broad line with arrows located above the second silicon carbide film 1216 of the semiconductor substrate 121 indicates that the atoms move downwards and attach to the first transition surface 1213 of the semiconductor substrate 121 to form the second silicon carbide film 1216.

[0148] The interpretations of the broad arrowed lines and thin arrowed lines in the other related attached figures are as follows: Figure 10 and Figure 11 The meanings are the same, and to avoid redundancy, this application will not repeat the corresponding labels in other figures. It should be understood that the downward movement of atoms and / or the downward movement of atoms mentioned herein are for ease of understanding and explanation in conjunction with the orientation of the figures, and are not specific restrictions on the direction of atomic movement, nor should they be regarded as limitations on this application.

[0149] This application etches the first silicon carbide film 1214 of the semiconductor substrate 121 under a second temperature field to obtain a second transition surface 1215. This removes excess growth material from the lower layer structure of the semiconductor substrate 121, maintains the uniformity of the overall thickness of the semiconductor substrate 121, and further improves the surface flatness of the semiconductor substrate 121. Furthermore, etching the first silicon carbide film 1214 to obtain the second transition surface 1215 can further enable atomic rearrangement of the second surface 1212 of the semiconductor substrate 121, thereby improving the flatness of the second surface 1212 of the semiconductor substrate 121.

[0150] Under the second temperature field, a second silicon carbide film 1216 is formed on the first transition surface 1213 of the semiconductor substrate 121. This can compensate for the material loss in the semiconductor substrate 121 caused by the etching of the first silicon carbide film 1214, thereby reducing material loss in the semiconductor substrate 121. At the same time, the formation of the second silicon carbide film 1216 on the first transition surface 1213 can fill the depressions in the first transition surface 1213, thereby rearranging the atoms of the first transition surface 1213. This can achieve surface reconstruction of the first transition surface 1213 of the semiconductor substrate 121, which helps to form a more uniform upper layer structure.

[0151] It should be noted that the terms "upper structure" and "lower structure" mentioned herein are for ease of understanding and explanation in conjunction with the illustrated orientation, and are not specific limitations on the upper and lower structures of the semiconductor substrate 121, nor should they be considered as limitations on this application. For example, in some embodiments, the upper structure may be a portion corresponding to the first surface 1211 of the semiconductor substrate 121, and the lower structure may be a portion corresponding to the second surface 1212 of the semiconductor substrate 121; or, in other embodiments, the upper structure may be a portion corresponding to the second surface 1212 of the semiconductor substrate 121, and the lower structure may be a portion corresponding to the first surface 1211 of the semiconductor substrate 121.

[0152] This application employs alternating etching and silicon carbide film formation. On one hand, this allows for the rearrangement of atoms on the first surface 1211 and the second surface 1212 of the semiconductor substrate 121, achieving surface reconstruction of the semiconductor substrate 121. This gradually reduces surface unevenness and damage, thereby improving the surface quality and structural performance of the semiconductor substrate 121, enhancing its planarization effect, and ultimately achieving planarization of the semiconductor substrate 121. On the other hand, because this application uses alternating etching and epitaxial growth, it is a non-contact planarization method compared to grinding and polishing. This eliminates the pressure applied to the semiconductor substrate 121 by traditional polishing processes, thus reducing or eliminating the presence of hidden damage layers. Furthermore, compared to traditional grinding and polishing processes, the surface treatment method for the semiconductor substrate 121 in this application saves on consumables related to grinding wheels and CMP processes, significantly reducing processing costs.

[0153] It should be understood that in this embodiment, step S100 is performed under the first temperature field, and step S200 is performed under the second temperature field. Along the thickness direction parallel to the semiconductor substrate 121, the temperature of the first temperature field can gradually decrease from the second surface 1212 towards the first surface 1211, and the temperature of the second temperature field can gradually increase from the first silicon carbide film 1214 towards the first transition surface 1213. It can be seen that the temperature gradient directions of the first and second temperature fields are opposite. Under the reversed temperature gradient trend, step S200 is equivalent to the reverse process of step S100, and the movement of all gaseous components will also be reversed accordingly.

[0154] Furthermore, step S100 is performed under the first temperature field, and step S200 is performed under the second temperature field. The switching between the first temperature field and the second temperature field can be achieved in at least the following two ways.

[0155] The first feasible method is to change the heating power or insulation efficiency of the working chamber.

[0156] Figure 12This diagram illustrates an implementation of a first temperature field and / or a second temperature field according to an embodiment of this application. In this implementation, corresponding heaters can be provided at the top and bottom of the working chamber, respectively. For example, a first heater 41 can be configured at the top of the working chamber, and a second heater 42 can be provided at the bottom of the working chamber. In this way, the required operating conditions can be achieved by adjusting the power of the first heater 41 and the second heater 42.

[0157] For example, to achieve a first temperature field (i.e., the temperature of the first surface 1211 is lower than the temperature of the second surface 1212), the power of the corresponding heater near the first surface 1211 can be adjusted to be lower than that of the other heater. For instance, if the upper surface of the semiconductor substrate 121 is the first surface 1211 and the lower surface is the second surface 1212, the power of the first heater 41 at the top of the working chamber can be adjusted to be lower than that of the second heater 42 at the bottom of the working chamber.

[0158] To achieve a second temperature field (i.e., the temperature at the first transition surface 1213 is higher than the temperature at the first silicon carbide film 1214), the power of the corresponding heater near the first silicon carbide film 1214 can be adjusted to be lower than that of the other heater. For example, if the upper surface of the semiconductor substrate 121 is the first surface 1211 and the lower surface is the second surface 1212, the power of the first heater 41 at the top of the working chamber can be adjusted to be higher than that of the second heater 42 at the bottom of the working chamber.

[0159] The implementation of the first temperature field and / or the second temperature field can achieve rapid switching of operating conditions by flexibly adjusting the power of the corresponding heater, without needing to move the semiconductor substrate 121 in the heating chamber. The implementation method is simple and easy to operate.

[0160] The first heater 41 and / or the second heater 42 may be an induction heater or a resistance heater, etc. This application does not impose any special restrictions on the specific types of the first heater 41 and the second heater 42.

[0161] Alternatively, the heating chamber can be a covered crucible 46, meaning that steps S100 and S200 can be performed inside the crucible 46.

[0162] Furthermore, to facilitate the introduction or discharge of gas into the heating chamber, an inlet pipe and an outlet pipe connected to the heating chamber can be provided respectively. The inlet pipe can be equipped with a first valve 43, and the outlet pipe can be equipped with a second valve 44. The first valve 43 is used to control the introduction of gas, and the second valve 44 is used to control the discharge of gas.

[0163] In addition, a pressure pipeline connected to the heating chamber can be installed, with a third valve 45 on the pressure pipeline for regulating the pressure inside the heating chamber. Alternatively, a pressure gauge can be installed for real-time or intermittent monitoring of the pressure inside the heating chamber.

[0164] The second possible approach is to keep the temperature field constant by flipping the semiconductor substrate 121.

[0165] In other words, in this implementation, the temperature field remains constant. Steps S100 and S200 are always performed within the same temperature field. When a temperature field needs to be switched, it can be achieved by flipping the semiconductor substrate 121. It should be noted that "temperature field remains constant" here refers to the temperature field remaining constant relative to the heating chamber. For the opposite sides of the semiconductor substrate 121, even if the temperature field of the heating chamber remains constant, the temperature field changes for the opposite sides of the semiconductor substrate 121 due to the switching of their positions. In step S100, the opposite sides of the semiconductor substrate 121 are in the first temperature field, while in step S200, due to the flipping of the semiconductor substrate 121, the opposite sides of the semiconductor substrate 121 are in the second temperature field.

[0166] For example, the temperature field can always be maintained at a preset temperature field (e.g., the top of the heating chamber is always kept at a relatively low temperature, and the bottom of the heating chamber is always kept at a relatively high temperature). In this case, if it is necessary to be in the first temperature field, the semiconductor substrate 121 is placed in the preset temperature field, and the first surface 1211 of the semiconductor substrate 121 is close to the top of the heating chamber, while the second surface 1212 of the semiconductor substrate 121 is close to the bottom of the heating chamber (i.e., the first surface 1211 of the semiconductor substrate 121 faces upward and the second surface 1212 faces downward). If it is necessary to be in the second temperature field, the semiconductor substrate 121 is placed in the preset temperature field, and the first silicon carbide film 1214 of the semiconductor substrate 121 is close to the top of the heating chamber, while the first transition surface 1213 of the semiconductor substrate 121 is close to the bottom of the heating chamber (i.e., the first silicon carbide film 1214 of the semiconductor substrate 121 faces upward and the first transition surface 1213 faces downward).

[0167] Among them, when the preset temperature field is such that the top of the heating chamber always maintains a relatively high temperature and the bottom of the heating chamber always maintains a relatively low temperature, it can be simply deduced from the previous case where the top of the heating chamber always maintains a relatively low temperature and the bottom of the heating chamber always maintains a relatively high temperature, and this application will not list it again.

[0168] Furthermore, the aforementioned flipping semiconductor substrate 121 refers to swapping the two opposite sides of the substrate. For example, if the first surface 1211 is facing up and the second surface 1212 is facing down, then after flipping the semiconductor substrate 121, the first surface 1211 should be facing down and the second surface 1212 should be facing up.

[0169] Please refer to Figures 13 to 16 ,in, Figure 13 A comparison image of the appearance of the Si surface of a semiconductor substrate 121 before and after surface treatment according to an embodiment of this application; Figure 14 A comparison image of the appearance of the C-side of a semiconductor substrate 121 before and after surface treatment according to an embodiment of this application; Figure 15 A comparative image of the Si surface of another semiconductor substrate 121 before and after surface treatment by a method provided in the embodiments of this application. Figure 16 This is a comparison image of the appearance of the C-side of another semiconductor substrate 121 before and after surface treatment by a surface treatment method provided in an embodiment of this application.

[0170] exist Figure 13 In (a), the original surface roughness of the semiconductor substrate 121 before processing is 18.1 nm when the area scanned by an atomic force microscope (AFM) is 5 μm × 5 μm; after the surface processing of this application, the processed semiconductor substrate 121 is as follows: Figure 13 As shown in (b), when the AFM scanning area size is 20 μm × 20 μm, the roughness of its Si surface is 1.6 nm. Figure 14 In (a), the roughness of the C-surface of the original surface of the semiconductor substrate 121 before processing is 11.3 nm when the AFM scanning area size is 5 μm × 5 μm; after the surface processing of this application, the processed semiconductor substrate 121 is as follows: Figure 14 As shown in (b), when the AFM scanning area is 20 μm × 20 μm, the roughness of its C-plane is 0.85 nm. It can be seen that after the surface treatment method provided in this application, the roughness of both the Si-plane and the C-plane of the semiconductor substrate 121 is improved, and the surface treatment method of this application is helpful for the planarization process.

[0171] exist Figure 15 In (a), the roughness of the Si surface of the original semiconductor substrate 121 before processing is 3.1 nm when the AFM scanning area size is 5 μm × 5 μm; after the surface processing of this application, the processed semiconductor substrate 121 is as follows: Figure 15As shown in (b), when the AFM scanning area size is 20 μm × 20 μm, the roughness of its Si surface is 1.4 nm. Figure 16 In (a), the roughness of the C-plane of the original surface of the semiconductor substrate 121 before processing is 2.4 nm when the AFM scanning area size is 5 μm × 5 μm; after the surface processing of this application, the processed semiconductor substrate 121 is as follows: Figure 16 As shown in (b), when the AFM scanning area is 20 μm × 20 μm, the roughness of its C-plane is 0.19 nm (while for CMP process, the standard for P-grade wafers is 0.2 nm. It can be seen that the planarization accuracy of the surface treatment method in this application has already met the standard). It can be seen that after the surface treatment method provided in this application, the roughness of the Si and C-planes of the semiconductor substrate 121 is also greatly improved.

[0172] In one feasible manner, the process conditions of the surface treatment method for the semiconductor substrate 121 include: the working gas pressure of the surface treatment method for the semiconductor substrate 121 is between 0.1 mbar and 100 mbar.

[0173] That is, when steps S100 and S200 are performed, the working air pressure is between 0.1 mbar and 100 mbar. In other words, when steps S100 and S200 are performed, the air pressure in the heating chamber is between 0.1 mbar and 100 mbar.

[0174] For example, the working air pressure can be 0.1 mbar, 1 mbar, 10 mbar, 30 mbar, 50 mbar, 80 mbar or 100 mbar, etc.

[0175] Steps S100 and S200 are performed in the aforementioned low-pressure environment, which reduces the vapor pressure of silicon. Vapor pressure is the pressure at which a substance reaches equilibrium between its gaseous and solid (or liquid) states. Therefore, reducing the vapor pressure means that silicon atoms are more likely to transition from a solid to a gaseous state, i.e., more likely to undergo sublimation. Because the low-pressure environment reduces the vapor pressure of silicon, silicon atoms are more likely to detach from the surface of the semiconductor substrate 121 after thermal decomposition and be removed in gaseous form. In addition, the low-pressure environment also helps to reduce interference from other impurity gases on the reaction process, thereby maintaining the purity of the reaction environment.

[0176] In one feasible manner, the process conditions of the surface treatment method for the semiconductor substrate 121 include at least one of the following:

[0177] The highest temperature in the first temperature field is between 1800℃ and 2100℃;

[0178] The highest temperature in the second temperature field is between 1800℃ and 2100℃;

[0179] The temperature gradient of the first temperature field is between 0.1℃ / mm and 5℃ / mm;

[0180] The temperature gradient of the second temperature field is between 0.1℃ / mm and 5℃ / mm.

[0181] The highest temperature of the first temperature field can be 1800℃, 1900℃, 2000℃ or 2100℃, etc.; the highest temperature of the second temperature field can be 1800℃, 1900℃, 2000℃ or 2100℃, etc.

[0182] Furthermore, the highest temperatures of the first and second temperature fields can be the same or different. Additionally, the lowest temperatures of the first and second temperature fields can also be the same or different. That is, the temperature range of the first temperature field can be the same as or different from the temperature range of the second temperature field.

[0183] The temperature gradient of the first temperature field can be 0.1℃ / mm, 0.5℃ / mm, 1℃ / mm, 2℃ / mm, 3℃ / mm, 4℃ / mm, or 5℃ / mm, etc. The temperature gradient of the second temperature field can also be 0.1℃ / mm, 0.5℃ / mm, 1℃ / mm, 2℃ / mm, 3℃ / mm, 4℃ / mm, or 5℃ / mm, etc. Here, the temperature gradient is the rate of change of temperature along the normal to its isothermal surface.

[0184] The temperature gradients of the first temperature field and the second temperature field can be the same or different.

[0185] In some feasible implementations, the temperature gradient direction of the first temperature field is opposite to that of the second temperature field. That is, the temperature change trend of the first temperature field is opposite to that of the second temperature field. Alternatively, it can be understood that one temperature gradient of the first temperature field is positive and the other is negative. For ease of understanding, this application illustrates this with the following example: if the temperature of the first temperature field gradually decreases from bottom to top, then the temperature of the second temperature field gradually increases from bottom to top; if the temperature of the first temperature field gradually increases from bottom to top, then the temperature of the second temperature field gradually decreases from bottom to top.

[0186] This application sets the first temperature field and / or the second temperature field to a high-temperature environment. This high temperature provides the necessary energy for etching the surface of the semiconductor substrate 121, making it easier to break the chemical bonds between silicon and carbon atoms on the surface of the semiconductor substrate 121. This allows the silicon atoms on the surface of the semiconductor substrate 121 to sublimate and detach from the first surface 1211. Furthermore, the high-temperature environment can accelerate the rate of chemical reactions, making the etching of the semiconductor substrate 121 more rapid and efficient.

[0187] This application achieves a gradual temperature change between the first and second temperature fields by setting temperature gradients for each. Under the influence of these temperature gradients, it facilitates the movement of gaseous products (such as sublimated silicon atoms and silicon carbide gaseous products) along the temperature gradient direction. This aids in the removal of silicon and carbon atoms from the surface of the semiconductor substrate 121 (e.g., removing silicon atoms from the surface of the semiconductor substrate 121 and transporting silicon carbide gaseous products to the bottom surface of the semiconductor substrate 121), thereby accelerating the etching rate. Furthermore, the temperature gradient can enhance the convection and diffusion of gas molecules, thus accelerating the material transport rate.

[0188] Please refer to Figure 17 As shown, Figure 17 The x-axis represents temperature, and the y-axis represents etching rate (μm / h). It can be seen that at the same temperature, the etching rate gradually increases as the operating pressure decreases. That is, operating pressure and etching rate are inversely proportional. At the same pressure, the etching rate gradually increases as the temperature increases. That is, temperature and etching rate are directly proportional. Therefore, there is a corresponding relationship between etching rate, temperature, and operating pressure, allowing for the selection of appropriate process conditions based on actual needs.

[0189] like Figure 7 As shown, in one possible implementation, the etching of the first surface 1211 to obtain the first transition surface 1213 in step S100 may include steps S110-S120.

[0190] S110, causing silicon atoms on the first surface 1211 to detach from the first surface 1211 to obtain the first sub-transition surface.

[0191] S120, causing the carbon atoms of the first sub-transition surface to detach from the first sub-transition surface, so as to obtain the first transition surface 1213.

[0192] That is, the silicon atoms and carbon atoms on the first surface 1211 are detached from the first surface 1211 of the semiconductor substrate 121 one after another.

[0193] In one possible implementation, in step S110, the silicon atoms of the first surface 1211 are detached from the first surface 1211 by causing the silicon atoms of the first surface 1211 to detach from the first surface 1211 under the action of thermal decomposition.

[0194] For example, the silicon atoms on the first surface 1211 can undergo the following reaction (1):

[0195] SiC(s)→Si(g)+C(s) (1)

[0196] The reaction conditions for the above reaction formula (1) can be high temperature and heating conditions. Si(g) represents silicon in gaseous (vapor) form, SiC(s) represents silicon carbide in solid form, and C(s) represents carbon in solid form. This reaction formula (1) is a thermal decomposition reaction. High temperature conditions can break the chemical bonds in silicon carbide, thereby separating silicon atoms and carbon atoms.

[0197] In this process, after silicon atoms detach from the first surface 1211 of the semiconductor substrate 121, a first sub-transition surface is obtained, which also has residual carbon atoms.

[0198] After step S110 is completed, in step S120, carbon atoms on the first sub-transition surface can be detached from the first sub-transition surface. In this way, the carbon atoms remaining on the first sub-transition surface can also detach from the first sub-transition surface, thereby obtaining the first transition surface 1213.

[0199] After steps S110 and S120, silicon atoms and carbon atoms on the first surface 1211 are removed from the first surface 1211, which can achieve etching of the first surface 1211 to obtain the first transition surface 1213.

[0200] In one possible implementation, step S120, which causes the carbon atoms of the first sub-transition surface to detach from the first sub-transition surface, can be achieved in the following way:

[0201] The reactant gas reacts chemically with the carbon atoms on the first transition surface to generate silicon carbide gaseous products.

[0202] In other words, in step S120, the carbon atoms of the first sub-transition surface can be separated from the first sub-transition surface by a chemical reaction between the reactant gas and the carbon atoms of the first sub-transition surface, thereby generating silicon carbide gaseous products.

[0203] The reaction gas can be introduced into the heating chamber from the outside, or it can be obtained from the solid material in the heating chamber through thermal decomposition or other methods. Of course, it can also be a combination of both methods (i.e., part of the reaction gas is introduced into the heating chamber from the outside, and the other part is obtained from the solid material in the heating chamber through thermal decomposition or other methods). This application does not impose any special restrictions on the specific source of the reaction gas.

[0204] This application removes residual carbon atoms from the first transition surface using a chemical method. The chemical reaction can be precisely controlled by adjusting the amount of reactant gas, reaction temperature, and reaction time. By combining different process environments with the carbon and silicon atom ratios of the semiconductor substrate 121, the roughness and step width of the first surface 1211 can be adjusted and controlled. This method offers high precision and controllability, enabling the more accurate removal of specific amounts of carbon atoms, thereby regulating the degree of planarization.

[0205] In one possible implementation, the aforementioned reactive gas may include at least one of silicon vapor, silane (SiH4), trichlorosilane (HCl3Si), disilane (Si2H6), or silicon tetrachloride (SiCl4).

[0206] Taking silicon vapor as an example, when the reactant gas is silicon vapor, the reactant gas reacts chemically with the carbon atoms of the first transition surface to generate silicon carbide gaseous products, which can be the following reaction formulas (2) and (3):

[0207] Si(g) + 2C(s) → SiC2(g) (2)

[0208] 2Si(g) + C(s) → Si₂C(g) (3)

[0209] That is, when the reaction gas is silicon vapor, the silicon vapor reacts chemically with the carbon atoms remaining on the first transition surface to generate gaseous SiC2 (silicon dicarbide) and Si2C (carbon disilicide).

[0210] In the above reaction formula (2), SiC2(g) indicates that silicon dicarbide exists in a gaseous state, and in the above reaction formula (3), Si2C(g) indicates that carbon disilicide exists in a gaseous state.

[0211] Chemical considerations during heating: Taking 1600℃ as an example, the partial pressures of Si, Si2C, and SiC2 on the silicon carbide surface are 1 Pa, 0.1 Pa, and 0.01 Pa, respectively. The partial pressure of Si is two orders of magnitude higher than that of SiC2. In other words, the temperatures required for the above gaseous components to reach 1 Pa are different. The sublimation temperature of Si is generally around 1600℃, while the sublimation temperature of SiC2 is generally 200℃-400℃ higher than that of Si. During the temperature rise process, there is often a delay in heating time (or waiting for the temperature to climb in the temperature field). Therefore, generally, Si will sublimate before SiC2, which will lead to carbon deposition on the surface of the semiconductor substrate 121. That is, generally, during the heating process, Si will sublimate and detach from the surface of the semiconductor substrate 121 first, followed by Si2C and SiC2.

[0212] When the reactant gas is SiH4, HCl3Si, or Si2H6, the product is also a silicon carbide gaseous product, and may be accompanied by other gaseous products, such as hydrogen (H2), hydrogen chloride (HCl), and chlorine (Cl2). These other gaseous products can escape from the reaction system, and the silicon carbide gaseous product will also detach from the semiconductor substrate 121.

[0213] In one possible implementation, the formation of the first silicon carbide film 1214 on the second surface 1212 in step S100 can be achieved by the following method:

[0214] The silicon carbide vapor product is deposited on the second surface 1212 to obtain the first silicon carbide film 1214.

[0215] That is, the formation of the first silicon carbide film 1214 in step S100 can be achieved by depositing the silicon carbide vapor products generated during the etching of the first surface 1211 onto the second surface 1212. In this way, the silicon carbide vapor products generated during the etching of the first surface 1211 can both detach from the first surface 1211 for etching and be deposited onto the second surface 1212 for reuse. This reduces the loss of the semiconductor substrate 121.

[0216] For example, when the silicon carbide vapor products generated during etching of the first surface 1211 are gaseous SiC2 and Si2C, due to the changing trend of the temperature gradient (i.e., the temperatures of the two opposite surfaces of the semiconductor substrate 121 are different), the sublimated SiC2 and Si2C will reach the second surface 1212 of the semiconductor substrate 121 and attach and grow. SiC2 will capture a silicon atom in the environment to generate silicon carbide. When Si2C generates silicon carbide, it will release a silicon atom, i.e., the following reactions (4) and (5) will occur:

[0217] Si(g) + SiC2(g) → 2SiC(s) (4)

[0218] Si₂C(g) + Si(g) → SiC(s) (5)

[0219] When performing step S100 on the semiconductor substrate 121, multiple stacked and spaced semiconductor substrates 121 may be surface-treated simultaneously, or a single semiconductor substrate 121 may be surface-treated individually. This application does not limit the specific number of semiconductor substrates 121.

[0220] For example, when there is only one semiconductor substrate 121, the silicon carbide vapor product generated by etching the first surface 1211 of the semiconductor substrate 121 can be guided by a certain guiding method or guiding device to deposit on the second surface 1212 of the semiconductor substrate 121 to obtain a first silicon carbide film 1214.

[0221] Alternatively, when there is only one semiconductor substrate 121, it can be placed inside a silicon carbide crucible 46. In this way, the silicon carbide vapor products generated by the semiconductor substrate 121 can be deposited on the top (or bottom) of the crucible 46, while the silicon carbide vapor products formed at the bottom (or top) of the crucible 46 due to the removal of carbon atoms can be deposited on the second surface 1212 of the semiconductor substrate 121. Therefore, it is also possible to deposit silicon carbide vapor products on the second surface 1212 to obtain a first silicon carbide film 1214.

[0222] In other words, this application does not restrict the specific source of the silicon carbide gaseous product. It can be obtained by etching the first surface 1211, or by a heating container such as a crucible 46, or by other materials.

[0223] For example, the semiconductor substrate 121 may include multiple semiconductor substrates 121, which are arranged at intervals along a first direction, the first direction being parallel to the thickness direction of the semiconductor substrate 121, such as... Figure 18 As shown. At this point, the deposition of the silicon carbide vapor products on the second surface 1212 can be achieved in the following way:

[0224] Silicon carbide vapor products of a semiconductor substrate 121 are deposited on a second surface 1212 of the semiconductor substrate 121 adjacent to it.

[0225] by Figure 20 For example, when there are multiple semiconductor substrates 121, the silicon carbide vapor products of one semiconductor substrate 121 can be deposited on the second surface 1212 of the adjacent semiconductor substrate 121. In this way, multiple semiconductor substrates 121 can be surface-treated simultaneously, which can improve the processing efficiency.

[0226] The two semiconductor substrates 121 at both ends can utilize a silicon carbide crucible 46 as an auxiliary device to achieve the deposition of silicon carbide vapor products. For example, assuming the semiconductor substrate 121 comprises three parts: upper, middle, and lower... Figure 20 As shown, the first surface 1211 of each semiconductor substrate 121 is in a low-temperature region and the second surface 1212 is in a high-temperature region. The silicon carbide vapor product formed by the detachment of carbon atoms at the bottom of the crucible 46 can be attached and grown on the second surface 1212 of the bottommost semiconductor substrate 121. The silicon carbide vapor product generated by etching the first surface 1211 of the bottommost semiconductor substrate 121 can be attached and grown on the second surface 1212 of the middle semiconductor substrate 121. The silicon carbide vapor product generated by etching the first surface 1211 of the middle semiconductor substrate 121 can be attached and grown on the second surface 1212 of the topmost semiconductor substrate 121. The silicon carbide vapor product generated by etching the first surface 1211 of the topmost semiconductor substrate 121 can be attached and grown on the top of the crucible 46.

[0227] Since the surface treatment method of the semiconductor substrate 121 in this application requires surface treatment of the semiconductor substrate 121 under a first temperature field and also under a second temperature field, the temperature field switching will not affect the top and bottom of the crucible 46, or the effect on the top and bottom of the crucible 46 is very small and can be ignored.

[0228] In one possible implementation, step S200 involves etching the first silicon carbide film 1214 to obtain the second transition surface 1215, as shown below. Figure 8 As shown, steps S210-S220 may be included:

[0229] S210, causing silicon atoms in the first silicon carbide film 1214 to detach from the first silicon carbide film 1214 to obtain the second sub-transition surface.

[0230] S220 causes the carbon atoms of the second sub-transition surface to detach from the second sub-transition surface, thus obtaining the second transition surface 1215.

[0231] That is, the silicon atoms and carbon atoms of the first silicon carbide film 1214 are detached from the first silicon carbide film 1214 of the semiconductor substrate 121 one after another.

[0232] In one possible implementation, in step S210, the silicon atoms of the first silicon carbide film 1214 are detached from the first silicon carbide film 1214 by causing the silicon atoms of the first silicon carbide film 1214 to detach from the first surface 1211 under the action of thermal decomposition.

[0233] For example, the silicon atoms of the first silicon carbide film 1214 can undergo the following reaction (6):

[0234] SiC(s)→Si(g)+C(s) (6)

[0235] The reaction conditions for the above reaction formula (6) can be high temperature and heating conditions. SiC(s) represents silicon carbide in solid form, Si(g) represents silicon in gaseous (vapor) form, and C(s) represents carbon in solid form. This reaction formula (6) is a thermal decomposition reaction. High temperature conditions can break the chemical bonds in silicon carbide, thereby separating silicon atoms and carbon atoms.

[0236] In this process, after silicon atoms detach from the first silicon carbide film 1214 of the semiconductor substrate 121, a second sub-transition surface is obtained, which also has residual carbon atoms.

[0237] After performing step S210, in step S220, carbon atoms on the second sub-transition surface can be detached from the second sub-transition surface. In this way, the carbon atoms remaining on the second sub-transition surface can also detach from the second sub-transition surface, thereby obtaining the second transition surface 1215.

[0238] After steps S210 and S220, silicon atoms and carbon atoms of the first silicon carbide film 1214 are removed from the first silicon carbide film 1214, which can realize the etching of the first silicon carbide film 1214 to obtain the second transition surface 1215.

[0239] In one feasible manner, step S220, which causes the carbon atoms of the second sub-transition surface to detach from the second sub-transition surface, can be achieved in the following way:

[0240] The reactant gas reacts chemically with the carbon atoms on the second transition surface to generate silicon carbide gaseous products.

[0241] That is, in step S120, the carbon atoms of the second sub-transition surface can be separated from the second sub-transition surface by a chemical reaction between the reactant gas and the carbon atoms of the second sub-transition surface, thereby generating silicon carbide gaseous products.

[0242] Similar to step S120, the reaction gas can be introduced into the heating chamber from the outside, or it can be obtained from the solid material in the heating chamber through thermal decomposition or other methods. Of course, both methods can be used (i.e., part of the reaction gas is introduced into the heating chamber from the outside, and the other part is obtained from the solid material in the heating chamber through thermal decomposition or other methods). This application does not impose any special restrictions on the specific source of the reaction gas.

[0243] This application removes residual carbon atoms from the second transition surface using a chemical method. The chemical reaction can be precisely controlled by adjusting the amount of reactant gas, reaction temperature, and reaction time. By combining different process environments with the carbon and silicon atom ratios of the semiconductor substrate 121, the roughness and step width of the first silicon carbide film 1214 can be adjusted and controlled. This method offers high precision and controllability, enabling more accurate removal of specific amounts of carbon atoms, thereby regulating the degree of planarization.

[0244] In one possible implementation, the reaction gas in step S220 may include at least one of silicon vapor, silane, trichlorosilane, ethoxysilane, or silicon tetrachloride.

[0245] Taking silicon vapor as an example, when the reactant gas is silicon vapor, the reactant gas reacts chemically with the carbon atoms of the second transition surface to generate silicon carbide gaseous products, which can be the following reaction formulas (7) and (8):

[0246] Si(g) + 2C(s) → SiC2(g) (7)

[0247] 2Si(g) + C(s) → Si₂C(g) (8)

[0248] That is, when the reaction gas is silicon vapor, the silicon vapor reacts chemically with the carbon atoms remaining on the second transition surface to generate gaseous SiC2 and Si2C.

[0249] In the above reaction formula (7), SiC2(g) indicates that silicon dicarbide exists in a gaseous state, and in the above reaction formula (8), Si2C(g) indicates that carbon disilicide exists in a gaseous state.

[0250] Chemical considerations during the heating process: Taking 1600℃ as an example, the partial pressures of Si, Si2C, and SiC2 on the silicon carbide surface are 1 Pa, 0.1 Pa, and 0.01 Pa, respectively. The partial pressure of Si is two orders of magnitude higher than that of SiC2. In other words, the temperatures required for the above gaseous components to reach 1 Pa are different. The sublimation temperature of Si is generally around 1600℃, while the sublimation temperature of SiC2 is generally 200℃-400℃ higher than that of Si. During the temperature rise process, there is often a delay in heating time (or waiting for the temperature to climb in the temperature field). Therefore, generally, Si will sublimate before SiC2, which will lead to carbon deposition on the first silicon carbide film 1214. That is, generally, during the heating process, Si will sublimate and detach from the first silicon carbide film 1214 first, followed by Si2C and SiC2.

[0251] When the reactant gas is SiH4, HCl3Si, or Si2H6, the product is also a silicon carbide gaseous product, and may be accompanied by other gaseous products, such as hydrogen (H2), hydrogen chloride (HCl), and chlorine (Cl2). These other gaseous products can escape from the reaction system, and the silicon carbide gaseous product will also detach from the semiconductor substrate 121.

[0252] In one possible implementation, the formation of the second silicon carbide film 1216 at the first transition surface 1213 in step S200 can be achieved by the following method:

[0253] The silicon carbide vapor product is deposited on the first transition surface 1213 to obtain the second silicon carbide film 1216.

[0254] That is, the formation of the second silicon carbide film 1216 in step S200 can be achieved by depositing the silicon carbide vapor products generated during the etching of the first silicon carbide film 1214 onto the first transition surface 1213. In this way, the silicon carbide vapor products generated during the etching of the first silicon carbide film 1214 can both detach from the first silicon carbide film 1214 for etching and be deposited onto the first transition surface 1213 for reuse. This reduces the loss of the semiconductor substrate 121.

[0255] For example, when the silicon carbide vapor products generated during the etching of the first silicon carbide film 1214 are gaseous SiC2 and Si2C, due to the changing trend of the temperature gradient (i.e., the temperatures of the two opposite surfaces of the semiconductor substrate 121 are different), the sublimated SiC2 and Si2C will reach the first transition surface 1213 of the semiconductor substrate 121 and attach and grow. SiC2 will capture a silicon atom in the environment to generate silicon carbide. When Si2C generates silicon carbide, it will release a silicon atom, i.e., the following reactions (9) and (10) will occur:

[0256] Si(g) + SiC2(g) → 2SiC(s) (9)

[0257] Si₂C(g) + Si(g) → SiC(s) (10)

[0258] In the process of performing step S200 on the semiconductor substrate 121, multiple semiconductor substrates 121 stacked and spaced apart may be surface-treated simultaneously, or a single semiconductor substrate 121 may be surface-treated individually. This application does not limit the specific number of semiconductor substrates 121.

[0259] For example, when there is only one semiconductor substrate 121, the silicon carbide vapor product generated by etching the first silicon carbide film 1214 of the semiconductor substrate 121 can be guided by a certain guiding method or guiding device to deposit on the first transition surface 1213 of the semiconductor substrate 121 to obtain the second silicon carbide film 1216.

[0260] Alternatively, when there is only one semiconductor substrate 121, it can be placed inside a silicon carbide crucible 46. In this way, the silicon carbide vapor products generated by the semiconductor substrate 121 can be deposited at the bottom (or top) of the crucible 46, while the silicon carbide vapor products formed on the top (or bottom) of the crucible 46 due to the removal of carbon atoms can be deposited on the first transition surface 1213 of the semiconductor substrate 121. Therefore, it is also possible to deposit silicon carbide vapor products on the first transition surface 1213 to obtain a second silicon carbide film 1216.

[0261] In other words, this application does not restrict the specific source of the silicon carbide gaseous product. It can be obtained by etching the first silicon carbide film 1214, or by a heating container such as a crucible 46, or by other materials.

[0262] For example, the semiconductor substrate 121 may include multiple semiconductor substrates 121, which are arranged at intervals along a first direction parallel to the thickness direction of the semiconductor substrate 121. In this case, the deposition of silicon carbide vapor products on the first transition surface 1213 can be achieved in the following manner:

[0263] Silicon carbide vapor products of a semiconductor substrate 121 are deposited on a first transition surface 1213 of the adjacent semiconductor substrate 121.

[0264] by Figure 22 For example, when there are multiple semiconductor substrates 121, the silicon carbide vapor product of one semiconductor substrate 121 can be deposited on the first transition surface 1213 of the adjacent semiconductor substrate 121. In this way, multiple semiconductor substrates 121 can be surface-treated simultaneously, which can improve the processing efficiency.

[0265] The two semiconductor substrates 121 at both ends can utilize a silicon carbide crucible 46 as an auxiliary device to achieve the deposition of silicon carbide vapor products. For example, assuming the semiconductor substrate 121 comprises three parts: upper, middle, and lower... Figure 22 As shown, the first silicon carbide film 1214 of each semiconductor substrate 121 is in a low-temperature region, and the first transition surface 1213 is in a high-temperature region. The silicon carbide vapor product formed by the detachment of carbon atoms at the top of the crucible 46 can be attached to and grown on the first transition surface 1213 of the uppermost semiconductor substrate 121. The silicon carbide vapor product generated by etching the first silicon carbide film 1214 of the uppermost semiconductor substrate 121 can be attached to and grown on the first transition surface 1213 of the middle semiconductor substrate 121. The silicon carbide vapor product generated by etching the first silicon carbide film 1214 of the middle semiconductor substrate 121 can be attached to and grown on the first transition surface 1213 of the lowermost semiconductor substrate 121. The silicon carbide vapor product generated by etching the first silicon carbide film 1214 of the lowermost semiconductor substrate 121 can be attached to and grown on the bottom of the crucible 46.

[0266] In one possible implementation, after the first silicon carbide film 1214 is formed on the second surface 1212 and before the first silicon carbide film 1214 is etched to obtain the second transition surface 1215, the surface treatment method of the semiconductor substrate 121 provided in this application embodiment may further include step S300.

[0267] That is, the surface treatment method for the semiconductor substrate 121 provided in this application embodiment may further include a step S300 between step S100 and step S200, such as... Figures 19 to 22 As shown.

[0268] S300, Anneal the semiconductor substrate 121 at a constant temperature, such as... Figure 21 As shown.

[0269] like Figure 19 After executing step S100, step S300 can be executed, and then step S200 can be executed.

[0270] Annealing can eliminate impurities, defects, and grain boundaries, improving the crystal integrity of the semiconductor substrate 121, reducing defect density and dislocation density, thereby optimizing the crystal structure of the semiconductor substrate 121. Simultaneously, it can restore lattice symmetry, making the internal arrangement of the material more ordered, mitigating lattice strain, and improving the reliability of the semiconductor substrate 121. Furthermore, it can also achieve a rearrangement of the surface atoms of the semiconductor substrate 121. Therefore, performing the annealing process in step S300 can improve the crystal structure of the semiconductor substrate 121 and improve its surface flatness.

[0271] In addition, this application uses an annealing process to process the semiconductor substrate 121. Since the annealing process can suppress the sublimation of silicon atoms, it can reduce the material loss of the semiconductor substrate 121 while improving the planarization effect.

[0272] In one feasible approach, the annealing temperature is between 1600°C and 2100°C.

[0273] For example, the annealing temperature can be 1600℃, 1700℃, 1800℃, 1900℃, 2000℃ or 2100℃, etc.

[0274] Annealing within this temperature range allows the atoms on the surface of the semiconductor substrate 121 to diffuse and sublimate, while simultaneously facilitating equal amounts of deposition and adsorption. This enables the reconstruction of the surface atoms of the semiconductor substrate 121, resulting in further surface planarization.

[0275] Furthermore, in this embodiment, steps S100, S200, and S300 can be repeated multiple times until the desired process effect is achieved. That is, after executing step S200, the process can return to step S100 and continue repeating the process. Of course, when the surface treatment method for the semiconductor substrate 121 of this application does not include step S200, it is also possible to return to step S100 and continue repeating the process after executing step S200.

[0276] This application also provides a support device 03, please refer to Figure 23 and Figure 24As shown, the support device 03 is used to support the semiconductor substrate 121. The support device 03 includes at least one support structure 30, which includes a fixing member 31 and a support member 32.

[0277] That is, the support device 03 provided in this application can be used to support the semiconductor substrate 121. Thus, when the semiconductor substrate 121 needs to undergo the aforementioned surface treatment method, the support device 03 can be used to support it. Of course, the application of the support device 03 in the surface treatment method of the semiconductor substrate 121 is only one feasible application scenario of this application and is not a limitation on the application scenarios of the support device 03. The support device 03 can also be applied in other scenarios.

[0278] Of course, in other implementations, the support device 03 can be used to support the semiconductor substrate 121, or it can be used to support other components. This application does not impose any specific restrictions on the objects that the support device 03 can support.

[0279] In addition, this application does not limit the specific number of support structures 30; there can be one, two, or more.

[0280] For example, when only one semiconductor substrate 121 needs to be supported, only one support structure 30 can be provided; when multiple semiconductor substrates 121 need to be supported, multiple support structures 30 can be provided in layers.

[0281] Please refer to Figure 25 and Figure 26 The aforementioned fastener 31 may have a first connecting portion 311.

[0282] The support member 32 may include a second connecting portion 321. In this way, the first connecting portion 311 of the fixing member 31 and the second connecting portion 321 of the support member 32 can be connected to realize the connection between the fixing member 31 and the support member 32.

[0283] The fastener 31 can be a ring structure. That is to say, the fastener 31 can be a ring structure.

[0284] The fixing member 31 has a ring structure, so that a hollow area can be formed inside the fixing member 31, which makes it easy to place the semiconductor substrate 121 (or other supported object) in the hollow area, and can expose more of the semiconductor substrate 121 (or other supported object) so as to facilitate the corresponding process processing of the semiconductor substrate 121 (or other supported object).

[0285] The support member 32 may further include a support portion 322, which is connected to the second connecting portion 321. The support portion 322 can be used to support the semiconductor substrate 121, thereby providing support for the semiconductor substrate 121.

[0286] In this embodiment, the melting point of the fastener 31 is greater than or equal to 1800°C, and / or the melting point of the support 32 is greater than or equal to 1800°C.

[0287] In other words, the melting point of the fastener 31 can be greater than or equal to 1800℃, the melting point of the support 32 can be greater than or equal to 1800℃, or both the melting points of the fastener 31 and the support 32 can be greater than or equal to 1800℃.

[0288] By setting the melting point of the fastener 31 and / or the support 32 to be greater than or equal to 1800°C, this application can improve the high temperature resistance of the support device 03, enabling the support device 03 of this application to be used in high temperature environments.

[0289] For example, the material of the fastener 31 can be at least one of graphite, metal, carbide, nitride, boride or polycrystalline silicon carbide (SiC).

[0290] For example, when the material of the fastener 31 is a metal, it can be molybdenum (Mo), tungsten (W), rhenium (Re) or tantalum (Ta), etc.; when the material of the fastener 31 is a carbide, it can be tantalum carbide (TaC) or tantalum discarbide (Ta2C), etc.; when the material of the fastener 31 is a nitride, it can be boron nitride (BN) or tantalum nitride (Ta2N), etc.

[0291] For example, the material of the support member 32 can be at least one of graphite, metal, carbide, nitride, boride or polycrystalline silicon carbide (SiC).

[0292] For example, when the material of the support member 32 is a metallic material, it can be molybdenum (Mo), tungsten (W), rhenium (Re) or tantalum (Ta), etc.; when the material of the support member 32 is a carbide, it can be tantalum carbide (TaC) or tantalum discarbide (Ta2C), etc.; when the material of the support member 32 is a nitride, it can be boron nitride (BN) or tantalum discarbide (Ta2N), etc.

[0293] In one possible approach, please refer to Figures 24 to 26 The support member 32 may include multiple members, and the multiple support members 32 may be arranged at intervals along the circumference of the fixing member 31.

[0294] By providing multiple support members 32 and arranging them at intervals along the circumference of the fixing member 31, the multiple support members 32 can cooperate with each other to support the semiconductor substrate 121 (or other supported objects), thereby improving the support reliability of the semiconductor substrate 121 (or other supported objects).

[0295] Furthermore, this application does not limit the structural form and mating relationship of the first connecting part 311 and the second connecting part 321. For example, the first connecting part 311 and the second connecting part 321 can be connected by mortise and tenon joints, or by screws, or by any other feasible method, as long as the first connecting part 311 can be connected to the second connecting part 321 to realize the connection between the fastener 31 and the support 32.

[0296] In one possible implementation, the second connecting part 321 includes an insert groove, and the first connecting part 311 includes a protrusion located in the insert groove, connecting the fixing member 31 and the support member 32.

[0297] That is, the protrusion of the first connecting part 311 is embedded in the groove of the second connecting part 321, so that the fixing member 31 and the supporting member 32 are connected. This connection method is simple and reliable.

[0298] Of course, in other possible implementations, the bump and the groove can also be interchanged, that is, the first connecting part 311 may include the groove, while the second connecting part 321 includes the bump.

[0299] In one possible approach, please refer to Figure 23 and Figure 25 The support portion 322 may have a sheet-like structure and extends in a direction away from the second connecting portion 321; along the direction away from the second connecting portion 321, the cross-sectional area of ​​the support portion 322 gradually decreases.

[0300] The cross-section of the support portion 322 is perpendicular to the thickness direction of the semiconductor substrate 121, or in other words, the cross-section of the support portion 322 is perpendicular to the axial centerline of the fixing member 31.

[0301] Since the end of the support portion 322 away from the second connection portion 321 needs to support the semiconductor substrate 121, the cross-sectional area of ​​the support portion 322 gradually decreases along the direction away from the second connection portion 321. This means that the contact area between the support portion 322 and the semiconductor substrate 121 will become smaller, which can minimize the contact area between the support portion 322 and the semiconductor substrate 121.

[0302] Please refer to Figure 23 and Figure 25The support portion 322 may have a support end 3221, which is used to contact the semiconductor substrate 121. The support end 3221 may make point contact with the semiconductor substrate 121. This allows the support end 3221 to achieve point contact with the semiconductor substrate 121 when supporting it, reducing the contact area between the support device 03 and the semiconductor substrate 121. When the support device 03 is used in a high-temperature environment, it can reduce localized high temperatures caused by heat conduction and improve the uniformity of heat conduction on the semiconductor substrate 121.

[0303] In one possible approach, please refer to Figure 24 and Figure 25 The fastener 31 also has a third connecting part 313, and a receiving groove 312 is provided between the third connecting part 313 and the first connecting part 311.

[0304] The third connecting part 313 is connected to the first connecting part 311. For example, the third connecting part 313 can be connected to the first connecting part 311 through the bottom of the receiving groove 312.

[0305] By setting up the receiving groove 312, solid materials or other materials can be placed in the receiving groove 312, thereby making effective use of the structure of the fixing part 31. The materials in the receiving groove 312 can also be used to provide uniform process gas.

[0306] For example, when the support device 03 of this application is applied to the surface treatment method of the semiconductor substrate 121 described above, the receiving groove 312 can be used to place solid materials or other materials for forming reactive gases.

[0307] This application places the receiving groove 312 between the third connecting part 313 and the first connecting part 311, which can effectively utilize the space of the fixing member 31 and will not interfere with the semiconductor substrate 121 (or other supported objects).

[0308] In one possible approach, please refer to Figure 23 and Figure 24 The support structure 30 may include multiple (the multiple means two or more), the multiple support structures 30 may be stacked, and the third connection portion 313 of two adjacent support structures 30 is connected, and there may be a gas channel 33 between two adjacent support structures 30.

[0309] The gas passage 33 is located between two adjacent support structures 30. For example, the gas passage 33 may be located between the first connecting portion 311 of one support structure 30 and the second connecting portion 321 of the other adjacent support structure 30, as shown below. Figure 23 and Figure 25 As shown.

[0310] Furthermore, the aforementioned gas channel 33 can be connected to the receiving tank 312, so that the solid material (or other materials) in the receiving tank 312, after being vaporized, can be introduced through the gas channel 33 to the outer periphery or surface of the semiconductor substrate 121 (or other supported object). At the same time, the gas channel 33 can also be used to allow external process gases to enter or exit the support device 03, thereby facilitating the corresponding process processing of the semiconductor substrate 121.

[0311] Additionally, in this embodiment, the distance between two adjacent semiconductor substrates 121 (or other supported objects) can be changed by adjusting the size (e.g., height) of each fixing member 31.

[0312] In one possible implementation, in one of the two adjacent support structures 30, the third connecting portion 313 includes a protrusion; in the other of the two adjacent support structures 30, the third connecting portion 313 includes a groove; the protrusion is located in the groove and connects the two adjacent support structures 30.

[0313] In other words, the third connecting portion 313 of two adjacent support structures 30 includes a protrusion in one third connecting portion 313 and a groove in the other third connecting portion 313. The two adjacent support structures can be connected together by the cooperation of the protrusion and the groove.

[0314] Alternatively, each support structure 30 may have a protrusion and a groove, distributed along a direction parallel to the arrangement of the multiple support structures 30. The protrusion may be located on one side of the third connecting portion 313, and the groove may be located on the other side of the third connecting portion 313. For ease of understanding, let's take... Figure 23 For example, in terms of orientation, the protrusion and the groove can be located above and below the third connecting part of each support structure 30, respectively. This facilitates the stacking and connection of multiple support structures 30.

[0315] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A surface treatment method for a semiconductor substrate, characterized in that, include: The first and second surfaces of a semiconductor substrate are processed under a first temperature field to etch the first surface to obtain a first transition surface and form a first silicon carbide film on the second surface. The semiconductor substrate includes silicon atoms and carbon atoms. The temperature of the first surface of the same semiconductor substrate is lower than the temperature of its second surface. The first surface and the second surface are arranged in opposite directions. The first transition surface and the first silicon carbide film are processed under a second temperature field to etch the first silicon carbide film to obtain a second transition surface, and a second silicon carbide film is formed on the first transition surface. The temperature of the first transition surface of the same semiconductor substrate is higher than the temperature of its first silicon carbide film.

2. The surface treatment method for a semiconductor substrate according to claim 1, characterized in that, The process conditions for the surface treatment method of the semiconductor substrate include: The working pressure of the surface treatment method for the semiconductor substrate is between 0.1 mbar and 100 mbar.

3. The surface treatment method for a semiconductor substrate according to claim 1 or 2, characterized in that, The process conditions for the surface treatment method of the semiconductor substrate include at least one of the following: The highest temperature in the first temperature field is between 1800℃ and 2100℃; The highest temperature in the second temperature field is between 1800℃ and 2100℃; The temperature gradient of the first temperature field is between 0.1℃ / mm and 5℃ / mm; The temperature gradient of the second temperature field is between 0.1℃ / mm and 5℃ / mm.

4. The surface treatment method for a semiconductor substrate according to any one of claims 1-3, characterized in that, The first surface is etched to obtain a first transition surface, including: This causes silicon atoms on the first surface to detach from the first surface, thereby obtaining a first sub-transition surface; This causes the carbon atoms of the first sub-transition surface to detach from the first sub-transition surface, thus obtaining the first transition surface.

5. The surface treatment method for a semiconductor substrate according to claim 4, characterized in that, The process of causing carbon atoms on the first sub-transition surface to detach from the first sub-transition surface includes: The reactant gas reacts chemically with the carbon atoms on the first transition surface to generate silicon carbide gaseous products.

6. The surface treatment method for a semiconductor substrate according to claim 5, characterized in that, The reaction gas includes at least one of silicon vapor, silane, trichlorosilane, ethoxysilane, or silicon tetrachloride.

7. The surface treatment method for a semiconductor substrate according to claim 5 or 6, characterized in that, Forming a first silicon carbide film on the second surface includes: The silicon carbide vapor product is deposited on the second surface to obtain a first silicon carbide film.

8. The surface treatment method for a semiconductor substrate according to claim 7, characterized in that, The semiconductor substrate includes a plurality of semiconductor substrates, which are arranged at intervals along a first direction, the first direction being parallel to the thickness direction of the semiconductor substrate; Depositing the silicon carbide vapor product onto the second surface includes: Silicon carbide vapor products of one of the semiconductor substrates are deposited on a second surface of the semiconductor substrate adjacent to it.

9. The surface treatment method for a semiconductor substrate according to any one of claims 1-8, characterized in that, The first silicon carbide film is etched to obtain a second transition surface, including: This causes silicon atoms in the first silicon carbide film to detach from the first silicon carbide film, thereby obtaining a second sub-transition surface; This causes the carbon atoms of the second sub-transition surface to detach from the second sub-transition surface, thus obtaining the second transition surface.

10. The surface treatment method for a semiconductor substrate according to claim 9, characterized in that, The process of causing carbon atoms on the second sub-transition surface to detach from the second sub-transition surface includes: The reactant gas reacts chemically with the carbon atoms on the second transition surface to generate silicon carbide gaseous products.

11. The surface treatment method for a semiconductor substrate according to claim 10, characterized in that, The reaction gas includes at least one of silicon vapor, silane, trichlorosilane, ethoxysilane, or silicon tetrachloride.

12. The surface treatment method for a semiconductor substrate according to claim 10 or 11, characterized in that, Forming a second silicon carbide film at the first transition surface includes: The silicon carbide vapor product is deposited on the first transition surface to obtain a second silicon carbide film.

13. The surface treatment method for a semiconductor substrate according to claim 12, characterized in that, The semiconductor substrate includes a plurality of semiconductor substrates, which are arranged at intervals along a first direction, the first direction being parallel to the thickness direction of the semiconductor substrate; Depositing the silicon carbide vapor product on the first transition surface includes: Silicon carbide vapor products of one of the semiconductor substrates are deposited on a first transition surface of the semiconductor substrate adjacent to it.

14. The surface treatment method for a semiconductor substrate according to any one of claims 1-13, characterized in that, After forming a first silicon carbide film on the second surface and before etching the first silicon carbide film to obtain a second transition surface, the method further includes: The semiconductor substrate is annealed at a constant temperature.

15. The surface treatment method for a semiconductor substrate according to claim 14, characterized in that, The annealing temperature is between 1600°C and 2100°C.

16. A semiconductor substrate, characterized in that, The semiconductor substrate is obtained by surface treatment of a semiconductor substrate as described in any one of claims 1-15.

17. A semiconductor device, characterized in that, include: Functional components; The semiconductor substrate of claim 16, wherein the functional component is disposed on the semiconductor substrate.

18. A support device, characterized in that, For supporting a semiconductor substrate, the support device includes at least one support structure, the support structure comprising: A fastener, the fastener having a ring-shaped structure, the fastener having a first connecting portion; A support member, the support member including a second connecting portion and a support portion connected to the second connecting portion, the second connecting portion being connected to the first connecting portion, the support portion being used to support the semiconductor substrate; The melting point of the fastener is greater than or equal to 1800°C, and / or the melting point of the support is greater than or equal to 1800°C.

19. The support device according to claim 18, characterized in that, The support members include multiple members, which are arranged at circumferential intervals along the fixing member.

20. The support device according to claim 18 or 19, characterized in that, The second connecting part includes an embedding groove, and the first connecting part includes a protrusion located in the embedding groove, connecting the fixing member and the support member.

21. The support device according to any one of claims 18-20, characterized in that, The support portion has a sheet-like structure and extends away from the second connecting portion; along the direction away from the second connecting portion, the cross-sectional area of ​​the support portion gradually decreases.

22. The support device according to any one of claims 18-21, characterized in that, The fastener also has a third connecting portion, and there is a receiving groove between the third connecting portion and the first connecting portion.

23. The support device according to claim 22, characterized in that, The support structure includes multiple structures, which are stacked in layers. The third connecting portion of two adjacent support structures is connected, and a gas channel is provided between two adjacent support structures. The gas channel is connected to the receiving groove.

24. The support device according to claim 23, characterized in that, In one of the two adjacent support structures, the third connecting portion includes a protrusion; in the other of the two adjacent support structures, the third connecting portion includes a groove; the protrusion is located within the groove and connects the two adjacent support structures.

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