Semiconductor package and method of adjusting semiconductor package

Abstract

A method of trimming a semiconductor package includes providing a semiconductor package including a die on a substrate, conductive pads on a lower surface of the substrate, wherein the conductive pads are electrically connected to the die, and wherein the conductive pads include first conductive pads and second conductive pads, and first solder balls connected to the first conductive pads, respectively, connecting second solder balls to the second conductive pads, respectively, and performing a trimming process on the die including generating first instructions through a first set of the second solder balls to determine an internal parameter type of the die, and generating second instructions through a second set of the second solder balls to trim a value of the internal parameter type. The method enables the semiconductor package to be implemented at a system level and support real-time and dynamically trimable tuning.

Description

Technical Field

[0001] This invention relates to semiconductor packaging and methods for adjusting semiconductor packaging. Background Technology

[0002] In current memory modules, error detection and parameter adjustment must be achieved by blowing a fuse. The entire process requires testing at the system level, then returning to the automated test equipment (ATE) for fuse programming, and finally back to the system for verification. This iterative back-and-forth process is time-consuming and significantly reduces the overall testing efficiency. Furthermore, fuse blowing is a one-time, irreversible operation, and cannot be adjusted instantly or dynamically at the system level. Summary of the Invention

[0003] One aspect of the present invention provides a method for adjusting a semiconductor package. The method includes: providing a semiconductor package comprising: a wafer located on a substrate; conductive pads located on a lower surface of the substrate, wherein the conductive pads are electrically connected to the wafer, and wherein the conductive pads include a first conductive pad and a second conductive pad; and first solder balls respectively connected to the first conductive pad; connecting second solder balls respectively to the second conductive pad; and performing an adjustment process on the wafer, comprising: generating a first instruction through a first group of the second solder balls to determine an internal parameter type of the wafer; and generating a second instruction through a second group of the second solder balls to adjust the value of the internal parameter type.

[0004] In some embodiments, the method further includes: attaching the semiconductor package to a circuit board before attaching the second solder ball to the semiconductor package; and removing the semiconductor package from the circuit board.

[0005] In some embodiments, there are no solder balls between the second conductive pad and the circuit board.

[0006] In some embodiments, once the adjustment process is complete, the semiconductor package is reconnected to the circuit board.

[0007] In some embodiments, the second solder ball is electrically isolated from the circuit board.

[0008] In some embodiments, the method further includes: after connecting the second solder ball to the second conductive pad, connecting the semiconductor package to an adjustment plate, wherein the adjustment plate generates the first instruction and the second instruction.

[0009] In some embodiments, the first solder ball of the semiconductor package is electrically isolated from the adjustment plate.

[0010] In some embodiments, after the adjustment process is completed, the adjustment board is removed from the semiconductor package and the semiconductor package is reattached to the circuit board.

[0011] In some embodiments, the first group of the second solder ball and the second group of the second solder ball are located on opposite sides of the first solder ball.

[0012] In some embodiments, the method further includes: bringing the wafer into a conditioning mode by applying a voltage to a third group of the second solder balls.

[0013] In some embodiments, the third group of the second solder balls has a single second solder ball.

[0014] In some embodiments, the single second solder ball of the third group is arranged along a line with the first group of the second solder balls.

[0015] In some embodiments, the adjustment process for the wafer and the generation of the first instruction are performed simultaneously.

[0016] In some embodiments, the second instruction is executed after the first instruction.

[0017] In some embodiments, the first instruction is generated by applying a voltage or zero voltage to each of the first group of the second solder balls, and the second instruction is generated by applying a voltage or zero voltage to each of the second group of the second solder balls.

[0018] One aspect of the present invention provides a semiconductor package. The semiconductor package includes: a wafer located on a substrate; a conductive pad located on a lower surface of the substrate, wherein the conductive pad is electrically connected to the wafer, and wherein the conductive pad includes a first conductive pad and a second conductive pad; and a first solder ball respectively connected to the first conductive pad, wherein the second conductive pad is not covered by the solder ball.

[0019] In some embodiments, the semiconductor package further includes: a circuit board connected to the semiconductor package via a first solder ball, wherein a second conductive pad is electrically isolated from the circuit board.

[0020] In some embodiments, the first conductive pad is located in the central region of the substrate, and the second conductive pad is located in the peripheral region of the substrate.

[0021] In some embodiments, the second conductive pad is located on opposite sides of the first conductive pad.

[0022] In some embodiments, a first set of second conductive pads is configured to receive a first instruction to determine the type of internal parameters of the wafer, and a second set of second conductive pads is configured to receive a second instruction to determine the value of the type of internal parameters of the wafer.

[0023] It should be understood that the above general description and the following detailed description are provided as examples to further explain the present invention. Attached Figure Description

[0024] The scope of the invention is best understood by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0025] Figure 1 According to some embodiments of the present invention, a circuit diagram of a memory cell of a memory is shown.

[0026] Figure 2A According to some embodiments of the present invention, a cross-sectional view of a semiconductor package is shown.

[0027] Figure 2B According to some embodiments of the present invention, a bottom view of the arrangement of a carrier substrate for a semiconductor package is shown.

[0028] Figure 3 According to some embodiments of the present invention, a cross-sectional view of a semiconductor package is shown.

[0029] Figure 4 According to some embodiments of the present invention, a cross-sectional view of a semiconductor package is shown.

[0030] Figure 5A According to some embodiments of the present invention, a cross-sectional view of a semiconductor package is shown.

[0031] Figure 5B According to some embodiments of the present invention, a bottom view of the arrangement of solder balls on a carrier substrate is shown.

[0032] Figure 5C According to some embodiments of the present invention, a top view is shown of the arrangement of conductive pads on an adjustment plate.

[0033] Figure 6 According to some embodiments of the present invention, a cross-sectional view of a semiconductor package is shown. Detailed Implementation

[0034] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the content of the invention. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, the content of the invention may repeatedly refer to numbers and / or letters. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0035] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0036] Figure 1 According to some embodiments of the present invention, circuit diagrams of memory cells of a memory are shown. Please refer to... Figure 1 The memory 100 comprises a plurality of memory cells 102 arranged in a rectangular matrix structure. In some embodiments, the memory 100 is a dynamic random access memory (DRAM) device. Each memory cell 102 of the memory 100 is primarily composed of a transistor 100T and a capacitor 100C electrically connected to the transistor 100T. One side of the capacitor 100C is coupled to the drain region of the transistor 100T, while the other side of the capacitor 100C is coupled to ground. The memory 100 also includes a word line 100W coupled to the gate region of the transistor 100T, and a bit line 100B coupled to the source of the transistor 100T.

[0037] Figure 2A According to some embodiments of the present invention, a cross-sectional view of a semiconductor package 200 is shown. The semiconductor package 200 includes a carrier substrate 210 and a wafer 220 disposed on the carrier substrate 210. In some embodiments, the wafer 220 may be a memory, such as a dynamic random access memory (DRAM) device. In some embodiments, the wafer 220 may be as follows: Figure 1The memory 100 is shown. In some embodiments, the carrier substrate 210 may be made of silicon, glass, ceramic, or plastic. The carrier substrate 210 has openings. A wafer 220 is placed on the upper surface of the carrier substrate 210, thereby exposing a portion of the bottom surface of the wafer 220 through the openings. The carrier substrate 210 may include a multilayer wiring pattern structure (not shown). The semiconductor package 200 also includes a plurality of conductive pads 250 located on the lower surface of the carrier substrate 210. The conductive pads 250 are electrically coupled to the carrier substrate 210 and the wafer 220 through the multilayer wiring pattern structure. A plurality of bonding wires 230 passing through the openings electrically connect the wafer 220 to the conductive pads 250 on the carrier substrate 210. The semiconductor package 200 also includes a sealant 240. The sealant 240 substantially encapsulates the wafer 220, the bonding wires 230, the carrier substrate 210, and the openings on the carrier substrate 210. The sealant 240 may be made of a polymer (e.g., a resin). For example, the sealant 240 may be made of epoxy molding compound (EMC).

[0038] Figure 2B According to some embodiments of the present invention, a bottom view of the arrangement of the carrier substrate 210 of the semiconductor package 200 is shown. Please refer to... Figure 2A and Figure 2B The conductive pad 250 includes conductive pad 250A and conductive pad 250B. In some embodiments, conductive pad 250A can serve as a signal input, signal output, and / or power input for the wafer 220. On the other hand, conductive pad 250B can serve as an adjustment pad for adjusting the internal parameters of the wafer 220, which will be discussed later. In some embodiments, conductive pad 250A is located in the central region of the carrier substrate 210, while conductive pad 250B is located in the peripheral region of the carrier substrate 210. In some embodiments, conductive pad 250B is located on opposite sides of conductive pad 250A.

[0039] Multiple solder balls 260 are connected to conductive pad 250A and electrically connected to carrier substrate 210 via conductive pad 250A. In some embodiments, when forming semiconductor package 200, no solder balls (e.g., solder balls 260) are formed on conductive pad 250B. In some embodiments, conductive pad 250 may comprise a variety of conductive materials, such as metals, metal alloys, and / or combinations thereof, such as gold (Au), copper (Cu), aluminum (Al).

[0040] Figure 3 A cross-sectional view of a semiconductor package 200 according to some embodiments of the present invention is shown. Figure 3As shown, the semiconductor package 200 can be bonded to the circuit board 270 via solder balls 260. The circuit board 270 includes a plurality of conductive pads 252. In some embodiments, the circuit board 270 may be a printed circuit board (PCB). In some embodiments, the method of mounting the semiconductor package 200 onto the circuit board 270 may employ surface mount technology (SMT). For example, firstly, the solder balls 260 are aligned with corresponding conductive pads 252 on the circuit board 270. Next, the semiconductor package 200 is placed on the circuit board 270 so that the solder balls 260 contact the conductive pads 252 on the circuit board 270. Subsequently, a reflow soldering process may be performed to melt the solder balls 260. Thus, the molten solder balls 260 can be attached to the conductive pads 252 of the circuit board 270. The surface tension of the solder balls 260 keeps them aligned with the corresponding conductive pads 252 on the circuit board 270 until the solder balls 260 cool and solidify. In some embodiments, the conductive pads 252 may include various conductive materials, such as metals, metal alloys, and / or combinations thereof, such as gold (Au), copper (Cu), aluminum (Al), etc.

[0041] In current memory modules, error detection and parameter adjustment must be achieved by blowing a fuse. The entire process requires testing at the system level, then returning to the automated test equipment (ATE) for fuse programming, and finally back to the system for verification. This iterative back-and-forth process is time-consuming and significantly reduces the overall testing efficiency. Furthermore, fuse blowing is a one-time, irreversible operation, and cannot be adjusted instantly or dynamically at the system level.

[0042] To address the aforementioned problems, this invention provides a semiconductor package with a fuse trimming mechanism, which can be implemented at the system level and supports real-time and dynamically adjustable trimming.

[0043] Figure 4 According to some embodiments of the present invention, a cross-sectional view of a semiconductor package 200 is shown. For example... Figure 4 As shown, during memory debugging or verification, the semiconductor package 200 is removed from the circuit board 270, and multiple solder balls 265 are connected to the conductive pad 250B. The solder balls 265 are electrically connected to the carrier substrate 210 through the conductive pad 250B.

[0044] Figure 5A According to some embodiments of the present invention, a cross-sectional view of a semiconductor package 200 is shown. For example... Figure 5AAs shown, the semiconductor package 200 can be bonded to an adjustment plate 280 via solder balls 265. The adjustment plate 280 includes a plurality of conductive pads 254. The adjustment plate 280 is configured to provide control signals to adjust the internal parameters of the wafer 220 in the semiconductor package 200. In some embodiments, the method of mounting the semiconductor package 200 onto the adjustment plate 280 can be similar to or the same as the method of mounting the semiconductor package 200 onto a circuit board 270. For example, firstly, the solder balls 265 are aligned with the corresponding conductive pads 254 of the adjustment plate 280. Next, the semiconductor package 200 is placed on the adjustment plate 280 so that the solder balls 265 contact the conductive pads 254 of the adjustment plate 280. Subsequently, a reflow soldering process can be performed to melt the solder balls 265. The molten solder balls 265 then adhere to the conductive pads 254 of the adjustment plate 280. The surface tension of the solder balls 265 keeps them aligned with the corresponding conductive pads 254 on the adjustment plate 280 until the solder balls 265 cool and solidify. In some embodiments, the conductive pad 254 may comprise various conductive materials, such as metals, metal alloys, and / or combinations thereof, including gold (Au), copper (Cu), and aluminum (Al). In some embodiments, the adjustment plate 280 may be a microprocessor, such as a central processing unit (CPU), a controller, or an application-specific integrated circuit (ASIC).

[0045] Figure 5B According to some embodiments of the present invention, a bottom view is shown of the arrangement of solder balls 265 on a carrier substrate 210. In such... Figure 5B In the bottom view shown, solder balls 265 are located on both sides of the carrier substrate 210. Solder balls 265 consist of solder ball regions 265A and 265B. Solder ball region 265A is located at the first edge of the carrier substrate 210, and solder ball region 265B is located at the second edge opposite the first edge. Solder ball region 265A may contain six solder balls, sequentially named solder ball A1, solder ball A2, ..., solder ball A6 from top to bottom. Similarly, solder ball region 265B may also contain six solder balls, sequentially named solder ball B1, solder ball B2, ..., solder ball B6 from top to bottom. Figure 5B As shown, solder balls A1 and A2-A6 in solder ball region 265A are arranged in a straight line. Similarly, solder balls B1-B6 in solder ball region 265B are also arranged in a straight line.

[0046] It should be understood that, in order to simplify explanations and improve the clarity of illustrations, Figure 5B Only six solder balls are shown in solder ball regions 265A and 265B. However, the layout of solder ball regions 265A and 265B is not limited to this. For example, the number of solder balls in solder ball regions 265A and 265B can each have different values. In some embodiments, the number of solder balls in solder ball region 265A may be different from the number of solder balls in solder ball region 265B.

[0047] Figure 5C According to some embodiments of the present invention, a top view of the arrangement of conductive pads 254 on an adjustment plate 280 is shown. The adjustment plate 280 does not contain conductive pads corresponding to the positions of the solder balls 260. Therefore, the solder balls 260 are in contact with the non-conductive surface of the adjustment plate 280 and are electrically isolated from the adjustment plate 280.

[0048] Please refer to Figures 5A to 5C Each solder ball 265 is assigned a logic value ([0] or [1]) via adjustment plate 280. For example, if solder ball A1 is given zero voltage (e.g., no signal input), its logic value is [0]. If solder ball A1 is given high voltage, its logic value is [1].

[0049] Solder ball A1 serves as a pin to initiate the adjustment mode. When solder ball A1 is supplied with a high voltage (logic state [1]), chip 220 enters the adjustment mode and is ready to receive the command sequence provided by solder balls A2-A6. This arrangement with a special start voltage allows chip 220 to quickly enter a special mode when dynamic parameter adjustment is required. On the other hand, if solder ball A1 is supplied with zero voltage (e.g., no signal input), chip 220 will not enter the adjustment mode, and chip 220 will not respond to any commands from solder balls A2-A6 or solder balls B1-B6.

[0050] Once solder ball A1 is activated and chip 220 enters adjustment mode, signals can be provided to solder balls A2-A6 via the corresponding conductive pads 254 on adjustment plate 280, thereby generating a first instruction. In other words, chip 220 entering adjustment mode and generating the first instruction occur simultaneously. More specifically, the first instruction is used to determine the type of internal parameters of the chip 220 to be adjusted.

[0051] When the first instruction is generated, each solder ball A2-Solder Ball A6 can be applied with a high voltage or a zero voltage, and this arrangement can provide a variety of combinations. For example, the logic states ([1] or [0]) of Solder Balls A2-Solder Ball A6 constitute a binary combination used to determine the type of internal parameters of the wafer 220 to be adjusted. In some embodiments, Solder Balls A2-Solder Ball A6 can provide up to 2 5 There are 32 possible combinations. Each combination (with a specific binary number) corresponds to an internal parameter type.

[0052] In some embodiments, the internal parameter type can be a timing-related parameter, such as tDQS2DQ (time delay between data strobe and actual data signal (DQ)), word line delay, internal clock delay, etc. In other embodiments, the internal parameter type can be a parameter related to an internal reference voltage or current, such as a sense amplifier reference voltage, sense amplifier reference current, array reference voltage, peripheral reference voltage, internal bias current, etc. In other embodiments, the internal parameter type can be an array-related parameter, such as word line voltage level, plate voltage, etc. In other embodiments, the internal parameter type can be an I / O interface-related parameter, such as on-die termination (ODT), output driver strength, I / O reference voltage, etc.

[0053] After determining the internal parameter type through the first instruction, a second instruction can be generated by providing signals to solder balls B1-B6 via the corresponding conductive pads 254 of the adjustment board 280. More specifically, the second instruction is configured to modify the parameter value corresponding to the selected internal parameter type.

[0054] When generating the second instruction, each solder ball B1-B6 can be applied with a high voltage or a zero voltage, and this configuration can provide a variety of combinations. For example, the logic states ([1] or [0]) of solder balls B1-B6 constitute a binary combination for modifying parameter values ​​corresponding to the selected internal parameter type. In some embodiments, solder balls B1-B6 can provide up to 2 6 There are 64 possible combinations. Each combination (with a specific binary number) corresponds to a specific numerical value.

[0055] In some embodiments, when the logic combination of solder balls A2-A6 is set to "00101", a first instruction is generated, which determines the internal parameter type to be tDQS2DQ. When the logic combination of solder balls B1-B6 is set to "100101", a second instruction is generated, which sets the internal offset to 15 ps. In some embodiments, the first and second instructions are generated by an adjustment board 280.

[0056] Figure 6 A cross-sectional view of a semiconductor package 200 according to some embodiments of the present invention is shown. Figure 6As shown, after adjusting the chip 220, the adjustment plate 280 is removed from the semiconductor package 200, and the semiconductor package 200 is reconnected to the circuit board 270. Solder balls 260 contact the conductive pads 252 of the circuit board 270. The method of connecting the semiconductor package 200 to the circuit board 270 can be similar to... Figure 3 The installation method described above.

[0057] Circuit board 270 does not contain conductive pads corresponding to the positions of solder balls 265. Therefore, the solder balls 265 of the wafer 220 used to adjust the semiconductor package 200 are in contact with the non-conductive surface of circuit board 270 and are electrically isolated from circuit board 270.

[0058] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art will understand that the invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

[0059] [Symbol Explanation] 100: Memory 100B: Bitline 100C: Capacitor 100T: Transistor 100W: Character Line 102: Memory Unit 200: Semiconductor Packaging 210: Carrier substrate 220: Chip 230: Bond wire 240: Sealing body 250: Conductive pad 250A: Conductive pad 250B: Conductive pad 252: Conductive pad 254: Conductive pad 260: Tin Ball 265: Tin Ball 265A: Tin ball area 265B: Tin ball area 270: Circuit board 280: Adjustment plate A1, A2, A3, A4, A5, A6: Tin balls B1, B2, B3, B4, B5, B6: Tin balls.

Claims

1. A method for adjusting a semiconductor package, characterized in that, Include: The semiconductor package provided comprises: The chip is located on the substrate; Multiple conductive pads are located on the lower surface of the substrate, wherein the multiple conductive pads are electrically connected to the wafer, and wherein the multiple conductive pads include multiple first conductive pads and multiple second conductive pads. as well as Multiple first solder balls are respectively connected to the multiple first conductive pads; Connect the plurality of second solder balls to the plurality of second conductive pads respectively; as well as Performing an adjustment process on the wafer includes: A first instruction is generated through the first group of the plurality of second solder balls to determine the type of internal parameters of the wafer; and A second instruction is generated by the second group of the plurality of second solder balls to adjust the value of the internal parameter type.

2. The method according to claim 1, wherein, Further includes: Before connecting the plurality of second solder balls to the semiconductor package, the semiconductor package is connected to the circuit board; and Remove the semiconductor package from the circuit board.

3. The method of claim 2, wherein there are no solder balls between the plurality of second conductive pads and the circuit board.

4. The method of claim 2, wherein after the adjustment process is completed, the semiconductor package is reconnected to the circuit board.

5. The method of claim 4, wherein the plurality of second solder balls are electrically isolated from the circuit board.

6. The method according to claim 2, wherein, Further includes: After the plurality of second solder balls are connected to the plurality of second conductive pads, the semiconductor package is connected to an adjustment plate, through which the first instruction and the second instruction are generated.

7. The method of claim 6, wherein the plurality of first solder balls of the semiconductor package are electrically isolated from the adjustment plate.

8. The method of claim 6, wherein after the adjustment process is completed, the adjustment plate is removed from the semiconductor package and the semiconductor package is reconnected to the circuit board.

9. The method according to claim 1, wherein the first group of the plurality of second solder balls and the second group of the plurality of second solder balls are respectively located on opposite sides of the plurality of first solder balls.

10. The method according to claim 1, wherein, Further includes: By applying voltage to a third group of the plurality of second solder balls, the wafer is brought into adjustment mode.

11. The method of claim 10, wherein the third group of the plurality of second solder balls has a single second solder ball.

12. The method of claim 11, wherein the single second solder ball of the third group and the first group of the plurality of second solder balls are arranged along a line.

13. The method of claim 1, wherein performing the adjustment process on the wafer and generating the first instruction are performed simultaneously.

14. The method of claim 1, wherein the second instruction is executed after the first instruction.

15. The method of claim 1, wherein the first instruction is generated by applying a voltage or zero voltage to each of the first group of the plurality of second solder balls, and the second instruction is generated by applying a voltage or zero voltage to each of the second group of the plurality of second solder balls.

16. A semiconductor package, characterized in that, Include: The chip is located on the substrate; Multiple conductive pads are located on the lower surface of the substrate, wherein the multiple conductive pads are electrically connected to the wafer, and wherein the multiple conductive pads include multiple first conductive pads and multiple second conductive pads. as well as Multiple first solder balls are respectively connected to multiple first conductive pads, wherein the multiple second conductive pads are not covered by multiple solder balls.

17. The semiconductor package of claim 16, wherein, Further includes: A circuit board is connected to the semiconductor package via the plurality of first solder balls, wherein the plurality of second conductive pads are electrically isolated from the circuit board.

18. The semiconductor package of claim 16, wherein the plurality of first conductive pads are located in the central region of the substrate and the plurality of second conductive pads are located in the peripheral region of the substrate.

19. The semiconductor package of claim 18, wherein the plurality of second conductive pads are located on opposite sides of the plurality of first conductive pads.

20. The semiconductor package of claim 16, wherein: The first group of the plurality of second conductive pads is configured to receive a first instruction to determine the type of internal parameters of the wafer, and A second group of the plurality of second conductive pads is configured to receive a second instruction to determine the value of the internal parameter type of the wafer.

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