A circuit for sampling and locating the maximum and minimum voltages of multi-cell series-connected batteries

Abstract

This invention relates to the field of electronic circuit technology, specifically to a circuit for sampling and locating the maximum and minimum voltages of multi-cell series-connected batteries. The circuit includes a voltage sampling circuit, a voltage buffer circuit, a maximum and minimum voltage selection circuit, and a maximum and minimum voltage location circuit. The voltage sampling circuit converts the floating ground voltage of each individual battery cell into a common ground voltage, transmits it to the voltage buffer circuit for buffering, and then compares and selects the maximum and minimum voltage values ​​through the maximum and minimum voltage selection circuit. These maximum and minimum voltage values ​​are then output as state level signals representing the locations of the maximum and minimum voltage values ​​to the maximum and minimum voltage values, respectively. The maximum and minimum voltage location circuit converts these two sets of input state level signals into two data signals representing the locations of the maximum and minimum voltage values, which are then output as two position data signals for the circuit. In summary, this invention achieves efficient and accurate acquisition of the maximum and minimum voltages of series-connected batteries, as well as rapid location of the corresponding battery cell serial numbers.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, specifically to a circuit for sampling and locating the maximum and minimum voltages of a multi-cell series-connected battery. Background Technology

[0002] With the rapid development of electric vehicles, new energy storage systems, aerospace power supplies, and portable electronic devices, battery packs, composed of multiple individual battery cells (such as lithium-ion batteries and solid-state batteries) connected in series, have become widely used. To ensure the safe, efficient, and long-life operation of battery packs, a Battery Management System (BMS) is crucial. One of the core functions of a BMS is to monitor the voltage of each individual battery cell in the battery pack in real time and accurately. Identifying the highest voltage (often corresponding to overcharge risk) and the lowest voltage (often corresponding to over-discharge risk) in the battery pack is key to achieving battery equalization management, overcharge and over-discharge protection, and state estimation (such as state of charge (SOC) and state of health (SOH)).

[0003] Currently, mainstream series battery voltage sampling circuits typically employ a multi-channel analog-to-digital converter (ADC) combined with multiplexed switches to sequentially scan and measure the voltage of each battery cell. This approach offers high integration and measurement accuracy, making it the mainstream choice for current commercial BMS systems. However, its sampling process is essentially a sequential scan; obtaining all individual cell voltage values, including their extreme values, requires completing a full scan cycle. When there are many battery cells, the scan cycle is long, resulting in a certain delay. Frequently initiating full-channel scans solely to obtain the extreme voltage and its location consumes significant system resources, leading to increased response delay and power consumption. This delay can pose safety hazards, especially in applications requiring rapid response to protect against extreme voltages (such as sudden overvoltage or undervoltage). Another approach, using differential amplification sampling circuits constructed with discrete components such as operational amplifiers, precision resistor networks, and analog switches, selects batteries for measurement cell by cell or in groups. While this method is relatively low-cost and flexible in design, it also faces the delay issues associated with channel switching and sequential measurement. Meanwhile, a large number of discrete components leads to an increase in the area of ​​the printed circuit board (PCB), and inconsistencies in component parameters between channels may introduce additional measurement errors, posing a significant challenge to the system reliability design.

[0004] In the prior art: Chinese invention patent CN105629029B discloses a battery pack voltage sampling circuit based on a level transfer circuit. Although this circuit can complete the sampling of the maximum and minimum voltage of the battery pack cells, it requires scanning each cell individually to obtain the voltage data, resulting in poor timeliness. Chinese invention patent CN114069567B discloses a battery voltage sampling circuit, but this circuit requires frequent full-channel scanning to obtain the maximum and minimum voltage, consuming significant system resources and power. Chinese invention patent CN110018340B discloses a battery voltage sampling circuit that uses the bias voltage unit of a first inverting amplifier to divide the voltage output of the voltage divider circuit into two intervals, thereby shielding the sampling range from 0V to the lowest battery voltage and improving voltage sampling accuracy. However, this circuit uses discrete components, which increases the PCB area due to the large number of components, and the inconsistency of component parameters between channels may introduce additional measurement errors, resulting in poor system design flexibility.

[0005] It is evident that existing technologies still have significant shortcomings in terms of sampling real-time performance, system response speed, and hardware reliability, and there is an urgent need for a high-efficiency sampling circuit that can quickly and accurately identify the maximum voltage in a battery pack. Summary of the Invention

[0006] The purpose of this invention is to provide a sampling and positioning circuit for the maximum and minimum voltages of multi-cell series-connected batteries, so as to solve the technical problems of the prior art in terms of timeliness, energy efficiency and system design flexibility.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A circuit for sampling and locating the maximum and minimum voltages of a multi-cell series-connected battery includes: a voltage sampling circuit, a voltage buffer circuit, a maximum and minimum voltage selection circuit, and a maximum and minimum voltage location circuit.

[0009] The voltage sampling circuit is used to convert the floating ground voltage of each individual battery cell connected in series in the battery pack into a common ground voltage under the control of an external enable signal. It includes N voltage sampling units, where N is a positive integer greater than or equal to 2. Each voltage sampling unit has a voltage input terminal, an enable input terminal, a voltage output terminal, and a current output terminal. The voltage input terminal of each voltage sampling unit is connected to the positive terminal of the corresponding individual battery cell, and the enable input terminal is connected to the same external enable signal. The voltage output terminal of each voltage sampling unit is used to output the common ground voltage of the corresponding individual battery cell.

[0010] The current output terminal of each voltage sampling unit is connected to the voltage output terminal of its adjacent upstream voltage sampling unit. The current output terminal of the Nth voltage sampling unit is left floating, and the current output terminal of the i-th voltage sampling unit is connected to the voltage output terminal of the (i+1)-th voltage sampling unit, i=1,2,…,N-1. All voltage sampling units share the same power supply terminal and the same common ground terminal.

[0011] The voltage buffer circuit includes N voltage buffers, where N is a positive integer greater than or equal to 2. The input terminals of the N voltage buffers are connected one-to-one with the voltage output terminals of the N voltage sampling units, and are used to buffer the received common ground voltage.

[0012] The voltage input terminal of the extreme value voltage selection circuit is connected to the output terminals of N voltage buffers one by one. The enable input terminal receives an external enable signal. The extreme value voltage selection circuit is used to compare and select the common ground voltages after buffering, and output the maximum value voltage and the minimum value voltage, as well as the maximum value state level signal and the minimum value state level signal.

[0013] The input terminal of the extreme voltage positioning circuit is connected to the state level signal output terminal of the extreme voltage selection circuit, and is used to convert the state level signal into a data signal representing the location of the extreme voltage.

[0014] Furthermore, the data signal representing the location of the extreme voltage is binary code, decimal code, I2C, SPI, 485, or CAN data.

[0015] By adopting the above technical solution, the present invention has the following advantages:

[0016] (1) Rapid response significantly improves system safety and dynamic balancing efficiency. This invention collects voltage data of each individual battery cell through a voltage sampling circuit, performs pairwise comparison and analysis by an extreme voltage selection circuit, and then locates the cells by an extreme voltage positioning circuit. It directly outputs the voltage values ​​of the highest and lowest voltage cells in the current battery pack and their accurate cell numbers. This significantly reduces the risk of protection hysteresis caused by scanning delay, while clearly identifying the cells that "most need to be discharged" (highest voltage) or "most need to be charged" (lowest voltage). This allows the balancing control strategy to be applied to the corresponding cells immediately and accurately, thereby improving balancing speed and overall energy efficiency. In addition, this "on-demand sampling" architecture significantly reduces the average operating power consumption of the system and effectively reduces the processing and communication burden of the main controller and data bus.

[0017] 2. The circuit structure is simple and reliable, combining high precision and cost advantages. This invention can be implemented using conventional analog switches, operational amplifiers / comparators, and logic devices. Compared to building a large fully parallel ADC array to achieve similar speeds, the circuit size, complexity, and cost of this solution are far lower, and the circuit structure is simple and reliable. Compared to solutions that rely on high-performance processors for fast software sorting, this solution hardwareizes the computational task, reducing the MCU load and achieving faster speeds. This invention is particularly suitable for high-end electric vehicles, high-power energy storage systems, and high-reliability special power supplies with stringent requirements for safety response speed and operating efficiency, and has significant engineering application value and market prospects.

[0018] In summary, this invention achieves efficient and accurate acquisition of the maximum / minimum voltage of a series battery pack (highest / lowest single cell voltage), as well as rapid location of the physical serial number corresponding to the maximum / minimum single cell. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is an example of the application of the circuit of the present invention in a battery management system (BMS).

[0021] Figure 2 This is a schematic diagram of the circuit structure of the present invention;

[0022] Figure 3 This is a schematic diagram of the voltage sampling unit circuit in an embodiment.

[0023] Figure 4 This is a connection diagram of the voltage sampling unit in the embodiment;

[0024] Figure 5 The connection diagram of the maximum value selection circuit and the minimum value selection circuit in the embodiment is shown below;

[0025] Figure 6 This is a schematic diagram of the maximum / minimum voltage selection circuit where N is an even number in the embodiment;

[0026] Figure 7 This is a schematic diagram of the maximum / minimum voltage selection circuit where N is an odd number in the embodiment;

[0027] Figure 8 The diagram below shows the selector schematic in the embodiment, where (a) is the larger value selector and (b) is the smaller value selector.

[0028] Figure 9 This is a schematic diagram of the maximum / minimum voltage positioning circuit for N=4 in the embodiment;

[0029] Figure 10 This is an example of a minimum voltage positioning circuit with N=4 in the embodiment;

[0030] Figure 11 This is an example of a maximum voltage positioning circuit with N=4 in the embodiment;

[0031] Reference numerals in the figures: 1 is the maximum / minimum voltage sampling and positioning circuit for multi-cell series-connected batteries of the present invention; 2 is the voltage sampling circuit; 3 is the voltage buffer circuit; 4 is the maximum / minimum voltage selection circuit; 5 is the maximum / minimum voltage positioning circuit; 10 is the voltage sampling unit; 101 is the voltage-to-current conversion circuit; 102 is the first current mirror circuit; 103 is the second current mirror circuit. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and functions of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified based on different applications without departing from the spirit of the present invention.

[0033] The illustrations provided in this embodiment are only for illustrating the working principle of the relevant circuits or modules in this invention. In actual implementation, the number of circuits or modules may change, and the circuit layout may be more complex. In the description of this invention, a battery pack refers to a system composed of two or more individual battery cells connected end to end in series; it can also be constructed by first connecting multiple individual battery cells in parallel and then connecting them end to end in series. For ease of description and understanding, the individual battery cell with the lowest potential, i.e., the negative terminal of the individual battery cell connected to the common ground GND, is defined as battery 1. The potential increases sequentially, with the cell immediately adjacent to the positive terminal of battery 1 being battery 2, the next one being battery 3, and the individual battery cell with the highest potential being battery N. Battery 1 to battery N correspond to B1, B2, B3, ... BN in the accompanying drawings.

[0034] Figure 1 As an example of the application of the circuit of this invention in a battery management system, the voltage input terminals of the circuit are connected one-to-one with the positive terminals of each individual battery cell connected in series in the battery pack. The enable input terminal, the extreme voltage output terminal, and the data signal output terminal representing the location of the extreme voltage are respectively connected to the MCU. The circuit of this invention is used to directly, quickly, and accurately provide the MCU with the voltage values ​​of the individual battery cells with the highest and lowest voltage in the battery pack, as well as their physical serial numbers in the battery string. Based on this, the MCU can realize functions such as active battery balancing management, overcharge and over-discharge protection, and state estimation.

[0035] like Figure 2 As shown, the present invention provides a sampling and positioning circuit 1 for the maximum and minimum voltage of a multi-cell series-connected battery, comprising a voltage sampling circuit 2, a voltage buffer circuit 3, a maximum and minimum voltage selection circuit 4, and a maximum and minimum voltage positioning circuit 5.

[0036] The voltage sampling circuit 2 is used to convert the floating ground voltage of each series-connected individual battery cell into a common ground voltage under the control of an external enable signal. In actual operation, the voltage sampling circuit 2 only operates when it receives an external enable signal, and is in standby mode at other times, thereby reducing system power consumption. It includes a first voltage sampling unit 10, a second voltage sampling unit 10, ..., an Nth voltage sampling unit 10, for a total of N voltage sampling units 10; where N is a positive integer greater than or equal to 2. Each voltage sampling unit 10 has a sampling voltage input terminal, an enable input terminal, a voltage output terminal, and a current output terminal. The voltage input terminal of each voltage sampling unit 10 is connected to the positive terminal of the corresponding individual battery cell, and the enable input terminals are all connected to the same external enable signal; the voltage output terminal of each voltage sampling unit 10 is used to output the common ground voltage of the corresponding individual battery cell; for example, the voltage input terminal of the first voltage sampling unit 10 is connected to the positive terminal of individual battery cell B1, and the voltage input terminal of the Nth voltage sampling unit is connected to the positive terminal of individual battery cell BN. The current output terminal of each voltage sampling unit 10 is connected to the voltage output terminal of its adjacent upstream voltage sampling unit 10, wherein the current output terminal of the Nth voltage sampling unit 10 is left floating, and the current output terminal of the i-th voltage sampling unit 10 is connected to the voltage output terminal of the (i+1)-th voltage sampling unit 10, i=1,2,…,N-1; and all voltage sampling units 10 share the same power supply terminal V. BN And the same public terminal, V BN This represents the positive terminal voltage of the Nth cell in the battery string. The voltage values ​​at the N output terminals are respectively the common ground voltage of each individual cell in the battery pack or a multiple thereof.

[0037] The voltage buffer circuit 3 includes a first buffer, a second buffer, ..., an Nth buffer, for a total of N voltage buffers. Each buffer buffers the common-ground voltage it receives. The input terminals of the N voltage buffers are connected one-to-one with the voltage output terminals of the N voltage sampling units 10. For example, the output terminal V of the first voltage sampling unit 10... S1 The output terminal V of the Nth voltage sampling unit is connected to the input terminal of the first voltage buffer. SN The input terminal of the Nth voltage buffer is connected to the input terminal of the Nth voltage buffer. The output terminals of the N voltage buffers are respectively connected to the N input terminals of the voltage selection circuit.

[0038] The input terminal of the maximum / minimum voltage selection circuit is connected to the output terminals of the N voltage buffers one by one, and receives an external enable signal to compare and select the buffered common ground voltages, output the maximum voltage and minimum voltage, and output the maximum value state level signal and the minimum value state level signal.

[0039] The input terminals of the extreme voltage positioning circuit 5 are connected one-to-one with the status level signal output terminals of the extreme voltage selection circuit 4, and are used to convert the status level signals into data signals representing the location of the extreme voltage. The extreme voltage positioning circuit 5 includes a maximum voltage positioning circuit and a minimum voltage positioning circuit. The extreme voltage positioning circuit 5 is used to convert the status level signals output by the extreme voltage selection circuit 4 into data signals representing the location of the extreme voltage, facilitating subsequent MCU processing. Wherein:

[0040] The maximum voltage positioning circuit has N-1 level input terminals and one data signal output terminal representing the position of the single cell with the maximum voltage. This output terminal has j wires, where j is a positive integer greater than or equal to 1, depending on the data format. These N-1 level input terminals are connected one-to-one with the status level signal output terminals of the N-1 maximum voltage selection circuits. The minimum voltage positioning circuit has N-1 level input terminals and one data signal output terminal representing the position of the single cell with the minimum voltage. This output terminal has j wires, where j is a positive integer greater than or equal to 1, depending on the data format. These N-1 level input terminals are connected one-to-one with the status level signal output terminals of the N-1 minimum voltage selection circuits.

[0041] It should be noted that in practical applications, the number of voltage sampling units 10 is the same as the number of individual cells in the battery pack.

[0042] In this embodiment, the voltage sampling unit 10 in the voltage sampling circuit 2 has the following structure: Figure 3 As shown, it includes a voltage-to-current conversion circuit 101, a first current mirror circuit 102, and a second current mirror circuit 103. Wherein:

[0043] The voltage-to-current conversion circuit 101 includes an operational amplifier OPA, a fourth PMOS transistor M4, and a first resistor R1. The positive input terminal of the operational amplifier OPA is connected to the input voltage V. BiThe operational amplifier OPA's negative input terminal is connected to one end of the first resistor R1 and the drain of the fourth PMOS transistor M4. The OPA's enable input terminal EN is connected to the external enable signal EN. The OPA's output terminal is connected to the gate of the fourth PMOS transistor M4. The source of the fourth PMOS transistor M4 is connected to the drain of the first PMOS transistor M1. The gate of the fourth PMOS transistor M4 is connected to the output terminal of the operational amplifier OPA. The drain of the fourth PMOS transistor M4 is connected to one end of the first resistor R1. One end of the first resistor R1 is connected to the drain of the fourth PMOS transistor M4, and the other end of the first resistor R1 is connected to the common ground GND. The voltage-to-current conversion circuit 101 is used to convert the input voltage V... Bi Converted to current I i Current I i =V Bi / R1.

[0044] The first current mirror circuit 102 includes a first PMOS transistor M1, a second PMOS transistor M2, and a second resistor R2. The source of the first PMOS transistor M1 is connected to the power supply V. BN The gate and drain of the first PMOS transistor M1 are shorted together. The gate of the first PMOS transistor M1 is connected to the gate of the second PMOS transistor M2 and the gate of the third PMOS transistor M3 in the second current mirror circuit 103. The drain of the first PMOS transistor M1 is connected to the source of the fourth PMOS transistor M4. The source of the second PMOS transistor M2 is connected to the power supply V. BN The gate of the second PMOS transistor M2 is connected to the gate of the first PMOS transistor M1 and the gate of the third PMOS transistor M3 in the second current mirror circuit 103. The drain of the second PMOS transistor M2 is connected to one end of the second resistor R2. One end of the second resistor R2 is connected to the drain of the second PMOS transistor M2, and the other end of the second resistor R2 is connected to the common ground GND. The first current mirror circuit 102 is used to replicate the current of the voltage-to-current conversion circuit 101 and convert the current into a voltage, outputting voltage V. Si =I i ×R2=(V Bi / R1)×R2.

[0045] The second current mirror circuit 103 includes a third PMOS transistor M3, a fifth NMOS transistor M5, and a sixth NMOS transistor M6. The source of the third PMOS transistor M3 is connected to the power supply V. BNThe gate of the third PMOS transistor M3 is connected to the source of the fourth PMOS transistor M4 in the voltage-to-current conversion circuit 101 and the gates of the first PMOS transistor M1 and the second PMOS transistor M2 in the first current mirror circuit 102. The drain of the third PMOS transistor M3 is connected to the drain of the fifth NMOS transistor M5 and the gates of the fifth NMOS transistor M5 and the sixth NMOS transistor M6. The drain and gate of the fifth NMOS transistor M5 are shorted, and the gate of the fifth NMOS transistor M5 is connected to the gate of the sixth NMOS transistor M6. The source of the fifth NMOS transistor M5 is connected to the common ground GND. The drain of the sixth NMOS transistor M6 is the current output terminal I. i The gate of the sixth NMOS transistor M6 is connected to the gate of the fifth NMOS transistor M5, and the source of the sixth NMOS transistor M6 is connected to the common ground GND. The second current mirror circuit 103 is used to replicate the current of the voltage-to-current conversion circuit 101 and convert the current direction to pumping current.

[0046] The connection relationship of each voltage sampling unit 10 is as follows: Figure 4 As shown: The voltage input terminal of each voltage sampling unit 10 is sequentially connected to the positive terminal of each individual battery cell connected in series in the battery pack. The enable input terminal EN of each voltage sampling unit 10 is connected to the same external enable signal EN. The power supply V of each voltage sampling unit 10... BN The voltage sampling units 10 are interconnected, with their ground (GND) terminals connected together. The current output terminals I of each voltage sampling unit 10 are also interconnected. i The voltage output terminals V of the adjacent upstream voltage sampling unit 10 are respectively Si Connections, such as the current output terminal I1 of the first voltage sampling unit 10 and the voltage output terminal V of the second voltage sampling unit 10. S2 The current output terminal of the Nth voltage sampling unit 10 is left floating. The voltage output terminal of each voltage sampling unit 10 is connected to the voltage input terminal of the voltage buffer circuit 3 respectively. Figure 4 Only the connection relationship between the first voltage sampling unit 10 and the second voltage sampling unit 10 is illustrated; the connection relationships of other voltage sampling units 10 can be deduced similarly. For example... Figure 4 As shown, the output voltage V S1 =I1×R2,V S2 =I3×R2, where I1=(V B1 / R1), I2=(V B2 / R1), I3=I2-I1=(V B2 -V B1 ) / R1, we can get V S1 =(R2 / R1)×V B1 V S2 =(R2 / R1)×(VB2 -V B1 Other voltages V S3 V S4 V SN And so on.

[0047] In this embodiment, the extreme value voltage selection circuit 4 includes a maximum value selection circuit and a minimum value selection circuit, such as... Figure 5 As shown: the input terminals of N maximum value selection circuits are connected one-to-one with the input terminals of N minimum value selection circuits, serving as the voltage input terminals of the extreme value voltage selection circuit 4. The N voltage input terminals of this circuit 4 are respectively connected one-to-one with the N voltage output terminals of the voltage buffer circuit 3; the enable input terminal is connected to the external enable signal EN; the N-1 maximum value state level signal output terminals are connected one-to-one with the N-1 input terminals of the maximum value voltage positioning circuit; the N-1 minimum value state level signal output terminals are connected one-to-one with the N-1 input terminals of the minimum value voltage positioning circuit; the maximum value voltage output terminal and the minimum value voltage output terminal serve as the two extreme value voltage output terminals of circuit 1 of this invention. The extreme value voltage selection circuit 4 is used to compare and select the buffered common ground voltages, outputting the maximum value voltage, the minimum value voltage, and outputting N-1 maximum value state level signals and N-1 minimum value state level signals.

[0048] The maximum value selection circuit internally includes N-1 larger value selectors, used to compare the common ground voltages of two individual batteries and select the larger value as the output voltage. The N-1 larger value selectors are divided into a first-stage selection circuit, a second-stage selection circuit, ..., a Kth-stage selection circuit, where K is a positive integer greater than or equal to 1. The first-stage selection circuit compares the N input voltages pairwise, specifically in the following two cases:

[0049] When N is even, such as Figure 6 As shown, V1 is compared with V2, V3 with V4, ... V N-1 With V N The two selectors are paired and compared, and the larger value output by each selector is used as the output result Y1, Y2, ..., Y of the first-stage selection circuit. N / 2.

[0050] When N is odd, such as Figure 7 As shown, the first N-1 voltages are compared pairwise, and Y2, ..., Y are output. N -1 / 2, and then take the remaining uncompared voltage along with these output results as the output of the first-stage selection circuit.

[0051] The output of the first-stage selection circuit serves as the input to the second-stage selection circuit, where pairwise comparisons continue. This process continues until the Kth-stage selection circuit compares and selects the larger of the two voltages, which becomes the maximum value of the N input voltages.

[0052] The internal connection structure of the minimum value selection circuit is the same as that of the maximum value selection circuit, that is, it also adopts a K-level comparator tree structure, and when N is even, it follows the... Figure 5 Pairing by method, when N is odd. Figure 6 Pairing method; the only difference lies in the internal selector used: the maximum value selection circuit uses, for example... Figure 8 The larger value selector shown in (a) outputs the larger of the two input voltages, and the minimum value selection circuit uses the following... Figure 8 The smaller value selector shown in (b) outputs the smaller of the two input voltages.

[0053] In this embodiment, the larger value selector is as follows: Figure 8 As shown in (a), the circuit includes a first voltage comparator, a first dead-time controller, a seventh NMOS transistor M7, and an eighth NMOS transistor M8. The positive input terminal of the first voltage comparator is connected to the source of the seventh NMOS transistor M7, and the negative input terminal is connected to the source of the eighth NMOS transistor M8. The output terminal of the first voltage comparator is connected to the input terminal of the first dead-time controller. The output terminal Q of the first dead-time controller is connected to the gate of the seventh NMOS transistor M7 and serves as the state level output terminal Z. The gate of the eighth NMOS transistor M8 is connected to the gate of the seventh NMOS transistor M7. The drain of the eighth NMOS transistor M8 is connected to the drain of the seventh NMOS transistor M7 and serves as the voltage output terminal Y of the larger value selector. The truth table of the larger value selector is shown in Table 1:

[0054] Table 1: Truth Table of Larger Value Selector

[0055]

[0056] As shown in Table 1, when the input voltage A > B, the comparator output level is high, the dead-time controller Q output level is high, the seventh NMOS transistor M7 is turned on, and the output status level Z is high. The output level is low, and the eighth NMOS transistor M8 is cut off, so the output Y=A.

[0057] In this embodiment, the smaller value selector is as follows: Figure 8 As shown in (b), it includes a second voltage comparator, a second dead-time controller, a ninth NMOS transistor M9, and a tenth NMOS transistor M10. 10 The positive input terminal of the second voltage comparator is connected to the drain of the ninth NMOS transistor M9, and the negative input terminal is connected to the drain of the tenth NMOS transistor M10.10 The drain of the transistor is connected, and its output is connected to the input of the second dead-time controller. The output Q of the second dead-time controller is connected to the tenth NMOS transistor M. 10 The gate is connected to the output terminal. It is connected to the gate of the ninth NMOS transistor M9 and serves as the state level output terminal Z. The source of the ninth NMOS transistor M9 is connected to the tenth NMOS transistor M... 10 The source is connected and serves as the voltage output Y of the smaller value selector. The truth table of this smaller value selector is shown in Table 2:

[0058] Table 2: Truth Table for Smaller Value Selector

[0059]

[0060] In this embodiment, the maximum and minimum voltage selection circuit 4 compares and selects the common ground voltage of each cell in the battery pack through the coordinated operation of the maximum value selection circuit and the minimum value selection circuit, and finally outputs the following signals: maximum voltage, minimum voltage, N-1 maximum value state level signals for maximum voltage positioning, and N-1 minimum value state level signals for minimum voltage positioning.

[0061] like Figure 9 As shown, the extreme voltage positioning circuit in this embodiment is an extreme voltage positioning circuit 5 composed of 2-to-1 multiplexers, used to locate the extreme value position among four input voltages. For extreme value positioning of more than four voltages, multiple such 2-to-1 multiplexers can be combined. The circuit has three input terminals S, A1, and A2, and two output terminals S0 and S1, where output terminal S0 = S; when input terminal S is low, output terminal S1 = A1; when input terminal S is high, output terminal S1 = A2. The extreme voltage positioning circuit composed of several 2-to-1 multiplexers is suitable for both maximum voltage positioning circuits and minimum voltage positioning circuits, used to convert the input state level signal into binary data representing the extreme voltage position, and its truth table is shown in Table 3.

[0062] Table 3: Truth Table for Maximum / Minimum Voltage Positioning Circuit 5

[0063] .

[0064] For ease of description and explanation, this embodiment uses a four-input minimum voltage selection circuit as an example to detail the operation of the maximum / minimum voltage positioning circuit:

[0065] The connection relationship between the extreme value voltage positioning circuit and the four-input minimum value voltage selection circuit is as follows: Figure 9As shown: the state level signal output terminal Z of the smaller value selector 1 is connected to the input terminal A1 of the maximum / minimum voltage positioning circuit, the Z terminal of the smaller value selector 2 is connected to A2, and the Z terminal of the smaller value selector 3 is connected to S.

[0066] Assume the sampled voltages of the four individual cells are V1=3.2V, V2=3.1V, V3=3.3V, and V4=3.4V, where V2 is the minimum voltage among the four. (See also...) Figure 10 The selector uses a smaller value selector. In the first-stage selection circuit, the inputs are V1=3.2V, V2=3.1V, V3=3.3V, and V4=3.4V. The outputs are Y1=3.1V, Y2=3.3V, Z1=1, and Z2=0. In the second-stage selection circuit, the inputs are Y1=3.1V and Y2=3.3V, and the outputs are Y=3.1V and Z3=0, indicating that the minimum voltage is 3.1V. Inputting Z1=1, Z2=0, and Z3=0 to the input terminals A1, A2, and S of the maximum / minimum voltage positioning circuit 5, respectively, and seeing the output of the maximum / minimum voltage positioning circuit 5 (see Table 4), specifically binary data 01, reveals that the single cell with the minimum voltage is located in the second cell, B2.

[0067] Table 4: Truth Table for Minimum Voltage Positioning Circuit

[0068]

[0069] Similarly, assuming the sampled voltages of the four individual cells are V1=3.2V, V2=3.1V, V3=3.3V, and V4=3.4V, with V4 being the highest voltage among the four. (See also...) Figure 11 The selector uses a larger value selector. In the first-stage selection circuit, the inputs are V1=3.2V, V2=3.1V, V3=3.3V, and V4=3.4V. The outputs are Y1=3.2V, Y2=3.4V, Z1=0, and Z2=1. In the second-stage selection circuit, the inputs are Y1=3.2V and Y2=3.4V, and the outputs are Y=3.4V and Z3=1, indicating that the maximum voltage is 3.4V. Inputting Z1=0, Z2=1, and Z3=1 to the input terminals A1, A2, and S of the maximum voltage positioning circuit 5, respectively, and seeing the output of the maximum voltage positioning circuit 5 (see Table 5), specifically binary data 11, reveals that the single cell with the maximum voltage is located in the fourth cell, B4.

[0070] Table 5: Truth Table for Maximum Voltage Positioning Circuit

[0071]

[0072] In summary, the extreme voltage sampling and positioning circuit of this embodiment compares and selects the extreme voltage through the extreme voltage selection circuit 4, outputting the maximum and minimum voltage values, and outputting state level signals representing the locations of the maximum and minimum voltage values. These state level signals are then input to the input terminal of the extreme voltage positioning circuit 5. The extreme voltage positioning circuit 5, based on the input state level signals, converts them into two data signals representing the locations of the maximum and minimum voltage values, which serve as the two position data outputs of the circuit. This achieves efficient and accurate acquisition of the extreme voltages of the series-connected batteries in the battery pack, as well as rapid positioning of the physical serial numbers corresponding to the extreme voltage batteries.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit for sampling and locating the maximum / minimum voltage of a multi-cell series-connected battery, characterized in that, include: Voltage sampling circuit, voltage buffer circuit, extreme voltage selection circuit, and extreme voltage positioning circuit; The voltage sampling circuit is used to convert the floating ground voltage of each individual battery cell into a common ground voltage under the control of an external enable signal; it includes N voltage sampling units, where N is a positive integer greater than or equal to 2; each voltage sampling unit has a voltage input terminal, an enable input terminal, a voltage output terminal, and a current output terminal; the voltage input terminal of each voltage sampling unit is connected one-to-one with the positive terminal of the corresponding individual battery cell in the battery string, and the enable input terminals are all connected to the same external enable signal; the voltage output terminal of each voltage sampling unit is used to output the common ground voltage of the corresponding individual battery cell; the voltage sampling unit includes a voltage-to-current conversion circuit, a first current mirror circuit, and a second current mirror circuit; wherein: The voltage-to-current conversion circuit includes an operational amplifier, a fourth PMOS transistor, and a first resistor. The enable input of the operational amplifier serves as the enable input of the voltage sampling unit. The positive input of the operational amplifier is connected to the voltage input of the voltage sampling unit, the negative input is connected to one end of the first resistor and the drain of the fourth PMOS transistor, and the output is connected to the gate of the fourth PMOS transistor. The source of the fourth PMOS transistor is connected to the drain of the first PMOS transistor in the first current mirror circuit. The drain is connected to one end of the first resistor and the negative input of the operational amplifier, and the gate is connected to the output of the operational amplifier. The other end of the first resistor is grounded. The first current mirror circuit includes a first PMOS transistor, a second PMOS transistor, and a second resistor; the source of the first PMOS transistor is connected to the power supply, the gate and drain are shorted and connected to the gates of the second PMOS transistor and the third PMOS transistor respectively, and the drain is connected to the source of the fourth PMOS transistor; the source of the second PMOS transistor is connected to the power supply, the drain is connected to one end of the second resistor and serves as the voltage output terminal of the voltage sampling unit; the other end of the second resistor is grounded. The second current mirror circuit includes a third PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the source of the third PMOS transistor is connected to the power supply, the gate is connected to the gate of the first PMOS transistor, and the drain is connected to the drain and gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor, respectively; the source of the fifth NMOS transistor is grounded; the source of the sixth NMOS transistor is grounded, and the drain serves as the current output terminal of the voltage sampling unit; The current output terminal of each voltage sampling unit is connected to the voltage output terminal of its adjacent previous voltage sampling unit. The current output terminal of the Nth voltage sampling unit is left floating, and the current output terminal of the i-th voltage sampling unit is connected to the voltage output terminal of the (i+1)-th voltage sampling unit, i=1,2,…,N-1. All voltage sampling units share the same power supply terminal and the same common ground terminal. The voltage buffer circuit includes N voltage buffers, and the input terminals of the N voltage buffers are connected one-to-one with the voltage output terminals of the N voltage sampling units, for buffering the received common ground voltage. The input terminal of the extreme value voltage selection circuit is connected to the output terminals of the N voltage buffers one by one, and receives external enable signals. The extreme value voltage selection circuit is used to compare and select the buffered common ground voltages, output the maximum value voltage and the minimum value voltage, and output the maximum value state level signal and the minimum value state level signal. The input terminal of the extreme voltage positioning circuit is connected to the state level signal output terminal of the extreme voltage selection circuit, and is used to convert the state level signal into a data signal representing the location of the extreme voltage.

2. The maximum / minimum voltage sampling and positioning circuit for a multi-cell series-connected battery according to claim 1, characterized in that, The maximum / minimum voltage selection circuit includes a maximum value selection circuit and a minimum value selection circuit; both the maximum value selection circuit and the minimum value selection circuit have N voltage input terminals; the N voltage input terminals of the maximum value selection circuit are connected one-to-one with the N voltage input terminals of the minimum value selection circuit, and the N voltage input terminals of the maximum value selection circuit are connected one-to-one with the output terminals of the N voltage buffers.

3. The maximum / minimum voltage sampling and positioning circuit for a multi-cell series-connected battery according to claim 2, characterized in that, The maximum value selection circuit includes N-1 larger value selectors, which are divided into K-level selection circuits, where K≥1; The first-stage selection circuit compares the N input voltages pairwise. When N is even, it outputs N / 2 comparison results; when N is odd, it compares the N-1 voltages pairwise, obtaining (N-1) / 2 comparison results, and uses the remaining uncompared voltage and the comparison results together as the output result. The subsequent selection circuit compares the output of the previous selection circuit pairwise again until the final selection circuit outputs the maximum value among the N input voltages.

4. The maximum / minimum voltage sampling and positioning circuit for a multi-cell series-connected battery according to claim 3, characterized in that, The larger value selector includes a first voltage comparator, a first dead-time controller, a seventh NMOS transistor, and an eighth NMOS transistor; The positive input terminal of the first voltage comparator is connected to the source of the seventh NMOS transistor and serves as the positive input terminal of the larger value selector. The negative input terminal is connected to the source of the eighth NMOS transistor and serves as the negative input terminal of the larger value selector. The output terminal is connected to the input terminal of the first dead-time controller, and the enable terminal is connected to an external enable signal. The first output terminal Q of the first dead-time controller is connected to the gate of the seventh NMOS transistor and serves as the status level output terminal, while the second output terminal is connected to the gate of the eighth NMOS transistor. The drain of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor to serve as the voltage output terminal.

5. The maximum / minimum voltage sampling and positioning circuit for a multi-cell series-connected battery according to claim 2, characterized in that, The minimum value selection circuit includes N-1 smaller value selectors, which are divided into K-level selection circuits, where K≥1; The first-stage selection circuit compares the N input voltages pairwise. When N is even, it outputs N / 2 comparison results; when N is odd, it compares the N-1 voltages pairwise, obtaining (N-1) / 2 comparison results, and uses the remaining uncompared voltage and the comparison results together as the output result. The subsequent selection circuit compares the output of the previous selection circuit pairwise again until the final selection circuit outputs the minimum value among the N input voltages.

6. The maximum / minimum voltage sampling and positioning circuit for a multi-cell series-connected battery according to claim 5, characterized in that, The smaller value selector includes a second voltage comparator, a second dead-time controller, a ninth NMOS transistor, and a tenth NMOS transistor; The positive input terminal of the second voltage comparator is connected to the drain of the ninth NMOS transistor and serves as the positive input terminal of the smaller value selector. The negative input terminal is connected to the drain of the tenth NMOS transistor and serves as the negative input terminal of the smaller value selector. The output terminal is connected to the input terminal of the second dead-time controller. The first output terminal Q of the second dead-time controller is connected to the gate of the tenth NMOS transistor, and the second output terminal is connected to the gate of the ninth NMOS transistor and serves as the status level output terminal. The source of the ninth NMOS transistor is connected to the source of the tenth NMOS transistor to serve as the voltage output terminal.

7. The maximum / minimum voltage sampling and positioning circuit for a multi-cell series-connected battery according to claim 2, characterized in that, The maximum and minimum voltage positioning circuit includes a maximum voltage positioning circuit and a minimum voltage positioning circuit. The maximum voltage positioning circuit is used to convert the state level signals output by the maximum value selection circuit into data signals representing the location of the maximum voltage. The minimum voltage positioning circuit is used to convert the state level signals output by the minimum value selection circuit into data signals representing the location of the minimum voltage.

8. The maximum / minimum voltage sampling and positioning circuit for a multi-cell series-connected battery according to claim 7, characterized in that, The data signal representing the location of the extreme voltage is binary code, decimal code, I2C, SPI, 485, or CAN data.

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