A method, device and electronic equipment for generating test instructions for an electric servo mechanism

Abstract

The application relates to a kind of electric servo mechanism test instruction generation method, device and electronic equipment, belong to electric servo mechanism test technical field.The whole type test instruction generation logic is integrated, the instruction type and parameter configuration are completed by host computer, and the instruction core information is issued to test equipment at one time, test equipment completes instruction analysis, data reading and instruction generation, and the electric servo mechanism of different interface is adapted by multi-channel communication peripheral, and instruction is sent frame by frame.The application can realize the generalization of test instruction generation and test equipment, avoid repeated development and resource waste, improve communication real-time and test stability, significantly reduce labor and equipment cost, and is suitable for the function and performance test of various electric servo mechanisms.

Description

Technical Field

[0001] This invention relates to the field of electric servo mechanism testing technology, and in particular to a method, apparatus, and electronic device for generating test instructions for electric servo mechanisms. Background Technology

[0002] As a core actuator in electric drives, the electric servo mechanism must undergo comprehensive functional and performance testing before being put into use, and the generation of test commands is the first step in the entire testing process. Electric servo mechanism test commands are diverse, mainly including fixed value commands, step commands, sine commands, ramp commands, polynomial commands, external irregular random commands, as well as combinations of the above commands and parameter adjustment commands.

[0003] In existing technologies, test commands for electric servo mechanisms are mainly generated by a host computer. The specific process is as follows: the operator selects the command type and parameters on the host computer interface, the host computer software jumps to the corresponding callback function to generate the command, and then sends it frame by frame to the test equipment according to the communication protocol. The test equipment performs baud rate conversion and other processing before forwarding it to the electric servo mechanism. This traditional method has many drawbacks: First, the command generation method is singular, and each type of command requires independent development of modules, resulting in scattered modules and serious duplication of development, leading to a waste of human resources; second, the host computer software and test equipment have poor versatility, with one set of equipment only adapting to a single product model, resulting in low equipment resource utilization; third, in high real-time communication scenarios, ordinary computers cannot meet the precise timing requirements of millisecond-level or microsecond-level communication cycles; fourth, long-term irregular random commands generated and continuously sent by the host computer are prone to failures such as host computer freezing and command transmission interruption, affecting test stability. Therefore, developing a universal, highly reliable, and low-resource-consumption test command generation scheme for electric servo mechanisms has become an urgent technical problem to be solved in this field. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of the present invention provide a method, apparatus, and electronic device for generating test instructions for electric servo mechanisms. These solutions resolve issues such as wasted human and equipment resources, insufficient real-time communication, and susceptibility to host computer failures in traditional test instruction generation processes, achieving integrated, universal, and highly reliable test instruction generation. The technical solution adopted by the present invention is as follows:

[0005] A method for generating test commands for an electric servo mechanism, the method comprising the following steps:

[0006] Complete the test command type selection and parameter configuration in the host computer software interface, and send the core command information to the test device all at once;

[0007] After receiving the core instruction information sent by the host computer, the test equipment performs data parsing, parameter extraction, instruction type determination, and external instruction data reading operations to provide a data foundation for subsequent instruction generation.

[0008] The testing equipment performs waveform calculations, combinations, splicing, and superposition of test commands based on the parsed command feature values ​​and corresponding parameters to generate target test commands that meet the testing requirements of electric servo mechanisms.

[0009] The generated target test commands are then adapted for communication and output to the electric servo mechanism.

[0010] Optionally, the instruction types include fixed value instructions, step instructions, sine instructions, ramp instructions, polynomial instructions, externally input irregular random instructions, and superimposed combination instructions based on the above instructions.

[0011] Optionally, the parameters in the parameter configuration include amplitude, period, phase, slope, frequency, polynomial coefficients, and time length.

[0012] Optionally, a unique numerical code is assigned as an instruction characteristic value for each instruction type.

[0013] Optionally, after the data parsing is completed, the test device judges the instruction feature value. When the instruction feature value is identified as the number 6, it is determined that the instruction to be generated is an externally input irregular random instruction. Through the SPI peripheral of the processor of the test device, a read operation instruction is initiated to the external large-capacity memory connected to it. From the dedicated storage area pre-allocated by the external memory, the original data of the long-term irregular random instruction that has been imported and stored in advance is read point by point and continuously in time sequence.

[0014] Optionally, for a single type of instruction, the test equipment can independently generate a waveform based on the parameter set matched by the current instruction feature value; for a combined instruction, the test equipment can generate instruction waveforms line by line according to the combined instruction sequence configured by the host computer, or algebraically superimpose the output values ​​of multiple corresponding instructions point by point to finally form a continuous or superimposed composite instruction waveform.

[0015] Optionally, the step command is used for step response performance testing of the electric servo mechanism, and the step command adopts a standard structure of symmetrical bidirectional step combined with equal-duration zero-instruction interval.

[0016] Optionally, a complete step instruction cycle may consist of four consecutive stages: First, a positive step instruction with the same amplitude as the configured step instruction is output, and the holding time is determined by the step time parameter set by the host computer. After the positive step is held, a zero instruction is output, and the duration of the zero instruction is exactly the same as the holding time of the aforementioned positive step instruction. After the zero instruction interval ends, a negative step instruction with the same absolute value as the positive step amplitude is output, and the holding time is also consistent with the positive step time. After the negative step is held, another zero instruction is output, and the duration is still equal to the positive step time, thus completing a complete step instruction cycle.

[0017] An apparatus for generating test instructions for an electric servo mechanism is provided for generating the aforementioned test instructions for the electric servo mechanism. The apparatus includes an instruction configuration and distribution module deployed on a host computer, and an instruction parsing and storage module, an instruction generation and processing module, and a communication adaptation and transmission module deployed on the test equipment.

[0018] The instruction configuration and distribution module is used to complete the selection of test instruction types and parameter configuration, and to distribute the core instruction information to the instruction parsing and storage module in the test device in one go.

[0019] The instruction parsing and storage module is used to perform data parsing, parameter extraction, instruction type determination, and external instruction data reading operations after receiving the core instruction information, so as to provide a data foundation for subsequent instruction generation.

[0020] The instruction generation and processing module performs test instruction waveform calculations, combination splicing, and superposition synthesis based on the parsed instruction feature values ​​and corresponding parameters to generate target test instructions that meet the test requirements of electric servo mechanisms.

[0021] The communication adaptation and sending module is used to output the generated target test command to the electric servo mechanism after communication adaptation.

[0022] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the method for generating test instructions for an electric servo mechanism described above.

[0023] This invention provides a method, apparatus, and electronic device for generating test commands for an electric servo mechanism. The technical solutions provided by the embodiments of this invention offer at least the following beneficial effects:

[0024] It integrates all types of test instruction generation methods, eliminating the need for redundant development of single-type instruction modules and significantly saving labor costs; it achieves universality between instruction generation logic and test equipment, allowing one set of equipment to adapt to multiple models of electric servo mechanisms, reducing equipment resource waste; instruction generation is completed by the test equipment, relying on the hardware processor to achieve microsecond / millisecond-level precise timing, meeting the requirements of high baud rate and high real-time communication; the host computer issues instruction information only once, without continuous data transmission, completely avoiding host computer freezing and instruction interruption failures during long-term testing.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the external communication components of the test equipment;

[0028] Figure 2 A flowchart illustrating the generation of test commands for an electric servo mechanism;

[0029] Figure 3 A schematic diagram of a step instruction in a "single type instruction area";

[0030] Figure 4a A schematic diagram of a ramp instruction for a "single-type instruction area" with a starting position of zero;

[0031] Figure 4b A schematic diagram of a ramp instruction for a "single type instruction area" where the starting position is not zero. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0033] Before describing the technical solution of the present invention in detail, the technical background and technical terms involved in the technical solution will be explained first:

[0034] Electric servo mechanism: A mechatronic actuator that uses an electric motor as a power source and employs closed-loop control to achieve high-precision, high-response, and high-stability automatic tracking and control of physical quantities such as position, speed, and torque / force. It is a core actuator in aerospace, aviation, and industrial automation. By collecting the actual state of the output terminal in real time through sensors and comparing it with the target command value, the controller quickly adjusts the motor drive signal according to the deviation, enabling the output to quickly and accurately follow the command changes, thus achieving closed-loop servo control. The test command generation scheme of this invention is specifically designed to output step, sine, ramp, polynomial, and irregular random commands to the electric servo mechanism to test its key performance indicators such as positioning accuracy, response speed, dynamic characteristics, stability, and long-term reliability.

[0035] Figure 1 This diagram illustrates the components of the test equipment's external communication system. It fully presents the core hardware structure, on-chip peripheral resources, external expansion components, and the electrical connections and data interaction relationships between the various components. This provides hardware architecture support for the generation and high real-time transmission of universal test commands for electric servo mechanisms, as described in this invention.

[0036] The test equipment shown in the figure is based on a dedicated processor, which has two optional hardware implementations. The first is a DSP processor with built-in multi-channel communication peripheral interfaces. This DSP processor integrates multiple communication interfaces such as UART, SPI, HDLC, CAN, I2C, and 1553B, and can directly complete the interaction of instruction configuration information with the host computer and the adaptation of instruction transmission with electric servo mechanisms with different communication protocols. The second is a ZYNQ processor, which adopts a heterogeneous architecture, divided into an ARM side and an FPGA side. The ARM side is used to run the control program and instruction parsing and generation software of the test equipment, while the FPGA side is used to implement the timing drive, protocol conversion, and data transmission and reception control of the multi-channel communication peripherals. Both processor solutions can meet the requirements of short cycle and high real-time instruction generation and communication.

[0037] In the processor's external expansion circuitry, a large-capacity external memory, preferably FLASH memory, is connected via SPI communication peripherals. This memory has a sufficiently large data storage space, primarily used to store the test equipment's operating program and pre-imported long-term irregular random instruction data. This ensures that instruction data can be read quickly and stably during irregular random instruction testing, without relying on real-time transmission from the host computer. The processor's integrated multi-channel communication peripherals handle two types of core communication tasks. One type of peripheral establishes a dedicated communication link with the host computer, receiving core instruction information such as instruction type, instruction characteristic value, cycle, duration, and various configuration parameters issued by the host computer before the start of a single test. Only one data transmission is required during the entire test, eliminating the need for continuous communication. The other type of peripheral establishes a communication connection with the electric servo mechanism, compatible with various industrial communication protocols such as UART, HDLC, CAN, I2C, and 1553B. It can adapt to different interface types and models of electric servo mechanisms, sending various standard test instructions or irregular random instructions generated internally by the test equipment frame by frame to the electric servo mechanism according to the corresponding communication protocol.

[0038] It should be noted that the "no continuous communication" mentioned above refers to the fact that the host computer does not need to continuously send test information to the test equipment, thus reducing the communication burden between the host computer and the test equipment. In actual engineering, after the host computer and the test equipment send instructions to the electric servo mechanism, they often need to receive data returned by the electric servo mechanism. It is not that there is no communication at all, but the content of the returned data is not within the scope of this invention and therefore is not described.

[0039] Overall, this communication architecture forms a complete communication system with the host computer as the configuration end, the test equipment as the core instruction generation and sending end, external memory as data support, and electric servo mechanism as the execution terminal. From the hardware level, it realizes multi-protocol compatibility, large-capacity data storage, short-cycle precise timing, and high-reliability communication, providing a solid hardware foundation for realizing universal test instruction generation and generalized testing.

[0040] On the one hand, the present invention provides a method for generating test instructions for an electric servo mechanism. Figure 2 A flowchart illustrating the generation of test commands for an electric servo mechanism. The method includes the following steps:

[0041] Step S201: Select the test command type and configure the parameters in the host computer software interface, and send the core command information to the test device all at once.

[0042] This step is the starting point of the entire test command generation process. All operations are completed on the host computer side. Its core function is to complete the visual configuration of the test command and send the key information of the command to the test device at once. Data is sent only once during the entire test process, without the need for continuous communication and interaction.

[0043] The host computer software interface pre-integrates all the instruction type configuration functions required for testing the electric servo mechanism. Instruction types include fixed-value instructions, step instructions, sine instructions, ramp instructions, polynomial instructions, externally input irregular random instructions, and superimposed combinations of the above instructions. Editable parameters are provided on the interface, including amplitude, period, phase, slope, frequency, polynomial coefficients, and time length, meeting the parameterization requirements of various instructions. To achieve standardized identification of instruction types, this step assigns a unique numerical code as an instruction feature value to each instruction. Feature value 1 corresponds to a fixed-value instruction, feature value 2 to a step instruction, feature value 3 to a sine instruction, feature value 4 to a ramp instruction, feature value 5 to a polynomial instruction, feature value 6 to an externally input irregular random instruction, and feature value 7 to instruction superposition.

[0044] The host computer software interface is divided into a single-type instruction area and a combined instruction area. The single-type instruction area is used for independent parameter configuration of single-type instructions such as fixed values, step, sine, ramp, and polynomial. The combined instruction area provides entry points for configuring multiple instructions continuously or superimposed in a table format. It supports directly entering parameters on the interface and also supports importing parameters from local Excel files in a unified format, facilitating rapid configuration and reuse of complex test tasks. The effective number of columns in the table is the maximum number of parameters for each single-type instruction plus one. The table definition for the "combined instruction area" interface is shown in Table 1 below. After receiving the combined instruction information, the test equipment generates continuous instruction information row by row, or superimposes the instruction information from each row as the final instruction.

[0045] Table 1 - Definition of the "Combined Command Area" Interface

[0046]

[0047] The parameters are defined as follows:

[0048] Instruction characteristic values: 1 represents a fixed value instruction, 2 represents a step instruction, 3 represents a sine instruction, 4 represents a ramp instruction, 5 represents a polynomial instruction, 6 represents an irregular random instruction from external input, and 7 represents instruction superposition.

[0049] Parameter 1: Fixed value instruction amplitude / Step instruction amplitude / Sine instruction amplitude / Ramp instruction slope / Polynomial instruction cubic coefficient.

[0050] Parameter 2: Fixed instruction time / Step instruction time / Sine instruction phase / Ramp instruction amplitude / Polynomial instruction quadratic coefficient.

[0051] Parameter 3: Step instruction cycle / Sine instruction start frequency / Ramp instruction start position / Polynomial instruction first degree coefficient.

[0052] Parameter 4: Sine instruction interval frequency / number of ramp instruction cycles / coefficient of polynomial instruction constant term.

[0053] Parameter 5: Sine instruction cutoff frequency / polynomial instruction start position x value (mathematical value, can be negative, representing the zero point of the test time).

[0054] Parameter 6: Sine instruction bias / final position x value of polynomial instruction (mathematical value, can be negative, representing the end of the test time).

[0055] Parameter 7: Number of cycles per frequency for a single sine command.

[0056] The meanings of parameters 1 through 7 in a specific instruction line are determined by the instruction characteristic value. When the instruction characteristic value is "1", the test equipment generates a constant value instruction; when the instruction characteristic value is "2", the step instruction generated by the test equipment includes a positive instruction and a negative instruction with the same amplitude, with the positive instruction preceding the negative one. Each step instruction contains a zero instruction of the same duration between them, as illustrated in the diagram below. Figure 3 As shown; when the instruction characteristic value is "3", the test equipment generates the corresponding sine wave instruction according to each parameter; when the instruction characteristic value is "4", the test equipment generates a ramp instruction from the starting position to the end of the entire cycle, including two cases: the starting position is zero and it is not zero. A schematic diagram is shown below. Figure 4a , Figure 4b As shown; when the instruction characteristic value is "5", the test device generates the corresponding polynomial instruction according to each parameter; when the instruction characteristic value is "6", the irregular random instruction value of the external input stored in the external memory of the test device is read in real time; when the instruction characteristic value is "7", the instruction characteristic value of each row can only be "7", and at this time the instructions of each row are superimposed.

[0057] According to the test requirements, the operator selects the instruction type and fills in or imports the corresponding parameters on the host computer interface. The host computer will automatically integrate core instruction information such as instruction characteristic values, amplitude, period, phase, slope, frequency, coefficients, and running time, forming a concise instruction configuration data packet. This data packet is then sent to the test equipment in one go via the communication link. Throughout the entire test cycle, from start to finish, the host computer will not send any instruction-related data to the test equipment, thus avoiding the computer performance pressure and communication failure risks caused by high-frequency continuous data transmission.

[0058] Step S202: After receiving the core instruction information sent by the host computer, the test device performs data parsing, parameter extraction, instruction type determination, and external instruction data reading operations to provide a data foundation for subsequent instruction generation.

[0059] This step is crucial for the testing equipment to receive configuration information from the host computer and prepare data for subsequent instruction generation. The entire process is executed independently by the testing equipment without the involvement of the host computer.

[0060] After receiving the core instruction information issued by the host computer once before a single test through its onboard communication peripherals, the test equipment immediately parses the received complete data frame. According to the preset communication protocol and data format, it accurately extracts the instruction feature value and all configuration parameters that match the instruction feature value, including key parameters such as amplitude, period, phase, slope, frequency, coefficients of each polynomial, time length, start position, and end position. The parsed instruction type identifier and parameter data are temporarily stored in the processor's internal memory area to provide accurate data basis for subsequent instruction generation.

[0061] After parsing, the testing equipment judges the instruction feature value. When the instruction feature value is identified as the number 6, it is determined that the instruction to be generated is an externally input irregular random instruction. At this time, the testing equipment no longer generates the instruction waveform by the processor in real time. Instead, it initiates a read operation instruction to the external large-capacity memory connected to it through the processor's built-in SPI peripheral. From the dedicated storage area pre-allocated by the external memory, it reads the original data of the long-term irregular random instruction that has been imported and stored in advance in a time sequence to meet the needs of the servo mechanism for irregular, customized, and long-duration test instructions.

[0062] This external high-capacity memory is a dedicated extended storage component for the test equipment. It achieves bidirectional data interaction with the processor through the SPI communication interface. It is not only used to store the test equipment's own running program and firmware data, but also has sufficient storage space to carry large-capacity irregular random instruction datasets with extremely long durations. This ensures that instruction data can be provided stably, quickly, and uninterruptedly throughout the entire test process, avoiding interruptions in instruction generation due to untimely data reading or insufficient storage capacity.

[0063] Step S203: The testing equipment performs test command waveform calculation, combination splicing and superposition synthesis based on the parsed command feature values ​​and corresponding parameters to generate target test commands that meet the testing requirements of electric servo mechanisms.

[0064] The above-mentioned instruction generation and processing steps are the core execution stage of this method, and are independently completed by the processor of the test equipment. In this step, the test equipment, based on the instruction feature values ​​parsed in the previous stage and all corresponding configuration parameters, calculates and generates target test instructions that meet the testing requirements of the electric servo mechanism according to a preset algorithm and waveform generation rules. For single-type instructions, the processor directly generates waveforms independently based on the parameter set matched by the current instruction feature value; for combined instructions, the processor generates instruction waveforms line by line according to the combined instruction sequence configured by the host computer, or performs algebraic superposition of the output values ​​of multiple corresponding instructions point by point to finally form a continuous or superimposed composite instruction waveform. The specific operation method is as follows:

[0065] When the instruction characteristic value corresponds to a fixed value instruction, the processor outputs a constant value instruction that remains unchanged throughout the entire process, according to the set amplitude and duration.

[0066] When the instruction characteristic value corresponds to a step instruction, the processor generates a standard step waveform containing positive step, negative step, and zero-level intervals of equal duration according to the configured amplitude, time, and cycle parameters. The output order is as follows: first, a positive step signal; then, a zero instruction with the same duration as the step is inserted; then, a negative step signal with the same amplitude is output; and then, a zero instruction of equal duration is inserted again. This cycle is repeated to form a complete step instruction sequence.

[0067] When the instruction characteristic value corresponds to a sine instruction, the processor generates a fixed-frequency or swept-frequency sine instruction waveform based on parameters such as amplitude, phase, start frequency, interval frequency, cutoff frequency, bias, and number of cycles per frequency.

[0068] When the instruction characteristic value corresponds to a ramp instruction, the processor generates a linearly changing ramp waveform based on parameters such as slope, amplitude, starting position, and number of cycles, covering two typical working scenarios. The first is a ramp instruction with a starting position of zero, which starts from zero and changes linearly with the set slope to the target amplitude. The second is a ramp instruction with a starting position of non-zero, which starts from the set initial position and changes linearly with the slope to the target amplitude, and outputs the waveform cyclically according to the configured number of cycles.

[0069] When the instruction feature value corresponds to a polynomial instruction, the processor calculates and outputs the corresponding curve instruction in real time according to the configured parameters such as cubic coefficient, quadratic coefficient, linear coefficient, constant coefficient, start position, and final position, thereby achieving smooth nonlinear trajectory output.

[0070] When the instruction characteristic value corresponds to an externally input irregular random instruction, the processor directly uses the pre-stored instruction value read from external memory and no longer performs waveform calculations.

[0071] When the instruction feature value corresponds to instruction superposition, the processor will add the output values ​​of multiple instruction lines involved in the superposition point by point to form the superimposed comprehensive instruction output, ensuring that various complex test requirements can be met.

[0072] Step S204: After the generated target test command is adapted for communication, it is output to the electric servo mechanism.

[0073] The aforementioned instruction transmission and communication adaptation steps are the final execution stage in this method, ensuring the reliable, timely, and protocol-compliant output of the generated target test instructions to the electric servo mechanism. These steps directly determine the real-time performance and stability of the test instruction transmission. In this step, the processor of the test equipment frames the continuous target test instruction data obtained through the instruction generation and processing stages according to the pre-agreed communication frame format, communication rate, and timing requirements with the electric servo mechanism under test. It then strictly adheres to the communication protocol supported by the electric servo mechanism, sending the data frame by frame, at regular intervals, and in an orderly manner.

[0074] To adapt to electric servo mechanisms of different models and interface specifications, the test equipment hardware integrates multiple flexibly configurable communication peripherals, including one or more of UART, SPI, HDLC, CAN, I2C, and 1553B. These peripherals can be independently selected and switched according to the communication interface type of the actual test object, without the need to replace hardware or repeatedly develop drivers.

[0075] During transmission, the processor maintains precise timing at the microsecond or millisecond level based on the timing and values ​​output by the instruction generation stage. This ensures that the transmission time of each frame of instruction data is strictly aligned with the instruction timeline, meeting the high real-time and high synchronization control requirements of the electric servo mechanism. For single-type instructions, continuously combined instructions, and composite instructions resulting from the superposition of multiple instructions, a unified transmission and communication adaptation mechanism is employed to guarantee continuous, uninterrupted, error-free, and frame-free waveform output. Simultaneously, the test equipment maintains a stable communication link with the electric servo mechanism throughout instruction transmission, eliminating the need for the host computer to participate in data forwarding or timing control. This fundamentally avoids instruction transmission anomalies caused by host computer performance issues, communication delays, or software lag, ensuring the reliable completion of the entire test process.

[0076] Figure 3 This is a schematic diagram of a step command in a "single-type command area". This command is automatically generated by the test equipment based on a step command parameter with a characteristic value of 2, and is used to test the step response performance of the electric servo mechanism. The schematic diagram uses time as the horizontal axis and command amplitude as the vertical axis to fully present the periodic structure, amplitude variation law, and timing arrangement of the step command.

[0077] This step instruction adopts a standard structure of symmetrical bidirectional step + equal-duration zero-instruction interval. Within a complete instruction cycle, it consists of four consecutive stages: First, a positive step instruction with the same amplitude as the configured step is output, and the holding time is determined by the step time parameter set by the host computer. After the positive step is held, a zero instruction is output, and the duration of this zero instruction is exactly equal to the holding time of the aforementioned positive step instruction. After the zero-instruction interval ends, a negative step instruction with the same absolute value as the positive step amplitude is output, and the holding time is also consistent with the positive step time. After the negative step is held, another zero instruction is output, and the duration is still equal to the positive step time, thus completing a complete step instruction cycle.

[0078] Throughout the test, the testing equipment will repeatedly output the aforementioned periodic waveform of "positive step - equal-duration zero command - negative step - equal-duration zero command" according to the configured number of cycles. Within the same cycle, the positive and negative amplitudes are equal in magnitude and opposite in direction, and the two zero command segments have equal durations and uniform intervals. This waveform structure can stably provide standard bidirectional step excitation for the electric servo mechanism, clearly reflecting the mechanism's positive response, negative response, steady-state error, and dynamic recovery characteristics, meeting all the requirements for high-precision step performance testing.

[0079] Figure 4a , Figure 4b These diagrams illustrate ramp commands in a "single-type command area" with a starting position of zero and a starting position not equal to zero. This command is automatically generated by the testing equipment based on ramp command parameters with a characteristic value of 4, and is used to test the linear response, speed characteristics, and tracking performance of the electric servo mechanism. The diagrams, with time on the horizontal axis and command amplitude / position on the vertical axis, clearly demonstrate the variation pattern, periodic structure, and two typical starting position forms of the ramp command.

[0080] The ramp command is a linearly monotonically changing periodic waveform, generated by the test equipment according to configured parameters such as slope, amplitude, starting position, and number of cycles. It exhibits a uniform linear change from the starting position to the target amplitude, and is output cyclically according to the set number of cycles. The diagram clearly shows two configurable working modes: the first is a ramp command with a starting position of zero. The waveform starts from the zero point on the vertical axis, rises linearly at a set slope to the target amplitude, and after reaching the amplitude, maintains or immediately enters the next cycle of linear change, forming a standard ramp shape starting from zero. The second is a ramp command with a non-zero starting position. The waveform starts from the user-defined initial position and changes linearly at the same slope to the target amplitude. The starting point can be set to a non-zero value according to test requirements to meet the linear loading test requirements under different initial states.

[0081] Within a complete cycle, the ramp command starts from the initial position and linearly changes in a single direction to the set amplitude. The rate of change is uniquely determined by the configured slope. The cycle length is determined by the initial position, amplitude, and slope. The number of cycles directly determines the number of times the ramp command is repeatedly output. Regardless of whether the initial position is zero or non-zero, the command maintains a strict linear change pattern, without abrupt changes or fluctuations. This provides a stable, continuous, and controllable linear excitation signal for the electric servo mechanism, accurately testing the servo mechanism's linear following capability, response smoothness, and steady-state accuracy.

[0082] The following is a detailed description of the entire process of the above solution through a specific application example. This example uses a multi-functional comprehensive performance test of a certain type of electric servo mechanism as the application scenario, covering the entire execution process from command configuration, issuance, parsing, generation to transmission. The specific operations are as follows:

[0083] 1. Preparation before testing

[0084] The test equipment uses a ZYNQ processor. The ARM side runs instruction parsing and generation software, and the FPGA side implements the UART, CAN, and 1553B communication peripheral drivers. The processor is connected to a large-capacity FLASH memory via SPI peripheral to store device programs and external irregular random instructions. The host computer is equipped with integrated test software. The interface includes a single-type instruction area and a combined instruction area, and supports instruction feature value encoding and parameter configuration.

[0085] The requirements for this test are as follows: perform four consecutive tests in sequence: fixed value hold, bidirectional step, linear ramp, and frequency sweep sine. Finally, perform a composite characteristic test by superimposing step and sine commands. The test equipment will generate and send commands independently throughout the process, and the host computer will only participate in the initial configuration and single information transmission.

[0086] 2. Target test command generation

[0087] Step 1: Command Configuration and Information Issuance

[0088] The operator completes the command configuration on the host computer software interface:

[0089] Open the command combination area table and enter 5 lines of command parameters in sequence, each line corresponding to a command type:

[0090] Line 1: Instruction feature value 1 (fixed value instruction), parameter 1 is amplitude 5, parameter 2 is duration 10s.

[0091] Line 2: Instruction characteristic value 2 (step instruction), parameter 1 is amplitude ±10, parameter 2 is hold time 2s, parameter 3 is number of cycles 3.

[0092] Line 3: Instruction characteristic value 4 (ramp instruction), parameter 1 is slope 2, parameter 2 is amplitude 20, parameter 3 is start position 0, parameter 4 is number of cycles 2.

[0093] Line 4: Instruction characteristic value 3 (sine instruction), parameter 1 is amplitude 8, parameter 2 is phase 0°, parameter 3 is start frequency 1Hz, parameter 4 is interval frequency 0.5Hz, parameter 5 is cutoff frequency 5Hz, parameter 6 is bias 0, parameter 7 is single frequency cycle number 2.

[0094] Line 5: Instruction Feature Value 7 (Instruction Overlay), overlaying all previous instruction lines (Line 1 fixed value instruction, Line 2 step instruction, Line 3 ramp instruction, Line 4 sine instruction). The host computer automatically packages the above instruction feature values, amplitude, period, slope, frequency, time, coefficient and other core parameters, and sends them to the test equipment at once via UART. No further instruction data will be sent during this test.

[0095] Step 2: Instruction parsing and data reading

[0096] The test equipment receives the instruction data packets sent by the host computer completely through the communication peripherals. The processor parses the data according to the protocol: extracting the instruction feature values ​​and corresponding parameters line by line and storing them in the internal storage unit.

[0097] Each instruction's characteristic value is evaluated: Characteristic values ​​1, 2, 3, and 4 are all standard instruction types, requiring no external memory read. Characteristic value 6 (external irregular random instruction) was not used in this case, therefore no FLASH read operation was triggered. When characteristic value 7 is used, the superimposed instructions may not necessarily be of a standard instruction type.

[0098] After parsing, the parameters are sorted according to the execution order and passed to the instruction generation module.

[0099] Step 3: Instruction Generation and Processing

[0100] The test equipment processor generates target test instructions one by one according to the instruction sequence and feature value rules:

[0101] Generate fixed value instruction: Continuously output a constant instruction with an amplitude of 5 for 10 seconds.

[0102] Generate step instructions: follow the cyclical structure of "positive step 10 → equal duration zero instruction → negative step -10 → equal duration zero instruction", repeat for 3 cycles, and hold each step for 2 seconds.

[0103] The ramp generation command is as follows: the ramp rises linearly from the starting position 0 with a slope of 2 to an amplitude of 20, then falls linearly to -20 with a slope of -2, and then rises linearly back to 0 with a slope of 2. This cycle repeats for 2 periods, forming a standard ramp waveform starting from zero.

[0104] The above ramp command is a standard linear ramp waveform starting from zero. Based on the preset algorithm of the test equipment command generation and processing module, the first stage uses a slope of 2 as the core rate of change, linearly rising from the starting position 0 to the target amplitude of 20 to complete a single cycle; the second stage uses a slope of -2 as the core rate of change, linearly decreasing from the current amplitude of 20 to the target amplitude of -20; the third stage uses a slope of 2 as the core rate of change, linearly rising from the starting position of -20 to position 0, and executing the second cycle according to the same rules, maintaining linearity without sudden changes and precise timing synchronization throughout the process.

[0105] Generate sine wave instruction: start at 1Hz, stop at 5Hz, and step by step at 0.5Hz to sweep the frequency and output a sine wave with an amplitude of 8 and no bias. Each frequency point runs for 2 cycles.

[0106] Generate superposition instructions: Add the values ​​of the waveforms of the above 4 lines of instructions (fixed value instruction, step instruction, ramp instruction, and sine instruction) point by point to form a composite excitation instruction.

[0107] All instructions are generated continuously in the configured order, without interruption or misalignment, and the contents of the combined instruction area are output continuously line by line.

[0108] Step 4: Command Sending and Communication Adaptation

[0109] The testing equipment transmits commands according to the CAN bus communication protocol of the electric servo mechanism under test: the processor frames the generated continuous command data according to the communication frame format, and sets the baud rate, data bits, parity bits, and frame interval. The CAN communication peripheral on the FPGA is enabled to establish a stable communication link with the electric servo mechanism. Commands are transmitted frame by frame with millisecond-level precise timing; fixed value, step, ramp, sine, and superposition commands are output sequentially and continuously.

[0110] The entire transmission process is independently controlled by the test equipment, without the need for forwarding by the host computer, and the communication is stable with no frame loss or lag.

[0111] 3. Test Execution Results

[0112] The electric servo mechanism sequentially completed tests of fixed-value steady-state holding, bidirectional step response, linear ramp tracking, swept-frequency sine tracking, and composite command tracking. All excitation commands were generated and sent in real time by the test equipment. The host computer only sent configuration information once before the test began. There was no computational load during the test, and no faults such as freezing, delay, or command interruption occurred. The entire set of equipment did not require the redevelopment of instruction modules for this model, and was directly compatible with the test, achieving significant savings in manpower and equipment costs, while meeting the requirements of short-cycle, high-real-time communication testing.

[0113] In summary, this invention, through integrated hardware and software design, fundamentally solves the problems of traditional test instruction generation methods, such as single methods, repetitive development, poor versatility, and bottlenecks in host computer performance and frequent crashes. It achieves universal, generalized, and highly reliable generation and transmission of all types of test instructions. This invention unifies and integrates all test instructions, including fixed values, step, sine, ramp, polynomial, external irregular random, and instruction superposition. It uses digital feature value encoding to distinguish instruction types. After the host computer completes the visual parameter configuration, only the core instruction information needs to be sent to the test equipment once; no real-time calculation is required throughout the process. The test equipment uses a DSP or ZYNQ as its core processor, relies on multi-channel communication peripherals adapted to electric servo mechanisms with different interfaces, and stores long-term irregular random instructions in an external large-capacity FLASH memory. It autonomously completes instruction parsing, data reading, waveform generation, and combination superposition processing, and sends instructions frame-by-frame with high precision at regular intervals according to the protocol. Among them, the step instruction adopts a zero-instruction interval structure with positive and negative amplitude plus equal duration, the ramp instruction supports two forms of zero point and non-zero point start, the polynomial instruction generates curves according to multi-order coefficients, and the combined instruction can be executed continuously or multiple waveforms can be superimposed, comprehensively covering various functional and performance testing requirements of electric servo mechanisms.

[0114] Compared with existing technologies, this invention achieves a high degree of versatility between the instruction generation module and the testing equipment, avoiding redundant development and significantly saving manpower and equipment costs; it delegates instruction generation and calculation to hardware testing equipment, meeting the high real-time requirements of short-cycle communication at the millisecond / microsecond level; the host computer only participates in configuration and single-time issuance, eliminating freezing, frame loss, and instruction interruption failures in long-term testing from the source. The overall solution is stable, reliable, highly adaptable, and easy to deploy, and can be widely applied to the batch general-purpose testing of various electric servo mechanisms.

[0115] Secondly, this invention provides a device for generating test instructions for an electric servo mechanism. This device includes an instruction configuration and distribution module, an instruction parsing and storage module, an instruction generation and processing module, and a communication adaptation and transmission module. These will be described in detail below.

[0116] The instruction configuration and distribution module, deployed on the host computer, is used to complete the selection of test instruction types and parameter configuration, and to distribute the core instruction information to the instruction parsing and storage module in the test device in one go.

[0117] The instruction parsing and storage module, deployed on the test equipment, is used to perform data parsing, parameter extraction, instruction type determination, and external instruction data reading operations after receiving the core instruction information, providing a data foundation for subsequent instruction generation.

[0118] The instruction generation and processing module is deployed on the test equipment. Based on the parsed instruction feature values ​​and corresponding parameters, the instruction generation and processing module performs test instruction waveform calculations, combination splicing, and superposition synthesis to generate target test instructions that meet the test requirements of electric servo mechanisms.

[0119] The communication adaptation and transmission module, deployed on the test equipment, outputs the generated target test commands to the electric servo mechanism after communication adaptation.

[0120] In practical applications, the instruction parsing and storage module, instruction generation and processing module, and communication adaptation and sending module are the core software functional units for the test equipment's processor operation. The instruction configuration and sending module provides external configuration data to the processor, and the communication adaptation and sending module is the hardware interface unit for the processor's external output. These four modules work together to complete all test instruction generation and sending tasks. The instruction configuration and sending module is deployed on the host computer and establishes a one-way instruction data sending channel with the test equipment's communication peripherals. The instruction configuration and sending module is the data sending end. The host computer only sends the configured instruction feature values, parameter sequences, and other core information to the test equipment. Only one connection and data transmission are established per test. After the transmission is completed, the connection remains silent until the next test configuration. The two are in a one-way data transmission relationship from the upstream configuration end to the downstream receiving end.

[0121] Both the instruction parsing and storage module and the instruction generation and processing module are integrated within the test equipment, forming a tightly coupled data interaction relationship. After completing instruction information parsing, parameter extraction, and external memory data reading, the instruction parsing and storage module directly transmits the processed instruction type identifier, valid parameters, and external random instruction data to the instruction generation and processing module via the processor's internal bus (or via internal software variables), providing all input data for instruction generation. The instruction generation and processing module only receives result data from the instruction parsing and storage module and does not output control instructions in reverse. The two modules form a sequential connection from front-end data processing to back-end computation and generation.

[0122] The instruction generation and processing module and the communication adaptation and sending module are both located inside the test equipment, and they are directly connected from the instruction stream output of the test equipment to the sending driver. After the instruction generation and processing module completes the calculation and generation of single-type instructions, continuous combined instructions, or superimposed instructions, it transmits the continuous instruction value stream arranged in time sequence to the communication adaptation and sending module in real time through the internal data bus (or it can be passed through the internal software variables of the test equipment). The communication adaptation and sending module performs framing, timing, and protocol encapsulation according to the instruction stream timing. The two maintain synchronous timing matching, and instruction generation and sending are seamlessly connected, forming a direct data flow relationship from the calculation output end to the driver sending end.

[0123] The communication adapter and transmission module establishes a bidirectional communication connection between the physical layer and the protocol layer with the electric servo mechanism directly through hardware communication peripherals such as UART, SPI, HDLC, CAN, I2C, and 1553B. It is responsible for sending the final instruction frame by frame to the electric servo mechanism at regular intervals, while maintaining link status monitoring. This module has no direct control connection with the host computer and only has internal data interaction with the instruction parsing and storage module and the instruction generation and processing module. It is the only external interface module in the entire device that directly interfaces with the electric servo mechanism.

[0124] Therefore, the overall structure and execution sequence of the electric servo mechanism test instruction generation device are as follows: instruction configuration and distribution module in the host computer → instruction parsing and storage module in the test equipment → instruction generation and processing module in the test equipment → communication adaptation and transmission module in the test equipment → linear topology relationship of sequential connection, step-by-step data transmission, and loop-free feedback of the electric servo mechanism. All modules work together to complete the entire process of instruction execution from configuration to output.

[0125] In a second aspect, the present invention provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the above-described method for generating test instructions for an electric servo mechanism.

[0126] The present invention may also provide a storage medium, which may be a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the above-described method for generating test instructions for electric servo mechanisms.

[0127] The computer-readable storage medium provided by this invention may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0128] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for generating test commands for an electric servo mechanism, characterized in that, The method includes the following steps: Complete the test command type selection and parameter configuration in the host computer software interface, and send the core command information to the test device all at once; After receiving the core instruction information sent by the host computer, the test equipment performs data parsing, parameter extraction, instruction type determination, and external instruction data reading operations to provide a data foundation for subsequent instruction generation. The testing equipment performs waveform calculations, combinations, splicing, and superposition of test commands based on the parsed command feature values ​​and corresponding parameters to generate target test commands that meet the testing requirements of electric servo mechanisms. The generated target test commands are adapted for communication and then output to the electric servo mechanism. After the data parsing is completed, the test equipment judges the instruction feature value. When the instruction feature value is identified as the number 6, it is determined that the instruction to be generated is an externally input irregular random instruction. Through the SPI peripheral of the processor of the test equipment, a read operation instruction is initiated to the external large-capacity memory connected to it. From the dedicated storage area pre-allocated by the external large-capacity memory, the original data of the long-term irregular random instruction that has been imported and stored in advance is read point by point and continuously in time sequence. For single-type instructions, the test equipment directly generates waveforms independently based on the parameter set matched by the current instruction feature value. For combined instructions, the test equipment generates instruction waveforms line by line according to the combined instruction sequence configured by the host computer, or performs algebraic superposition of the output values ​​of multiple corresponding instructions point by point to finally form a continuous or superimposed composite instruction waveform.

2. The method for generating test instructions for an electric servo mechanism according to claim 1, characterized in that, The instruction types include fixed value instructions, step instructions, sine instructions, ramp instructions, polynomial instructions, externally input irregular random instructions, and superimposed combination instructions based on the above instructions.

3. The method for generating test instructions for an electric servo mechanism according to claim 1, characterized in that, The parameters in the parameter configuration include amplitude, period, phase, slope, frequency, polynomial coefficients, and time length.

4. The method for generating test instructions for an electric servo mechanism according to claim 2, characterized in that, Each instruction type is assigned a unique numerical code as an instruction characteristic value.

5. The method for generating test instructions for an electric servo mechanism according to claim 2, characterized in that, The step command is used for step response performance testing of the electric servo mechanism. The step command adopts a standard structure of symmetrical bidirectional step combined with equal duration and zero instruction interval.

6. The method for generating test instructions for an electric servo mechanism according to claim 5, characterized in that, A complete step instruction cycle consists of four consecutive stages: First, a positive step instruction with the same amplitude as the configured step instruction is output, and the holding time is determined by the step time parameter set by the host computer. After the positive step is held, a zero instruction is output, and the duration of the zero instruction is exactly the same as the holding time of the aforementioned positive step instruction. After the zero instruction interval ends, a negative step instruction with the same absolute value as the positive step amplitude is output, and the holding time is also the same as the positive step time. After the negative step is held, another zero instruction is output, and the duration is still the same as the positive step time, thus completing a complete step instruction cycle.

7. An apparatus for generating test instructions for an electric servo mechanism, used to implement the method for generating test instructions for an electric servo mechanism as described in any one of claims 1 to 6, characterized in that, The device for generating test instructions for the electric servo mechanism includes an instruction configuration and distribution module deployed on a host computer, and an instruction parsing and storage module, an instruction generation and processing module, and a communication adaptation and transmission module deployed on the test equipment. The instruction configuration and distribution module is used to complete the selection of test instruction types and parameter configuration, and to distribute the core instruction information to the instruction parsing and storage module in the test device in one go. The instruction parsing and storage module is used to perform data parsing, parameter extraction, instruction type determination, and external instruction data reading operations after receiving the core instruction information, so as to provide a data foundation for subsequent instruction generation. The instruction generation and processing module performs test instruction waveform calculations, combination splicing, and superposition synthesis based on the parsed instruction feature values ​​and corresponding parameters to generate target test instructions that meet the test requirements of electric servo mechanisms. The communication adaptation and sending module is used to output the generated target test command to the electric servo mechanism after communication adaptation.

8. An electronic device, characterized in that, The device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the method for generating test instructions for an electric servo mechanism as described in any one of claims 1 to 6.

Images