A method for generating a test vector of a sequential logic unit and related products
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RUNPENG SEMICONDUCTOR (SHENZHEN) CO LTD
- Filing Date
- 2025-12-25
- Publication Date
- 2026-06-16
AI Technical Summary
Existing sequential logic unit detection methods lack comprehensiveness in test vectors, failing to fully cover the pre- and post-operational conditions and state transitions of flip-flops.
By determining the number of bits, value range, and initial value of the test vector, and combining this with measures to avoid sticking and trigger-type faults, the target code system is extended to generate test vectors that comprehensively cover all pre- and post-flip operating conditions and state transitions of all triggers.
This improves the comprehensiveness of test vectors, ensuring coverage of all trigger operating conditions and state transitions, thus increasing test coverage.
Smart Images
Figure CN122220171A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip manufacturing technology, and in particular to a method for generating test vectors for sequential logic units and related products. Background Technology
[0002] Sequential logic units are fundamental building blocks in digital circuits. Their output depends not only on the current input value but also on the circuit's past input history. Test vectors, on the other hand, are carefully designed sequences of input signals used to verify the correct functionality of sequential logic units in simulations or actual tests.
[0003] Existing sequential logic unit testing typically uses a convenient and very stable structure. The test vectors introduced only consider the correctness of the transmission from the D terminal to the Q terminal of the D flip-flop. That is, the Q port is set to zero or one by inputting the test vector to the D port. However, the setting and resetting of "stored or controlled data" internally by control ports such as set and reset or other data paths are not considered, which leads to the problem of insufficient comprehensiveness of the test vectors.
[0004] Therefore, how to improve the comprehensiveness of test vectors is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] To address the aforementioned issues, this application provides a method for generating test vectors for sequential logic units and related products. By expanding the initial values of the test vectors, the test vectors based on the target code system can comprehensively cover all the pre- and post-operational conditions and state transitions of all flip-flops, thereby improving the comprehensiveness of the test vectors.
[0006] In a first aspect, embodiments of this application provide a method for generating test vectors for sequential logic units, including:
[0007] Determine the number of bits of information corresponding to the test vector;
[0008] The range of values for the test vector is determined based on the number of bits of information.
[0009] The initial value of the test vector is determined based on the range of values.
[0010] To avoid adhesion and triggering faults, the initial value is expanded to obtain the target code system corresponding to the test vector;
[0011] The test vector is generated based on the target code.
[0012] Optionally, determining the number of information bits corresponding to the test vector includes:
[0013] Determine the number of non-clock input ports corresponding to the target sequential logic unit;
[0014] The number of non-clock input ports determines the number of information bits corresponding to the test vector, and the number of non-clock input ports is the same as the number of information bits corresponding to the test vector.
[0015] Optionally, determining the initial value of the test vector based on the value range includes:
[0016] Determine the number of test sequences;
[0017] The maximum signal value in each test sequence is determined based on the range of values.
[0018] Each test sequence is constructed based on the maximum signal value in each test sequence, and the initial value of the test vector is obtained.
[0019] Optionally, determining the number of test sequences includes:
[0020] The number of test sequences is determined based on the number of information bits, using the quantity calculation formula.
[0021] The formula for calculating the quantity is: N=2 w In the formula, N is the number of test sequences, and W is the number of bits of information.
[0022] Optionally, determining the maximum signal value in each test sequence based on the value range includes:
[0023] Determine each signal value within the range of values;
[0024] Each signal value is taken as the maximum signal value of the corresponding test sequence.
[0025] Optionally, the step of constructing each test sequence based on the maximum signal value in each test sequence to obtain the initial value of the test vector includes:
[0026] Combining computer traversal logic, all signal values corresponding to each test sequence are determined based on the value range and the maximum signal value in each test sequence;
[0027] Each test sequence is constructed based on all signal values corresponding to each test sequence, and the initial value of the test vector is obtained.
[0028] Optionally, to avoid adhesion and triggering faults, the initial value is expanded to obtain the target code corresponding to the test vector, including:
[0029] The maximum value of the signal corresponding to each test sequence is inserted between every two signal values in the corresponding test sequence to expand the initial value;
[0030] The expanded initial values in each test sequence are combined to obtain the target code system corresponding to the test vector.
[0031] Secondly, embodiments of this application provide an apparatus for generating test vectors for sequential logic units, comprising:
[0032] The first determining module is used to determine the number of information bits corresponding to the test vector;
[0033] The second determining module is used to determine the value range of the test vector based on the number of information bits;
[0034] The third determining module is used to determine the initial value of the test vector based on the value range;
[0035] An extension module is used to extend the initial value to obtain the target code system corresponding to the test vector, with the goal of avoiding sticking and triggering faults;
[0036] The generation module is used to generate the test vector based on the target code.
[0037] Thirdly, embodiments of this application provide a state machine, including:
[0038] Memory, used to store computer programs;
[0039] A processor, configured to implement the steps of the method for generating test vectors for sequential logic units as described above when executing the computer program.
[0040] Fourthly, embodiments of this application provide a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method for generating test vectors of sequential logic units as described above.
[0041] As can be seen from the above technical solutions, compared with the prior art, this application has the following advantages:
[0042] This application provides a method for generating test vectors for sequential logic units. First, it determines the number of information bits corresponding to the test vector and then determines the value range of the test vector based on the number of information bits. Next, it determines the initial value of the test vector based on the value range. Finally, aiming to avoid sticking and trigger-type faults, the initial value is expanded to obtain the target code system corresponding to the test vector, and the test vector is generated based on the target code system. Thus, by expanding the initial value of the test vector, the test vector based on the target code system can comprehensively cover all pre- and post-flip-flop operating conditions and state transitions, improving the comprehensiveness of the test vector. Attached Figure Description
[0043] Figure 1A flowchart illustrating a method for generating test vectors for sequential logic units, provided in an embodiment of this application;
[0044] Figure 2 A schematic diagram illustrating the alternating characteristics of a sequence provided in an embodiment of this application;
[0045] Figure 3 A schematic diagram of a device for generating test vectors for a sequential logic unit provided in an embodiment of this application;
[0046] Figure 4 This is a schematic diagram of a state machine design provided in an embodiment of this application. Detailed Implementation
[0047] As mentioned earlier, existing technologies suffer from insufficient comprehensiveness in generating test vectors. Specifically, while existing technologies consider the correctness of transmission from the D terminal to the Q terminal of the D flip-flop when generating test vectors, this combination of zeroing and setting Gray codes alone cannot simulate all the pre-flip-flop states. For example, in some asynchronous and synchronous reset flip-flops, the RN is immediately set to zero when enabled. However, if the RN is canceled from reset, the zeroing effect only disappears and the value sampled by the data port is transmitted when the rising edge of the clock arrives. In this case, the test vectors generated by existing technologies cannot meet the testing requirements. In terms of test coverage, existing methods only consider the correctness of transmission from the D terminal to the Q terminal of the D flip-flop, setting the Q port to zero and one by inputting the test vector to the D port. They do not consider the zeroing and setting of data stored or controlled internally by control ports such as set and reset ports or other data paths, thus leading to insufficient comprehensiveness of the test vectors.
[0048] To address the aforementioned issues, this application provides a method for generating test vectors for sequential logic units, comprising: first, determining the number of information bits corresponding to the test vector, and then determining the value range of the test vector based on the number of information bits; then, determining the initial value of the test vector based on the value range; and finally, expanding the initial value to avoid sticking and triggering faults, obtaining the target code system corresponding to the test vector, and generating the test vector based on the target code system.
[0049] In this way, by expanding the initial value of the test vector, the test vector based on the target code can fully cover all the pre- and post-flip-flop operating conditions and state transitions, thus improving the comprehensiveness of the test vector.
[0050] It should be noted that the method for generating test vectors for sequential logic units and related products provided in this application can be applied to the field of chip manufacturing technology. The above are merely examples and do not limit the application areas of the method for generating test vectors for sequential logic units and related products provided in this application.
[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0052] Figure 1 This is a flowchart illustrating a method for generating test vectors for sequential logic units, as provided in an embodiment of this application. (Combined with...) Figure 1 As shown, the method for generating the test vector of the sequential logic unit may include:
[0053] S101: Determine the number of bits of information corresponding to the test vector.
[0054] In practical applications, the first step is to determine the number of bits in the signal (test vector) to be loaded. A bit is the smallest unit of information in a calculator, representing a binary digit. The number of bits in a test vector indicates the number of bits it contains. For example, if a test vector has 3 bits (the number of bits in a binary digit is 3), then the number of bits in the test vector is 3.
[0055] Furthermore, since the methods for determining the number of information bits are not entirely the same, this application embodiment can describe one possible determination method.
[0056] In one case, S101: Determine the number of information bits corresponding to the test vector, which may specifically include:
[0057] Determine the number of non-clock input ports corresponding to the target sequential logic unit;
[0058] The number of non-clock input ports determines the number of information bits corresponding to the test vector, and the number of non-clock input ports is the same as the number of information bits corresponding to the test vector.
[0059] In practical applications, the number of bits in the test vector is related to the input ports of the flip-flop (target sequential logic unit). It's understandable that the generated test vector is still contained within the same clock sampling point, and the system loads signals onto all input ports of the flip-flop except for the Clock input. Therefore, the number of bits in the test vector should correspond to the other input ports of the flip-flop besides the Clock input port. Specifically, taking a scan D flip-flop with a reset bit as an example, it contains SE, SI, SN, RN, D, and E inputs, i.e., six non-clock input ports. The signal waiting to be loaded (test vector) should then have 6 bits, corresponding to these six ports: SE, SI, SN, RN, D, and E. It's understandable that the number of bits in the test vector should be the same as the number of non-clock input ports corresponding to the target sequential logic unit. Therefore, the number of bits in the test vector can be determined based on the number of non-clock input ports corresponding to the target sequential logic unit.
[0060] S102: Determine the value range of the test vector based on the number of information bits.
[0061] In practical applications, continuing with the example of a 6-bit test vector, which corresponds to the six ports SE, SI, SN, RN, D, and E, the value range of the test vector, represented in binary, is 6'b000000 to 6'b111111, and in decimal, it ranges from 0 to 63. It should be noted that in practical applications, the example is not the only possibility; the test vector can also correspond to other bit lengths, such as 2 bits, 3 bits, 7 bits, 8 bits, etc., without specific limitations.
[0062] S103: Determine the initial value of the test vector based on the range of values.
[0063] In practical applications, the values of test vectors cannot exceed their corresponding value range. Continuing with the explanation that test vectors are 6 bits, and the value range of a test vector is 0~63, then the value of each test vector cannot exceed 111111 (binary representation) or 63 (decimal representation). Therefore, a vector group composed of multiple values selected based on this value range can be called the initial value of the test vector corresponding to the target sequential logic unit. For example, the selected values can be 0, 1, and 2 (between 0 and 63), and the vector group (0, 1, 2) composed of multiple selected values is the initial value of the test vector. Furthermore, since the methods for determining the initial value of the test vector are not entirely the same, this application embodiment can describe one possible determination method.
[0064] In one case, S103: Determine the initial value of the test vector based on the value range, which may specifically include:
[0065] Determine the number of test sequences;
[0066] The maximum signal value in each test sequence is determined based on the range of values.
[0067] Each test sequence is constructed based on the maximum signal value in each test sequence, and the initial value of the test vector is obtained.
[0068] In practical applications, several (test) sequences can be created first. Then, each value in the sequence is used as a test vector for the trigger and input to the unit under test. All sequences are combined into a set of numbers, which is the new vector group in this embodiment, i.e., the initial value of the test vector corresponding to the target sequential logic unit. For this purpose, each sequence needs to be constructed separately. Specifically, first, the number of test sequences is determined, i.e., how many test sequences need to be constructed. Then, the maximum signal value of each test sequence is determined based on the value range. Finally, for each test sequence, the maximum signal value is extended from its corresponding maximum value to any state, i.e., "test n" traverses all states, and the initial value of the test vector is obtained. For example, in decimal form, if a test sequence has a maximum signal value of 3, then after traversal and construction, the sequence contains the values 0, 1, 2, and 3. Furthermore, the set of numbers formed by combining the signal values in each constructed test sequence is the initial value of the test vector corresponding to the target sequential logic unit. In addition, in practical applications, the example is not limited to the above; the maximum signal value may also be other values, such as 2, 4, etc., without specific limitations.
[0069] It is understandable that determining the maximum value of the signal is necessary to expand to any state, thereby traversing all states and obtaining the initial value of the test vector. The maximum value of the signal can be any value within its range.
[0070] Furthermore, since there are different ways to determine the number of test sequences, this application embodiment can describe one possible determination method.
[0071] In one case, determining the number of test sequences includes:
[0072] The number of test sequences is determined based on the number of information bits, using the quantity calculation formula.
[0073] The formula for calculating the quantity is: N=2 w In the formula, N is the number of test sequences, and W is the number of bits of information.
[0074] In practical applications, the number of test sequences and the number of bits of information corresponding to the test vector satisfy the formula "N=2". w Taking a test vector requiring 3 bits as an example, with W equal to 3, the number of test sequences can be calculated using the formula, resulting in 8 sequences. It should be noted that in practical applications, the example is not the only one; test vectors can correspond to other bit lengths, such as 2 bits, 4 bits, 6 bits, 7 bits, 8 bits, etc., without specific limitations.
[0075] In one case, since the methods for determining the maximum value of the signal in each test sequence are not entirely the same, the embodiments of this application can describe one possible determination method.
[0076] In one case, determining the maximum signal value in each test sequence based on the value range includes:
[0077] Determine each signal value within the range of values;
[0078] Each signal value is taken as the maximum signal value of the corresponding test sequence.
[0079] In practical applications, continuing with the example of a 3-bit test vector, the value range of the test vector, represented in binary, is 000~111. For ease of explanation, in decimal representation, the test vector values (signal values) include 0, 1, 2, 3, 4, 5, 6, and 7. Furthermore, each signal value can be considered as the maximum value in a test sequence. It's understandable that defining the maximum value in each test sequence allows for rapid traversal to determine all signal values contained in each sequence.
[0080] Furthermore, since there are different ways to determine the initial value of the test vector, this application embodiment can describe one possible determination method.
[0081] In one case, constructing the test sequences based on the maximum signal values in each test sequence to obtain the initial values of the test vector includes:
[0082] Combining computer traversal logic, all signal values corresponding to each test sequence are determined based on the value range and the maximum signal value in each test sequence;
[0083] Each test sequence is constructed based on all signal values corresponding to each test sequence, and the initial value of the test vector is obtained.
[0084] In practical applications, continuing with the example of a 3-bit test vector, and representing it in decimal form, if the maximum signal value of a test sequence is 0, then all signal values it contains are 0; if the maximum signal value of a test sequence is 1, then all signal values it contains are 0 and 1; if the maximum signal value of a test sequence is 2, then all signal values it contains are 0, 1, and 2. And so on. Combined with computer traversal logic, the total signal values corresponding to each test sequence can be determined by the maximum signal value in each test sequence and the range of values for the test vector. At this point, all signal values under each test sequence constitute the test sequence itself, and the set of numbers formed by combining the signal values in each test sequence is the initial value of the test vector corresponding to the target sequential logic unit.
[0085] S104: To avoid adhesion and triggering faults, the initial value is expanded to obtain the target code corresponding to the test vector.
[0086] In practical applications, the test vector value, besides implementing the "state-to-state" logic by extending the setting from the original "D set to 1 and D set to 0" to any state and "test n" traversing all states, also needs to avoid sticking and triggering faults caused by previous states. This means that "test n" should not only set the bit to 1 or 0 at the previous moment, but should test any state before and after it, ensuring that any vector appears once before and once after any other vector. Therefore, to avoid sticking and triggering faults, the initial value needs to be expanded to obtain the target code system corresponding to the test vector, and then the test vector for the sequential logic unit is obtained based on the target code system.
[0087] Furthermore, since the methods for determining the target code system corresponding to the test vector are not entirely the same, this application embodiment can describe one possible determination method.
[0088] In one scenario, S104: With the goal of avoiding adhesion and trigger-type faults, the initial value is expanded to obtain the target code corresponding to the test vector, which may specifically include:
[0089] The maximum value of the signal corresponding to each test sequence is inserted between every two signal values in the corresponding test sequence to expand the initial value;
[0090] The expanded initial values in each test sequence are combined to obtain the target code system corresponding to the test vector.
[0091] Furthermore, the target code system is a digital encoding code system;
[0092] In the target code system, any numeric value can appear once before and once after other numeric values.
[0093] Specifically, a set of initial values can be defined based on each natural number, and then the initial values can be expanded into a corresponding sequence, and the sequence can be synthesized into a complete digital encoding code system.
[0094] In practical applications, simply adding other states before and after each state may double the amount of data generated for the test vector, and a large number of state changes may result in repetition. Therefore, this embodiment alternates between setting and testing, allowing the larger vector to cover some cases that have appeared in the smaller vector, thus reducing redundancy while ensuring that any state appears once before or after the test state. Continuing with the example of a 3-bit test vector, represented in decimal, there are 8 sequences. Without expansion, each sequence contains the signal values 0, 0, 1; 0, 1, 2; 0, 1, 2, 3; 0, 1, 2, 3, 4; 0, 1, 2, 3, 4, 5; 0, 1, 2, 3, 4, 5; 0, 1, 2, 3, 4, 5, 6; and 0, 1, 2, 3, 4, 5, 6, 7. Thus, combining the design principles described above, each permuted and expanded test sequence has 2d+1 signal values (where d is the maximum signal value of each test vector, d≠0, d=1,2,…,7). Each test sequence contains the following signal values: d, d, d-1, d, d-2, d, d-3,…, d,2, d,1, d,0. When d=0, the test sequence contains three signal values: 0,0,0. Therefore, we can first arrange all signal values in each test sequence in descending order, and then, based on the arranged test sequences, insert the maximum signal value corresponding to each test sequence between every two signal values in the corresponding test sequence. This allows for alternating setting and testing, and the larger vector covers some cases that have occurred in the smaller vector, achieving weight reduction. Specifically, the test sequence corresponding to d=0, after permutation and expansion, contains signal values of 0,0,0, indicating that the 3 bits of the three consecutive test vectors in this test sequence are all 0, so that vector 3'b000 appears once before and once after 3'b000 (in fact, two consecutive 3'b000s are enough to make 3'b000 appear once before and once after 3'b000; the extra one is the initial state of the state machine, used for the zeroing operation). The second test sequence (d=1), after permutation and expansion, contains signal values of 1,1,0, indicating that the three consecutive test vectors are 3'b1, 3'b1, and 3'b0. This makes the first 3'b1 appear once before the second 3'b1, and the second 3'b1 appear once after the first 3'b1. In addition, the first 3'b1 appears once after 3'b0 in the previous sequence, and the second 3'b1 appears once before 3'b0 in this sequence.The subsequent arrangement and expansion of the test sequences follow the same principle. Each arranged and expanded test sequence is arranged in ascending order of its corresponding signal maximum value. The combination of signal values from each arranged and expanded test sequence forms a set of numbers (000110221203323130…776757473727170), which is the target code for the test vector corresponding to the target sequential logic unit. This target code can simulate various pre- and post-states of the flip-flop, ensuring 100% coverage of all flip-flop operating conditions and state transitions. Therefore, after selecting the target code as "pre- and post-traversal code," test vectors for the sequential logic unit can be generated. Figure 2 This is a schematic diagram illustrating the alternating characteristics of a sequence, as provided in an embodiment of this application. (Combined with...) Figure 2 As shown, the larger numerical sequence "22120 (signal values contained in the test sequence d=2 after permutation and expansion)" is used for illustration. In this sequence, the first 3'b010 appears once before the second 3'b010, and the second 3'b010 appears once after the first 3'b010; 3'b010 appears once before and once after 3'b001 in this sequence; the first 3'b010 appears once after 3'b0 in the previous sequence, and the third 3'b010 appears once before 3'b0 in this sequence. Thus, this embodiment considers all possible cases in the trigger truth table and uses the minimum number of test vectors, improving test coverage to 100% while ensuring maximum engineering efficiency. The improved test vectors obtained through the above method can be applied to more advanced process nodes and more complex sequential logic unit tests.
[0095] S105: Generate the test vector based on the target code.
[0096] In practical applications, each signal value in the target code obtained through the above steps is a test vector. It can be understood that the target code specifies the timing and specific values of the test vectors input to the unit under test. Continuing with the example of 6 information bits, the target code obtained through the above steps is “000110221203323130…776757473727170”. The generated test vectors for the input unit under test are then 0, 0, 1, 1, 0, 2, 2, 1, 2, 0, 3, 3, 2, 3, 1, 3, 0…7, 7, 6, 7, 5, 7, 4, 7, 3, 7, 2, 7, 1, 7, 0. It should be noted that in practical applications, the example is not the only one; the test vectors can also correspond to other information bit lengths, such as 2 bits, 4 bits, 7 bits, 8 bits, etc., without specific limitations.
[0097] In summary, the method for generating a code system for test vectors of sequential logic units provided in this application first determines the number of information bits corresponding to the test vector, and then determines the value range of the test vector based on the number of information bits. Next, the initial value of the test vector is determined in conjunction with the value range. Finally, with the goal of avoiding sticking and trigger-type faults, the initial value is expanded to obtain the target code system corresponding to the test vector, and the test vector is generated based on the target code system. Thus, by expanding the initial value of the test vector, the test vector based on the target code system can comprehensively cover all pre- and post-flip-flop operating conditions and state transitions, improving the comprehensiveness of the test vector.
[0098] Figure 3 This is a schematic diagram of a device for generating a code system for test vectors of sequential logic units, provided in an embodiment of this application. (Combined with...) Figure 3 As shown, the code generation device 300 for the test vector of sequential logic units may include:
[0099] The first determining module 301 is used to determine the number of information bits corresponding to the test vector;
[0100] The second determining module 302 is used to determine the value range of the test vector based on the number of information bits;
[0101] The third determining module 303 is used to determine the initial value of the test vector in combination with the value range;
[0102] Extension module 304 is used to extend the initial value with the goal of avoiding adhesion and triggering faults, so as to obtain the target code system corresponding to the test vector;
[0103] The generation module 305 is used to generate the test vector based on the target code.
[0104] As one implementation method, regarding how to determine the number of information bits corresponding to the test vector, the first determining module 301 is specifically used for:
[0105] Determine the number of non-clock input ports corresponding to the target sequential logic unit;
[0106] The number of non-clock input ports determines the number of information bits corresponding to the test vector, and the number of non-clock input ports is the same as the number of information bits corresponding to the test vector.
[0107] As one implementation method, the third determining module 303 mentioned above may specifically include: a first determining submodule, a second determining submodule, and a construction module, regarding how to determine the initial value of the test vector by combining the value range;
[0108] The first determining submodule is used to determine the number of test sequences;
[0109] The second determining submodule is used to determine the maximum value of the signal in each test sequence based on the value range;
[0110] A construction module is used to construct each test sequence based on the maximum signal value in each test sequence, thereby obtaining the initial value of the test vector.
[0111] As one implementation method, regarding how to determine the number of test sequences, the aforementioned first determining submodule is specifically used for:
[0112] The number of test sequences is determined based on the number of information bits, using the quantity calculation formula.
[0113] The formula for calculating the quantity is: N=2 w In the formula, N is the number of test sequences, and W is the number of bits of information.
[0114] As one implementation method, regarding how to determine the maximum signal value in each test sequence based on the value range, the aforementioned second determining submodule is specifically used for:
[0115] Determine each signal value within the range of values;
[0116] Each signal value is taken as the maximum signal value of the corresponding test sequence.
[0117] As one implementation method, regarding how to construct each test sequence based on the maximum signal value in each test sequence and obtain the initial value of the test vector, the aforementioned construction module is specifically used for:
[0118] Combining computer traversal logic, all signal values corresponding to each test sequence are determined based on the value range and the maximum signal value in each test sequence;
[0119] Each test sequence is constructed based on all signal values corresponding to each test sequence, and the initial value of the test vector is obtained.
[0120] As one implementation method, with the goal of avoiding adhesion and triggering failures, the initial values are arranged and expanded. Specifically, the expansion module 304 is used for:
[0121] The maximum value of the signal corresponding to each test sequence is inserted between every two signal values in the corresponding test sequence to expand the initial value;
[0122] The expanded initial values in each test sequence are combined to obtain the target code system corresponding to the test vector.
[0123] Furthermore, the target code system is a digital encoding code system;
[0124] In the target code system, any numeric value can appear once before and once after other numeric values.
[0125] Specifically, a set of initial values can be defined based on each natural number, and then the initial values can be expanded into a corresponding sequence, and the sequence can be synthesized into a complete digital encoding code system.
[0126] In summary, this application first determines the number of information bits corresponding to the test vector and then determines the value range of the test vector based on the number of information bits. Next, it determines the initial value of the test vector based on the value range. Finally, aiming to avoid sticking and trigger-type faults, the initial value is expanded to obtain the target code system corresponding to the test vector, and the test vector is generated based on the target code system. Thus, by expanding the initial value of the test vector, the test vector based on the target code system can comprehensively cover all pre- and post-flip-flop operating conditions and state transitions, improving the comprehensiveness of the test vector.
[0127] In addition, embodiments of this application also provide a state machine, including:
[0128] Memory, used to store computer programs;
[0129] A processor, configured to implement the steps of the method for generating test vectors for sequential logic units as described above when executing the computer program.
[0130] Figure 4 This is a schematic diagram of a state machine design provided for an embodiment of this application. (In conjunction with...) Figure 4 As shown, this state machine is a Mealy state machine, where the part before the " / " symbol represents two conditional statements, and the part after the " / " symbol represents four outputs of the state. `$width` represents the bit width of the test vector, `$depth` represents the maximum natural number depth of the test sequence, `$type` represents the identifier for the device under test group with the same number of ports to match vector groups of different lengths, `array` represents the natural number (i.e., the maximum signal value `d`) on which the current test sequence is based, `counter` acts as a counter to record whether each test sequence gradually decreases from a natural number to 0, `vector` is the output test vector, and `flag` is the flag signal generated when all test sequences corresponding to the current values of `d` have been generated (active high). In the state transition diagram, `a` and `c` refer to the current state's `array` and `counter`, respectively. Figure 4In the code, `next_a` and `next_c` represent the `array` and `counter` values for the next cycle of the current state's output. `array` and `counter` are the values from the previous state's input for the current state's cycle. This design uses parameterization to achieve length matching and precise generation of vector groups. When designing test chips using different standard cell libraries, the code supports modifications to `width`, `depth`, and `type` without needing to redesign the state machine and test vectors; only the parameters in the design need to be updated, greatly saving design resources and effectively improving design efficiency. For any standard cell library, as long as the type of sequential logic units and the number of ports do not change significantly, the test vector generation module can be maintained without any changes. When the number of input ports is the same, test vector bitlines can be shared to reduce the amount of design code. Furthermore, due to the small changes in module parameterization, synthesis efficiency can be improved, further enhancing design efficiency. This design is also easier to maintain and port RTL and synthesis scripts.
[0131] In addition to designing classification and matching logic to ensure accurate bit width during test vector generation, control signals must be designed before the state machine is started. These signals control the state machine to return to zero or not start when it is in various test or state states, such as non-sequential logic testing, manual testing, completion of a round of DTD testing, port number mismatch, or end of a test cycle, in order to reduce power consumption. The signals indicating whether a sequential logic unit is currently being tested and those representing the current manual testing state are externally sourced signals. The signals representing the completion of a round of DTD testing and the end of a test cycle can be generated by the module itself. The logic for port number mismatch is a comparator logic, and the state machine is activated based on the update of the external parameter $type.
[0132] In addition, this application embodiment also provides a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method for generating test vectors of sequential logic units as described above.
[0133] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for generating test vectors for sequential logic units, characterized in that, The generation method includes: Determine the number of bits of information corresponding to the test vector; The range of values for the test vector is determined based on the number of bits of information. The initial value of the test vector is determined based on the range of values. To avoid adhesion and triggering faults, the initial value is expanded to obtain the target code system corresponding to the test vector; The test vector is generated based on the target code.
2. The generation method according to claim 1, characterized in that, Determining the number of information bits corresponding to the test vector includes: Determine the number of non-clock input ports corresponding to the target sequential logic unit; The number of non-clock input ports determines the number of information bits corresponding to the test vector, and the number of non-clock input ports is the same as the number of information bits corresponding to the test vector.
3. The generation method according to claim 1, characterized in that, Determining the initial value of the test vector based on the aforementioned value range includes: Determine the number of test sequences; The maximum signal value in each test sequence is determined based on the range of values. Each test sequence is constructed based on the maximum signal value in each test sequence, and the initial value of the test vector is obtained.
4. The generation method according to claim 3, characterized in that, Determining the number of test sequences includes: The number of test sequences is determined based on the number of information bits, using the quantity calculation formula. The formula for calculating the quantity is: N=2 w In the formula, N is the number of test sequences, and W is the number of bits of information.
5. The generation method according to claim 3, characterized in that, Determining the maximum signal value in each test sequence based on the value range includes: Determine each signal value within the range of values; Each signal value is taken as the maximum signal value of the corresponding test sequence.
6. The generation method according to claim 3, characterized in that, The process of constructing each test sequence based on the maximum signal value in each test sequence to obtain the initial value of the test vector includes: Combining computer traversal logic, all signal values corresponding to each test sequence are determined based on the value range and the maximum signal value in each test sequence; Each test sequence is constructed based on all signal values corresponding to each test sequence, and the initial value of the test vector is obtained.
7. The generation method according to claim 6, characterized in that, To avoid adhesion and triggering faults, the initial value is expanded to obtain the target code system corresponding to the test vector, including: The maximum value of the signal corresponding to each test sequence is inserted between every two signal values in the corresponding test sequence to expand the initial value; The expanded initial values in each test sequence are combined to obtain the target code system corresponding to the test vector.
8. The method according to claim 1, characterized in that, The target code system is a digital encoding code system; In the target code system, any numeric value can appear once before and once after other numeric values.
9. A device for generating test vectors for sequential logic units, characterized in that, include: The first determining module is used to determine the number of information bits corresponding to the test vector; The second determining module is used to determine the value range of the test vector based on the number of information bits; The third determining module is used to determine the initial value of the test vector based on the value range; An extension module is used to extend the initial value to obtain the target code system corresponding to the test vector, with the goal of avoiding sticking and triggering faults; The generation module is used to generate the test vector based on the target code.
10. A state machine, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the method for generating test vectors of sequential logic units as described in any one of claims 1 to 8 when executing the computer program.
11. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for generating test vectors of sequential logic units as described in any one of claims 1 to 8.