Implementation method of ethernet card based on eMMC bus interface and ethernet card

Abstract

The application provides an implementation method of an Ethernet card based on an eMMC bus interface and the Ethernet card, and belongs to the technical field of Ethernet, and comprises the following steps: constructing a state machine scheduler based on device driver software, initializing the eMMC Ethernet card, entering a waiting interrupt state when sending and receiving are idle, and exiting the waiting interrupt state and performing Ethernet frame block reading when an interrupt trigger is received; during scheduling, based on block transmission of the eMMC bus, using a pre-constructed special transmission data format of the Ethernet frame adapted to the eMMC bus, aggregating and transmitting one or more Ethernet data packets, and multiplexing a reserved command of the eMMC bus to read and write a configuration of an internal register of the Ethernet card. The beneficial effect is that approximate full-duplex transmission balanced scheduling of the half-duplex eMMC bus is realized, the problem of incompatibility between the eMMC format and the Ethernet frame transmission is solved, and the bus reserved command is multiplexed to realize register reading and writing.

Description

Technical Field

[0001] This invention relates to the field of Ethernet technology, and in particular to an implementation method and an Ethernet card based on an eMMC bus interface. Background Technology

[0002] Ethernet cards, as components that enable wired network access for devices, are widely used in various electronic devices such as personal computers (PCs), laptops, customer premises equipment (CPE), smart TVs, and industrial control equipment. Currently, Ethernet cards typically use Peripheral Component Interconnect Express (PCIe) or Universal Serial Bus (USB) interfaces to achieve data exchange with the host.

[0003] In areas with relatively low population density, mobile access is an efficient way to achieve home internet access. The Customer Premises Equipment (CPE), as the core network terminal in this scenario, connects to the wide area network (WAN) via 4G, 5G, or other mobile communication standards at its front end, and provides network services to intranet devices at its back end via WiFi and Ethernet interfaces. These CPE devices typically use cost-effective mobile communication processing chips. These chips generally suffer from a limited number of high-speed expansion interfaces, or even lack a standard Ethernet interface, and their built-in embedded Multi Media Card (eMMC) bus interface is only designed for storage devices.

[0004] However, the embedded multimedia card (eMMC) bus is designed for storage device applications from the protocol level. It supports half-duplex communication mode and specifies the reading and writing of internal registers of the memory. Its protocol architecture, communication mechanism and transmission characteristics are incompatible with the data interaction requirements of Ethernet. It does not have the ability to directly connect to Ethernet cards, making it difficult to implement Ethernet cards through the embedded multimedia card (eMMC) bus interface. Summary of the Invention

[0005] To address the above technical problems, this invention provides a method for implementing an Ethernet card based on an eMMC bus interface; on the other hand, it also provides an Ethernet card based on an eMMC bus interface.

[0006] The technical problem solved by this invention can be achieved by the following technical solution: A method for implementing an Ethernet card based on an eMMC bus interface, comprising: constructing a state machine scheduler based on device driver software, initializing the Ethernet card based on the eMMC bus interface, entering a waiting interrupt state when both transmission and reception are idle, and exiting the waiting interrupt state and performing Ethernet frame block reading when a reception interrupt is triggered, thereby achieving near full-duplex transmit and receive balanced scheduling for the half-duplex eMMC bus; during scheduling, block transmission based on the eMMC bus adopts a pre-built dedicated transmission data format for Ethernet frames adapted to the eMMC bus, aggregating and transmitting one or more Ethernet data packets, and reusing reserved commands of the eMMC bus to read and write configurations of the Ethernet card's internal registers.

[0007] The implementation method of the Ethernet card based on the eMMC bus interface described in this invention, wherein the state machine scheduler built based on the device driver software includes: Step A1, loading the device driver software, reusing the reserved commands of the eMMC bus to read and write configurations of the internal registers of the Ethernet card to initialize the Ethernet card, and reporting a receive idle event to the power management arbitration module; Step A2, starting a transmit idle software timer of preset duration, according to the packet sending requirements of the operating system, transmitting the Ethernet data packets to be sent via the eMMC bus in a pre-built dedicated transmission data format adapted to the eMMC bus, until the preset termination condition is met, and terminating the transmission, and reporting to the power management arbitration module. The management arbitration module reports a transmit idle event; Step A3: When both the receive idle event and the transmit idle event are detected simultaneously, the system enters a wait-for-interrupt state; Step A4: When a network data receive interruption is detected, the system exits the interrupt wait state, reads the interrupt status register to determine the interrupt type, and if the interrupt type is a receive interrupt, the system enters the receive state, reads the receive frame count register to obtain the number of aggregated packets received during this interruption, reports an exit-for-receive idle event to the power management arbitration module, and reads the aggregated packets encapsulated in the Ethernet frame dedicated transmission data format adapted to the eMMC bus through the eMMC bus block read command, parses them into the operating system adapted format, and submits them to the operating system.

[0008] The Ethernet card implementation method based on the eMMC bus interface described in this invention has a preset termination condition where the remaining amount of the first-in-first-out transmission is less than the maximum length of a single Ethernet packet or the idle software timer for transmission times out.

[0009] The implementation method of the Ethernet card based on the eMMC bus interface described in this invention includes a dedicated transmission data format for Ethernet frames adapted to the eMMC bus, comprising a transmit frame header and a receive frame trailer. The transmit frame header consists of 16 bytes, including an 8-byte command descriptor and an 8-byte transmit descriptor, used to describe the slots and associated parameters of the Ethernet data packets for the device driver software. The receive frame trailer is a 16-byte receive descriptor used to carry the parsing results of the received Ethernet data packets by the media access control module.

[0010] The method for implementing an Ethernet card based on an eMMC bus interface according to the present invention includes, in which the command descriptor comprises one or more combinations of fields such as inner VLAN tag, outer VLAN tag, maximum transmission control protocol segment size, valid bits of inner VLAN tag, valid bits of VLAN tag, and valid bits of maximum transmission control protocol segment size; and in which the transmit descriptor comprises one or more combinations of fields such as VLAN tag insertion enable bit, cyclic redundancy check padding enable bit, transmission control protocol segment offload enable bit, Internet Protocol version checksum enable bit, Layer 4 checksum enable bit, frame length, and frame header length.

[0011] The method for implementing an Ethernet card based on an eMMC bus interface according to the present invention includes, in which the receive descriptor comprises one or more combinations of fields such as inner VLAN tag, outer VLAN tag, opcode, payload type, third-layer type, Internet Protocol checksum, Internet Protocol payload error, cyclic redundancy check error, frame header length, and packet length.

[0012] The method for implementing an Ethernet card based on an eMMC bus interface according to the present invention includes at least a first reserved command, a second reserved command, and a third reserved command in the reserved commands of the eMMC bus. The first reserved command is configured to write the address of the register to be operated to the target register address cache unit of the bridging module; the second reserved command is configured to read the register data pointed to by the target register address cache unit; and the third reserved command is configured to carry the data to be written and write it to the register pointed to by the target register address cache unit. The multiplexing of the eMMC bus reserved commands to configure read / write operations on the internal registers of the Ethernet card includes: when the device driver software reads a register, it writes the address of the target register to the target register address cache unit through the first reserved command; the bridging module responds to the second reserved command by reading the register whose address is stored in the target register address cache unit and returning the read data as a response to the second reserved command to the host; when the device driver software writes a register, it writes the address of the target register to the target register address cache unit through the first reserved command and carries the data to be written through the third reserved command; the bridging module responds to the third reserved command by writing the data to be written carried by the third reserved command to the register whose address is stored in the target register address cache unit.

[0013] On the other hand, an Ethernet card based on an eMMC bus interface includes a first interface module, a controller module, a bridge module, a media access control module, and a second interface module connected in sequence; wherein, the first interface module interacts with the host based on the eMMC bus interface; the second interface module is used to access the network; the bridge module is used to implement the above-described implementation method of the Ethernet card based on the eMMC bus interface, and interacts with the controller module and the media access control module.

[0014] The Ethernet card based on the eMMC bus interface of the present invention includes a second interface module comprising: a high-speed serial-to-parallel conversion interface, wherein the high-speed serial-to-parallel conversion interface is connected to an external Ethernet physical layer chip or optical module based on a serial gigabit media independent interface.

[0015] The Ethernet card based on the eMMC bus interface described in this invention further includes an Ethernet physical layer in its second interface module, wherein the Ethernet physical layer accesses a wired network via an Ethernet cable.

[0016] The advantages or beneficial effects of the technical solution of this invention are as follows: This invention initializes the eMMC bus interface Ethernet card through a state machine scheduler built based on device driver software. When both transmission and reception are idle, the device is controlled to enter a waiting interrupt state. When a reception interrupt is triggered, the device exits the waiting interrupt state and performs Ethernet frame block reading, thereby achieving near full-duplex transmit and receive balanced scheduling of the half-duplex eMMC bus, avoiding transmit and receive blocking, and ensuring transmission stability. During scheduling, based on the block transmission mechanism of the eMMC bus, a pre-built dedicated transmission data format for Ethernet frames adapted to the eMMC bus is used to aggregate and transmit one or more Ethernet data packets, solving the problem of incompatibility between the native eMMC format and Ethernet frame transmission, improving data transmission efficiency. At the same time, the reserved commands of the eMMC bus are reused to read and write the internal registers of the Ethernet card for configuration, without modifying the underlying eMMC protocol or adding an additional high-speed interface, simplifying the hardware design and configuration process, reducing implementation costs, and breaking through the bottleneck of the eMMC bus interface being unable to be used as an Ethernet card interface due to its half-duplex characteristics and native storage design in the prior art, filling the gap in the existing market for Ethernet cards without an eMMC bus interface. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an Ethernet card based on an embedded multimedia card bus interface in a preferred embodiment 1 of the present invention; Figure 2 This is a flowchart illustrating a preferred embodiment of the present invention for implementing an Ethernet card based on an eMMC bus interface. Figure 3 This is a flowchart illustrating the device driver software state machine scheduler in a preferred embodiment of the present invention. Figure 4 This is a schematic diagram of the data packet format on the embedded multimedia card bus interface in a preferred embodiment of the present invention. Figure 5 This is a schematic diagram of the format of the transmitted frame header and the received frame trailer in a preferred embodiment of the present invention; Figure 5 In the image, (a) shows the format of a single packet data being sent, and (b) shows the format of a single packet data being received. Figure 6 This is a schematic diagram of the structure of an Ethernet card based on an embedded multimedia card bus interface in a preferred embodiment 2 of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0021] The purpose of this invention is to address the technical shortcomings of existing embedded multimedia card (eMMC) bus interfaces, which are inherently designed for storage and only support half-duplex communication, thus preventing them from being directly used as Ethernet card interfaces. This invention provides an Ethernet card based on the eMMC bus interface and its implementation method. Utilizing existing eMMC bus resources, through innovative data format design, register read / write schemes, and transmit / receive scheduling mechanisms, the eMMC bus interface can meet the various technical specifications of Ethernet access. This provides a compatible Ethernet card for cost-effective customer premises equipment (CPE) solutions, filling the gap in the existing market for Ethernet cards without eMMC bus interfaces.

[0022] like Figure 1 The diagram shown is a structural schematic of an Ethernet card based on an eMMC bus interface in a preferred embodiment of the present invention. The Ethernet card includes a first interface module 10, a controller module 20, a bridge module 30, a medium access control (MAC) module 40, and a second interface module 50, which are electrically connected in sequence. The modules work together to realize the transmission and reception of Ethernet data and interaction with the host.

[0023] Specifically, the first interface module 10 is an eMMC bus interface module, which follows the eMMC protocol specification and operates at a 1.8V analog input / output (IO) level. It is used to establish a communication connection with the host's eMMC interface to realize data interaction, command transmission and control signal interaction between the host and the Ethernet card.

[0024] The host is an electronic device with an eMMC bus interface, preferably a customer premises equipment (CPE). Such CPE devices typically use cost-effective mobile communication processing chips. These chips generally have a limited number of high-speed expansion interfaces or even lack a standard Ethernet interface. Their built-in eMMC bus interface is only designed for storage devices. The Ethernet card of this invention interfaces with the eMMC bus interface of such CPE devices through the first interface module 10. This allows for Ethernet function expansion without the need to add an additional high-speed interface, thereby improving the cost-effectiveness of the CPE device.

[0025] The controller module 20 is an eMMC controller, used to parse the eMMC commands, responses and data sent by the host through the first interface module 10, realize the timing control and data transmission management of the eMMC bus, and forward the host's control instructions to the bridge module 30, and send the data and status information fed back by the bridge module 30 back to the host.

[0026] The bridging module 30 is an embedded multimedia card to media access control bridge (eMMC to MAC Bridge), which is one of the core innovative modules of this invention to achieve eMMC bus and Ethernet protocol adaptation. It works in conjunction with the device driver software to realize the format conversion between eMMC protocol and Ethernet protocol, the parsing and execution of eMMC bus reservation commands, and the data interaction relay between the host and the media access control module 40. Specifically, the bridging module 30 can parse the eMMC bus reservation commands issued by the host, complete the read and write operations of the Ethernet card's internal control and status register (CSR), and convert the Ethernet frames received by the media access control module 40 into data formats adapted for eMMC bus transmission, or convert the adapted format data sent by the host through the eMMC bus into Ethernet frames and transmit them to the media access control module 40.

[0027] The Media Access Control (MAC) module conforms to the Ethernet protocol specification and implements functions such as Ethernet frame encapsulation, decapsulation, verification, VLAN processing, TCP segmentation (TSO), and checksum hardware offloading. Specifically, it includes CRC verification and VLAN tag insertion for sent Ethernet frames, CRC verification and frame parsing for received Ethernet frames, as well as the calculation and replacement of IP checksums and L4 checksums, reducing the load on the host CPU and improving Ethernet data transmission efficiency.

[0028] The second interface module 50 is the external network access module for the Ethernet card, used to connect the Ethernet card to an external network. For example, two implementation methods can be used: the first method is as follows... Figure 1As shown, the second interface module 50 includes a high-speed serial-to-parallel conversion interface (SERDES interface). This high-speed serial-to-parallel conversion interface connects to an external Ethernet physical layer (Ethernet PHY, EPHY) chip or optical module based on a serial gigabit media independent interface (SGMII) or a gigabit media independent interface (GMII), thereby achieving interfacing with a wired network through the external physical layer chip or optical module; the second method is as follows... Figure 6 As shown, the second interface module 50 integrates the Ethernet physical layer (EPHY), which can be directly connected to the wired network via Ethernet cable, simplifying the hardware connection structure and reducing hardware costs.

[0029] Based on the aforementioned hardware structure of the Ethernet card based on the eMMC bus interface, this embodiment also provides an implementation method for the Ethernet card based on the eMMC bus interface. This method, through the collaborative work of device driver software and hardware modules, resolves the contradiction between the half-duplex characteristic of the eMMC bus and the Ethernet transmission and reception requirements, achieving stable, efficient, and low-power Ethernet access. Figure 2 As shown, the specific steps include: building a state machine scheduler based on the device driver software. This state machine scheduler runs in the host's device driver software and serves as the core of the eMMC bus transmit and receive timing scheduling. It is used to achieve near full-duplex transmit and receive balanced scheduling of the half-duplex eMMC bus, avoid mutual blocking during transmit and receive, and at the same time achieve low-power standby to reduce system power consumption.

[0030] Specifically, such as Figure 3 As shown, the workflow of the state machine scheduler includes: First, the device driver software is loaded. By reusing the reserved commands of the eMMC bus, the device driver software reads and writes the internal control and status register (CSR) of the Ethernet card to complete the initialization operation of the Ethernet card, including the parameter configuration of the media access control module 40, the bridging module 30, the controller module 20 and the second interface module 50. At the same time, the software's internal status variables and local variables are initialized, including the transmit first-in-first-out remaining amount (fifo_tx_left) used to record the number of bytes that can be transmitted. The software also reports a "receive idle" event to the power management arbitration module implemented by the device driver software, informing the power management arbitration module that the current receive link is in an idle state and can receive data at any time.

[0031] After initialization, the state machine scheduler starts a preset duration transmission idle software timer (preferably 100 milliseconds). Before the transmission idle software timer expires, it monitors the packet sending needs of the operating system (OS) in real time. If the operating system has Ethernet data packets to send, it aggregates one or more Ethernet data packets to be sent into an eMMC block transmission format according to a pre-built dedicated transmission data format for Ethernet frames adapted to the eMMC bus. This data is then transmitted to the media access control module 40 via the eMMC bus (first interface module 10, controller module 20, bridge module 30). The media access control module 40 then completes the subsequent frame processing and transmission operations. Simultaneously, for each Ethernet data packet sent, the length of the data packet is subtracted from the transmission first-in-first-out remaining amount (fifo_tx_left) until the transmission first-in-first-out remaining amount (fifo_tx_left) is less than the maximum length of a single Ethernet packet (MTU), or the transmission idle software timer expires. At this point, the state machine scheduler terminates the transmission operation and reports a "transmission idle" event to the power management arbitration module, releasing the timing resources of the eMMC bus and reserving time slices for the data reception process to ensure balanced transmission and reception.

[0032] When the state machine scheduler simultaneously detects both the "receive idle" and "transmit idle" events fed back by the power management arbitration module, it determines that the current eMMC bus is in an idle state. The state machine scheduler then controls the Ethernet card to enter an interrupt waiting state. At this time, the device driver software sends the eMMC command CMD40 (GO_IRQ_STATE) to the eMMC controller. After the eMMC Ethernet card responds to the command, it enters the interrupt waiting mode. If no interrupt is triggered (including transmit completion interrupt, receive interrupt, Ethernet link status interrupt, etc.), the entire system will maintain a low-power state to avoid resource consumption caused by CPU polling and reduce system power consumption.

[0033] When data is transmitted from the external network to the Ethernet card, the second interface module 50 receives the data and transmits it to the media access control module 40. After parsing the data, the media access control module 40 triggers a receive interrupt. Upon detecting this interrupt, the state machine scheduler immediately exits the wait-for-interrupt state, reads the interrupt status register inside the Ethernet card, and determines the interrupt type. If it is determined to be a receive interrupt, it enters the receive state, reads the receive frame count register (RX_FRAMES_CNT) to obtain the number of Ethernet aggregate packets received during this interruption, and reports the exit "receive idle" event to the power management arbitration module, informing the power management arbitration module that the current receive link is in working state. Subsequently, the device driver software uses the block read commands (CMD17, CMD18, CMD40) of the eMMC bus to read the aggregate packets encapsulated by the media access control module 40 in the Ethernet frame dedicated transmission data format adapted to the eMMC bus through the first interface module 10, controller module 20, and bridge module 30. After parsing the aggregate packets into the Ethernet frame format adapted to the operating system, it submits them to the operating system to complete data reception.

[0034] Throughout the state machine scheduler's transmit / receive balancing scheduling process, the block transmission mechanism based on the eMMC bus adopts a pre-built dedicated transmission data format for Ethernet frames adapted to the eMMC bus to aggregate and transmit one or more Ethernet data packets, solving the problem that the native eMMC storage format is not compatible with Ethernet frame transmission and improving data transmission efficiency.

[0035] like Figure 4 The diagram shows the data packet format on the eMMC bus. A TX transmission indicates the sending of an Ethernet data packet from the host (such as a CPE SoC) to an external Ethernet cable. For a single Ethernet data packet, its structure consists of a TX header and an Ethernet payload. When transmitting multiple Ethernet data packets, they are aggregated into a single long eMMC frame. The aggregated frame is constructed using a "TX header + Ethernet payload + padding" method. The padding bytes are used to byte-align the starting address of the next TX header, improving internal bus transmission efficiency.

[0036] The RX receiver receives data packets from the Ethernet cable and sends them back to the host. A single Ethernet packet consists of a receive frame header (RXHeader), an Ethernet payload, padding bytes, and a receive frame tail (RXTail). When transmitting multiple Ethernet packets, they can be aggregated into a single long frame, using a format of "receive frame header + Ethernet payload + padding bytes + receive frame tail" joined end-to-end. The padding bytes are used to byte-align the start address of the receive frame tail, improving internal bus transmission efficiency.

[0037] like Figure 5 The diagram shows a dedicated Ethernet frame transmission data format adapted to the embedded multimedia card (eMMC) bus. Figure 5 (a) shows the format for sending a single-packet message, used by a host (such as a CPE SoC) to send Ethernet data packets to an Ethernet card. It consists of two parts: the TX Header and the Ethernet Payload. The TX Header is located at the beginning of the data and carries the control information of the data packet. It has a total length of 24 bytes and includes a 4-byte characteristic number with a fixed value of 0xFFAA8855, a 4-byte Ethernet Payload Length field, an 8-byte Command Descriptor, and an 8-byte Send Descriptor. The Ethernet Payload follows the TX Header and is the standard Ethernet data packet content. Its length is specified by the Ethernet Payload Length field in the TX Header.

[0038] Figure 5 (b) shows the received single-packet message data format, used by the Ethernet card to transmit received Ethernet data packets to the host. It consists of four parts: the receive frame header (RX Header), the Ethernet payload, padding bytes, and the receive frame tail (RX Tail). The receive frame header (RX Header) is located at the beginning of the data and is similar to the transmit frame header. It contains two parts: a 4-byte characteristic number with a fixed value of 0xFFAA8855 and a 4-byte Ethernet payload length field, for a total length of 8 bytes. The Ethernet payload follows the transmit frame header, and its length is specified by the Ethernet payload length field in the receive frame header (RX Header). The Ethernet payload is followed by padding bytes, which are used to align the start address of the subsequent receive frame tail to the 8-byte boundary. The receive frame tail is a 16-byte receive descriptor.

[0039] The Ethernet frame-specific transmission data format adapted to the eMMC bus includes a transmit frame header and a receive frame trailer. The transmit frame header consists of 16 bytes, specifically an 8-byte command descriptor and an 8-byte transmit descriptor. The command descriptor is used by the device driver software to configure the hardware module's processing actions and associated parameters for subsequently transmitted Ethernet data packets. It includes at least the Inner VLAN Tag, Outer VLAN Tag, Transmission Control Protocol Maximum Segment Size (TCP MSS), Inner VLAN Tag Valid, VLAN Tag Valid, and Transmission Control Protocol Maximum Segment Size Valid fields (MSS Valid). The definitions of each field are shown in Table 1 below.

[0040] Table 1. Definition of 8-byte command descriptor fields in the transmit frame header

[0041] The command descriptor is used to configure the hardware's insertion of VLAN tags for subsequent data packets and the maximum TCP segment size (TCP MSS) required for TCP segment offload. Once configured, this command descriptor applies to all subsequent data packets until the device driver software issues a new command descriptor to update the parameters. A command descriptor value of zero indicates that no configuration parameter updates are currently required.

[0042] The transmit descriptor is used to inform the hardware of the specific processing requirements for the currently transmitted Ethernet packet. It includes at least the following fields: VLAN Insert Enable, CRCPadding Enable, Transmission Control Protocol Segmentation Offload Enable, IPv4 CSUM Enable, L4 CSUM Enable, FrameLength, and Header Length. The definitions of each field are shown in Table 2 below.

[0043] Table 2. Definition of 8-byte Transmit Descriptor Fields in the Transmit Frame Header

[0044] The received frame tail is a 16-byte receive descriptor, which carries the parsing results of the media access control module 40 for the received Ethernet packets. It includes at least the following fields: Inner VLAN TAG, Outer VLAN TAG, Opcode (OPC), Payload Type, Layer 3 Type, IP Checksum, IP Payload Error, Cyclic Redundancy Check Error (CRCError), Header Length, and Packet Length. The definitions of each field are shown in Table 3 below.

[0045] Table 3. Definition of the 16-byte receive descriptor field in the received frame tail.

[0046] By parsing the receive descriptor, the device driver software can obtain specific information about the received data packets and their verification status, ensuring the accuracy of data reception.

[0047] Meanwhile, to improve the transmission efficiency of the internal bus, padding is used for byte alignment when aggregating and sending multiple Ethernet packets. This ensures that the starting addresses of the headers of the sent frames and the tails of the received frames in the aggregated frame meet the byte alignment requirements, thus avoiding a decrease in transmission efficiency due to address misalignment.

[0048] During operation, device driver software often needs to read and write configurations of the internal registers of the Ethernet card, such as to implement the Wake On Lans (WLAN) function. However, because the command (COMMAND, hereinafter abbreviated as CMD) length specified by the embedded multimedia card protocol (eMMC spec) is 48 bits, it is impossible to simultaneously carry the register address and 32 bits of write data when directly writing to the device register. Therefore, this invention reuses the reserved commands (COM60~62) of the eMMC bus during scheduling and sets up a target register address cache unit (TARGET_CSR_ADDR) on the bridge module 30 to temporarily store the target register address to be operated, so as to realize indirect read and write operations of the registers and read and write configurations of the control and status registers (CSR) inside the Ethernet card. This solves the problem of the limited command length of the eMMC standard and the inability to directly carry the register address and write data, and realizes flexible configuration of the Ethernet card hardware module.

[0049] The aforementioned eMMC bus reservation commands include at least a first reservation command, a second reservation command, and a third reservation command. In this embodiment, the first reservation command is CMD60 reserved in the eMMC protocol, configured as the SET_TARGET_CSR_ADDR command, used to write the register address to be operated to the target register address cache unit (TARGET_CSR_ADDR) of the bridging module 30; the second reservation command is CMD61 reserved in the eMMC protocol, configured as the READ_TARGET_CSR command, used to read the register data pointed to by the target register address cache unit (TARGET_CSR_ADDR); and the third reservation command is CMD62 reserved in the eMMC protocol, configured as the WRITE_TARGET_CSR command, used to carry the data to be written and write it to the register pointed to by the target register address cache unit (TARGET_CSR_ADDR).

[0050] The specific parameters and functions of the three reserved commands are shown in Table 4 below.

[0051] Table 4 eMMC bus CMD60~62 register read / write

[0052] The specific register read / write process is as follows: When the device driver software needs to perform a register read operation, the first step is to write the address of the target register into the target register address cache unit (TARGET_CSR_ADDR) of the bridge module 30 through the first reserved command (CMD60); the second step is to initiate the second reserved command (CMD61). After the bridge module 30 captures the CMD61 command in real time, it reads the Ethernet card internal register whose address is stored in the target register address cache unit (TARGET_CSR_ADDR) through the internal bus (such as the Advanced High Performance Bus AHB), and returns the read data to the host as the response of the CMD61 command (R1 format, conforming to the eMMC protocol specification), thus completing the register read operation.

[0053] When the device driver software needs to perform a register write operation, it first writes the address of the target register into the target register address cache unit (TARGET_CSR_ADDR) of the bridge module 30 through the first reserved command (CMD60). Then, it carries the data to be written through the third reserved command (CMD62). After the bridge module 30 captures the CMD62 command in real time, it immediately retrieves the data to be written carried by the CMD62 command and writes the data into the Ethernet card internal register stored in the target register address cache unit (TARGET_CSR_ADDR) through the internal bus, thus completing the register write operation.

[0054] It should be noted that the first reserved command (CMD60), the second reserved command (CMD61), and the third reserved command (CMD62) mentioned above are all addressing (ac) commands specified in the eMMC protocol. This type of command is a point-to-point command, with no data transmission on the data (DAT) line. Their response format all adopts the R1 response format of the eMMC protocol standard (48 bits in length, with bits 40 to 45 being the index of the command to be responded to, and the remaining 32 bits being the device status code), ensuring compatibility with the eMMC protocol, without needing to modify the underlying protocol of the eMMC bus, thus reducing implementation costs.

[0055] The Ethernet card based on the eMMC bus interface and its implementation method of the present invention have the following beneficial effects: It can provide a compatible Ethernet card for CPE devices using cost-effective mobile communication chips, eliminating the need for additional high-speed interfaces, significantly improving the cost-effectiveness of CPE devices and filling existing market gaps; it achieves transmit / receive balance through a state machine scheduler, and uses the network performance testing tool iperf for bidirectional transmit / receive streaming tests, ensuring that the transmit / receive bandwidth difference does not exceed 20%, avoiding prolonged blocking of half-duplex transmit / receive; when there is no network traffic, the system enters a low-power waiting interrupt state, eliminating the need for continuous CPU polling and reducing system power consumption; the media access control module 40 implements hardware offloading functions such as TCP segmentation, IP / TCP / UDP checksum, VLAN insertion / stripping, and CRC filling, reducing the host CPU load; and through register read / write configuration, it can achieve the Wake On LAN function, improving the device's usability.

[0056] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A method for implementing an Ethernet card based on an eMMC bus interface, characterized in that, include: A state machine scheduler is built based on device driver software to initialize Ethernet cards based on the eMMC bus interface. When the transmission is idle and the reception is idle, the scheduler enters the interrupt waiting state and exits the interrupt waiting state when the reception interrupt is triggered, and performs Ethernet frame block reading, thereby realizing full-duplex transmit and receive balanced scheduling of the half-duplex eMMC bus. During scheduling, block transmission based on the eMMC bus uses a pre-built dedicated transmission data format for Ethernet frames adapted to the eMMC bus to aggregate and send / receive one or more Ethernet packets, and reuses reserved commands of the eMMC bus to read and write configurations of the internal registers of the Ethernet card. The state machine scheduler built based on device driver software includes: Step A1: Load the device driver software, reuse the reserved commands of the eMMC bus to read and write the internal registers of the Ethernet card to initialize the Ethernet card, and report the receive idle event to the power management arbitration module. Step A2: Start the preset duration of the transmission idle software timer. According to the packet sending requirements of the operating system, the Ethernet data packets to be sent are aggregated and transmitted via the eMMC bus according to the pre-built dedicated transmission data format for Ethernet frames adapted to the eMMC bus. The transmission is terminated when the preset termination condition is met, and the transmission idle event is reported to the power management arbitration module. Step A3: When both the receive idle event and the send idle event are detected simultaneously, enter the waiting interrupt state; Step A4: When a network data reception interruption is detected, exit the interrupt waiting state, read the interrupt status register to determine the interrupt type. If the interrupt type is a reception interrupt, enter the reception state, read the received frame count register to obtain the number of aggregated packets received during this interruption, report the exit reception idle event to the power management arbitration module, and read the aggregated packets encapsulated in the Ethernet frame dedicated transmission data format adapted to the eMMC bus through the block read command of the eMMC bus. After parsing them into the operating system adapted format, submit them to the operating system.

2. The implementation method of the Ethernet card based on the eMMC bus interface according to claim 1, characterized in that, The preset termination condition is that the remaining amount of the first-in-first-out transmission is less than the maximum length of a single Ethernet packet or the transmission idle software timer times out.

3. The implementation method of the Ethernet card based on the eMMC bus interface according to claim 1, characterized in that, The dedicated Ethernet frame transmission data format adapted for the eMMC bus includes a transmit frame header and a receive frame trailer; wherein, the transmit frame header consists of 16 bytes, including an 8-byte command descriptor and an 8-byte transmit descriptor, used to describe the slot and associated parameters of the Ethernet data packet for the device driver software; the receive frame trailer is a 16-byte receive descriptor, used to carry the parsing results of the media access control module on the received Ethernet data packet.

4. The method for implementing an Ethernet card based on an eMMC bus interface according to claim 3, characterized in that, The command descriptor includes one or more combinations of the following fields: inner VLAN tag, outer VLAN tag, maximum segment size of Transmission Control Protocol (TCP), valid bits of inner VLAN tag, valid bits of VLAN tag, and valid bits of maximum segment size of TCP. The transmit descriptor includes one or more combinations of the following fields: Virtual LAN tag insertion enable bit, Cyclic Redundancy Check padding enable bit, Transmission Control Protocol segmentation offload enable bit, Internet Protocol version checksum enable bit, Layer 4 checksum enable bit, frame length, and frame header length.

5. The method for implementing an Ethernet card based on an eMMC bus interface according to claim 3, characterized in that, The receive descriptor includes one or more combinations of the following fields: inner VLAN tag, outer VLAN tag, opcode, payload type, layer 3 type, Internet checksum, Internet payload error, cyclic redundancy check error, frame header length, and packet length.

6. The method for implementing an Ethernet card based on an eMMC bus interface according to claim 1, characterized in that, The eMMC bus reservation command includes at least a first reservation command, a second reservation command, and a third reservation command; wherein, the first reservation command is configured to write the address of the register to be operated to the target register address cache unit of the bridge module; the second reservation command is configured to read the register data pointed to by the target register address cache unit; the third reservation command is configured to carry the write data and write it to the register pointed to by the target register address cache unit; the multiplexing of the eMMC bus reservation command for reading and writing the internal registers of the Ethernet card includes: When the device driver software reads the register, it writes the address of the target register into the target register address cache unit through the first reservation command; the bridging module responds to the second reservation command, reads the register whose address is stored in the target register address cache unit, and returns the read data to the host as a response to the second reservation command; When the device driver software writes to the register, it writes the address of the target register to the target register address cache unit through a first reserved command, and carries the data to be written through a third reserved command. The bridging module responds to the third reserved command and writes the data to be written carried by the third reserved command to the register in the target register address cache unit.

7. An Ethernet card based on an eMMC bus interface, characterized in that, The system includes a first interface module, a controller module, a bridge module, a media access control module, and a second interface module connected in sequence. The first interface module interacts with the host via an eMMC bus interface. The second interface module is used to access the network. The bridge module is used to implement the method for implementing an Ethernet card based on an eMMC bus interface as described in any one of claims 1-6, and interacts with the controller module and the media access control module.

8. The Ethernet card based on the eMMC bus interface according to claim 7, characterized in that, The second interface module includes: A high-speed serial-to-parallel conversion interface, which is based on a serial gigabit media independent interface for connecting to an external Ethernet physical layer chip or optical module.

9. The Ethernet card based on the eMMC bus interface according to claim 7, characterized in that, The second interface module also includes: Ethernet physical layer, which accesses the wired network via Ethernet cable.

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