A memory system and a control method for coexistence of on-chip storage and cache functions

Abstract

This invention discloses a memory system and control method that integrates on-chip storage and caching functions, belonging to the field of chip design technology. The invention includes a physical memory array, a configuration register group, a request processing unit, and a memory access pipeline. The physical memory array is divided into multiple paths; the configuration register group dynamically configures at least one path as an OCM region, and the rest as cache regions; the request processing unit receives and parses access requests; the memory access pipeline processes requests according to the standard cache access path. The request processing unit also includes bypass signal generation logic. When a request hits an OCM region, it bypasses tag RAM lookup and generates a bypass control signal for direct access to the physical memory array; the selection unit selects to output either a bypass or standard control signal based on whether the OCM region is hit. This invention achieves dynamic coordination and resource sharing between OCM and cache, improving resource utilization, reducing software complexity, and ensuring deterministic latency and hardware consistency for OCM access.

Description

Technical Field

[0001] This invention belongs to the field of chip design technology, specifically relating to a storage system and control method that combines on-chip storage and cache functions, and particularly to a method for implementing coupled functional memory. Background Technology

[0002] In modern high-performance system-on-chip (SoC) design, the efficient utilization of on-chip storage resources has a decisive impact on system performance, power consumption, and real-time performance. On-chip memory (OCM) and cache are two important functional forms of static random access memory (SRAM), each serving different application scenarios. Traditionally, OCM and cache are two types of storage systems with fixed hardware functions, and their functions are not coexisting.

[0003] OCM is a dedicated SRAM resource that is explicitly managed by software, with low latency and deterministic latency access. It is commonly used in the following scenarios: (1) In scenarios with high deterministic latency and security requirements (such as automotive electronics, industrial control, and aerospace), OCM, being close to the CPU core, can ensure fixed access latency and avoid time jitter caused by cache hits / misses; (2) For frequently called algorithms, interrupt service routines, etc., manually allocating them to OCM can greatly reduce the latency of accessing main memory; (3) When the address access mode is complex, using a cache method may lead to performance degradation due to frequent misses. Changing to OCM storage, which is directly managed by software, can alleviate this problem; (4) During the startup phase of the Basic Input / Output System (BIOS), placing the key code of the hardware initialization process in OCM can significantly reduce the instruction and data reading time and speed up the startup. The traditional implementation of OCM is as follows: a dedicated SRAM area is opened in the chip independently of the cache system. This area has an independent address space; it does not participate in the cache coherence protocol; the central processing unit (CPU) can directly access it through a dedicated bus; and the software needs to manually maintain data consistency between multiple cores.

[0004] Cache is a hardware-managed, transparent, high-speed storage layer. Its core objective is to improve average memory access performance. Typical features include: (1) automatic data prefetching and replacement; (2) hardware-automatic maintenance of data consistency; (3) software does not need to be aware of the existence of the cache, and all memory access is uniformly performed through virtual addresses. The traditional implementation of cache is as follows: the physical SRAM array is divided into multiple groups, each containing N paths. The address is used to generate an index to locate the group through a hash algorithm, and the specific path is matched by the label; the hardware cache controller maintains global data consistency, usually using cache consistency protocols (such as MESI, MOESI protocols); the hardware automatically manages the replacement and write-back strategies of data rows.

[0005] The rise of edge artificial intelligence (AI), autonomous driving, and industrial control has brought new demands to chips. A single chip needs to simultaneously support general-purpose computing and low-latency real-time hardware tasks, creating a strong need for the coexistence of cache and OCM (Optical Character Memory) functions. For example, in AI inference accelerator scenarios, model weights, activation values, and function lookup tables need to remain on-chip to avoid bandwidth bottlenecks caused by frequent access to double data rate (DDR) memory. Simultaneously, intermediate computation results exhibit strong temporal and spatial locality, making them suitable for local cache reuse.

[0006] The limitations of existing technology are:

[0007] (1) Resource fragmentation: The SRAM of OCM and Cache is physically isolated, for example, the capacity of Cache cannot be used when OCM is idle;

[0008] (2) Consistency risk: Cache maintenance operations may mishandle OCM data;

[0009] (3) High software complexity: requires explicit management of data migration and consistency;

[0010] (4) Low area efficiency: The two types of resources are managed independently, often with redundant control and management.

[0011] Therefore, there is an urgent need for a technical solution that can achieve dynamic coordination, resource sharing, and protocol isolation between OCM and Cache at the hardware level, in order to solve the problems of resource fragmentation, consistency risks, high software complexity, and low area efficiency in existing technologies. Summary of the Invention

[0012] To achieve the above objectives, this invention provides a storage system and control method that allows on-chip storage and caching functions to coexist. By implementing on-demand partitioning and collaborative operation of OCM and Cache within a single physical SRAM array, it solves the problems of resource fragmentation and complex management in traditional architectures.

[0013] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0014] The core technical concepts adopted in this invention include: introducing a programming model to dynamically configure the sharing of some or all of the SRAM into one or more OCM regions as needed; determining the access method by requesting address resolution information, automatically identifying the OCM address and bypassing the tag RAM access before entering the memory access pipeline, and directly accessing the data RAM; automatically tracking the replica holder and maintaining data consistency when multiple masters share OCM data through a hardware-integrated consistency maintenance module; and automatically cleaning up dirty data and protecting the target region when the OCM region is enabled / disabled through hardware flush control logic and status feedback mechanism.

[0015] Based on the above concept, the present invention provides a storage system in which on-chip storage and caching functions coexist, the structure of which is as follows:

[0016] Physical storage resource layer: This includes the physical storage array, which is divided into multiple ways, each containing multiple sets of data, serving as a unified physical storage resource in the system. By default, this array operates according to a standard set-associative architecture, serving the cache function.

[0017] Configurable Functional Layer: This layer includes a configuration register set used to store configuration information issued by the user or software. The core function of this configuration information is to functionally re-divide multiple paths in the physical storage array, dynamically configuring at least one path as one or more on-chip memory (OCM) regions, while the remaining paths are retained as cache regions. This configuration register set provides a programming interface for software, supporting flexible adjustments to the capacity and number of OCM regions.

[0018] Request Identification and Processing Layer: This layer includes a request processing unit that receives access requests from the upstream master controller and parses the address information of the access requests. This unit integrates address identification logic, enabling real-time comparison of the request address with the configured OCM region.

[0019] Memory access execution layer: This includes the memory access pipeline, coupled with the physical storage array, and is used to process access requests according to the standard cache access path (i.e., steps including tag RAM lookup, status checks, etc.). The pipeline is responsible for request arbitration, resource allocation, and operation execution.

[0020] The key improvement of this invention lies in the introduction of a bypass access mechanism, specifically:

[0021] The request processing unit is equipped with bypass signal generation logic. When the address identification logic determines that the access request has hit a certain OCM area based on the configuration information and address information, the bypass signal generation logic is activated, directly bypassing the standard cache access path, especially skipping the query step of the tag RAM, and instead generating a set of bypass control signals that can directly address specific paths and specific data groups in the physical storage array based on the preset address-to-physical location mapping relationship.

[0022] To enable hardware switching between the standard path and the bypass path, the storage system also includes a selection unit. This selection unit has two inputs and one output: the first input is coupled to the output of the memory access pipeline and receives the standard control signal generated by the standard cache access path; the second input is coupled to the bypass signal generation logic and receives the bypass control signal; the output is coupled to the access port of the physical storage array. The selection unit is controlled by the OCM hit indication signal output by the request processing unit. When an OCM hit occurs, the bypass control signal is selected and output to the physical storage array; otherwise, the standard control signal is selected.

[0023] Through the above structure, the present invention achieves that on the same physical storage array, the OCM area enjoys a low-latency, deterministic direct access path, while the Cache area still maintains a high-performance automatic caching function, and the two do not interfere with each other and work together.

[0024] Furthermore, the request processing unit integrates a parallel address comparator group. This comparator group maintains real-time communication with the configuration register group to obtain the base address and mask information configured for each OCM region. When a new access request arrives, the parallel address comparator group synchronously compares the requested address with the base address-mask pairs of all configured OCM regions, enabling it to quickly determine whether the requested address falls within a certain OCM region within a single clock cycle and generate OCM region information containing the hit region number. After receiving valid OCM region information, the bypass signal generation logic calculates the specific bypass control signal based on pre-established address-to-physical storage location mapping rules (e.g., determining the target path based on the hit region number and determining the target group based on the index bits in the address), thereby achieving precise positioning of the data RAM.

[0025] Furthermore, in application scenarios that support multiple masters sharing OCM data, the storage system of the present invention can further integrate a hardware consistency maintenance mechanism. Specifically, a consistency maintenance unit is added to the memory access pipeline to automatically track the access status of each master to OCM data, ensuring the consistency of shared data among multiple masters and avoiding the complexity and error risk of manual software maintenance.

[0026] As an efficient implementation, the consistency maintenance unit can directly reuse the existing snoop filter hardware resources in the system without adding additional dedicated logic. This snoop filter maintains a simplified directory table for the OCM region. Each entry in the directory table records key information about OCM data blocks shared by multiple masters: including the address tag of the data block, the bitmasks of all masters holding replicas of the data block (each master occupies one bit), and the current cache consistency protocol status of each replica. Considering the usage characteristics of the OCM region, this embodiment uses a simplified MSI protocol (Modified, Shared, Invalid) for state management, reducing hardware overhead while ensuring consistency.

[0027] When the consistency maintenance unit detects that any master is performing a write operation on the OCM region, it looks up the directory table based on the write address to quickly locate other masters currently holding a copy of that data block. Unlike traditional broadcast snooping, this unit only sends precise snooping requests to the specific master that actually holds the copy, based on the master bitmask recorded in the directory table. This significantly reduces unnecessary snooping transactions and improves the utilization efficiency of the system bus and snooping filters.

[0028] Furthermore, to ensure data security during the OCM area reconfiguration process, the storage system of this invention also incorporates a hardware-automated flushing control mechanism. Specifically, the configuration information includes a configuration field indicating whether to perform a flushing operation on a specific target path. This field can be set simultaneously when the software configures OCM to be enabled or disabled, triggering the hardware-level flushing process.

[0029] The flushing control logic is coupled with the configuration register group. Once the flushing field is detected as enabled, the flushing operation on the target path is immediately initiated. The core of this logic is a flushing state machine, which can reuse existing power-down flushing state machines in the system to reduce hardware design redundancy. The state machine automatically traverses all group indices of the target path, checking the validity of cache lines group by group. For each valid dirty cache line, the state machine automatically generates a write-back request, writing its contents back to the next level of storage to ensure no data loss.

[0030] To prevent new access requests from interfering with the flushing process, the storage system also includes an arbitrator to arbitrate regular access requests initiated by the request processing unit and flushing transactions initiated by the flushing control logic. During the flushing operation, the arbitrator is configured to grant flushing transactions higher priority than regular access requests, thereby physically preventing new requests from occupying the path being flushed and ensuring the integrity and atomicity of the flushing operation.

[0031] Once the flush state machine has traversed all group indices and all write-back requests have been successful, the system will automatically update the status register, setting the flush completion flag and allowing normal access to the reconfigured OCM or Cache regions to resume. The software can query this status register to obtain the flush progress and result.

[0032] Furthermore, to achieve flexible control over the OCM region, the configuration register group specifically includes the following key registers:

[0033] Base Address Register: For each configurable OCM region (e.g., regions 0 to 3), a corresponding base address register is set up to store the starting address of that region in the system's physical address space. Software defines the address range of the OCM region by writing to these registers.

[0034] Policy Register: Used to store policy information related to OCM configuration, including but not limited to: the number of paths allocated to OCM (which determines the total capacity of OCM), the capacity allocation method for each region, and the processing policy for cache lines during flushing operations (such as write-back policy).

[0035] Status Register: Used to reflect the current OCM configuration status information, including but not limited to: whether the configuration parameters are valid, whether there are any exceptions, and whether the OCM mode has been successfully enabled. The software can obtain the execution result of the configuration operation by reading this register.

[0036] Based on the above storage system, the present invention also provides a storage control method that allows on-chip storage and caching functions to coexist. This method also realizes dynamic collaborative management of OCM and Cache at the hardware level, and together with the aforementioned system architecture, it constitutes a complete technical solution.

[0037] The core process of this method is as follows:

[0038] When the system receives a memory access request from the upstream master controller, it first parses the requested address. Then, based on the currently effective configuration information in the configuration register set, it determines whether the requested address matches a pre-configured OCM region. This determination process is completed quickly using parallel address comparison logic.

[0039] If an OCM region is determined to be hit, a bypass access path is executed: bypassing the standard Cache Tag RAM lookup process, a bypass control signal is generated directly based on the preset address mapping relationship. This signal precisely points to the corresponding path and data group in the physical storage array, thus completing data access through the most direct path. If an OCM region is determined to be missed, the standard Cache access path is followed: first, the tag RAM is queried, the tag is compared, the status is checked, and then the data RAM is accessed.

[0040] Furthermore, based on the above method, in order to further improve the efficiency of address determination, a parallel address comparator group can be used to synchronously compare the requested address with the base address-mask pairs of all configured OCM regions to quickly generate hit region information.

[0041] Furthermore, when generating the bypass control signal, the specific implementation method is as follows: the target road for this access is determined according to the preset mapping relationship between the hit OCM area number and the physical road; at the same time, the bit segment (i.e., index bit) used for indexing data group is extracted from the request address to determine the target group; the target road and target group information are combined to form a complete bypass control signal.

[0042] Furthermore, this method includes a comprehensive flushing process to ensure data security during OCM mode switching: when the software triggers the enable or exit operation of OCM mode, the hardware automatically responds and initiates a flushing operation on the target path. The flushing operation traverses all group indices of the target path through a state machine, checking and writing back valid dirty cache lines one by one. After all index traversal is completed and all write-back operations are successful, the system updates the status register to indicate that the flushing is complete, and then restores normal access to the newly configured area.

[0043] The innovation of this invention lies in introducing the OCM (Optical Character Movement) mode into the traditional cache memory access system, dynamically allocating existing SRAM resources to the cache and OCM regions, thus meeting the comprehensive requirements of simultaneously considering resources, performance, energy efficiency, and flexibility. Compared with existing on-chip storage architectures (such as fixed partitioning of OCM+Cache or pure cache solutions), this invention has the following significant advantages and positive effects:

[0044] 1. Significantly improves on-chip SRAM resource utilization: In traditional solutions, OCM and Cache are physically isolated, resulting in OCM being unusable by Cache when idle, and vice versa. This invention, through a dynamically configurable SRAM sharing mechanism, allows OCM and Cache to allocate a unified physical storage array on demand, avoiding resource waste, and is especially suitable for real-time systems with large load fluctuations or heterogeneous computing scenarios.

[0045] 2. Achieving deterministic latency for OCM access while preserving high cache performance: This invention automatically identifies the OCM address region through hardware and bypasses tagged RAM queries, shortening the pipeline stages of the OCM access path and saving approximately several clock cycles (e.g., about 3 clock cycles); while the cache region still maintains full-featured cache acceleration. Both operate in parallel without interference, balancing real-time performance and throughput requirements.

[0046] 3. Relieves software from the burden of OCM region consistency management: In traditional inconsistent OCM, multi-core data sharing requires software to explicitly perform flush / invalidation operations, which is prone to errors. This invention, through an optional hardware consistency maintenance module (reusing the listener filter mechanism), automatically handles OCM data replica tracking and invalidation, allowing software to use OCM like accessing ordinary memory, significantly reducing software development complexity.

[0047] 4. Supports smooth mode switching and data security: During OCM enabling / disabling, the hardware automatically performs a flushing operation and locks the target path. The arbitrator prioritizes flushing transactions to prevent dirty data loss or accidental replacement. Compared to solutions requiring software to pause all memory accesses and manual cleanup, this invention achieves simple and secure resource reconfiguration.

[0048] 5. Compatible with mainstream interconnect protocols, easy to port and integrate: This solution does not depend on a specific bus or protocol and can be seamlessly integrated into standard SoC architectures such as CHI, ACE, and AXI of Advanced Microcontroller Bus Architecture (AMBA) without the need for additional protocol support. It has good engineering feasibility and can flexibly expand and upgrade SRAM functions. Attached Figure Description

[0049] The present invention will be further described below with reference to the accompanying drawings:

[0050] Figure 1 This is a structural diagram of the OCM and Cache functional coupling circuit provided in Embodiment 1 of the present invention;

[0051] Figure 2 This is a flowchart of switching from Cache mode to Cache-OCM coupled working mode provided in Embodiment 1 of the present invention;

[0052] Figure 3 This is a flowchart of switching from Cache-OCM coupled working mode to Cache mode provided in Embodiment 1 of the present invention;

[0053] Figure 4 This is a circuit structure diagram for supporting hardware maintenance consistency provided in Embodiment 2 of the present invention;

[0054] Figure 5 This is a state transition diagram of the flushing control state machine provided in Embodiment 1 of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be described in further detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only for a better understanding of this invention and do not constitute a limitation on the scope of protection of this invention.

[0056] Example 1

[0057] This embodiment provides a storage system that combines on-chip storage and caching functions. By implementing on-demand partitioning and collaborative operation of OCM and Cache within a single physical SRAM array, it solves the problems of resource fragmentation and complex management in traditional architectures.

[0058] Figure 1 This is a schematic diagram of the OCM and Cache functional coupling circuit provided in this embodiment. Figure 1 As shown, the storage system includes:

[0059] The physical storage array is divided into multiple ways, each containing multiple sets, serving as a unified physical storage resource in the system. In this embodiment, the physical storage array is SRAM with a total capacity of 16MB, employing a 16-way set-associative structure. The data block size of each way is 64B, and the set index width is 14 bits. By default, this array operates according to a standard set-associative structure, serving as a cache.

[0060] The configuration register set (OCM Program Registers) stores configuration information issued by the user or software. The core function of this configuration information is to functionally re-divide multiple paths in the physical memory array, dynamically configuring at least one path as one or more on-chip memory (OCM) regions, while the remaining paths are retained as cache regions. This configuration register set provides a programming interface for software, supporting flexible adjustments to the capacity and number of OCM regions. The specific structure of the configuration register set will be detailed later.

[0061] The Request Unit receives access requests from upstream controllers (such as CPU, GPU, DMA controllers, etc.) and parses the address information of the access requests. The Request Unit integrates OCM region process logic, which is responsible for maintaining the entire lifecycle of all source requests.

[0062] The memory access pipeline (PIPE), coupled to the physical storage array, is used to process access requests according to the standard cache access path (i.e., steps including tag RAM lookup, status checks, etc.). The memory access pipeline contains multiple pipeline stages (Stage 0 to Stage N), which sequentially use the access ports of each SRAM and are responsible for request arbitration, resource allocation, and operation execution.

[0063] The key improvement of this invention lies in the introduction of a bypass access mechanism. Specifically:

[0064] A bypass signal generation logic is added to the request processing unit. When the address identification logic inside the request processing unit determines that the access request has hit a certain OCM region based on the configuration information and address information, the bypass signal generation logic is activated, directly bypassing the standard cache access path, especially skipping the lookup step of the tag RAM, and instead generating a set of bypass control signals that can directly address specific paths and specific data groups in the physical memory array according to the preset address-to-physical location mapping relationship.

[0065] To enable hardware switching between the standard path and the bypass path, the storage system also includes a selection unit (e.g., a multiplexer, MUX). This selection unit has two inputs and one output: the first input is coupled to the output of the memory access pipeline and receives the standard control signal generated by the standard cache access path; the second input is coupled to the bypass signal generation logic and receives the bypass control signal; the output is coupled to the access port of the physical storage array. The selection unit is controlled by the OCM hit indication signal output by the request processing unit. When an OCM hit occurs, the bypass control signal is selected and output to the physical storage array; otherwise, the standard control signal is selected.

[0066] Through the above structure, the present invention achieves that on the same physical storage array, the OCM area enjoys a low-latency, deterministic direct access path, while the Cache area still maintains a high-performance automatic caching function, and the two do not interfere with each other and work together.

[0067] OCM address recognition mechanism

[0068] The request processing unit integrates the following:

[0069] The parallel address comparator group maintains real-time communication with the configuration register group to obtain the base address and mask information configured for each OCM region. When a new access request arrives, the parallel address comparator group synchronously compares the requested address with the base address-mask pairs of all configured OCM regions. It can quickly determine whether the requested address falls within a certain OCM region within a single clock cycle and generate OCM region information containing the hit region number.

[0070] The bypass signal generation logic is coupled with the parallel address comparator group. After receiving valid OCM region information, it calculates the specific bypass control signal according to the pre-established address-to-physical storage location mapping rules (e.g., determining the target path based on the hit region number and determining the target group based on the index bit in the address), thereby achieving precise positioning of the data RAM.

[0071] This identification function is implemented in the request processing unit, meaning that the OCM region hit determination and bypass control signal calculation are completed before entering the memory access pipeline. Compared to the standard cache access path (which typically includes: Tag lookup → Tag data buffer → Tag information comparison → data RAM access), this scheme can save several clock cycles (e.g., about 3 clock cycles).

[0072] Example of OCM region mapping relationship

[0073] The following section, using the configuration example in the appendix, illustrates the indexing method for the OCM region. Assuming the system physical address width is 40 bits, the total SRAM capacity is 16MB, the structure is 16-way set-associative, and each way's data block size is 64B, then the set's index width is 14 bits.

[0074] Table 1 shows a specific configuration example of OCM. OCM can support configuration of up to 4 regions.

[0075] Table 1. Specific Configuration Examples of OCM

[0076] 16MB 1 1MB 0 1 1MB - - - 16MB 2 2MB 0-1 1,1 1MB 1MB - - 16MB 4 4MB 0-3 1,1,1,1 1MB 1MB 1MB 1MB 16MB 8 8MB 0-7 2,2,2,2 2MB 2MB 2MB 2MB 16MB 16 16MB 0-15 4,4,4,4 4MB 4MB 4MB 4MB

[0077] The number of valid address bits is determined by the capacity of each OCM sub-region.

[0078] Table 2 shows the correspondence between OCM area capacity and configuration valid bits.

[0079] Table 2. Correspondence between OCM area capacity and configuration valid bits

[0080] 1MB [PA_WIDTH-1:20] 2MB [PA_WIDTH-1:21] 4MB [PA_WIDTH-1:22] 8MB [PA_WIDTH-1:23] 16MB [PA_WIDTH-1:24]

[0081] Example 1: OCM occupies 1 way.

[0082] The total capacity of the OCM area is 1MB, with only OCM area 0 being valid and having a capacity of 1MB. The address allocation is as follows:

[0083] OCM tag OCM access set Byte offset

[0084] In OCM mode, the request processing unit determines whether it is an access to OCM region 0 based on the address [39:20] bits. If it does not match the base address configured for OCM region 0, it is processed as a normal cache transaction; if it matches, the address [19:6] is taken as the set for SRAM access, and by default only way0 is accessed.

[0085] Example 2: OCM occupies 4 ways.

[0086] The total OCM area capacity is 4MB, with areas 0-3 all valid, and each area having a capacity of 1MB. Address bit allocation is as follows:

[0087] OCM tag OCM access set Byte offset

[0088] The request processing unit determines which region it matches based on the address [39:20]. If it does not match any of the base addresses configured in OCM regions 0-3, it is processed as a normal transaction. If it matches any region, the address [19:6] is taken as the set for SRAM access. The access way depends on which region it matches: if it matches region 0, it accesses way0; if it matches region 1, it accesses way1, and so on.

[0089] Example 3: OCM occupies 16 ways.

[0090] The total OCM area capacity is 16MB, with areas 0-3 all valid, and each area having a capacity of 4MB. Address bit allocation is as follows:

[0091] OCM tag Way offset within the area OCM access set Byte offset

[0092] In OCM mode, when the transaction queue receives a new request, it needs to determine whether it is an access to OCM region 0-3 based on the address [39:22] bits. If it does not match any of the base addresses configured for OCM region 0-3, it is processed as a normal transaction. If it matches any region, the address [19:6] is taken as the SRAM access set. The access way depends on which region it matches and the value of address [21:20]. For example, if the address falls in OCM region 0 and address [21:20] = 2'b10, then way2 is accessed; if the address falls in OCM region 1 and address [21:20] = 2'b11, then way7 is accessed.

[0093] Configuration register group

[0094] To enable flexible control of the OCM region, the configuration register group specifically includes the following key registers:

[0095] Table 3 shows the key configuration fields of the OCM configuration register group.

[0096] Table 3. OCM Configuration Register Group

[0097] Base address register For each configurable OCM region (e.g., regions 0 to 3), a corresponding base address register is set up to store the starting address of that region in the system's physical address space. The software defines the address range of the OCM region by writing to these registers. Policy Register This is used to store policy information related to OCM configuration, including but not limited to: the number of roads allocated to OCM (which determines the total capacity of OCM), the capacity allocation method for each region, and the processing strategy for cache lines during flushing operations (such as write-back strategy). Status Register This register is used to reflect the current status information of the OCM configuration, including but not limited to: whether the configuration parameters are valid, whether there are any exceptions, and whether the OCM mode has been successfully enabled. The software can obtain the execution result of the configuration operation by reading this register.

[0098] OCM mode switching process

[0099] Figure 2 A flowchart illustrating the switch from standalone Cache operating mode to Cache-OCM coupled operating mode is shown. Figure 2 As shown, the process includes the following steps:

[0100] Step 201: The requesting end stops accessing the memory subsystem.

[0101] Step 202: The software configures the registers related to OCM mode through the programming interface, including setting the OCM region base address, mask, number of occupied channels, etc.

[0102] Step 203: Hardware checks the validity of configuration parameters. If the configuration is not supported (e.g., the number of requested ways exceeds the range), the OCM process ends directly, and the status register is updated to indicate an error; if the configuration is supported, the flush process is started.

[0103] Step 204: The hardware performs a flush operation on the target way to clear the valid cache line data in the SRAM target way.

[0104] Step 205: After flushing is complete, update the status register and enable OCM mode. This allows the requesting end to resume access to the memory subsystem. At this time, the cache area and the OCM area operate in parallel.

[0105] Figure 3 A flowchart illustrating the switch from Cache-OCM coupled operating mode to Cache-only operating mode is shown. Figure 3 As shown, the process includes the following steps:

[0106] Step 301: The requesting end stops accessing the memory subsystem.

[0107] Step 302: The software migrates the valid data in the OCM region to a new address space (such as DDR memory) to avoid data loss.

[0108] Step 303: Configure the OCM control register, disable the OCM valid bit, and exit OCM mode.

[0109] Step 304: Allow the requesting end to resume access to the memory subsystem. The original OCM area is reused as a cache.

[0110] scour control mechanism

[0111] To ensure data security during the OCM area reconfiguration process, the storage system of this invention also incorporates a hardware-automated flushing control mechanism. Specifically, the configuration information includes a configuration field indicating whether to perform a flushing operation on a specific target path. This field can be set simultaneously when the software configures OCM to be enabled or disabled, triggering the hardware-level flushing process.

[0112] Figure 5 The state transition diagram of the flushing control state machine provided in Embodiment 1 of the present invention is shown. Figure 5As shown, the flushing control logic is coupled with the configuration register set. Once the flushing field is detected as enabled, the flushing operation on the target path is immediately initiated. The core of this logic is a flushing state machine, which can reuse the existing power-down flushing state machine in the system to reduce hardware design redundancy.

[0113] like Figure 5 As shown, the state transition process of the flushing state machine is as follows:

[0114] Idle state: Waiting for flush trigger. When the flush field in the configuration register group is enabled, the state machine is activated, enters the flush process, and initializes the access group number (set index), preparing to traverse from the first group.

[0115] Querying Tag Information: The state machine queries the tag information of all ways in the current group through the memory access pipeline (PIPE) to determine whether there are any valid cache lines in the current traversal group that need to be written back to the next level of storage.

[0116] Write-back request: If there are dirty cache lines in the current group that need to be written back, the state machine sends a write-back request to the requesting unit and waits for the requesting unit to receive it. If the requesting unit does not receive it, it continues to wait until it receives the request.

[0117] Waiting for write-back to complete: After the requesting unit receives the write-back request, the state machine enters a waiting state, waiting for all flush-triggered write-back operations to complete.

[0118] Determining PIPE access completion: After the write-back operation of the current group is completed, the state machine further waits for the memory access pipeline (PIPE) to complete, ensuring that all pending operations have ended.

[0119] Increment group number: After all operations in the current group are completed, the state machine will increment the group number by one and begin processing the next group.

[0120] Determining if traversal is complete: The state machine checks whether all groups have been traversed. If not, it returns to the "Query Tag Information" step to continue processing the next group; if complete, it enters the completion state.

[0121] Completion Status: After all group traversals and all write-back operations have been successfully completed, the state machine updates the status register, setting the flush completion flag to indicate that the flush operation is complete and allowing normal access to the reconfigured OCM region or cache region to resume. The software can query this status register to obtain the flush progress and result.

[0122] To prevent new access requests from interfering with the flushing process, the storage system also includes an arbitrator to arbitrate regular access requests initiated by the request processing unit and flushing transactions initiated by the flushing control logic. During the flushing operation, the arbitrator is configured to grant flushing transactions higher priority than regular access requests, thereby physically preventing new requests from occupying the path being flushed and ensuring the integrity and atomicity of the flushing operation.

[0123] Through the above mechanism, the state machine automatically traverses all group indices of the target path and checks the validity of cache lines group by group. For each valid dirty cache line, the state machine automatically generates a write-back request and writes its contents back to the next level of storage to ensure that no data is lost.

[0124] Example 2

[0125] This embodiment, based on Embodiment 1, further considers the consistency maintenance problem in a scenario where multiple master controllers share an OCM.

[0126] Figure 4 This embodiment provides a circuit structure diagram to support hardware maintenance consistency. (See diagram below.) Figure 4 As shown, with Figure 1 In comparison, this embodiment adds a Coherency Unit to the memory access pipeline to maintain the consistency of shared OCM data among multiple masters.

[0127] As an efficient implementation, the consistency maintenance unit can directly reuse the existing snoop filter hardware resources in the system without adding additional dedicated logic. This snoop filter maintains a simplified directory table for the OCM region. Each entry in the directory table records key information about OCM data blocks shared by multiple masters: including the address tag of the data block, the bitmasks of all masters holding replicas of the data block (each master occupies one bit), and the current cache consistency protocol status of each replica.

[0128] Table 4 shows an example format for a directory entry:

[0129] Table 4. Table of Contents Item Format

[0130] OCM_Addr_Tag OCM data block address label Master_ID_Bitmask The master bitmask for replicas, with each master represented by 1 bit. State Replica status (Modified / Shared / Invalid)

[0131] Based on the custom mapping method, a specific OCM region address can only be mapped to one group of the listening filter. Each group contains several items, and each item records the necessary information for the specific OCM region address.

[0132] Considering the usage characteristics of the OCM region, this embodiment adopts a simplified MSI protocol (Modified, Shared, Invalid) for state management, reducing hardware overhead while ensuring consistency. For the cacheable region, the full MOESI protocol can be used.

[0133] When the consistency maintenance unit detects that any master is performing a write operation on the OCM region, it looks up the directory table based on the write address to quickly locate other masters currently holding a copy of that data block. Unlike traditional broadcast snooping, this unit only sends precise snooping requests to the specific master that actually holds the copy, based on the master bitmask recorded in the directory table. This significantly reduces unnecessary snooping transactions and improves the utilization efficiency of the system bus and snooping filters.

[0134] This mechanism allows consistency operations that traditionally require explicit software maintenance to be completed automatically by hardware, significantly reducing the complexity of software development.

[0135] Example 3

[0136] This embodiment provides a control method based on any of the above-mentioned storage systems. This method realizes dynamic collaborative management of OCM and Cache at the hardware level, and together with the aforementioned system architecture, it constitutes a complete technical solution.

[0137] The core process of this method is as follows:

[0138] Step S1: When the system receives a memory access request from the upstream master controller, it first parses the request address.

[0139] Step S2: Based on the currently effective configuration information in the configuration register group, determine whether the requested address hits a pre-configured OCM region. This determination process is completed quickly through parallel address comparison logic. Specifically, a parallel address comparator group can be used to synchronously compare the requested address with the base address-mask pairs of all configured OCM regions to quickly generate hit region information.

[0140] Step S3: If an OCM region hit is detected, a bypass access path is executed: bypassing the standard Cache Tag RAM lookup process, a bypass control signal is directly generated based on a preset address mapping relationship. The specific method for generating the bypass control signal is as follows: based on the preset mapping relationship between the hit OCM region number and the physical path, the target path for this access is determined; simultaneously, the bit segment used to index the data group (i.e., the index bit) is extracted from the requested address to determine the target group; the target path and target group information are combined to form a complete bypass control signal. This signal precisely points to the corresponding path and data group in the physical storage array, thus completing data access through the most direct path.

[0141] Step S4: If the OCM region is determined to be missing, the standard Cache access path is followed: first query the tag RAM, compare the tags, check the status, and then access the data RAM.

[0142] The method also includes a complete flushing process to ensure data security during OCM mode switching:

[0143] Step S5: When the software triggers the enable or exit operation of OCM mode, in response to the enable or exit configuration of OCM mode, a flushing operation on the target path is triggered.

[0144] Step S6: The flush operation traverses all group indices of the target path through a state machine, checking and writing back valid dirty cache lines one by one. During the flush, flush transactions are given higher priority than regular access requests to prevent new requests from occupying the path to be flushed.

[0145] Step S7: After all index traversals are completed and all write-back operations are successfully completed, the system updates the status register to indicate that the flush is complete, and then restores normal access to the new configuration area.

[0146] Through the above steps, this invention achieves dynamic coexistence and collaborative work between OCM and Cache on the same physical storage array, ensuring deterministic low latency for OCM access while retaining the high-performance automatic caching function of the Cache area. At the same time, it solves the problems of multi-core consistency and data security during mode switching through hardware mechanisms.

[0147] The above are merely specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions, or modifications made based on the present invention to solve essentially the same technical problems and achieve essentially the same technical effects are all covered within the protection scope of the present invention.

Claims

1. A storage system with coexisting on-chip storage and caching functions, characterized in that, include: The physical storage array is divided into multiple paths to serve as a unified physical storage resource. A configuration register group is used to store configuration information, which is used to dynamically configure at least one of the multiple paths as one or more on-chip storage OCM regions, and the remaining paths as cache regions. The request processing unit is used to receive access requests and parse the address information of the access requests; A memory access pipeline, coupled to the physical storage array, is used to process the access requests according to the standard cache access path; The request processing unit further includes bypass signal generation logic, which is used to bypass the query of tag RAM in the standard cache access path and generate a bypass control signal to directly access the corresponding path and data group in the physical storage array when it is determined that the access request hits the OCM region based on the configuration information and the address information. The storage system further includes a selection unit. The first input terminal of the selection unit is coupled to the output terminal of the memory access pipeline to receive a standard control signal, the second input terminal is coupled to the bypass signal generation logic to receive the bypass control signal, and the output terminal is coupled to the access port of the physical storage array. The selection unit selects the bypass control signal or the standard control signal to output to the physical storage array based on whether the access request hits the OCM region.

2. A storage system with on-chip storage and caching functions coexisting as described in claim 1, characterized in that, The request processing unit includes: A parallel address comparator group, coupled to the configuration register group, is used to compare the address information with the base address and mask of each OCM region recorded in the configuration information to generate the information of the hit OCM region. The bypass signal generation logic is coupled to the parallel address comparator group and is used to generate the bypass control signal according to the address information and the preset mapping relationship between the hit OCM region information and the path and group in the physical storage array when the hit OCM region information is valid.

3. A storage system with coexisting on-chip storage and caching functions according to claim 1, characterized in that, The request processing unit is used to process access requests initiated by multiple master controllers.

4. A storage system with coexisting on-chip storage and caching functions according to claim 3, characterized in that, The memory access pipeline also includes a consistency maintenance unit, which is used to maintain the consistency of OCM data shared among multiple masters.

5. A storage system with coexisting on-chip storage and caching functions according to claim 4, characterized in that, The consistency maintenance unit reuses the listening filter in the system.

6. A storage system with coexisting on-chip storage and caching functions according to claim 5, characterized in that, The listening filter maintains a directory table for the OCM region. Each entry in the directory table records the address label of an OCM data block shared by multiple masters, the bitmask of the master holding a copy of the data block, and the MSI protocol status of each copy.

7. A storage system with on-chip storage and caching functions coexisting as described in claim 6, characterized in that, The consistency maintenance unit is also used to, when any master is detected to perform a write operation on the OCM region, look up the directory table according to the address information, obtain the bitmask of other master holding the corresponding OCM data block replica, and initiate a precise listening request to the corresponding other master only according to the bitmask, so as to maintain data consistency.

8. A storage system with coexisting on-chip storage and caching functions according to claim 1, characterized in that, The configuration information also includes a configuration field for instructing the target road to be flushed.

9. A storage system with on-chip storage and caching functions coexisting as described in claim 8, characterized in that, The storage system further includes flush control logic coupled to the configuration register group, for performing a flush operation on the target path in response to the enabling of the configuration field; the flush control logic includes a flush state machine for traversing all group indices of the target path and generating write-back requests for valid cache lines therein to complete the flush.

10. A storage system with on-chip storage and caching functions coexisting according to claim 9, characterized in that, The storage system also includes an arbitrator for arbitrating access requests initiated by the request processing unit and flush transactions initiated by the flush control logic; during the flush operation, the arbitrator is configured to grant the flush transaction a higher priority than the access request, so as to physically prevent new requests from occupying the path to be flushed.

11. A storage system with on-chip storage and caching functions coexisting according to claim 9, characterized in that, The storage system also includes a status register coupled to the flush control logic, which is updated after the flush state machine has traversed all group indices and all write-back requests have been completed, to indicate that the flush operation is complete.

12. A storage system with on-chip storage and caching functions coexisting as described in claim 1, characterized in that, The configuration register group includes: One or more base address registers are used to store the base address of the corresponding OCM region; The policy register stores the configured number of OCM channels and the flushing operation policy; The status register stores information indicating whether the configuration is abnormal and whether OCM mode is enabled.

13. A control method for a storage system according to any one of claims 1 to 12, characterized in that, include: Receive an access request and parse the address information of the access request; Based on the configuration information stored in the configuration register group, determine whether the address information hits the pre-configured OCM region; If so, the query path of the tag RAM is bypassed, and control signals are generated to directly access the corresponding path and data group in the physical storage array; If not, the physical storage array is accessed via the tag RAM after querying according to the standard cache access path.

14. The control method for a storage system with coexisting on-chip storage and caching functions according to claim 13, characterized in that, The steps for determining whether the address information matches a pre-configured OCM region include: A set of parallel address comparators compares the address information with the base address and mask of each OCM region recorded in the configuration information to obtain the information of the hit OCM region.

15. The control method for a storage system with coexisting on-chip storage and caching functions according to claim 13, characterized in that, The steps for generating control signals for the corresponding paths and data groups in a direct-access physical memory array include: The target road is determined based on the mapping relationship between the hit OCM region and the road. The target group is determined based on the index bits in the address information; The control signal is generated by combining the target road and the target group.

16. The control method for a storage system with coexisting on-chip storage and caching functions according to claim 13, characterized in that, Also includes: In response to enabling or disabling the OCM mode configuration, a flushing operation is triggered on the target path. Traverse all group indices of the target path and perform write-back operations on the valid cache lines therein; After the flushing operation is complete, update the status register and allow access to the reconfigured OCM region or cache region.

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