A real wafer proportion-based visual data processing method

Abstract

The application discloses a kind of based on real wafer proportion visual data processing method, including model construction, sparse index construction, mapping table establishment and Die positioning, the model construction contains wafer information, the sparse index construction is based on the model construction, the sparse index construction includes three-level sparse index structure, the mapping table is two-way mapping table, including positive direction mapping and reverse mapping, the model construction is drawn by wafer visualization, and index trigger drawing mechanism of multi-state linkage is used.The application can achieve wafer real proportion accurate visualization, with the effect of efficient data processing, with the advantages of simple realization, efficient operation, avoid the problems of traditional wafer visualization, such as morphological distortion, rendering lag, slow query and resource waste caused by technical limitations.

Description

Technical Field

[0001] This invention relates to the field of wafer technology, and in particular to a visualization data processing method based on the actual wafer scale. Background Technology

[0002] Current domestic industrial host computer software primarily displays wafers as an overview, prioritizing functionality. Detailed wafer die displays are mostly presented with fixed shapes and sizes, lacking depth and failing to accurately represent the actual wafer layout and die style. Therefore, there is a technological gap in current software for detailed wafer display. Given the current emphasis on domestically produced alternatives to equipment, future industrial software will face higher demands in visualization. Existing visualization methods will be insufficient to meet diverse needs. To address these issues, we propose a visualization data processing method based on the actual wafer proportions. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of existing industrial host computer software, which mainly displays wafers in an overview manner and focuses on functional achievement. The detailed display of wafer dies is mostly shown in a fixed shape and size, without much attention to the details of wafer display, and cannot restore the real wafer layout and die style. Therefore, this invention proposes a visualization data processing method based on the real wafer ratio.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: A visualization data processing method based on real wafer scale, including the entire process of visualization data model construction, hierarchical sparse index construction, dual mapping table establishment, visualization drawing, and precise positioning: S1: Construct a visualization data model based on the actual wafer scale. This visualization data model includes basic wafer information, wafer size information, wafer row and column information, die size information, and die distribution information. The basic wafer information includes wafer type, wafer model number, type name, product name, and description information. The wafer size information includes size specifications, total number of dies that can be deployed within the area, total number of effective dies within the area, wafer radius value, and bottom facet position. The wafer row and column information includes descriptions of the rows and columns where the dies are located. The die size information includes the width, height, and spacing between dies. The die distribution information includes a description of the association between die number and row / column information, and a description of whether a die is usable. S2: Based on the visualization data model constructed in step S1, establish a wafer-specific three-level sparse index structure, wherein the three-level sparse index structure includes: First-level index: Wafer effective area mask, which only marks the effective areas within the wafer arc, non-cut-out areas, and non-keep areas, and excludes invalid areas; Secondary index: Row block index, which only stores rows containing valid dies and skips rows that are completely invalid; Level 3 Index: Die-level index, storing only valid dies and defective dies, skipping blank placeholder dies; simultaneously, taking into account the circular outline characteristics of the wafer, it adopts a dual-index design of polar coordinates and rectangular coordinates for the arc edge adaptive indexing design, adapting to the circular structure of the wafer. S3: Establish a bidirectional mapping table, which includes: Forward mapping: Index ID → Physical coordinates → Screen pixel, realizing the mapping from index to pixel coordinates; Reverse mapping: screen pixels → physical coordinates → index ID + full Die information, realizing reverse lookup from pixel coordinates to index and Die information; S4: Based on a three-level sparse index, a bidirectional mapping table, and a visualization data model, wafer visualization drawing is performed using wafer drawing logic. The wafer drawing logic includes incremental drawing and block rendering with invalid die pre-elimination, dynamic rendering weight based on availability status, and adaptive clipping drawing of irregular edge dies. Combining the wafer bottom facet features, facet regions are automatically excluded during index construction, and facet contours are automatically adapted during drawing to avoid indexing and drawing invalid regions. S5: It adopts a multi-state linkage index-triggered drawing mechanism, using availability, yield, defect type, and test results as composite keys to build the index. During the query, it can filter and trigger the corresponding die drawing by any one or more composite conditions. For batch die status updates, the index is refreshed in real time, and only the die corresponding to the index is redrawn, without redrawing the entire wafer.

[0005] Preferably, in step S1, the information storage formats include TXT format, XML format, JSON format, and custom storage formats.

[0006] Preferably, in step S2, the dual-index collaborative logic of the arc edge adaptive index is as follows: the rectangular coordinate index is used to locate the die in the regular region inside the wafer, and the polar coordinate index is used to locate the die in the arc edge region of the wafer.

[0007] Preferably, in step S2, the hierarchical association logic of the three-level sparse index is as follows: the first-level index limits the range of the second-level index, and after the second-level index filters out rows containing valid dies, it is associated with the corresponding third-level index.

[0008] Preferably, in step S4, the specific logic for adaptive trimming and drawing of the irregular edge die is as follows: based on the circular outline of the wafer and the location of the die, determine whether the die is an irregular edge die. If it is an irregular edge die, then adaptively trim the die according to the circular outline of the wafer to draw an incomplete irregular die shape and restore the true physical shape of the die; if it is a non-iron die, then draw a complete rectangular die.

[0009] Preferably, in step S4, the specific implementation of adapting the bottom section of the wafer is as follows: during index construction, the position of the bottom section of the wafer is automatically identified, all dies within the section area are excluded, and no index is generated for that area; during drawing, the drawing logic of the corresponding area is automatically adjusted according to the bottom section outline to accurately adapt the section shape.

[0010] Preferably, in step S5, the construction logic of the composite key index is as follows: the four parameters of availability, yield, defect type and test result are combined as composite index keys, each composite key corresponds to a group of dies, and when querying, inputting any one or more parameters can filter out the corresponding dies and trigger drawing.

[0011] Preferably, in step S4, the incremental rendering logic for invalid die pre-removal is as follows: before rendering, valid dies are selected through a three-level sparse index, invalid dies, blank placeholder dies, and sectional area dies are pre-removed, and incremental rendering is performed only on valid dies. Block rendering divides the valid area of ​​the wafer into multiple independent blocks for rendering.

[0012] Compared with the prior art, the beneficial effects of the present invention are: 1. Based on the actual wafer scale, a visualization data model is built, integrating core information from all dimensions such as wafer basics, size, rows and columns, and die distribution. With the collaborative design of polar coordinates and rectangular coordinates and the adaptive clipping and drawing logic of irregular edge dies, it can accurately restore the real physical shape of the wafer and the actual outline of the edge dies. It effectively solves the problems of wafer shape not matching the actual physical structure and edge die drawing distortion in traditional visualization solutions, and greatly improves the accuracy and realism of wafer visualization.

[0013] 2. A three-level sparse index structure is constructed, which includes a wafer valid area mask, row block index, and die-level index. Combined with the design of automatically excluding the bottom sectional area of ​​the wafer during index construction, the system can accurately pre-remove invalid areas, blank placeholder dies, and sectional area dies. This reduces the computation and rendering overhead of invalid data from the source, effectively reduces system resource consumption, and solves the problems of low rendering efficiency and system lag caused by full rendering in traditional wafer visualization.

[0014] 3. Establish a bidirectional mapping between index ID → physical coordinates → screen pixels and a reverse mapping between screen pixels → physical coordinates → index ID + full Die information. This enables bidirectional and fast mutual lookup of pixel coordinates with Die physical information and index information, allowing for accurate location of full Die information corresponding to any pixel. This solves the problems of pixel location without Die information and low Die information query efficiency in traditional visualization solutions, significantly improving the accuracy of wafer data location and query.

[0015] 4. An incremental drawing and block rendering mechanism with invalid die pre-removal is adopted. For batch die state updates, only the corresponding index area is redrawn, rather than the entire wafer is redrawn. This reduces unnecessary rendering operations and achieves efficient block rendering of wafer data. It solves the problem of slow response and high resource consumption caused by the need for full redrawing for batch state updates in traditional visualization solutions, and greatly improves the response speed and rendering efficiency of wafer drawing.

[0016] 5. An index is built using availability, yield, defect type, and test results as composite keys. It supports filtering based on single or multiple conditions and quickly triggers the corresponding die drawing. Combined with a multi-state linkage index-triggered drawing mechanism, it enables rapid filtering and visualization of multi-dimensional wafer data. This solves the problems of single filtering dimensions and slow response to batch data updates in traditional visualization solutions, effectively improving the convenience and efficiency of data analysis and status monitoring in the wafer production process.

[0017] In summary, this invention achieves accurate visualization of the true scale of wafers and efficient data processing, with the advantages of simple implementation and high efficiency. It solves the problem of redundant calculation in invalid areas through three-level sparse indexing and cross-section exclusion, solves the problem of shape rendering distortion through dual-coordinate indexing and adaptive clipping, solves the problem of inefficient precise positioning and information query through bidirectional mapping table, solves the problem of full-scale rendering lag through incremental redrawing and block rendering, and solves the problem of inefficient multi-condition filtering and batch updates through composite key indexing. It avoids the problems of shape distortion, rendering lag, slow query and resource waste caused by the technical limitations of traditional wafer visualization. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall structure of a visualization data processing method based on the actual wafer ratio proposed in this invention. Figure 2 This is a schematic diagram illustrating the workflow of a visualization data processing method based on the actual wafer ratio proposed in this invention. Figure 3 This is a schematic diagram of a three-level sparse index structure for a visualization data processing method based on the actual wafer ratio proposed in this invention. Figure 4This is a schematic diagram of the default state of a wafer in a visualization data processing method based on the actual wafer ratio proposed in this invention. Figure 5 This is a schematic diagram of the wafer working state of a visualization data processing method based on the actual wafer ratio proposed in this invention. Detailed Implementation

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the examples in the specification.

[0020] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0021] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0022] Unless otherwise specified, all raw materials used in the examples were commercially purchased.

[0023] like Figures 1-5 As shown, this application discloses a visualization data processing method based on the actual wafer scale, including the entire process of constructing a visualization data model, constructing a hierarchical sparse index, establishing a dual mapping table, visualization drawing, and precise positioning: S1: Construct a visualization data model based on the actual wafer scale. The visualization data model includes basic wafer information, wafer size information, wafer row and column information, die size information, and die distribution information. The basic wafer information includes wafer type, wafer model, type name, product name, and description information. The wafer size information includes size specifications, total number of dies that can be deployed within the area, total number of effective dies within the area, wafer size radius value, and bottom facet position. The wafer row and column information includes descriptions of the row and column where the die is located. The die size information includes the width, height, and spacing between dies. The die distribution information includes a description of the association between the die number and the row and column information, and a description of whether the die is available. S2: Based on the visual data model constructed in step S1, establish a wafer-specific three-level sparse index structure, which includes: First-level index: Wafer effective area mask, which only marks the effective areas within the wafer arc, non-cut-out areas, and non-keep areas, and excludes invalid areas; Secondary index: Row block index, which only stores rows containing valid dies and skips rows that are completely invalid; Level 3 index: Die-level index, which stores only valid dies and defective dies, skipping blank placeholder dies; at the same time, combined with the circular outline characteristics of the wafer, it adopts a circular edge adaptive index design with dual indexes of polar coordinates and rectangular coordinates to adapt to the circular structure of the wafer. S3: Establish a bidirectional mapping table, which includes: Forward mapping: Index ID → Physical coordinates → Screen pixel, realizing the mapping from index to pixel coordinates; Reverse mapping: screen pixels → physical coordinates → index ID + full Die information, realizing reverse lookup from pixel coordinates to index and Die information; S4: Based on a three-level sparse index, a bidirectional mapping table, and a visualization data model, wafer visualization drawing logic is used for wafer drawing. The wafer drawing logic includes incremental drawing and block rendering with invalid die pre-elimination, dynamic rendering weight based on availability status, and adaptive clipping drawing of irregular edge dies. Combining the wafer bottom facet features, facet regions are automatically excluded during index construction and automatically adapted to the facet contours during drawing to avoid indexing and drawing invalid regions. S5: It adopts a multi-state linkage index-triggered drawing mechanism, using availability, yield, defect type, and test results as composite keys to build the index. During the query, it can filter and trigger the corresponding die drawing by any one or more composite conditions. For batch die status updates, the index is refreshed in real time, and only the die corresponding to the index is redrawn, without redrawing the entire wafer.

[0024] In the above implementation, in step S1, the information storage formats include TXT format, XML format, JSON format and custom storage format. In step S2, the dual-index collaborative logic of the arc edge adaptive index is as follows: the rectangular coordinate index is used to locate the die in the regular area inside the wafer, and the polar coordinate index is used to locate the die in the arc edge area of ​​the wafer.

[0025] In step S2, the hierarchical association logic of the three-level sparse index is as follows: the first-level index (wafer effective area mask) limits the range of the second-level index (row block index), and after the second-level index filters out rows containing effective dies, it is associated with the corresponding third-level index (die-level index).

[0026] like Figures 4-5As shown, in a preferred embodiment, the specific logic for adaptive trimming and drawing of the irregular edge die in step S4 is as follows: Based on the circular outline of the wafer and the location of the die, it is determined whether the die is an irregular edge die. If it is an irregular edge die, the die is adaptively trimmed according to the circular outline of the wafer to draw an incomplete irregular die shape, restoring the true physical shape of the die; if it is a non-edge die, a complete rectangular die is drawn. The automatic calculation method for the effective display area of ​​the die is as follows: A physical coordinate system is established with the wafer center as the origin. The coordinates of the four vertices of the Die rectangle are calculated based on the center coordinates, width, and height of the Die. The validity of each vertex is determined, and vertices located within the valid area of ​​the wafer are retained. For each side of the Die rectangle, the intersection points with the wafer arc and the bottom tangent are calculated, and the valid intersection points are added to the vertex set. The valid vertices and valid intersection points are connected in sequence to form a closed polygon, which serves as the real valid display area of ​​the Die.

[0027] Sort the "valid vertices + valid intersections" clockwise / counterclockwise to obtain a closed polygon: if the die data is inside, it is still a rectangle; if the die data is on the edge, the polygon is cut with arcs. The dies near the bottom face are directly clipped with flat edges to create polygons. If the die data is at the edge, it is affected by both the edge and the cut surface, resulting in a combined clipping polygon. This polygon is the actual and effective display area that the die should be drawn in the visualization.

[0028] In step S3, Sw is the width of the screen display area in pixels; k is the coordinate scaling ratio in pixels / mm, and k=2Sw. Forward mapping: The wafer physical coordinates (x, y) of the corresponding die are calculated using the wafer die index ID. These wafer physical coordinates are then converted to screen pixel coordinates (X, Y). The conversion formula is as follows: X = Sw / 2 + kx, Y = Sw / 2 - ky; Reverse mapping: Screen pixel coordinates → Physical coordinates → Index ID and complete Die information. The inverse transformation formula for the reverse retrieval mapping is as follows: x=(kX-Sw / 2) / k,y=(Sw / 2-Y) / k, For any screen pixel coordinates (X,Y), the wafer physical coordinates (x,y) are first obtained by inverse transformation. Then, the obtained wafer physical coordinates (x,y) are matched to obtain the corresponding Die index ID and complete Die attribute information, realizing the reverse retrieval mapping from screen pixel to Die index and complete information.

[0029] In the above implementation, the Y-axis is inverted because downward is positive in the screen coordinate system.

[0030] In step S4, the specific implementation of adapting the bottom facet of the wafer is as follows: during index construction, the position of the bottom facet of the wafer is automatically identified, all dies within the facet area are excluded, and no index is generated for that area; during drawing, the drawing logic of the corresponding area is automatically adjusted according to the bottom facet outline to accurately adapt the facet shape. In step S5, the construction logic of the composite key index is as follows: the four parameters of availability, yield, defect type, and test result are combined as composite index keys, and each composite key corresponds to a group of dies. When querying, inputting any one or more parameters can filter out the corresponding dies and trigger drawing.

[0031] In the above implementation, the specific logic of incremental drawing for invalid die pre-removal in step S4 is as follows: before drawing, valid dies are selected by three-level sparse index, invalid dies, blank placeholder dies and sectional area dies are pre-removed, and incremental drawing is performed only on valid dies. Block rendering divides the valid area of ​​the wafer into multiple independent blocks.

[0032] In summary, this invention achieves accurate visualization of the true scale of wafers and efficient data processing, with the advantages of simple implementation and high efficiency. It solves the problem of redundant calculation in invalid areas through a three-level sparse index and cross-section exclusion, solves the problem of shape rendering distortion through dual-coordinate index and adaptive clipping, solves the problem of inefficient precise positioning and information query through a bidirectional mapping table, solves the problem of full-scale rendering lag through incremental redrawing and block rendering, and solves the problem of inefficient multi-condition filtering and batch updates through composite key index. It avoids the problems of shape distortion, rendering lag, slow query and resource waste caused by the technical limitations of traditional wafer visualization.

[0033] It should be noted that the foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A visualization data processing method based on the actual wafer scale, comprising model construction, sparse index construction, and mapping table establishment, characterized in that: S1: Construct a visual data model, which includes specific information about the wafer; The specific information mentioned includes: availability, yield, defect type, and test results; S2: Based on step S1, establish a three-level sparse index structure, which includes: Primary index: Wafer valid area mask, excluding invalid areas; Secondary index: Row block index, which only stores rows containing valid dies and skips invalid rows; Third-level index: Die-level index, which only stores valid dies and defective dies, skipping blank placeholder dies; In step S2, the three-level index combines the characteristics of the wafer's circular outline and adopts a dual-index design of polar coordinates and rectangular coordinates for the arc edge adaptive index to adapt to the wafer's circular structure. The operating logic of the arc edge adaptive index is as follows: the rectangular coordinate index is used to locate the die in the regular area inside the wafer, and the polar coordinate index is used to locate the die in the arc edge area of ​​the wafer. S3: Establish a bidirectional mapping table, which includes forward mapping and reverse mapping. The forward mapping is a mapping from index to pixel coordinates, and the reverse mapping is a reverse lookup from pixel coordinates to index and Die information. S4: Based on the aforementioned steps, wafer rendering logic is used for wafer visualization rendering. The wafer rendering logic includes incremental rendering with invalid die pre-removal, block rendering, and adaptive clipping rendering of irregular edge dies. Combined with the wafer bottom facet features, the facet area is excluded during index construction, and the facet outline is adapted during rendering to avoid rendering invalid areas. The adaptive trimming and drawing logic for edge irregular dies in step S4 is as follows: Based on the circular outline of the wafer and the location of the die, determine whether the die is an edge irregular die. If it is an edge irregular die, then adaptively trim the die according to the circular outline of the wafer to draw an incomplete irregular die shape and restore the true physical shape of the die; if it is a non-edge die, then draw a complete rectangular die shape. S5: It adopts an index-triggered drawing mechanism, using the specific information of the wafer as a composite key to build an index. During the query, it filters according to the conditions and triggers the drawing of the corresponding die.

2. The visualization data processing method based on the actual wafer ratio according to claim 1, characterized in that, In step S2, the first-level index in the sparse index construction is a wafer effective region mask, which only marks the effective regions within the wafer arc, non-cut-out regions, and non-forbidden regions, and excludes invalid regions. The hierarchical association logic of the third-level sparse index is as follows: the first-level index limits the range of the second-level index, and after the second-level index filters out rows containing effective dies, it is associated with the corresponding third-level index.

3. The visualization data processing method based on the actual wafer scale according to claim 1, characterized in that, The operating logic for adapting the facet contour in step S4 is as follows: When constructing the index, the bottom facet position of the wafer is automatically identified, all dies within the facet area are excluded, and no index is generated for that area; when drawing, the drawing logic of the corresponding area is automatically adjusted according to the bottom facet contour to adapt to the facet shape.

4. The visualization data processing method based on the actual wafer ratio according to claim 1, characterized in that, The rendering logic for invalid die pre-removal in step S4 is as follows: Before rendering, valid dies are filtered out by a three-level sparse index, and invalid dies, blank placeholder dies, and sectional area dies are pre-removed. Only valid dies are rendered incrementally. The block rendering divides the valid area of ​​the wafer into multiple independent blocks for rendering.

5. The visualization data processing method based on the actual wafer scale according to claim 1, characterized in that, The operating logic of the index-triggered drawing mechanism in step S5 is as follows: the four wafer-specific information parameters, namely availability, yield, defect type, and test result, are combined as a composite index key. Each composite key corresponds to a set of dies. When querying, one or more of the above parameters can be entered to filter out the corresponding dies and view and draw them.

6. The visualization data processing method based on the actual wafer scale according to claim 1, characterized in that, The information storage formats used in the model construction include TXT, XML, JSON, and custom storage formats.

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