An artificial intelligence-based chip manufacturing process error online monitoring method

Abstract

The application discloses a chip manufacturing process error online monitoring method based on artificial intelligence, and belongs to the technical field of chip manufacturing process monitoring. First, internal timing characteristic data of chips to be stacked and independently tested is collected, batches are grouped, and process scene labels are marked to construct an initial timing characteristic baseline library. After selecting a stacking combination, the chip timing characteristic matching degree and the conflict index are calculated based on the baseline library to generate a cross-layer timing offset representing the cross-layer signal transmission timing deviation. Then, historical stacking data of the same process scene is filtered to construct an error association dataset, the offset is classified by error source, the dominant error type is determined, and the offset contribution probability of each error source is calculated. Finally, the offset is compared with the preset timing margin, the contribution probability, the offset proportion and the conflict index are combined to evaluate the chip pairing risk level, high-risk schemes are screened, core error nodes are marked, and a chip stacking error detection report is generated.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing process monitoring technology, specifically an online monitoring method for chip manufacturing process errors based on artificial intelligence. Background Technology

[0002] 3D stacked chips are two chips with different processes and designs stacked and connected to each other by stacking them one on top of the other. The high-density interconnection between the upper and lower layers of chips can achieve performance improvement and size reduction. The manufacturing process requires key steps such as independent chip testing, pairing and screening, and bonding interconnection. In this process, process error control directly affects the stability and performance limit of the chip system.

[0003] In existing technologies, the manufacturing and testing of upper and lower layer chips are mostly carried out independently, focusing only on the parameter compliance of a single chip and ignoring the error problems caused by cross-layer coordination mismatch after stacking. These errors are not caused by the obvious defects of a single chip, but rather by the incompatibility of their performance characteristics. Even if the upper and lower layer chips meet their respective specifications in independent testing, due to the inherent differences or mutual exclusions in their timing and electrical characteristics such as signal setup / hold time, clock to output delay, and noise margin, after actual stacking, they will cause serious timing offsets, synchronization failures, and other signal faults through parasitic effects of vertical interconnects, impedance discontinuities, and changes in signal return paths.

[0004] Current process error monitoring solutions mostly focus on the detection of local parameters in a single process or chip, which are local and static quality control methods. They lack the ability to analyze and predict the correlation between signal behavior before and after stacking. Therefore, existing methods cannot effectively predict the risk of chip pairing failure due to signal feature mismatch before the physical bonding process is performed. Problems can only be found during system testing after stacking, resulting in difficult debugging, high rework costs, and limited yield improvement. Summary of the Invention

[0005] The purpose of this invention is to provide an online monitoring method for chip manufacturing process errors based on artificial intelligence, so as to solve the problems mentioned in the background art.

[0006] To address the aforementioned technical problems, this invention provides the following technical solution: an online monitoring method for chip manufacturing process errors based on artificial intelligence, comprising the following steps: Step S100: Collect internal timing feature data of the upper and lower layer chips to be stacked during independent testing, divide the data sets according to chip manufacturing batches, label each data set with the corresponding process scenario label, and build an initial timing feature baseline library; Step S200: When the upper and lower layer chips are selected as the combination to be stacked, the matching degree and conflict index of the timing characteristics of the two are calculated based on the initial timing feature baseline library to generate a preliminary cross-layer timing offset; the cross-layer timing offset represents the deviation of the transmission signal between the upper layer chip and the lower layer chip to be stacked from the reference value in timing. Step S300: Filter historical stacking data with the same process scenario as the chips to be stacked, including qualified pairing data, failed pairing data and corresponding process parameter records, to construct an error association dataset; classify the error sources of the initially generated cross-layer timing offsets, determine the dominant error type, and calculate the offset contribution probability of each type of error source; the offset contribution probability represents the probability value that the offset is caused by a certain type of error source when the chips to be stacked generate cross-layer timing offsets. Step S400: Compare the cross-layer timing offset with the preset timing margin, and evaluate the chip pairing risk level by combining the error source contribution probability, offset ratio and conflict index. Select high-risk chip pairing schemes, mark the core error nodes, and generate a chip stacking error detection report.

[0007] Step S100 includes: Step S101: Collect internal timing characteristic data of the upper and lower layer chips to be stacked in independent test mode in parallel using an automatic test device; denote the upper layer chip as chip A and the lower layer chip as chip B; the timing characteristic data includes at least signal path delay time, input and output circuit drive values, and signal rise and fall edge times; Step S102: Group the collected time-series feature data according to chip manufacturing batches, and label each batch data set with a corresponding process scenario label, the process scenario label including process manufacturing node, manufacturing cycle, and test temperature conditions; For each dataset, the mean, standard deviation, peak threshold, and fluctuation range of the time-series feature parameters are calculated to construct an initial time-series feature baseline library. Each baseline in the baseline library is associated with the manufacturing batch and process scenario label of the corresponding dataset.

[0008] Step S200 includes: Step S201: Retrieve baseline data for the corresponding batches and process scenarios of the upper and lower layer chips to be stacked from the initial timing feature baseline library; extract the mean value of the i core timing feature parameters of chip A, and construct the parameter matrix MA=[a1,a2,…,a…] of chip A. i Extract the mean values ​​of the i core timing feature parameters of chip B, and construct the parameter matrix MB=[b1,b2,…,b] of chip B. i ]; where a i Let b be the mean of the i-th timing characteristic parameter of chip A. iLet be the mean value of the i-th timing characteristic parameter of chip B; Step S202: Calculate the timing feature matching degree between chip A and chip B: Where n is the number of time-series feature parameters, and the closer the time-series feature matching degree is to 1, the stronger the time-series adaptability between the two. Step S203: For each timing characteristic parameter, calculate the difference between the mean values ​​of the corresponding parameters of chip A and chip B, and then compare it with the maximum value of the baseline fluctuation range of that timing characteristic parameter to obtain the conflict value of a single timing characteristic parameter. The formula is: C i =(|a i -b i |) / M i M i The maximum value of the baseline fluctuation range of the i-th parameter is taken, and then the weighted average of the conflict values ​​of all parameters is taken to obtain the final parameter conflict index C. The closer the index is to 1, the more serious the parameter conflict is. Step S204: Combining the temporal feature matching degree S and the parameter conflict index C, a temporal error correction coefficient α is introduced to calculate the cross-layer temporal offset: ΔT=α×(w1×(1-S)×T) ref +w2×C×σ), where ΔT is the preliminary estimated cross-layer temporal offset; α is the error correction coefficient, w1 and w2 are the weighting coefficients of the temporal feature mismatch term and the parameter conflict term, respectively, and w1+w2=1; T ref The mean signal path delay time corresponding to the current process scenario is extracted from the initial timing feature baseline library, and σ is the standard deviation of the signal path delay time under the corresponding process scenario. The error correction coefficient α is obtained by extracting chip pairing records that have been stacked under the same process scenario from the chip manufacturing history database, and obtaining the measured cross-layer timing offset ΔT. real And calculate the uncorrected estimate ΔT; fit ΔT by linear regression. real Using ΔT, we obtain the correction coefficient α for this process scenario.

[0009] Step S300 includes: Step S301: From the chip manufacturing history database, filter historical stacked chip data that are in the same process scenario (same manufacturing node, manufacturing cycle, test temperature) as the chips to be stacked, and divide them into two subsets: Qualified pairing data subset Dpass: Filters chip pairing records in historical stacked chips where the actual cross-layer timing offset obtained from actual testing is ≤ the preset timing margin; Dfail, a subset of failed pairing data, filters chip pairing records in historical stacked chips where the actual cross-layer timing offset obtained from actual testing is greater than the preset timing margin. For each historical record in Dpass and Dfail, extract the time-series feature deviation data, process parameter fluctuation data, and stacking effect labels simultaneously; The time-series feature deviation data consists of the mean values ​​of each time-series feature parameter of chip A' and chip B' in historical pairings, forming an m-dimensional time-series deviation vector: ΔX={Δx1,Δx2,...,Δxm}, where Δxm=|xA'm-xB'm|; xA'm and xB'm are the batch mean values ​​of historical chips A' and B' on the m-th type of time-series feature, respectively; The process parameter fluctuation data is the set of key process parameter fluctuation ranges P={P1,P2,...,Pq} of historical chips A' and B' during the manufacturing process, where q is the total number of process parameters and Pq represents the fluctuation value of the qth type of process parameter in the corresponding manufacturing batch. The stacking effect label is the effect label L marked for each historical record, where the qualified pair label L=0 and the invalid pair label L=1; Step S302: Remove outliers from the three types of extracted data and standardize the process parameter records, mapping the parameter values ​​to the [0,1] interval; The preprocessed time-series feature deviation data, process parameter fluctuation data, and stacking effect labels are bound together to construct an error association dataset Derror. Each record in the dataset has the following format: Derror={(ΔXj,Pj,Lj)|j=1,2,...,N}; where N is the total number of preprocessed historical samples, ΔXj is the time-series deviation vector of the j-th record, Pj is the set of process parameter fluctuation values ​​of the j-th record, and Lj is the stacking effect label of the j-th record.

[0010] Step S303: For each record in the error association dataset Derror, concatenate the m-dimensional timing deviation vector ΔXj with the q-dimensional standardized process parameter fluctuation set Pk to form a (m+q)-dimensional fused feature vector Fj=[ΔXj, Pj]; combining chip manufacturing process and historical failure data, label all failure samples in Derror with error source type labels Ek. Error sources are divided into three types: Ek=1: inherent equipment error, caused by the precision limitations of manufacturing equipment and the deviation of testing instrument system; Ek=2: process fluctuation error, caused by the loss of control of process parameters; Ek=3: coupling superposition error, caused by the incompatibility of timing parameters between upper and lower layers of chips, which is unrelated to process parameters; among them, qualified samples are uniformly labeled as having no error source, Ek=0; Step S304: Construct an error source classification model, taking the fused feature vector Fj as input and outputting the probability distributions of three error sources: inherent equipment error, process fluctuation error, and coupled superposition error. The input layer uses a linear activation function; the feature extraction layer consists of two 1D convolutional layers and one BiLSTM layer. The convolutional layers extract locally related features, and the BiLSTM layer captures temporal dependencies. The attention weighting layer generates weight vectors through a channel attention mechanism to weight the BiLSTM output features. The classification output layer has three neurons, activated by Softmax, and outputs the probabilities of each error source. During model training, the dataset labeled with error source tags is stratified in a 7:2:1 ratio to form a training set, validation set, and test set. The Adam optimizer and cross-entropy loss function are used to optimize the parameters, with an initial learning rate of 0.001. Training is completed when the classification accuracy of the validation set is ≥95% for two consecutive rounds. For chips A and B to be stacked, their m-dimensional timing deviation vector and standardized q-dimensional process parameter fluctuation values ​​are extracted and concatenated into a feature vector to be tested. The input model outputs three types of error source probability distributions. The error source type corresponding to the maximum probability is taken as the dominant error source type of the chip to be stacked. Finally, the three types of error source probability distributions of the chip to be stacked are output, and the dominant error source type is determined. Step S305: Then calculate the offset contribution probability of each error source: ; Wherein, P(Ek|ΔT) is the offset contribution probability of the k-th error source; k=1,2,3, corresponding to three types of error sources: E1 is the inherent error of the equipment, E2 is the process fluctuation error, and E3 is the coupling superposition error; P(Ek) is the occurrence probability of the k-th error source, which is obtained by calculating the proportion of the number of samples of the k-th error source in the error association dataset Derror to the total number of failure samples; P(ΔT|Ek) is the conditional probability, which represents the probability that the cross-layer timing offset is ΔT under the premise that the k-th error source occurs. It is obtained by calculating the proportion of the number of samples in the error association dataset Derror where the absolute value of the difference between the actual cross-layer timing offset under the k-th error source and the cross-layer timing offset ΔT of the chip to be stacked is ≤±5% to the total number of samples of this type of error source; The final output is the error source analysis results, which clarifies the error source types of the current chip combination to be stacked, the offset contribution probability of each type of error source, and generates an error source analysis report.

[0011] Step S400 includes: Step S401: Based on the estimated cross-layer timing offset ΔT, the dominant error source type, and the error source offset contribution probability, first retrieve the preset timing margin T0 that matches the process scenario of the chip to be stacked, and calculate the offset ratio R=ΔT / T0. From the chip manufacturing historical database, historical qualified stacking samples that are completely consistent with the process scenario of the to-be-stacked chip are screened. For each sample, the ratio of the actual cross-layer timing offset to the preset timing margin is calculated, then the 95th percentile of this ratio of all samples is taken and set as the critical offset proportion value R0; the parameter conflict index C output in step S203 is synchronously extracted to perform error risk level determination: Level 1 low risk: R ≤ R0, and the parameter conflict index C is within the conventional fluctuation range of qualified samples in the same process scenario, while the contribution probability of the dominant error source is lower than the historical average occurrence probability, no adjustment is required, and the stacking process is directly executed; Level 2 medium-low risk: R ≤ R0, but the parameter conflict index C exceeds the conventional fluctuation range, and the dominant error source is the inherent equipment error. This type of pairing has a potential risk caused by slight equipment accuracy, so it is necessary to perform accuracy calibration on the corresponding manufacturing or testing equipment, and re-collect parameters and conduct review and evaluation after the calibration is completed; Level 3 medium-high risk: R0 < R ≤ 1.2R0, and the dominant error source is the process fluctuation error. The risk of this type of pairing is caused by process parameter fluctuations, so it is necessary to locate the specific out-of-control process and corresponding parameters, re-conduct the full-process evaluation after optimizing the parameter range; Level 4 high risk: R > 1.2R0, or the dominant error source is the coupling superposition error. This type of pairing either has a severely exceeded offset or essentially incompatible timing parameters, and stacking is directly prohibited, requiring re-screening of chip pairing combinations.

[0012] Step S402: According to the above risk level determination result, the level 1 low-risk pairs are included in the priority stacking list, the level 2 medium-low risk and level 3 medium-high risk pairs are included in the risk rectification list, and the level 4 high-risk pairs are included in the elimination list; for the pairs in the risk rectification list, the core error nodes are marked in combination with the dominant error source type and offset contribution probability, the inherent equipment error is marked with the corresponding equipment number and parameters to be calibrated, the process fluctuation error is marked with the out-of-control process and parameter items, the coupling superposition error is marked with the incompatible timing parameter dimensions, and the rectification priority is clarified by sorting according to the contribution probability; Step S403: Integrate the basic information of the to-be-stacked chip pairs, the offset proportion and parameter conflict index, the risk level, the pairing scheme screening result, the core error node mark and the rectification suggestions, generate a standardized inspection report, and synchronously archive the report to the chip manufacturing historical database.

[0013] Compared with the prior art, the beneficial effects achieved by the present invention are: 1. This invention constructs a baseline library by collecting independent chip test timing feature data, extracts core parameters such as signal path delay and edge time, and generates cross-layer timing offset by combining matching degree and conflict index; effectively quantifies the signal transmission timing deviation between chips, solves the defect of traditional technology that only focuses on single chip parameters and ignores cross-layer signal adaptability, and realizes the advance prediction of implicit signal errors; 2. This invention constructs an error correlation dataset based on historical data, generates feature vectors by fusing time-series deviations and process parameters, and achieves accurate classification of error sources based on a classification model; it breaks through the limitations of traditional local detection, and can quickly locate three types of error sources: equipment, process, and coupled superposition, providing a clear direction for targeted rectification and improving the accuracy of error analysis; 3. This invention calculates the offset contribution probability and quantifies the impact of various error sources on signal timing offset. Compared with the existing fuzzy error tracing method, it can identify the core error and prioritize the handling of high-impact error nodes, further ensuring the stability of signal transmission after stacking. At the same time, this invention integrates multi-dimensional indicators to evaluate the chip pairing risk level, screens high-risk solutions and archives reports. Risk control can be completed before bonding, avoiding rework losses after stacking, and effectively improving the manufacturing yield and capacity of 3D stacked chips. Attached Figure Description

[0014] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of an online monitoring method for chip manufacturing process errors based on artificial intelligence. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Please see Figure 1 This invention provides a technical solution: an online monitoring method for chip manufacturing process errors based on artificial intelligence, comprising the following steps: Step S100: Collect internal timing feature data of the upper and lower layer chips to be stacked during independent testing, divide the data sets according to chip manufacturing batches, label each data set with the corresponding process scenario label, and build an initial timing feature baseline library; Step S200: When the upper and lower layer chips are selected as the combination to be stacked, the matching degree and conflict index of the timing characteristics of the two are calculated based on the initial timing feature baseline library to generate a preliminary cross-layer timing offset; the cross-layer timing offset represents the deviation of the transmission signal between the upper layer chip and the lower layer chip to be stacked from the reference value in timing. Step S300: Filter historical stacking data with the same process scenario as the chips to be stacked, including qualified pairing data, failed pairing data and corresponding process parameter records, to construct an error association dataset; classify the error sources of the initially generated cross-layer timing offsets, determine the dominant error type, and calculate the offset contribution probability of each type of error source; the offset contribution probability represents the probability value that the offset is caused by a certain type of error source when the chips to be stacked generate cross-layer timing offsets. Step S400: Compare the cross-layer timing offset with the preset timing margin, and evaluate the chip pairing risk level by combining the error source contribution probability, offset ratio and conflict index. Select high-risk chip pairing schemes, mark the core error nodes, and generate a chip stacking error detection report.

[0017] Step S100 includes: Step S101: Collect internal timing characteristic data of the upper and lower layer chips to be stacked in independent test mode in parallel using an automatic test device; denote the upper layer chip as chip A and the lower layer chip as chip B; the timing characteristic data includes at least signal path delay time, input and output circuit drive values, and signal rise and fall edge times; Step S102: Group the collected time-series feature data according to chip manufacturing batches, and label each batch data set with a corresponding process scenario label, the process scenario label including process manufacturing node, manufacturing cycle, and test temperature conditions; For each dataset, the mean, standard deviation, peak threshold, and fluctuation range of the time-series feature parameters are calculated to construct an initial time-series feature baseline library. Each baseline in the baseline library is associated with the manufacturing batch and process scenario label of the corresponding dataset.

[0018] Step S200 includes: Step S201: Retrieve baseline data for the corresponding batches and process scenarios of the upper and lower layer chips to be stacked from the initial timing feature baseline library; extract the mean value of the i core timing feature parameters of chip A, and construct the parameter matrix MA=[a1,a2,…,a…] of chip A. i Extract the mean values ​​of the i core timing feature parameters of chip B, and construct the parameter matrix MB=[b1,b2,…,b] of chip B. i ]; where a i Let b be the mean of the i-th timing characteristic parameter of chip A. iLet be the mean value of the i-th timing characteristic parameter of chip B; Step S202: Calculate the timing feature matching degree between chip A and chip B: Where n is the number of time-series feature parameters, and the closer the time-series feature matching degree is to 1, the stronger the time-series adaptability between the two. Step S203: For each timing characteristic parameter, calculate the difference between the mean values ​​of the corresponding parameters of chip A and chip B, and then compare it with the maximum value of the baseline fluctuation range of that timing characteristic parameter to obtain the conflict value of a single timing characteristic parameter. The formula is: C i =(|a i -b i |) / M i M i The maximum value of the baseline fluctuation range of the i-th parameter is taken, and then the weighted average of the conflict values ​​of all parameters is taken to obtain the final parameter conflict index C. The closer the index is to 1, the more serious the parameter conflict is. Step S204: Combining the temporal feature matching degree S and the parameter conflict index C, a temporal error correction coefficient α is introduced to calculate the cross-layer temporal offset: ΔT=α×(w1×(1-S)×T) ref +w2×C×σ), where ΔT is the preliminary estimated cross-layer temporal offset; α is the error correction coefficient, w1 and w2 are the weighting coefficients of the temporal feature mismatch term and the parameter conflict term, respectively, and w1+w2=1; T ref The mean signal path delay time corresponding to the current process scenario is extracted from the initial timing feature baseline library, and σ is the standard deviation of the signal path delay time under the corresponding process scenario. The error correction coefficient α is obtained by extracting chip pairing records that have been stacked under the same process scenario from the chip manufacturing history database, and obtaining the measured cross-layer timing offset ΔT. real And calculate the uncorrected estimate ΔT; fit ΔT by linear regression. real Using ΔT, we obtain the correction coefficient α for this process scenario.

[0019] Step S300 includes: Step S301: From the chip manufacturing history database, filter historical stacked chip data that are in the same process scenario (same manufacturing node, manufacturing cycle, test temperature) as the chips to be stacked, and divide them into two subsets: Qualified pairing data subset Dpass: Filters chip pairing records in historical stacked chips where the actual cross-layer timing offset obtained from actual testing is ≤ the preset timing margin; Dfail, a subset of failed pairing data, filters chip pairing records in historical stacked chips where the actual cross-layer timing offset obtained from actual testing is greater than the preset timing margin. For each historical record in Dpass and Dfail, extract the time-series feature deviation data, process parameter fluctuation data, and stacking effect labels simultaneously; The time-series feature deviation data consists of the mean values ​​of each time-series feature parameter of chip A' and chip B' in historical pairings, forming an m-dimensional time-series deviation vector: ΔX={Δx1,Δx2,...,Δxm}, where Δxm=|xA'm-xB'm|; xA'm and xB'm are the mean values ​​of historical chips A' and B' on the m-th type of time-series feature, respectively; The process parameter fluctuation data is the set of key process parameter fluctuation ranges P={P1,P2,...,Pq} of historical chips A' and B' during the manufacturing process, where q is the total number of process parameters and Pq represents the fluctuation value of the qth type of process parameter in the corresponding manufacturing batch. The stacking effect label is the effect label L marked for each historical record, where the qualified pair label L=0 and the invalid pair label L=1; Step S302: Remove outliers from the three types of extracted data and standardize the process parameter records, mapping the parameter values ​​to the [0,1] interval; The preprocessed time-series feature deviation data, process parameter fluctuation data, and stacking effect labels are bound together to construct an error association dataset Derror. Each record in the dataset has the following format: Derror={(ΔXj,Pj,Lj)|j=1,2,...,N}; where N is the total number of preprocessed historical samples, ΔXj is the time-series deviation vector of the j-th record, Pj is the set of process parameter fluctuation values ​​of the j-th record, and Lj is the stacking effect label of the j-th record.

[0020] Step S303: For each record in the error association dataset Derror, concatenate the m-dimensional timing deviation vector ΔXj with the q-dimensional standardized process parameter fluctuation set Pk to form a (m+q)-dimensional fused feature vector Fj=[ΔXj, Pj]; combining chip manufacturing process and historical failure data, label all failure samples in Derror with error source type labels Ek. Error sources are divided into three types: Ek=1: inherent equipment error, caused by the precision limitations of manufacturing equipment and the deviation of testing instrument system; Ek=2: process fluctuation error, caused by the loss of control of process parameters; Ek=3: coupling superposition error, caused by the incompatibility of timing parameters between upper and lower layers of chips, which is unrelated to process parameters; among them, qualified samples are uniformly labeled as having no error source, Ek=0; Step S304: Construct an error source classification model, taking the fused feature vector Fj as input and outputting the probability distributions of three error sources: inherent equipment error, process fluctuation error, and coupled superposition error. The input layer uses a linear activation function; the feature extraction layer consists of two 1D convolutional layers and one BiLSTM layer. The convolutional layers extract locally related features, and the BiLSTM layer captures temporal dependencies. The attention weighting layer generates weight vectors through a channel attention mechanism to weight the BiLSTM output features. The classification output layer has three neurons, activated by Softmax, and outputs the probabilities of each error source. During model training, the dataset labeled with error source tags is stratified in a 7:2:1 ratio to form a training set, validation set, and test set. The Adam optimizer and cross-entropy loss function are used to optimize the parameters, with an initial learning rate of 0.001. Training is completed when the classification accuracy of the validation set is ≥95% for two consecutive rounds. For chips A and B to be stacked, their m-dimensional timing deviation vector and standardized q-dimensional process parameter fluctuation values ​​are extracted and concatenated into a feature vector to be tested. The input model outputs three types of error source probability distributions. The error source type corresponding to the maximum probability is taken as the dominant error source type of the chip to be stacked. Finally, the three types of error source probability distributions of the chip to be stacked are output, and the dominant error source type is determined. Step S305: Then calculate the offset contribution probability of each error source: ; Wherein, P(Ek|ΔT) is the offset contribution probability of the k-th error source; k=1,2,3, corresponding to three types of error sources: E1 is the inherent error of the equipment, E2 is the process fluctuation error, and E3 is the coupling superposition error; P(Ek) is the occurrence probability of the k-th error source, which is obtained by calculating the proportion of the number of samples of the k-th error source in the error association dataset Derror to the total number of failure samples; P(ΔT|Ek) is the conditional probability, which represents the probability that the cross-layer timing offset is ΔT under the premise that the k-th error source occurs. It is obtained by calculating the proportion of the number of samples in the error association dataset Derror where the absolute value of the difference between the actual cross-layer timing offset under the k-th error source and the cross-layer timing offset ΔT of the chip to be stacked is ≤±5% to the total number of samples of this type of error source; The final output is the error source analysis results, which clarifies the error source types of the current chip combination to be stacked, the offset contribution probability of each type of error source, and generates an error source analysis report.

[0021] Step S400 includes: Step S401: Based on the estimated cross-layer timing offset ΔT, the dominant error source type, and the error source offset contribution probability, first retrieve the preset timing margin T0 that matches the process scenario of the chip to be stacked, and calculate the offset ratio R=ΔT / T0. From the chip manufacturing historical database, historical qualified stacking samples that are completely consistent with the process scenario of the to-be-stacked chips are screened. For each sample, the ratio of the actual cross-layer timing offset to the preset timing margin is calculated, then the 95th percentile of this ratio for all samples is taken and set as the offset proportion threshold R0; the parameter conflict index C output in step S203 is synchronously extracted to perform error risk level determination: Level 1 low risk: R ≤ R0, and the parameter conflict index C is within the conventional fluctuation range of qualified samples in the same process scenario, while the contribution probability of the dominant error source is lower than the historical average occurrence probability, no adjustment is required, and the stacking process is directly executed; Level 2 medium-low risk: R ≤ R0, but the parameter conflict index C exceeds the conventional fluctuation range, and the dominant error source is the inherent equipment error. This type of pairing has a potential risk caused by slight equipment accuracy, so it is necessary to perform accuracy calibration on the corresponding manufacturing or test equipment, and re-collect parameters for re-evaluation after the calibration is completed; Level 3 medium-high risk: R0 < R ≤ 1.2R0, and the dominant error source is process fluctuation error. The risk of this type of pairing is caused by process parameter fluctuation, so it is necessary to locate the specific out-of-control process and corresponding parameters, and re-conduct the full-process evaluation after optimizing the parameter range; Level 4 high risk: R > 1.2R0, or the dominant error source is coupling superposition error. This type of pairing either has a seriously excessive offset, or the timing parameters are essentially incompatible, stacking is directly prohibited, and the chip pairing combination needs to be re-screened.

[0022] Step S402: According to the above risk level determination results, the level 1 low-risk pairs are included in the priority stacking list, the level 2 medium-low risk and level 3 medium-high risk pairs are included in the risk rectification list, and the level 4 high-risk pairs are included in the elimination list; for the pairs in the risk rectification list, core error nodes are marked in combination with the dominant error source type and offset contribution probability: mark the corresponding equipment number and parameters to be calibrated for the inherent equipment error, mark the out-of-control process and parameter items for the process fluctuation error, mark the incompatible timing parameter dimension for the coupling superposition error, and clarify the rectification priority by sorting according to the contribution probability; Step S403: Integrate the basic information of the to-be-stacked chip pairs, the offset proportion and parameter conflict index, the risk level, the pairing scheme screening result, the core error node mark and the rectification suggestions, generate a standardized test report, and archive the report synchronously to the chip manufacturing historical database.

[0023] This embodiment takes the 3D stacking process of a 28nm logic chip (upper chip A) and a 14nm memory chip (lower chip B) as an example: First, independent timing characteristic data of chip A and chip B are collected in parallel using an automated testing device. Chips A and B both come from the same manufacturing cycle, and the test temperature is 25℃. The collected timing characteristic data includes: signal path delay time, input and output circuit drive value, signal rise edge time, and signal fall edge time, a total of 4 core indicators. Data is grouped by manufacturing batch: Chip A is batch 20260108-01, and Chip B is batch 20260108-02; Process scenario tags are added: 28nm / 14nm manufacturing node, manufacturing cycle of week 1, 2026, and test temperature of 25℃; Statistical values ​​are calculated for each group of data: mean signal path delay time T. ref =80ps, standard deviation σ=5ps, mean input and output driving value 1.2V, fluctuation range 0.1V, mean rise / fall edge time 12ps and 10ps respectively, construct an initial time series feature baseline library, and associate the corresponding batch and scene labels; Retrieve the corresponding batch data from the baseline library, extract the average values ​​of the four core timing parameters of chips A and B, and construct parameter matrices MA=[80ps,1.2V,12ps,10ps] and MB=[78ps,1.18V,11ps,9.5ps]; The timing feature matching degree S was calculated, and the result was S=0.98, indicating that the timing compatibility between the two is good. The conflict value of individual parameters was calculated; taking signal path delay as an example, the maximum baseline fluctuation range M was calculated. i =10ps, C i =|80-78| / 10=0.2; Similarly, calculate the remaining parameters C. i The values ​​were 0.2, 0.1, and 0.05 respectively, with a weight of 0.25 for each. After weighted averaging, the parameter conflict index C = 0.1375 was obtained. With the timing error correction coefficient set to α=1.05 and weights w1=0.6 and w2=0.4, substituting into the formula ΔT=1.05×(0.6×(1-0.98)×80+0.4×0.1375×5)=1.29ps, the preliminary estimate of the cross-layer timing offset is 1.29ps; Historical data from the same scenario were filtered, and qualified subsets Dpass (actual cross-layer timing offset ≤ 5ps) and failed subsets Dfail (offset > 5ps) were divided. Timing deviation vectors, process parameter fluctuation data (such as bonding pressure fluctuations and etching depth fluctuations) and tag L were extracted, resulting in 1000 valid records: Dpass = 850 records and Dfail = 150 records. Twelve outlier data points were removed, and the process parameters were standardized and mapped to the [0,1] interval to construct an error association dataset Derror (N=988 records). Each record contains a 4-dimensional time series deviation vector, a 6-dimensional process parameter fluctuation value, and a label L. The spliced ​​10-dimensional fusion feature vector Fj is used to label the error sources of 150 failure samples: equipment inherent error E1=20, process fluctuation error E2=80, coupled superposition error E3=50, and qualified samples are labeled E0=0. An error source classification model was constructed, and the training set, validation set, and test set were divided in a 7:2:1 ratio. After training, the classification accuracy of the validation set reached 95.5% for two consecutive rounds, which met the requirements. The timing deviation vectors and standardized process parameters of chips A and B were extracted to generate the feature vector to be tested and input into the model. The output probability distribution was: E1=10%, E2=65%, E3=25%, and the dominant error source was determined to be process fluctuation error E2. Calculating the offset contribution probability, P(E1) = 20 / 150 ≈ 13.3%, P(E2) = 80 / 150 ≈ 53.3%, P(E3) = 50 / 150 ≈ 33.4%. The number of samples in class E2 with a difference of ≤ ±5% from ΔT = 1.29 ps is 52, so P(ΔT|E2) = 52 / 80 = 65%. Similarly, P(ΔT|E1) = 40% and P(ΔT|E3) = 30%. Substituting into Bayes' theorem, P(E2|ΔT) = (65% × 53.3%) / (40% × 13.3% + 65% × 53.3% + 30% × 33.4%) ≈ 68.2%, meaning the offset contribution probability of process fluctuation error is 68.2%, while E1 and E3 are 7.8% and 24%, respectively. The preset time margin is set to 5 ps, and the offset ratio is calculated as R = 1.29 / 5 = 0.258. After screening historical qualified samples, the ratio is calculated and taken as the 95th quantile, resulting in R0 = 0.3, where R ≤ R0. The parameter conflict index C = 0.1375 is within the normal fluctuation range (0.05-0.2), and the contribution probability of the dominant error source is 68.2%, which is lower than the historical average of 70%, thus it is judged as a level 1 low risk. The pairing is included in the priority stacking list without requiring rectification; the chip pairing information, R=0.258, C=0.1375, level 1 low risk, priority stacking recommendations, etc. are integrated to generate a standardized test report and archive it to the chip manufacturing history database.

[0024] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. An online monitoring method for chip manufacturing process errors based on artificial intelligence, characterized in that: The method includes: Step S100: Collect internal timing feature data of the upper and lower layer chips to be stacked during independent testing, divide the data sets according to chip manufacturing batches, label each data set with the corresponding process scenario label, and build an initial timing feature baseline library; Step S200: When the upper and lower layer chips are selected as the combination to be stacked, the matching degree and conflict index of the timing characteristics of the two are calculated based on the initial timing feature baseline library to generate a preliminary cross-layer timing offset; the cross-layer timing offset represents the deviation of the transmission signal between the upper layer chip and the lower layer chip to be stacked from the reference value in timing. Step S300: Filter historical stacking data with the same process scenario as the chips to be stacked, including qualified pairing data, failed pairing data and corresponding process parameter records, to construct an error association dataset; classify the error sources of the initially generated cross-layer timing offsets, determine the dominant error type, and calculate the offset contribution probability of each type of error source; the offset contribution probability represents the probability value that the offset is caused by a certain type of error source when the chips to be stacked generate cross-layer timing offsets. Step S400: Compare the cross-layer timing offset with the preset timing margin, assess the chip pairing risk level by combining the offset contribution probability, offset ratio and conflict index of the error source, screen out high-risk chip pairing schemes, and mark the core error nodes according to the dominant error source type. When the dominant error source is the inherent error of the equipment, mark the corresponding equipment number and the parameters that need to be calibrated; when the dominant error source is the process fluctuation error, mark the out-of-control process and parameter items; when the dominant error source is the coupled superposition error, mark the incompatible timing parameter dimensions, and generate a chip stacking error detection report.

2. The method for online monitoring of chip manufacturing process errors based on artificial intelligence according to claim 1, characterized in that: Step S100 includes: Step S101: Collect internal timing characteristic data of the upper and lower layer chips to be stacked in independent test mode in parallel using an automatic test device; denote the upper layer chip as chip A and the lower layer chip as chip B; the timing characteristic data includes at least signal path delay time, input and output circuit drive values, and signal rise and fall edge times; Step S102: Group the collected time-series feature data according to chip manufacturing batches, and label each batch data set with a corresponding process scenario label, the process scenario label including process manufacturing node, manufacturing cycle, and test temperature conditions; For each dataset, the mean, standard deviation, peak threshold, and fluctuation range of the time-series feature parameters are calculated to construct an initial time-series feature baseline library. Each baseline in the baseline library is associated with the manufacturing batch and process scenario label of the corresponding dataset.

3. The method for online monitoring of chip manufacturing process errors based on artificial intelligence according to claim 1, characterized in that: Step S200 includes: Step S201: Retrieve baseline data for the corresponding batches and process scenarios of the upper and lower layer chips to be stacked from the initial timing feature baseline library; extract the mean value of the i-th timing feature parameter of chip A, and construct the parameter matrix MA=[a1,a2,…,a] of chip A. i Extract the mean value of the i-th time-series feature parameter of chip B, and construct the parameter matrix MB=[b1,b2,…,b] of chip B. i ]; where a i Let b be the mean of the i-th timing characteristic parameter of chip A. i Let be the mean value of the i-th timing characteristic parameter of chip B; Step S202: Calculate the temporal feature matching degree between chip A and chip B using cosine similarity; Step S203: For each timing feature parameter, calculate the difference between the mean values ​​of the corresponding parameters of chip A and chip B, and then compare it with the maximum value of the baseline fluctuation range of the timing feature parameter to obtain the conflict value of the single timing feature parameter. Finally, take the weighted average of the conflict values ​​of all parameters to obtain the final parameter conflict index C.

4. The method for online monitoring of chip manufacturing process errors based on artificial intelligence according to claim 3, characterized in that: Step S200 further includes: Step S204: Combining the temporal feature matching degree S and the parameter conflict index C, a temporal error correction coefficient α is introduced to calculate the cross-layer temporal offset: ΔT=α×(w1×(1-S)×T) ref +w2×C×σ), where ΔT is the preliminary estimated cross-layer temporal offset; w1 and w2 are the weight coefficients of the temporal feature mismatch term and the parameter conflict term, respectively, and w1+w2=1; T ref σ represents the mean signal path delay time extracted from the initial time-series feature baseline library corresponding to the current process scenario, and σ is the standard deviation of the signal path delay time under the corresponding process scenario.

5. The method for online monitoring of chip manufacturing process errors based on artificial intelligence according to claim 1, characterized in that: Step S300 includes: Step S301: From the chip manufacturing history database, filter historical stacked chip data with the same process scenario as the chip to be stacked, and divide them into two subsets: Qualified pairing data subset Dpass: Filters chip pairing records in historical stacked chips where the actual cross-layer timing offset obtained from actual testing is ≤ the preset timing margin; Dfail, a subset of failed pairing data, filters chip pairing records in historical stacked chips where the actual cross-layer timing offset obtained from actual testing is greater than the preset timing margin. For each historical record in Dpass and Dfail, extract the time-series feature deviation data, process parameter fluctuation data, and stacking effect labels simultaneously; The time-series feature deviation data consists of the mean values ​​of each time-series feature parameter of chip A' and chip B' in historical pairings, forming an m-dimensional time-series deviation vector: ΔX={Δx1,Δx2,...,Δxm}, where Δxm=|xA'm-xB'm|; xA'm and xB'm are the mean values ​​of historical chips A' and B' on the m-th type of time-series feature, respectively; The process parameter fluctuation data is the set of key process parameter fluctuation ranges P={P1,P2,...,Pq} of historical chips A' and B' during the manufacturing process, where q is the total number of process parameters and Pq represents the fluctuation value of the qth type of process parameter in the corresponding manufacturing batch. The stacking effect label is the effect label L marked for each historical record, where the qualified pair label L=0 and the invalid pair label L=1.

6. The method for online monitoring of chip manufacturing process errors based on artificial intelligence according to claim 5, characterized in that: Step S300 further includes: Step S302: Remove outliers from the three types of extracted data and standardize the process parameter records, mapping the parameter values ​​to the [0,1] interval; The preprocessed time-series feature deviation data, process parameter fluctuation data, and stacking effect labels are bound together to construct an error association dataset Derror. Each record in the dataset has the following format: Derror={(ΔXj,Pj,Lj)|j=1,2,...,N}; where N is the total number of preprocessed historical samples, ΔXj is the time-series deviation vector of the j-th record, Pj is the set of process parameter fluctuation values ​​of the j-th record, and Lj is the stacking effect label of the j-th record. Step S303: For each record in the error association dataset Derror, concatenate the m-dimensional timing deviation vector ΔXj with the q-dimensional standardized process parameter fluctuation set Pk to form a (m+q)-dimensional fused feature vector Fj=[ΔXj, Pj]; combining chip manufacturing process and historical failure data, label all failure samples in Derror with error source type labels Ek. Error sources are divided into three types: Ek=1: inherent equipment error, caused by the precision limitations of manufacturing equipment and the deviation of testing instrument system; Ek=2: process fluctuation error, caused by the loss of control of process parameters; Ek=3: coupling superposition error, caused by the incompatibility of timing parameters between upper and lower layers of chips, which is unrelated to process parameters; among them, qualified samples are uniformly labeled as having no error source, Ek=0.

7. The method for online monitoring of chip manufacturing process errors based on artificial intelligence according to claim 6, characterized in that: Step S300 further includes: Step S304: Construct an error source classification model, taking the fused feature vector Fj as input and outputting the probability distributions of three error sources: inherent equipment error, process fluctuation error, and coupled superposition error. The input layer uses a linear activation function; the feature extraction layer consists of two 1D convolutional layers and one BiLSTM layer. The convolutional layers extract locally related features, and the BiLSTM layer captures temporal dependencies. The attention weighting layer generates weight vectors through a channel attention mechanism to weight the BiLSTM output features. The classification output layer has three neurons, activated by Softmax, and outputs the probabilities of each error source. During model training, the dataset labeled with error source tags is stratified proportionally into training, validation, and test sets. The Adam optimizer and cross-entropy loss function are used to optimize parameters. An initial learning rate is set, and training is completed when the classification accuracy of the validation set is ≥95% for two consecutive rounds. For chips A and B to be stacked, their m-dimensional timing deviation vector and standardized q-dimensional process parameter fluctuation values ​​are extracted and concatenated into a feature vector to be tested. The input model outputs three types of error source probability distributions. The error source type corresponding to the maximum probability is taken as the dominant error source type of the chip to be stacked. Finally, the three types of error source probability distributions of the chip to be stacked are output, and the dominant error source type is determined.

8. The method for online monitoring of chip manufacturing process errors based on artificial intelligence according to claim 7, characterized in that: Step S300 further includes: Step S305: Then calculate the offset contribution probability of each error source: ； Wherein, P(Ek|ΔT) is the offset contribution probability of the k-th error source; k=1,2,3, corresponding to three types of error sources: E1 is the inherent error of the equipment, E2 is the process fluctuation error, and E3 is the coupling superposition error; P(Ek) is the occurrence probability of the k-th error source, which is obtained by calculating the proportion of the number of samples of the k-th error source in the error association dataset Derror to the total number of failure samples; P(ΔT|Ek) is the conditional probability, which represents the probability that the cross-layer timing offset is ΔT under the premise that the k-th error source occurs. It is obtained by calculating the proportion of the number of samples in the error association dataset Derror where the absolute value of the difference between the actual cross-layer timing offset under the k-th error source and the cross-layer timing offset ΔT of the chip to be stacked is ≤±5% to the total number of samples of this type of error source; finally, the error source analysis results are output, which clarify the error source type of the current chip combination to be stacked and the offset contribution probability of each type of error source, and form an error source analysis report.

9. The method for online monitoring of chip manufacturing process errors based on artificial intelligence according to claim 4, characterized in that: Step S400 includes: Step S401: Based on the estimated cross-layer timing offset ΔT, the dominant error source type, and the error source offset contribution probability, first retrieve the preset timing margin T0 that matches the process scenario of the chip to be stacked, and calculate the offset ratio R=ΔT / T0. From the chip manufacturing history database, select historical qualified stacking samples that are completely consistent with the process scenario of the chips to be stacked. For each sample, calculate the ratio of the actual cross-layer timing offset to the preset timing margin. Then, take the 95th percentile of this ratio for all samples and set it as the offset proportion critical value R0. Simultaneously extract the parameter conflict index C output from step S203 to determine the error risk level. Level 1 low risk: R≤R0, the parameter conflict index C is within the conventional fluctuation range of qualified samples in the same process scenario, and the contribution probability of the dominant error source is lower than the historical average occurrence probability, no adjustment is required, and the stacking process is directly executed; Level 2 medium-low risk: R≤R0, but the parameter conflict index C exceeds the conventional fluctuation range, and the dominant error source is the inherent equipment error. This type of pairing has potential risks caused by equipment accuracy, it is necessary to perform accuracy calibration on the corresponding manufacturing or test equipment, and re-collect parameters and conduct re-evaluation after the calibration is completed; Level 3 medium-high risk: R0<R≤1.2R0, and the dominant error source is process fluctuation error. The risk of this type of pairing is caused by process parameter fluctuation, it is required to locate the specific out-of-control process and the corresponding parameters, and re-conduct evaluation after optimizing the parameter range; Level 4 high risk: R>1.2R0, or the dominant error source is coupling superposition error. For this type of pairing, either the offset exceeds the standard severely, or the timing parameters are inherently incompatible, the stacking is directly prohibited, and the chip pairing combination needs to be re-screened.

10. The method for online monitoring of chip manufacturing process errors based on artificial intelligence according to claim 9, characterized in that: The step S400 further includes: Step S402: According to the above risk level determination result, include the level 1 low-risk pairings into the priority stacking list, include the level 2 medium-low risk and level 3 medium-high risk pairings into the risk rectification list, and include the level 4 high-risk pairings into the elimination list; for the pairings in the risk rectification list, mark the core error nodes in combination with the dominant error source type and the offset contribution probability, mark the corresponding equipment number and the parameters to be calibrated for the inherent equipment error, mark the out-of-control process and parameter items for the process fluctuation error, mark the incompatible timing parameter dimension for the coupling superposition error, and clarify the rectification priority sorted by the contribution probability at the same time; Step S403: Integrate the basic information of the chip pairs to be stacked, the offset proportion and the parameter conflict index, the risk level, the pairing scheme screening result, the core error node mark and the rectification suggestion, generate a standardized detection report, and synchronously archive the report to the chip manufacturing historical database.

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