A layout post multi-bit flip-flop synthesis method for power consumption timing co-optimization
By optimizing the synthesis of multi-bit flip-flops using the nearest neighbor enumeration algorithm and a greedy strategy, the problem of insufficient timing control and power consumption optimization in the existing technology is solved, and better timing control and power consumption reduction effects are achieved.
Patent Information
- Application Number
- CN202610408564.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-31
- Publication Date
- 2026-11-06
- Estimated Expiration
- 2046-03-31
AI Technical Summary
Existing post-layout multi-bit flip-flop synthesis methods have shortcomings in timing control and power consumption optimization, making it difficult to achieve precise timing control and limiting power consumption optimization.
The nearest neighbor enumeration algorithm is used to generate merge combinations and construct a time-accurate comprehensive cost function. Combined with a greedy strategy and a local exchange optimization algorithm, the solution space is expanded by enumerating merge candidates, and the synthesis of multi-bit flip-flops is optimized to reduce chip power consumption.
It achieves significant power consumption reduction while improving the accuracy of timing control, and can be integrated into other complete process tools to reduce chip power consumption.
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Figure CN122221504B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer-aided design technology, and in particular to a post-layout multi-bit trigger synthesis method with power consumption and timing co-optimization. Background Technology
[0002] Existing post-layout multi-flip trigger synthesis methods fall into two main categories: methods based on trigger clustering and maximum clique merging strategies based on feasible region cross-graphs. The former uses a designed clustering method to rationally cluster unit triggers into a single cluster, then determines candidate groups for trigger merging and replaces them with multi-flip triggers. It uses the displacement of triggers before and after clustering as a constraint to avoid excessive changes to the initial layout, thus ensuring timing. However, in practice, using displacement to simulate timing effects is too coarse and difficult to achieve precise timing control. The maximum clique merging strategy based on feasible region cross-graphs extracts the winding length (i.e., converting timing relaxation constraints (slack) into line length) as the radius to construct Manhattan rings. The overlapping rectangular regions of all Manhattan rings are considered feasible merging regions. The maximum clique is then extracted from the cross-graph formed by the overlapping regions to determine the multi-flip trigger synthesis. This method constrains the merging of multi-flip triggers with relatively precise timing relaxation information, resulting in good timing control, but it also significantly limits the merging rate, leading to limited power consumption optimization.
[0003] Therefore, providing a post-layout multi-bit trigger synthesis method with power consumption and timing co-optimization to solve the difficulties of the existing technology is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] In view of this, the present invention provides a post-layout multi-flip-flop synthesis method with power consumption and timing co-optimization. While achieving significant power consumption reduction, it can be integrated into other complete process tools to realize the function of multi-flip-flop synthesis to reduce chip power consumption.
[0005] To achieve the above objectives, the present invention adopts the following technical solution: A post-layout multi-bit flip-flop synthesis method with power consumption and timing co-optimization includes the following steps: After obtaining the distribution of unit triggers after global layout, the nearest neighbor enumeration algorithm is used to generate a merged combination and its initial position for each unit trigger that is adapted to the multi-bit trigger library, forming a candidate pool; Determine the internal power consumption value of the multi-bit flip-flops corresponding to the combined combination, construct a combined timing model to calculate the timing cost, and combine the internal power consumption value and timing cost to construct a timing-accurate comprehensive cost function; Each merged combination is treated as a node. A conflict graph is constructed based on the trigger conflict relationship and the comprehensive cost function. A greedy strategy is used as an approximate solution to find the initial solution of the conflict graph, forming an initial solution set. A local exchange optimization algorithm is introduced to optimize the initial solution set to obtain a combined subset. Then, the triggers are adjusted based on the solutions within the combined subset, and finally, the synthesis of multi-bit triggers is achieved.
[0006] Optionally, constructing merged combinations includes: Based on the two-dimensional coordinate information of the unit triggers, construct an R-tree to find the nearest neighbor of each unit trigger; Determine the maximum number of bits K of the multi-bit triggers provided in the library, find K nearest neighbors for each unit trigger, and then enumerate the combination of each type of multi-bit trigger; Based on the multi-bit trigger types in the provided library, enumerate the combinations of corresponding bit lengths to form a combined combination of all unit triggers.
[0007] Optionally, constructing a time-accurate comprehensive cost function includes: Determine the mapping relationship and path cost of each bit from unit flip-flops to multi-bit flip-flops in the merged combination, and construct a weighted bipartite graph; Build size is The cost matrix is combined with a weighted bipartite graph and the Hungarian algorithm is used to achieve perfect matching, thus obtaining the optimal bit mapping from unit triggers to bits. Static timing analysis is performed on the layout before merging to obtain the timing relaxation value of each unit trigger, and a timing-accurate comprehensive cost function is constructed by combining the path cost.
[0008] Optionally, constructing a weighted bipartite graph includes: Use the unit flip-flop and the bit as the left and right nodes respectively; Each unit flip-flop and bit is connected to form an edge. The change in Steiner line length of the network connecting the input and output pins of the unit flip-flops before and after merging is used as the mapping path cost, expressed as: ); in, The length of the Steiner tree line generated by the D pin before and after merging. The length of the Steiner tree generated by the Q pins before and after merging. For the i-th unit trigger node, Let i be the j-th bit node, i be the number of trigger nodes, and j be the number of bit nodes; Construct a weighted bipartite graph based on nodes and edges.
[0009] Optionally, perform static timing analysis on the layout before merging to obtain the timing relaxation value (slack) of each unit trigger, and construct key weights using the slack values, with the expression as follows: , in, This is represented as the current combined relaxation value. The maximum relaxation value. The minimum relaxation value; The precise time-series comprehensive cost function expression, constructed by combining path costs, is as follows: , in, The cost of the unit trigger i path to achieve optimal bit mapping.
[0010] Optionally, forming the initial solution set includes: Each candidate merging combination is treated as a node, and a conflict graph is constructed based on the trigger conflict relationship. Each node in the graph corresponds to a merging combination. If two combinations contain the same trigger, there is a conflict edge between them. A comprehensive cost function is defined for each combination. Sort all nodes in descending order of combinatorial cost, and then select nodes that do not conflict with the currently selected nodes to add to the solution set, thus constructing a valid and low-cost initial solution and forming the initial solution set.
[0011] Optionally, obtaining a subset of the combination includes: Traverse sequentially Each combination in And attempt to remove it from the solution set, while searching for one or more unselected alternative subsets that do not conflict with existing solutions, expressed as: , in, For replacement A subset of candidate combinations For combination The cost, For combination The cost, For combination The set of triggers, The currently selected combination set, .
[0012] As can be seen from the above technical solution, compared with the prior art, the present invention provides a post-layout multi-bit flip-flop synthesis method with power consumption and timing co-optimization, which has the following beneficial effects: 1) This invention can expand the solution space by enumerating and merging candidates, and obtain a good solution to the multi-bit trigger synthesis problem after layout by combining more refined merging timing cost settings and greedy strategies. While achieving significant power consumption reduction, it can also make the timing of the design better controlled. 2) This invention is relatively independent and can be integrated into other complete process tools to realize the function of multi-bit trigger synthesis to reduce chip power consumption. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0014] Figure 1 This is a flowchart of a post-layout multi-bit flip-flop synthesis method for power consumption and timing co-optimization disclosed in this invention; Figure 2 This is a schematic diagram of the nearest neighbor enumeration method disclosed in this invention; Figure 3 This is a schematic diagram of bit mapping in the merged combination disclosed in this invention; Figure 4 This is a schematic diagram illustrating the timing cost calculation and perfect matching disclosed in this invention. Detailed Implementation
[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0016] Reference Figure 1 As shown, this invention discloses a post-layout multi-bit flip-flop synthesis method with power consumption and timing co-optimization, comprising the following steps: After obtaining the distribution of unit triggers after global layout, the nearest neighbor enumeration algorithm is used to generate a merged combination and its initial position for each unit trigger that is adapted to the multi-bit trigger library, forming a candidate pool; Determine the internal power consumption value of the multi-bit flip-flops corresponding to the combined combination, construct a combined timing model to calculate the timing cost, and combine the internal power consumption value and timing cost to construct a timing-accurate comprehensive cost function; Each merged combination is treated as a node. A conflict graph is constructed based on the trigger conflict relationship and the comprehensive cost function. A greedy strategy is used as an approximate solution to find the initial solution of the conflict graph, forming an initial solution set. A local exchange optimization algorithm is introduced to optimize the initial solution set to obtain a combined subset. Then, the triggers are adjusted based on the solutions within the combined subset, and finally, the synthesis of multi-bit triggers is achieved.
[0017] Furthermore, constructing a merged portfolio includes: Based on the two-dimensional coordinate information of the unit trigger, an R-tree is constructed to find the nearest neighbor of each unit trigger. Since merging triggers that are too far apart can lead to uncontrollable timing changes, the favorable merging objects for a certain unit trigger are found in its nearest neighbors. Determine the maximum number of bits K of the multi-bit triggers provided in the library, find K nearest neighbors for each unit trigger, and then enumerate the combination of each type of multi-bit trigger; Based on the multi-bit trigger types in the provided library, enumerate the combinations of corresponding bit lengths to form a combined combination of all unit triggers.
[0018] In one specific embodiment, such as Figure 2 As shown, when the maximum number of bits K for a multi-bit flip-flop is 4, four nearest neighbors are found for R0: R1, R2, R3, and R4. Then, based on the multi-bit flip-flop types (1-bit flip-flop, 2-bit flip-flop, 4-bit flip-flop) in the provided library, the corresponding number of bit combinations are enumerated, resulting in a total of 9 combinations for R0.
[0019] Furthermore, an initial position is assigned to each merge combination for calculating the time series cost. The corresponding initial position coordinates of multiple triggers ( , The weighted geometric center of the unit trigger in the combination is calculated as follows: , in, This indicates the combination The corresponding number of bits for multi-bit triggers, ( , () represents the layout coordinates of the i-th unit trigger in the combination. This is the sum of the fan-in and fan-out counts of the trigger. The initial position calculated in this way will be biased towards the unit trigger, which has a higher wiring complexity, based on the geometric center.
[0020] Furthermore, such as Figure 3 As shown, based on the initial position, the mapping relationship between the unit flip-flop and the multi-bit flip-flop on each bit is further refined, that is... Each unit trigger is assigned to The goal is to minimize the overall impact on timing across all bits. The constraint is set so that each unit flip-flop can correspond to only one bit, and each bit can only hold one unit flip-flop.
[0021] Furthermore, refer to Figure 4 As shown, constructing a time-accurate comprehensive cost function includes: Determine the mapping relationship and path cost of each bit from unit flip-flops to multi-bit flip-flops in the merged combination, and construct a weighted bipartite graph; Build size is The cost matrix is combined with a weighted bipartite graph and the Hungarian algorithm O(n log n) is used. 3 Achieve perfect matching quickly with a complexity of ) and obtain the optimal bit mapping from unit trigger to bit; Static timing analysis is performed on the layout before merging to obtain the timing relaxation value of each unit trigger, and a timing-accurate comprehensive cost function is constructed by combining the path cost.
[0022] Furthermore, constructing a weighted bipartite graph includes: Use the unit flip-flop and the bit as the left and right nodes respectively; Each unit flip-flop and bit is connected to form an edge. The change in Steiner line length of the network connecting the input and output pins of the unit flip-flops before and after merging is used as the mapping path cost, expressed as: ); in, The length of the Steiner tree line generated by the D pin before and after merging. The length of the Steiner tree generated by the Q pins before and after merging. For the i-th unit trigger node, Let i be the j-th bit node, i be the number of trigger nodes, and j be the number of bit nodes. A positive cost value for increasing line length indicates a penalty, and a negative cost value for decreasing line length indicates a reward. Construct a weighted bipartite graph based on nodes and edges.
[0023] Specifically, When performing bit mapping for a merged combination, the mapping relationship from the unit flip-flop to the slot is uncertain before the mapping algorithm is executed. Therefore, it is necessary to calculate the total mapping cost from the unit flip-flop i to any slot of the multi-bit flip-flop in the combination. Compared with the traditional approach that only relies on the coordinate displacement value from the unit flip-flop to the bit, this application considers the possibility of non-deterioration of timing after merging and takes into account the difference between the fan-in and fan-out numbers of different unit flip-flops. Therefore, it is more accurate to estimate the timing impact by using the Steiner tree line length of the connection network where the pin is located.
[0024] Furthermore, for a merged combination After obtaining the mapping relationship, the overall timing cost is the timing cost generated by each unit trigger after mapping. Based on the sum, further consideration is given to specific timing relaxations. A static timing analysis of the pre-merge layout is performed to obtain the timing relaxation value (slack) for each unit trigger. The slack value is then used to construct key weights, expressed as follows: , in, This represents the current combined relaxation value. The maximum relaxation value. The minimum relaxation value is slack; the smaller the slack, the better. The larger the value, the more critical it is. The precise time-series comprehensive cost function expression, constructed by combining path costs, is as follows: , in, The cost of the unit trigger i path to achieve optimal bit mapping.
[0025] Specifically, after the mapping algorithm is completed, the specific slot to which the unit trigger i in the combination is mapped is determined. Therefore, the cost incurred in mapping the unit trigger i to that specific slot is denoted as... .
[0026] Furthermore, forming the initial solution set includes: Treat each candidate merge combination as a node. And a conflict graph is constructed based on the trigger conflict relationship, where each node of the graph Corresponding to a combination If two combinations contain the same trigger, that is Then there is a conflict edge between them, for each combination Define the overall cost function (or score). :
[0027] in, To normalize the product of the internal power consumption per bit and the number of bits for the corresponding multi-bit flip-flops, the coefficients are... An adjustment factor for controlling the trade-off between power consumption and timing; Select the largest independent set in the graph. A set of mutually unconnected nodes minimizes the total cost.
[0028] Since this problem is NP-hard, we adopt a greedy strategy as an approximate solution. We sort all nodes in descending order of combinatorial cost and select nodes that do not conflict with the currently selected nodes to add to the solution set, thus constructing a valid and low-cost initial solution and forming the initial solution set.
[0029] Furthermore, to overcome the drawback of greedy algorithms easily getting trapped in local optima, this application introduces local exchange optimization to obtain combinatorial subsets including: Traverse sequentially Each combination in It attempts to remove it from the solution set while searching for one or more unselected alternative subsets that do not conflict with existing solutions. This ensures that the conflict independence constraint is still satisfied after the replacement operation and the total cost of the objective function is better. The expression is: , in, For replacement A subset of candidate combinations For combination The cost, For combination The set of triggers, The currently selected combination set, .
[0030] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for synthesizing multi-bit flip-flops after layout with power consumption and timing co-optimization, characterized in that, Includes the following steps: After obtaining the distribution of unit triggers after global layout, the nearest neighbor enumeration algorithm is used to generate a merged combination and its initial position for each unit trigger that is adapted to the multi-bit trigger library, forming a candidate pool; For each merge combination within the candidate pool, construct a time-accurate comprehensive cost function, including: Determine the mapping relationship and path cost of each bit from unit flip-flops to multi-bit flip-flops in the merged combination, and construct a weighted bipartite graph; Build size is The cost matrix is combined with a weighted bipartite graph and the Hungarian algorithm is used to achieve a perfect match to obtain the optimal bit mapping from unit triggers to bits, where k represents the number of multi-bit triggers corresponding to the current merge combination; Static timing analysis is performed on the layout before merging to obtain the timing relaxation value of each unit trigger, and a timing-accurate comprehensive cost function is constructed by combining the path cost. Determine the internal power consumption value of the multi-bit flip-flops corresponding to the combined combination, and determine the combination cost function based on the timing-accurate synthesis cost function and the internal power consumption value of the multi-bit flip-flops corresponding to the combined combination; Each merged combination is treated as a node. A conflict graph is constructed based on the trigger conflict relationship and the combination cost function. A greedy strategy is used as an approximate solution to find the initial solution of the conflict graph, forming an initial solution set. A local exchange optimization algorithm is introduced to optimize the initial solution set to obtain a combined subset. Then, the triggers are adjusted based on the solutions within the combined subset, and finally, the synthesis of multi-bit triggers is achieved.
2. The method for synthesizing multi-bit flip-flops after layout with power consumption and timing co-optimization according to claim 1, characterized in that, Constructing a merged portfolio includes: Based on the two-dimensional coordinate information of the unit triggers, construct an R-tree to find the nearest neighbor of each unit trigger; Determine the maximum number of bits K of the multi-bit triggers provided in the library, find K nearest neighbors for each unit trigger, and then enumerate the combination of each type of multi-bit trigger; Based on the multi-bit trigger types in the provided library, enumerate the combinations of corresponding bit lengths to form a combined combination of all unit triggers.
3. The method for synthesizing multi-bit flip-flops after layout with power consumption and timing co-optimization according to claim 2, characterized in that, Constructing a weighted bipartite graph includes: Use the unit flip-flop and the bit as the left and right nodes respectively; Connect each unit flip-flop and bit to form an edge, and use the change in Steiner line length of the connection network containing the input and output pins of the unit flip-flops before and after merging as the path cost, expressed as: ）； in, The length of the Steiner tree line generated by the D pin before and after merging. The length of the Steiner tree generated by the Q pins before and after merging. For the i-th unit trigger node, Let i be the j-th bit node, i be the number of trigger nodes, and j be the number of bit nodes; Construct a weighted bipartite graph based on nodes and edges.
4. The method for synthesizing multi-bit flip-flops after layout with power consumption and timing co-optimization according to claim 3, characterized in that, Static timing analysis is performed on the pre-merge layout to obtain the timing relaxation value (slack) for each unit trigger, and the key weights are constructed using the slack values. The expression is as follows: ， in, This is represented as the current combined relaxation value. The maximum relaxation value, The minimum relaxation value; The time-accurate comprehensive cost function constructed by combining path costs is as follows: ， in, The cost of the unit trigger i path to achieve optimal bit mapping.
5. The method for synthesizing multi-bit flip-flops after layout with power consumption and timing co-optimization according to claim 1, characterized in that, The formation of the initial solution set includes: Each candidate merge combination is treated as a node, and a conflict graph is constructed based on the trigger conflict relationship. Each node in the graph corresponds to a merge combination. If two combinations contain the same trigger, there is a conflict edge between them. A combination cost function is defined for each combination. Sort all nodes according to their combinatorial cost from smallest to largest, and then select nodes that do not conflict with the currently selected nodes to add to the solution set, thus constructing a valid and low-cost initial solution and forming the initial solution set.
6. The method for synthesizing multi-bit flip-flops after layout with power consumption and timing co-optimization according to claim 5, characterized in that, Obtaining a subset of combinations includes: Iterate through each combination in the initial solution set in turn. And attempt to remove it from the solution set, while searching for one or more unselected alternative subsets that do not conflict with existing solutions, expressed as: ， in, For use in replacement combinations A subset of candidate combinations For combination The cost, For combination The cost, For combination The set of triggers, This is the set of currently selected combinations. Let r be the set of triggers for the selected combination set, and r be the number of alternative combination subsets.
Citation Information
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