A multi-level hypergraph partitioning method and system based on a netlist

Abstract

The application discloses a kind of multi-level hypergraph partitioning method and system based on netlist, comprising: obtaining user design netlist and constraint information, node pre-merging is carried out;Hypergraph topology structure is constructed using flow chart construction technology, block loading netlist, the ID of node is rearranged to make the ID of logic level close successively, only core topological information is stored in memory, and non-topological attribute is stored in disk;Multi-level parallel coarsening is carried out using hybrid coarsening strategy, first, the logical hierarchy with containing relationship is merged, then, node pairs with many connections are merged based on connectivity;When the size of graph is coarsened to the preset threshold, initial partitioning is carried out using multi-path spectral clustering;Parallel anti-coarsening and refinement are carried out on initial partitioning scheme, parallel boundary FM algorithm is used to optimize node movement, local difficult to optimize area is identified, maximum flow minimum cut model is constructed for local repartitioning, and finally the result is output. Significantly reduce memory consumption, support manual intervention, improve partitioning quality, and speed up operation.

Description

Technical Field

[0001] This invention belongs to the field of ultra-large-scale integrated circuit verification technology, and in particular relates to a multi-level hypergraph partitioning method and system based on netlists, specifically designed for the verification of ultra-large-scale chips with hundreds of billions of gates. Background Technology

[0002] With the rapid development of chip manufacturing processes, the design scale of very large-scale integrated circuits (VLSI) is growing exponentially. For example, NVIDIA's DGX B200 chip, released in 2024, has reached 208 billion transistors. Assuming an average of four transistors per logic gate, this equates to 50 billion logic gates. Faced with such a massive design scale, a single FPGA cannot handle it; hardware simulation accelerators or prototyping systems composed of dozens or even hundreds of interconnected FPGAs are necessary for verification.

[0003] Traditional hardware simulation and verification systems face the following severe challenges when handling user designs of this scale: 1) Excessive memory consumption: Traditional partitioning tools (such as HMetis and KaHyPar) require the construction of massive adjacency lists and auxiliary data structures when processing netlists with hundreds of billions of gates, often exceeding TB-level memory usage, causing OOM errors on ordinary servers and rendering them unable to run; 2) Partitioning quality bottlenecks: Existing algorithms are mostly general-purpose mathematical solvers, lacking an understanding of the chip design hierarchy. Simply pursuing the mathematical minimum cut often leads to frequent cutting of critical paths or a large number of cross-chip hops, severely affecting the running frequency of the simulation system; 3) Excessive iteration time: Existing algorithms are mainly optimized for single-threaded or limited multi-threaded approaches. When dealing with hundreds of billions of nodes, a single partitioning iteration can take tens of hours, severely slowing down the iteration cycle of chip verification; 4) Lack of manual intervention mechanisms: Existing tools are mostly black-box fully automated operations, making it difficult for engineers to force specific modules to be constrained within specific FPGAs, resulting in placement and routing difficulties. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a netlist-based multi-level hypergraph partitioning method and system for verification of chips with hundreds of billions of gates, so as to solve the problems of large memory consumption, poor partitioning quality, long iteration time and lack of manual intervention in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A multi-level hypergraph partitioning method based on netlists includes the following steps: S100: Obtain the user-designed netlist and user constraint information, and perform pre-merging processing on the nodes in the user-designed netlist based on the user constraint information; S200: It uses streaming graph construction technology to build a hypergraph topology, loads the netlist in blocks, rearranges the node IDs so that the physical addresses of node IDs with similar logical levels are continuous, and stores only the core topology information in memory, while storing non-topology attribute information to disk. S300: A hybrid coarsening strategy is used for multi-level coarsening to gradually reduce the size of the graph. The hybrid coarsening strategy includes the first stage of merging logical hierarchical structures with containment relationships to preserve the original hierarchical features of the design, and the second stage of merging numerous node pairs by calculating the connectivity between nodes. The multi-level coarsening process is implemented in parallel. S400: When the graph size is coarsened to a preset threshold, multi-path clustering is used to initially partition the coarsened graph and generate an initial partitioning scheme. S500: Performs parallel anti-coarsening and refinement processing on the initial partitioning scheme. At each level of anti-coarsening, the parallel boundary FM algorithm is used to optimize node movement and identify regions that are difficult to optimize locally. For these regions, a maximum flow minimum cut model is constructed to perform local repartitioning, and the final partitioning result is output.

[0006] Preferably, obtaining the user design netlist and user constraint information in S100 includes: Read the netlist file to identify all logical units, modules, and interconnection information; user constraint information is provided through files or system built-in commands, including at least one of fixed location constraints and in-slice constraints. When multiple constraints exist, the system presets priorities, with hard constraints having higher priority than soft constraints. If there is a conflict among hard constraints, an error will be reported, and soft constraints will be selected according to priority order. The pre-merging process in S100 includes: before formally constructing the hypergraph topology, marking the nodes that need to be bound according to the user constraint information and aggregating the nodes that need to be bound into one node.

[0007] Preferably, the construction of the hypergraph topology using streaming graph construction technology in S200 specifically includes: S210: Load the netlist in blocks according to the hierarchical instantiation order. When the number of nodes accumulated in memory reaches a preset threshold, convert it into the topology of the hypergraph and release the temporary string occupied by the parser. S220: A remapping algorithm based on depth-first search order is used to rearrange the IDs of nodes. When parsing the netlist hierarchy tree, consecutive integer IDs are assigned according to the hierarchical path of the instance, so that the physical addresses of the IDs of nodes with similar logical levels are consecutive, thereby improving the CPU cache hit rate. S230: Core topology information includes a unique integer ID and weight for each node, an ID and weight for each hyperedge, and a list of IDs for all nodes connected by that hyperedge. Non-topology attribute information includes the instance's original string name, port physical coordinates, and attribute description. Non-topology attribute information is stored in a disk database and is only backfilled in the final output.

[0008] Preferably, the hybrid coarsening strategy in S300 includes: S310: The first stage of merging logical hierarchical structures with inclusion relationships includes: parsing the hierarchical path of nodes; when all child nodes within a logical module exhibit high cohesion in the hypergraph and belong to the same logical unit type definition in the netlist definition, they are determined to be inclusion relationships and merged; during merging, an area threshold is set; if the size of the sub-module does not exceed the area threshold, it is merged into a super node; if the size of the sub-module exceeds the area threshold, only the bottom-level units with the tightest connections within the module are merged. S320: In the second stage, the connectivity between nodes is calculated to merge pairs of nodes with numerous connections. The connectivity between nodes is calculated using the weighted hyperedge connectivity formula, which is: ; in, and There are two nodes. and It connects nodes simultaneously. and nodes The set of superedges It is a super-edge The weight, It is a super-edge The total number of nodes included, denominator Used to punish giant super-edges.

[0009] Preferably, the multi-level coarsening process in S300 is implemented in parallel, specifically including: Color the nodes of the hypergraph so that adjacent nodes have different colors, and the sets of nodes with the same color are independent of each other; The set of nodes to be processed is divided into multiple tasks and distributed to multiple threads for parallel processing. During the merging process, only the local neighborhood connectivity affected by the merging is recalculated, and physical address isolation between tasks is achieved through ID rearrangement in S200 to reduce false sharing.

[0010] Preferably, the multi-path spectral clustering in S400 includes: Multi-path clustering processes the smallest hypergraph that has been reduced to a preset threshold size after multiple rounds of S300 coarsening. A Laplacian matrix is ​​constructed based on the connectivity of the hypergraph. The first k smallest eigenvalues ​​of the matrix and their corresponding eigenvectors are calculated. Each node is mapped to a k-dimensional space composed of eigenvectors. The K-means algorithm is used for clustering to capture the topological characteristics of the graph from a global perspective and identify the natural community structure in the graph. After clustering, a local correction based on dynamic programming is used to ensure that the difference in logical resource utilization among the partitions is minimal, thus meeting the resource balance requirements of hardware verification.

[0011] Preferably, the parallel boundary FM algorithm in S500 specifically includes: If a node is connected by at least one hyperedge that spans different partition blocks, then the node is defined as a boundary node; boundary nodes are colored so that non-adjacent nodes can move in parallel in different threads. Only the gains of neighboring nodes affected by the moving node are recalculated; the gains are calculated using a gain function, which is: ; in, For the current node, For the target partition, Indicates due to node The movement transforms the set of hyperedges from spanning partitions to being completely contained within a certain partition. Indicates due to node The movement transforms it from a set of superedges that were originally within a single partition into a set that spans multiple partitions. For super-edge The weight.

[0012] Preferably, identifying locally difficult-to-optimize regions in S500 includes at least one of the following methods: In multiple iterations, regions where node labels frequently switch between two partitions and the total number of cut edges decreases by less than a preset change threshold are identified as high-frequency flip regions. Local subgraphs with a hyperedge-to-node ratio higher than the average of the whole graph are identified as high-density subgraphs. The region where the objective function value stagnates after multiple rounds of parallel FM movement is identified as the gain stagnation region.

[0013] Preferably, the maximum flow minimum cut model constructed in S500 includes: Extract adjacent nodes of a preset level from the center of a region that is difficult to optimize to form a local subgraph. Shrink the core node sets of the subgraph that belong to two different partitions into source and sink nodes. Transform hyperedges into edges and set the capacity of the edges to the weight of the original hyperedges. Use the ISAP algorithm to solve the minimum cut of the local subgraph to find a better partition boundary that the FM algorithm cannot find and break the local minimum. The optimization objective of the partitioning is represented by the objective function, which is: ; in, For super-edge The weight, It is a super-edge The number of partitions spanned.

[0014] A multi-level hypergraph partitioning system based on netlists includes: The preprocessing module is used to obtain the user-designed netlist and user constraint information, and to pre-merge the nodes in the user-designed netlist according to the user constraint information. The graph construction module is used to construct the hypergraph topology using streaming graph construction technology. It loads the netlist in blocks, rearranges the node IDs so that the physical addresses of nodes with similar logical levels are continuous, and stores only the core topology information in memory while storing non-topology attribute information to disk. The parallel coarsening module is used to perform multi-level coarsening processing using a hybrid coarsening strategy to gradually reduce the size of the graph. The hybrid coarsening strategy includes a first stage of merging logical hierarchical structures with containment relationships to preserve the original hierarchical features of the design, and a second stage of merging node pairs with many connections by calculating the connectivity between nodes. The multi-level coarsening processing is implemented in a parallel manner. The initial partitioning module is used to perform initial partitioning of the coarsened graph by multi-path clustering when the graph size is coarsened to a preset threshold, and to generate an initial partitioning scheme. The refinement and optimization module is used to perform parallel anti-coarsening and refinement processing on the initial partitioning scheme. At each level of anti-coarsening, the parallel boundary FM algorithm is used to optimize node movement and identify regions that are difficult to optimize locally. For these regions, a maximum flow minimum cut model is constructed to perform local repartitioning and output the final partitioning result.

[0015] The aforementioned multi-level hypergraph partitioning method and system based on netlists employs streaming graph construction technology, loads netlists in blocks, and stores non-topological attributes separately, avoiding memory explosion caused by full loading and enabling a single server to handle ultra-large-scale netlist partitioning. By allowing users to input constraints and pre-merge them before graph construction, it overcomes the limitations of black-box automated tools, protecting critical paths and physical interfaces. The hybrid coarsening strategy preserves the hierarchical characteristics of the design and merges dense nodes. Combined with the parallel boundary FM algorithm and the maximum flow minimum cut model for locally difficult-to-optimize regions, it performs fine-tuning, effectively reducing the number of cross-chip interconnects. At the same time, the use of node coloring, incremental updates, and parallel movement mechanisms significantly shortens the partitioning iteration time and accelerates the chip verification cycle. Attached Figure Description

[0016] Figure 1 This is a flowchart of a multi-level hypergraph partitioning method based on a netlist in one embodiment of the present invention; Figure 2 This is an overall architecture diagram of a multi-level hypergraph partitioning method based on netlists in one embodiment of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0018] This invention provides a multi-level hypergraph partitioning method and system based on netlists, specifically designed for ultra-large-scale chip verification designs with hundreds of billions of gates. This method models the circuit netlist as a hypergraph. ,in It is a collection of nodes (representing a Cell or Module). It is a set of hyperedges (representing a Net). The goal of partitioning is to... Divided into Subset This minimizes the sum of the weights of the hyperedges connecting different subsets, while simultaneously satisfying the resource balance constraints of each subset.

[0019] The following combination Figure 1 The method flowchart shown and Figure 2 The overall architecture diagram is provided to illustrate the method steps of this invention in detail.

[0020] (a) S100: Obtain the user-designed netlist and user constraint information, and perform pre-merging processing on the nodes in the user-designed netlist based on the user constraint information.

[0021] In one embodiment, obtaining the user design netlist and user constraint information in S100 includes: Read EDIF format netlist files to identify all logic units, modules, and interconnection information; user constraint information is provided through files or system built-in commands, including but not limited to at least one of fixed location constraints (such as specifying that a certain IP core must be placed in a certain FPGA) and co-chip constraints (such as specifying that multiple modules must be located in the same FPGA); When multiple constraints exist, the system presets priorities, with hard constraints having higher priority than soft constraints. If there is a conflict among hard constraints, an error will be reported, and soft constraints will be selected according to priority order. The pre-merging process in S100 includes: before formally constructing the hypergraph topology, marking the nodes that need to be bound according to the user constraint information and aggregating the nodes that need to be bound into one node.

[0022] For example, if a user requires that hundreds of thousands of logic units within a CPU core be located on the same FPGA, the system directly aggregates these logic units into a supernode, instead of creating hundreds of thousands of independent nodes in the supergraph. This pre-merging significantly simplifies the subsequent graph building process.

[0023] (ii) S200: For the scale of hundreds of billions of gates, this invention abandons the traditional full loading method and adopts the streaming graph construction technology to construct the hypergraph topology structure. The netlist is loaded in blocks, and the node IDs are rearranged using a hash map so that the physical addresses of node IDs with similar logical levels are continuous. Only the core topology information is stored in memory, and the non-topology attribute information is stored on the disk.

[0024] In one embodiment, the construction of the hypergraph topology using streaming graph construction technology in S200 specifically includes: S210: Since the original netlist has a nested hierarchical structure, the system loads the netlist in blocks according to the hierarchical instantiation order. When the number of nodes accumulated in memory reaches a preset threshold, it is converted into the topology of the hypergraph and the temporary string occupation of the parser is released, thereby avoiding memory explosion caused by full loading. S220: To address the performance bottleneck caused by randomized node access in traditional algorithms, the system employs a remapping algorithm based on depth-first search (DFS) order to rearrange node IDs. When parsing the netlist hierarchy tree, consecutive integer IDs are assigned according to the hierarchical path of the instance. For example, all Cells inside CPU_Core_0 are assigned consecutive physical IDs (such as 1000001~2000000), making the physical addresses of nodes with similar logical levels consecutive, thereby improving the CPU cache hit rate. S230: To significantly reduce memory usage, the system retains only core topology information in memory. This core topology information includes a unique integer ID and weight for each node, the ID and weight for each hyperedge, and a list of IDs of all nodes connected by that hyperedge. Non-topology attribute information includes the instance's original string name, port physical coordinates, and attribute descriptions. This non-topology attribute information is stored in a disk database and only populated during the final output. It is then read from disk when needed.

[0025] (III) S300: After completing the memory-optimized graph construction, a hybrid coarsening strategy is adopted to perform multi-level coarsening to gradually reduce the size of the graph. The hybrid coarsening strategy includes the first stage of merging logical hierarchical structures with containment relationships to retain the original hierarchical features of the design, and the second stage of merging numerous node pairs by calculating the connectivity between nodes. The multi-level coarsening is implemented in parallel.

[0026] In one embodiment, the hybrid coarsening strategy in S300 includes: S310: The first stage merges logical hierarchical structures with containment relationships, including: resolving the hierarchical paths of nodes; when all child nodes within a logical module exhibit high cohesion in the hypergraph and belong to the same logical unit type definition in the netlist definition, they are determined to be in a containment relationship and merged; to avoid resource imbalance in subsequent partitioning due to merging, an area threshold is set during merging. If the size of a submodule does not exceed the area threshold, it is merged into a super node; if the size of a submodule exceeds the area threshold, only the most tightly connected bottom-level units within that module are merged, allowing them to gradually converge rather than being directly packaged. This preserves the original hierarchical characteristics of the design while effectively reducing the total number of nodes.

[0027] S320: In the second stage, the connectivity between nodes is calculated to merge pairs of nodes with numerous connections. The connectivity between nodes is calculated using the weighted hyperedge connectivity formula, which is: ; in, and There are two nodes. and It connects nodes simultaneously. and nodes The set of superedges It is a super-edge The weight, It is a super-edge The total number of nodes included, denominator This is used to penalize giant superedges (such as global reset signals) because large-scale broadcast signals have little guiding significance for local clustering.

[0028] In one embodiment, the multi-level coarsening process in S300 is implemented in parallel, specifically including: Color the nodes of the hypergraph so that adjacent nodes have different colors, and the sets of nodes with the same color are independent of each other; The set of nodes to be processed is divided into multiple tasks, which are then distributed to multiple threads for parallel processing. Multiple threads can simultaneously search for the neighbor with the highest connectivity for these nodes; for example, thread A processes the merging of core 0, while thread B processes the merging of core 5. During the merging process, only the local neighborhood connectivity affected by the merging is recalculated. Physical address isolation between tasks is achieved through ID rearrangement in S200 to reduce false sharing and avoid deadlock or race conditions caused by multiple threads competing for the same merging target.

[0029] (iv) S400: When the graph size is coarsened to a preset threshold (e.g., several thousand nodes), multi-path spectral clustering is used to initially partition the coarsened graph, generating an initial partitioning scheme. Due to the small graph size, a high-complexity algorithm can be used here to ensure global optimality.

[0030] In one embodiment, the target of multi-path spectral clustering is the smallest hypergraph whose size has been reduced to a preset threshold after more than S300 rounds of coarsening. Since the coarsening process is based on local connectivity, while spectral clustering can capture the topological characteristics of the graph from a global perspective, near-optimal initial partitioning results can be obtained on this extremely small-scale graph.

[0031] The specific algorithm includes: constructing a Laplacian matrix based on the connectivity of the hypergraph, calculating the first k smallest eigenvalues ​​of the matrix and their corresponding eigenvectors, mapping each node to a k-dimensional space composed of eigenvectors, and using the K-means algorithm for clustering to capture the topological characteristics of the graph from a global perspective and identify the natural community structure in the graph, thereby minimizing cross-segment cuts. Compared to a simple greedy strategy, a local correction based on dynamic programming is used after clustering to ensure that the difference in logical resource utilization among the partitions is minimal, thus meeting the resource balance requirements of hardware verification.

[0032] (v) S500: Perform parallel anti-coarsening and refinement processing on the initial partitioning scheme. At each level of anti-coarsening, the parallel boundary FM algorithm is used to optimize node movement and identify regions that are difficult to optimize locally. For regions that are difficult to optimize locally, a maximum flow minimum cut model is constructed to perform local repartitioning and output the final partitioning result.

[0033] In one embodiment, the parallel boundary FM algorithm in S500 specifically includes: If a node is connected by at least one hyperedge that spans different partition blocks, then that node is defined as a boundary node; boundary nodes are colored so that non-adjacent nodes can move in parallel in different threads without conflict. Only the gains of neighboring nodes affected by the moving node are recalculated, avoiding a full recalculation; the gain function is used to measure the impact on nodes. To move from the current partition to the target partition The reduction in the objective function is calculated using the following formula: ; in, For the current node, For the target partition, Indicates due to node The movement transforms the set of hyperedges from spanning partitions to being completely contained within a certain partition. Indicates due to node The movement transforms it from a set of superedges that were originally within a single partition into a set that spans multiple partitions. For super-edge The weight.

[0034] In a network table with billions of gates, some regions are so densely connected that single-node movement using the FM algorithm alone cannot escape local optima. The S500 identifies these locally difficult-to-optimize regions using at least one of the following methods: In multiple iterations, regions where node labels frequently switch between two partitions and the total number of cut edges decreases by less than a preset change threshold are identified as high-frequency flip regions. Local subgraphs with a hyperedge-to-node ratio higher than the average of the whole graph are identified as high-density subgraphs. The region where the objective function value stagnates after multiple rounds of parallel FM movement is identified as the gain stagnation region.

[0035] In one embodiment, constructing the maximum flow minimum cut model in S500 includes: This approach extracts adjacent nodes of a predetermined level from the center of a region that is difficult to optimize, forming a local subgraph. The core node sets belonging to two different partitions in the subgraph are then shrunk into a source and a sink. Hyperedges are transformed into edges with their capacities set to the weights of the original hyperedges. The ISAP algorithm is then used to solve for the minimum cut of this local subgraph. Because the size of the local subgraph is limited to a small range (e.g., a few thousand nodes), this exact solution can find better partitioning boundaries that the FM algorithm cannot discover, thus breaking local minima and further reducing the number of cut edges. The optimization objective of the partitioning is represented by the objective function, which is: ; in, For super-edge The weight, It is a super-edge The number of partitions spanned.

[0036] The technical effects of the present invention are illustrated below with a specific embodiment. Assume the DUT design to be verified is a massively multi-scale SoC containing 64 general-purpose CPU cores, a large shared L3 cache, and a DDR5 controller, with a total size of approximately 12 billion gates. The goal is to divide this design into a verification cluster consisting of 32 FPGAs.

[0037] S100: Preprocessing and User Constraint Injection The user specifies via Tcl script that CPU_Core_0 through CPU_Core_3 must be placed in FPGA_0 (because this FPGA is connected to the debug interface). After recognizing the constraints, the system marks the hundreds of millions of logic gates involved in these four cores as the same supernode before graphing. If the user incorrectly specifies a submodule in CPU_Core_0 to be placed in FPGA_1, the system pre-scan detects the conflict and issues an error message.

[0038] S200: Flow Graph Construction and Memory Optimization The system does not read the terabyte-level netlist all at once. Instead, it reads the netlist in a streaming manner, following the hierarchy of Core → Cache → Peripheral. All cells within CPU_Core_0 are assigned consecutive physical IDs (e.g., 1000001-2000000). Only the node ID and connection relationships are stored in memory; the specific instance name (e.g., inst_x_alu_reg_0) is stored in the disk database. Actual memory usage was reduced from 1.2TB to below 400GB.

[0039] S300: Multi-stage parallel coarsening In the first stage, the algorithm identifies that the cells inside the ALU (Arithmetic Logic Unit) module are extremely densely connected and merges them. In the second stage, cache units with frequent signal round trips are matched and merged with memory controllers according to the connectivity formula.

[0040] Multi-core servers start simultaneously, with different cores handling different CPU_Core regions. Using node coloring technology, thread A processes the merging of core 0, while thread B processes the merging of core 5, without interference.

[0041] S400: Initial partitioning reduces scale After multiple rounds of coarsening, the original 12 billion nodes were compressed to only 5,000 supernodes. The system then invoked high-quality multi-path spectral clustering. Due to the extremely small number of nodes, the algorithm can perform complex eigenvalue decomposition and K-means clustering to find the most scientifically sound dividing boundaries between the 32 FPGAs from a global perspective, ensuring minimal cross-chip signals.

[0042] S500: Parallel refinement and local surgery parallel FM optimization During the anti-coarsening process, the system locks the bus interface nodes located on the FPGA boundary and uses the parallel boundary FM algorithm to calculate the gain generated by moving these interface nodes simultaneously in multiple threads, continuously fine-tuning to reduce the edge cutting.

[0043] When the cut edge in the Data Crossbar region is still high and FM cannot be optimized, the system automatically extracts the region to construct a maximum flow minimum cut model, and re-divides the local region through precise numerical calculations, successfully further reducing the cross-chip connection.

[0044] Corresponding to the above method, the present invention also provides a multi-level hypergraph partitioning system based on netlists, comprising: The preprocessing module is used to obtain the user-designed netlist and user constraint information, and to pre-merge the nodes in the user-designed netlist according to the user constraint information. The graph construction module is used to construct the hypergraph topology using streaming graph construction technology. It loads the netlist in blocks, rearranges the node IDs so that the physical addresses of nodes with similar logical levels are continuous, and stores only the core topology information in memory while storing non-topology attribute information to disk. The parallel coarsening module is used to perform multi-level coarsening processing using a hybrid coarsening strategy to gradually reduce the size of the graph. The hybrid coarsening strategy includes a first stage of merging logical hierarchical structures with containment relationships to preserve the original hierarchical features of the design, and a second stage of merging node pairs with many connections by calculating the connectivity between nodes. The multi-level coarsening processing is implemented in a parallel manner. The initial partitioning module is used to perform initial partitioning of the coarsened graph by multi-path clustering when the graph size is coarsened to a preset threshold, and to generate an initial partitioning scheme. The refinement and optimization module is used to perform parallel anti-coarsening and refinement processing on the initial partitioning scheme. At each level of anti-coarsening, the parallel boundary FM algorithm is used to optimize node movement and identify regions that are difficult to optimize locally. For these regions, a maximum flow minimum cut model is constructed to perform local repartitioning and output the final partitioning result.

[0045] For specific limitations regarding a netlist-based multilevel hypergraph partitioning system, please refer to the limitations of the netlist-based multilevel hypergraph partitioning method described above, which will not be repeated here. Each module in the aforementioned netlist-based multilevel hypergraph partitioning system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0046] Compared with the prior art, the present invention has the following beneficial effects: Reduced memory consumption: By using streaming loading and separating non-topology data storage, memory consumption is reduced by more than 60%, and a single server can handle the partitioning of tens of billions of gate-level network lists.

[0047] Supports semi-automatic partitioning with manual intervention: The user constraint preprocessing injection mechanism allows engineers to incorporate design knowledge into the algorithm, solving the problem of purely automatic algorithms violating critical paths or I / O constraints.

[0048] Superior partitioning quality: By combining structure-aware coarsening and streaming refinement techniques, cross-chip interconnects are reduced by approximately 15% to 20% compared to HMetis, effectively alleviating the time-division multiplexing (TDM) bandwidth pressure in multi-FPGA systems.

[0049] Fast running speed: It adopts a parallelized boundary FM algorithm, which is 3-5 times faster than KaHyPar in a single iteration on a 64-core server.

[0050] The foregoing has provided a detailed description of the method and system for multi-level hypergraph partitioning based on netlists provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A method for partitioning a multi-level hypergraph based on a netlist, characterized in that, Includes the following steps: S100: Obtain the user-designed netlist and user constraint information, and perform pre-merging processing on the nodes in the user-designed netlist based on the user constraint information; S200: It uses streaming graph construction technology to build a hypergraph topology, loads the netlist in blocks, rearranges the node IDs so that the physical addresses of node IDs with similar logical levels are continuous, and stores only the core topology information in memory, while storing non-topology attribute information to disk. S300: A hybrid coarsening strategy is used for multi-level coarsening to gradually reduce the size of the graph. The hybrid coarsening strategy includes the first stage of merging logical hierarchical structures with containment relationships to preserve the original hierarchical features of the design, and the second stage of merging numerous node pairs by calculating the connectivity between nodes. The multi-level coarsening process is implemented in parallel. S400: When the graph size is coarsened to a preset threshold, multi-path clustering is used to initially partition the coarsened graph and generate an initial partitioning scheme. S500: Performs parallel anti-coarsening and refinement processing on the initial partitioning scheme. At each level of anti-coarsening, the parallel boundary FM algorithm is used to optimize node movement and identify regions that are difficult to optimize locally. For these regions, a maximum flow minimum cut model is constructed to perform local repartitioning, and the final partitioning result is output.

2. The method according to claim 1, characterized in that, The S100 process retrieves user-designed netlists and user constraint information, including: Read the netlist file to identify all logical units, modules, and interconnection information; user constraint information is provided through files or system built-in commands, including at least one of fixed location constraints and in-slice constraints. When multiple constraints exist, the system presets priorities, with hard constraints having higher priority than soft constraints. If there is a conflict among hard constraints, an error will be reported, and soft constraints will be selected according to priority order. The pre-merging process in S100 includes: before formally constructing the hypergraph topology, marking the nodes that need to be bundled according to the user constraint information and aggregating the nodes that need to be bundled into one node.

3. The method according to claim 2, characterized in that, The S200 uses streaming graph construction technology to build hypergraph topologies, specifically including: S210: Load the netlist in blocks according to the hierarchical instantiation order. When the number of nodes accumulated in memory reaches a preset threshold, convert it into the topology of the hypergraph and release the temporary string occupied by the parser. S220: A remapping algorithm based on depth-first search order is used to rearrange the IDs of nodes. When parsing the netlist hierarchy tree, consecutive integer IDs are assigned according to the hierarchical path of the instance, so that the physical addresses of the IDs of nodes with similar logical levels are consecutive, thereby improving the CPU cache hit rate. S230: Core topology information includes a unique integer ID and weight for each node, an ID and weight for each hyperedge, and a list of IDs of all nodes connected by that hyperedge. Non-topology attribute information includes the original string name of the instance, port physical coordinates, and attribute description. Non-topology attribute information is stored in a disk database and is only backfilled in the final output.

4. The method according to claim 3, characterized in that, The hybrid coarsening strategies in S300 include: S310: The first stage of merging logical hierarchical structures with inclusion relationships includes: parsing the hierarchical path of nodes; when all child nodes within a logical module exhibit high cohesion in the hypergraph and belong to the same logical unit type definition in the netlist definition, they are determined to be inclusion relationships and merged; during merging, an area threshold is set; if the size of the sub-module does not exceed the area threshold, it is merged into a super node; if the size of the sub-module exceeds the area threshold, only the bottom-level units with the tightest connections within the module are merged. S320: In the second stage, the connectivity between nodes is calculated to merge pairs of nodes with numerous connections. The connectivity between nodes is calculated using the weighted hyperedge connectivity formula, which is: ; in, and There are two nodes. and It connects nodes simultaneously. and nodes The set of superedges It is a super-edge The weight, It is a super-edge The total number of nodes included, denominator Used to punish giant super-edges.

5. The method according to claim 4, characterized in that, The multi-level coarsening process in S300 is implemented in parallel, specifically including: Color the nodes of the hypergraph so that adjacent nodes have different colors, and the sets of nodes with the same color are independent of each other; The set of nodes to be processed is divided into multiple tasks and distributed to multiple threads for parallel processing. During the merging process, only the local neighborhood connectivity affected by the merging is recalculated, and physical address isolation between tasks is achieved through ID rearrangement in S200 to reduce false sharing.

6. The method according to claim 1, characterized in that, Multipath clustering in S400 includes: Multi-path clustering processes the smallest hypergraph that has been reduced to a preset threshold size after multiple rounds of S300 coarsening. A Laplacian matrix is ​​constructed based on the connectivity of the hypergraph. The first k smallest eigenvalues ​​of the matrix and their corresponding eigenvectors are calculated. Each node is mapped to a k-dimensional space composed of eigenvectors. The K-means algorithm is used for clustering to capture the topological characteristics of the graph from a global perspective and identify the natural community structure in the graph. After clustering, a local correction based on dynamic programming is used to ensure that the difference in logical resource utilization among the partitions is minimal, thus meeting the resource balance requirements of hardware verification.

7. The method according to claim 1, characterized in that, The parallel boundary FM algorithm in S500 specifically includes: If a node is connected by at least one hyperedge that spans different partition blocks, then the node is defined as a boundary node; boundary nodes are colored so that non-adjacent nodes can move in parallel in different threads. Only the gains of neighboring nodes affected by the moving node are recalculated; the gains are calculated using a gain function, which is: ; in, For the current node, For the target partition, Indicates due to node The movement transforms the set of hyperedges from spanning partitions to being completely contained within a certain partition. Indicates due to node The movement transforms it from a set of superedges that were originally within a single partition into a set that spans multiple partitions. For super-edge The weight.

8. The method according to claim 1, characterized in that, The S500 identifies regions that are difficult to optimize locally using at least one of the following methods: In multiple iterations, regions where node labels frequently switch between two partitions and the total number of cut edges decreases by less than a preset change threshold are identified as high-frequency flip regions. Local subgraphs with a hyperedge-to-node ratio higher than the average of the whole graph are identified as high-density subgraphs. The region where the objective function value stagnates after multiple rounds of parallel FM movement is identified as the gain stagnation region.

9. The method according to claim 1, characterized in that, The maximum flow minimum cut model constructed in S500 includes: Extract adjacent nodes of a preset level from the center of a region that is difficult to optimize to form a local subgraph. Shrink the core node sets of the subgraph that belong to two different partitions into source and sink nodes. Transform hyperedges into edges and set the capacity of the edges to the weight of the original hyperedges. Use the ISAP algorithm to solve the minimum cut of the local subgraph to find a better partition boundary that the FM algorithm cannot find and break the local minimum. The optimization objective of the partitioning is represented by the objective function, which is: ; in, For super-edge The weight, It is a super-edge The number of partitions spanned.

10. A multi-level hypergraph partitioning system based on netlists, characterized in that, include: The preprocessing module is used to obtain the user-designed netlist and user constraint information, and to pre-merge the nodes in the user-designed netlist according to the user constraint information. The graph construction module is used to construct the hypergraph topology using streaming graph construction technology. It loads the netlist in blocks, rearranges the node IDs so that the physical addresses of nodes with similar logical levels are continuous, and stores only the core topology information in memory while storing non-topology attribute information to disk. The parallel coarsening module is used to perform multi-level coarsening processing using a hybrid coarsening strategy to gradually reduce the size of the graph. The hybrid coarsening strategy includes a first stage of merging logical hierarchical structures with containment relationships to preserve the original hierarchical features of the design, and a second stage of merging node pairs with many connections by calculating the connectivity between nodes. The multi-level coarsening processing is implemented in a parallel manner. The initial partitioning module is used to perform initial partitioning of the coarsened graph by multi-path clustering when the graph size is coarsened to a preset threshold, and to generate an initial partitioning scheme. The refinement and optimization module is used to perform parallel anti-coarsening and refinement processing on the initial partitioning scheme. At each level of anti-coarsening, the parallel boundary FM algorithm is used to optimize node movement and identify regions that are difficult to optimize locally. For these regions, a maximum flow minimum cut model is constructed to perform local repartitioning and output the final partitioning result.

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