Gate driving circuit and display panel

Abstract

This application provides a gate driving circuit and a display panel. The display panel includes a partition control module. The gate driving circuit includes a driving switch circuit, a first switch circuit, a first voltage node, and a second switch circuit. The first switch circuit includes a first transistor and a first capacitor. The first terminal of the first transistor is connected to a clock trace, the second terminal of the first transistor is connected to the clock input terminal of the driving switch circuit, and the control terminal of the first transistor is connected to the first voltage node. The first terminal of the first capacitor is connected to the first terminal of the first transistor, and the second terminal of the first capacitor is connected to the control terminal of the first transistor. Through the first and second switch circuits, the driving switch circuit can obtain a full-amplitude clock input under normal system power supply voltage, realizing low-power driving under partition refresh.

Description

Technical Field

[0001] This application belongs to the field of display panel technology, and particularly relates to a gate driving circuit and a display panel. Background Technology

[0002] Currently, in liquid crystal display panels, the gate driver on array (GOA) circuit is used to generate scan signals to drive the pixel array.

[0003] To reduce the overall power consumption of LCD panels, transistors are typically added to the gate drive circuit. By controlling the input of a clock signal, the output of the scan drive signal is controlled to achieve zoned refresh (a display control technology that divides the screen into multiple areas and sets an independent refresh rate for each area). However, because transistors experience threshold voltage loss when transmitting high-level signals, a higher control voltage is required to control the transistors, which in turn increases the overall circuit power consumption. Summary of the Invention

[0004] The purpose of this application is to provide a gate driving circuit and a display panel, which aims to solve the problem of excessively high control voltage required for partition refresh in conventional technology.

[0005] A first aspect of this application provides a gate driving circuit applied in a display panel. The display panel includes a partition control module. The gate driving circuit includes a driving switch circuit for outputting a gate driving signal based on a clock signal. The gate driving circuit further includes a first switch circuit, a first voltage node, and a second switch circuit. The first switch circuit includes a first transistor and a first capacitor. A first terminal of the first transistor is connected to a clock trace, a second terminal of the first transistor is connected to the clock input terminal of the driving switch circuit, and a control terminal of the first transistor is connected to the first voltage node. A first terminal of the first capacitor is connected to the first terminal of the first transistor, and a second terminal of the first capacitor is connected to the control terminal of the first transistor. The second switch circuit is connected between the partition control module and the first voltage node. The partition control module outputs a control signal. The second switch circuit is configured to pre-charge the first voltage node based on the control signal when the control signal is high and the clock signal is low. The second switch circuit is also configured to disconnect the connection between the partition control module and the first voltage node when the clock signal is high.

[0006] In one embodiment, the second switching circuit includes a second transistor, a third transistor, and a second capacitor; the first terminal of the second transistor is connected to the partition control module and the first terminal of the third transistor respectively, for receiving the control signal; the second terminal of the second transistor is connected to the first terminal of the second capacitor and the control terminal of the third transistor; the control terminal of the second transistor is connected to a high-level trace; and the second terminal of the third transistor and the second terminal of the second capacitor are both connected to the first voltage node.

[0007] In one embodiment, the second switching circuit further includes a fourth transistor, the first terminal of which is connected to the high-level trace, the second terminal of which is connected to the first terminal of the second transistor, and the control terminal of which is connected to the first terminal of the fourth transistor.

[0008] In one embodiment, the gate driving circuit further includes a third switching circuit, which is connected between the first voltage node and the low-level trace. The third switching circuit is used to control the first voltage node to be connected to the low-level trace when a first reset signal is received, and to control the first voltage node to be disconnected from the low-level trace when the first reset signal is not received.

[0009] In one embodiment, the third switching circuit includes a fifth transistor, the first terminal of which is connected to the first voltage node, the second terminal of which is connected to the low-level trace, and the control terminal of which is used to receive the first reset signal.

[0010] In one embodiment, the gate driving circuit further includes a pull-up circuit, a second voltage node, and a third voltage node; the driving switch circuit is connected to the second voltage node and the third voltage node respectively, and the pull-up circuit is connected to the high-level trace and the second voltage node respectively; the third voltage node of the gate driving circuit of the na-th stage is connected to the control terminal of the pull-up circuit of the gate driving circuit of the n-th stage; the driving switch circuit is used to generate and output a gate driving signal based on a clock signal under the control of the voltage of the second voltage node, and to generate and output a cascade trigger signal based on the clock signal, the cascade trigger signal being output through the third voltage node.

[0011] In one embodiment, the gate driving circuit further includes a fourth switching circuit. The first terminal of the fourth switching circuit is connected to the second voltage node, and the second terminal of the fourth switching circuit is connected to the driving switching circuit. The fourth switching circuit is also connected to the partition control module. The fourth switching circuit is used to control the second voltage node to conduct with the driving switching circuit when a high-level control signal is received.

[0012] In one embodiment, the fourth switching circuit is also connected to a low-level trace. The fourth switching circuit is also used to control the second terminal of the fourth switching circuit to be connected to the low-level trace when a first reset signal is received, and to control the second terminal of the fourth switching circuit to be disconnected from the low-level trace when no first reset signal is received.

[0013] A second aspect of this application also provides a display panel, the display panel including the gate driving circuit as described above, the display panel further including a pixel array, and the gate driving circuit being connected to the pixel array.

[0014] In one embodiment, the display panel includes a plurality of gate driving circuits, which are cascaded in sequence.

[0015] The beneficial effects of this invention compared to existing technologies are as follows: By using a first switching circuit and a second switching circuit, the action path of the partition control signal on the driving switching circuit is separated from the power path in the traditional solution. The first switching circuit is used independently to handle the clock signal's on / off state, while the second switching circuit provides lossless pre-charge and high-voltage bootstrap isolation. In this way, the partition control module no longer directly drives the heavily loaded first transistor, avoiding the insufficient output amplitude problem caused by threshold voltage loss in the control path in the traditional solution. The driving switching circuit can obtain a full-amplitude clock input under normal system power supply voltage, with no attenuation in the scan output amplitude. This eliminates the risk of display abnormalities during partition refresh in principle, and eliminates the need for additional power supply voltage, achieving low-power driving under partition refresh. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 2 Specific circuit diagrams of the second and third switching circuits provided in an embodiment of this application; Figure 3 A detailed circuit diagram of a gate driving circuit provided in an embodiment of this application; Figure 4 This is another structural schematic diagram of a display panel provided in an embodiment of this application.

[0017] Specific element symbols: 10, gate drive circuit; 20, display panel; 100, drive switch circuit; 200, zone control module; 300, first switch circuit; 400, second switch circuit; 500, third switch circuit; 600, pull-up circuit; 700, fourth switch circuit. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] Please see Figure 1 , Figure 1 A schematic diagram of the structure of the display panel provided in this embodiment is shown.

[0023] A gate driving circuit 10 is applied in a display panel 20. The display panel 20 includes a partition control module 200. The gate driving circuit 10 includes a drive switch circuit 100, which outputs a gate driving signal based on a clock signal CK. The gate driving circuit 10 also includes a first switch circuit 300, a first voltage node PU_M0, and a second switch circuit 400. Specifically, the partition control module 200 can be an independent logic control unit used to generate and output control signals CTL. The number of control signals CTL can be the same as the number of partitions in the display panel 20.

[0024] The first switching circuit 300 includes a first transistor M0 and a first capacitor C1. The first terminal of the first transistor M0 is connected to the clock trace to receive the clock signal CK. The second terminal of the first transistor M0 is connected to the clock input terminal of the driving switching circuit 100. The control terminal of the first transistor M0 is connected to the first voltage node PU_M0. The first terminal of the first capacitor C1 is connected to the first terminal of the first transistor M0. The second terminal of the first capacitor C1 is connected to the control terminal of the first transistor M0.

[0025] The second switching circuit 400 is connected between the partition control module 200 and the first voltage node PU_M0. The partition control module 200 is used to output the control signal CTL.

[0026] The second switching circuit 400 is configured to precharge the first voltage node PU_M0 based on the control signal CTL when the control signal CTL is high and the clock signal CK is low.

[0027] The second switching circuit 400 is also used to disconnect the partition control module 200 from the first voltage node PU_M0 when the clock signal CK is high.

[0028] It should be noted that the gate drive circuit 10 can control the charging and discharging of the corresponding pixel unit by outputting a high-level gate drive signal, thereby realizing precise addressing and grayscale control of the pixel unit.

[0029] The first terminal of the transistor is the drain, the second terminal is the source, and the control terminal is the gate. The transistor is turned on when the gate-source voltage is greater than the turn-on threshold. When the first transistor M0 is turned on, the clock signal CK can be transmitted to the clock input of the drive switch circuit 100 through the first transistor M0, thereby ensuring the establishment of the gate drive signal. When the first transistor M0 is turned off, the clock signal CK is blocked, and the drive switch circuit 100 cannot output a high-level gate drive signal, thereby stopping the refresh of the corresponding pixel unit and realizing partitioned refresh.

[0030] By using the first switching circuit 300 and the second switching circuit 400, the path of the control signal CTL to drive the switching circuit 100 is separated from the power path in the conventional scheme. The first switching circuit 300 is set up to handle the on and off of the clock signal CK, and the second switching circuit 400 provides lossless pre-charge and high-voltage bootstrap isolation. In this way, the partition control module 200 no longer directly drives the heavily loaded first transistor M0, avoiding the problem of insufficient output amplitude caused by threshold voltage loss in the control path in the conventional scheme.

[0031] The drive switch circuit 100 in this embodiment can obtain a full-amplitude clock input under normal system power supply voltage, and the scan output amplitude has no attenuation. In principle, it eliminates the risk of display abnormalities during partition refresh, and at the same time, it does not require additional power supply voltage, thus truly realizing low-power drive under partition refresh.

[0032] In one embodiment, please refer to Figure 2 The second switching circuit 400 includes a second transistor MA, a third transistor MB, and a second capacitor C2.

[0033] The first terminal of the second transistor MA is connected to the partition control module 200 and the first terminal of the third transistor MB respectively, and is used to receive the control signal CTL. The second terminal of the second transistor MA is connected to the first terminal of the second capacitor C2 and the control terminal of the third transistor MB. The control terminal of the second transistor MA is connected to the high-level trace. The second terminal of the third transistor MB and the second terminal of the second capacitor C2 are both connected to the first voltage node PU_M0.

[0034] Among them, the high-level trace can provide a high-level signal VGH.

[0035] It should be noted that the gate drive circuit 10, which is provided with a first switching circuit 300 and a second switching circuit 400, has a first working stage and a second working stage.

[0036] In the first operating phase, when the control signal CTL is high, the second transistor MA is turned on. The high-level control signal CTL charges the second capacitor C2 through the second transistor MA, establishing a voltage difference across C2. This voltage difference then controls the third transistor MB to turn on. The high-level control signal CTL charges the first voltage node PU_M0 through the third transistor MB, bringing its voltage to the pre-charge voltage, thus pre-charging PU_M0. When the clock signal CK is low, a voltage difference is established across the first capacitor C1. Simultaneously, the rising voltage of the first voltage node PU_M0 further raises the potential of the second terminal of the second transistor MA, causing MA to tend to turn off. This electrically isolates the control terminal of the third transistor MB from the control signal CTL, ensuring that the third transistor MB remains on during the first operating phase and improving the transmission stability and anti-interference capability of the clock signal CK.

[0037] In the second operating phase, when the clock signal CK changes from low to high, the rising edge of the clock signal CK further raises the voltage of the first voltage node PU_M0 through the coupling effect of the first capacitor C1. The voltage of the first voltage node PU_M0 will eventually reach the sum of the pre-charge voltage and the high level of the clock signal CK, which is much greater than the voltage of the control signal CTL. This ensures that the second transistor MA and the third transistor MB remain off in the second operating phase, locking the charge in the first voltage node PU_M0. At this time, the first voltage node PU_M0 becomes a high-voltage floating node, making the on-resistance of the first transistor M0 remain at an extremely low level in the second phase. This ensures the reliable conduction of the first transistor M0 without relying on the high-voltage signal.

[0038] In one embodiment, please refer to Figure 2 The second switching circuit 400 also includes a fourth transistor M_P, the first terminal of the fourth transistor M_P is connected to the high-level trace, the second terminal of the fourth transistor M_P is connected to the first terminal of the second transistor MA, and the control terminal of the fourth transistor M_P is connected to the first terminal of the fourth transistor M_P.

[0039] It should be noted that during the operation of the gate drive circuit 10, the control signal CTL may be lost due to electrostatic discharge (ESD), open circuit, or power fluctuation, resulting in the control signal CTL being floating or constantly low, which in turn prevents the first transistor M0 from conducting normally. The gate drive circuit 10 enters an uncontrollable state, which may lead to a full-screen black screen, screen flickering, or even device burnout.

[0040] When the control terminal of the fourth transistor M_P is connected to its first terminal, the fourth transistor M_P will be continuously conducting. Under normal circumstances, due to the strong driving capability of the control signal CTL, the high-level signal VGH will not affect the level change of the control signal CTL. When the control signal CTL is abnormally lost, the fourth transistor M_P acts as a redundant path, directly injecting the stable voltage of the high-level trace into the first terminal of the second transistor MA and the first terminal of the third transistor MB, thereby maintaining the conducting state of the second transistor MA and the third transistor MB. This ensures that the first transistor M0 can still reliably turn on under abnormal operating conditions, effectively avoiding the risks of black screen, flickering, and thermal failure.

[0041] The fourth transistor M_P can significantly improve the reliability and lifespan of the second switching circuit 400 under long-term high-frequency operation without affecting the bootstrap speed and the final high voltage amplitude.

[0042] In one embodiment, please refer to Figure 2The gate drive circuit 10 also includes a third switch circuit 500, which is connected between the first voltage node PU_M0 and the low-level trace. The third switch circuit 500 is used to control the first voltage node PU_M0 to be connected to the low-level trace when the first reset signal CLR is received, and to control the first voltage node PU_M0 to be disconnected from the low-level trace when the first reset signal CLR is not received.

[0043] The first reset signal CLR can be provided to the third switching circuit 500 after the gate drive circuit 10 completes a frame scan, quickly discharging the charge on the first voltage node PU_M0 to a low level to prevent residual charge from interfering with the normal start of the next frame scan and ensuring the accuracy and stability of the progressive drive timing. The low-level trace can be used to provide a low-level voltage or a reference ground voltage.

[0044] The third switching circuit 500 is turned on only when a valid first reset signal CLR is received, forcibly pulling the first voltage node PU_M0 down to a low level. At other times, it remains in a high impedance state, without affecting the normal pre-charge and bootstrap of the first voltage node PU_M0.

[0045] Specifically, the first reset signal CLR can be a global clear signal or a cascaded trigger signal. The specific configuration can be determined according to actual needs.

[0046] In one embodiment, please refer to Figure 2 The third switching circuit 500 includes a fifth transistor MC. The first terminal of the fifth transistor MC is connected to the first voltage node PU_M0, the second terminal of the fifth transistor MC is connected to the low-level trace, and the control terminal of the fifth transistor MC is used to receive the first reset signal CLR.

[0047] The fifth transistor MC can be configured to turn on and quickly pull the first voltage node PU_M0 low when the first reset signal CLR is received. When the first reset signal CLR is not received, the fifth transistor MC remains off to ensure that the charge of the first voltage node PU_M0 remains stable and does not affect the generation and output of the gate drive circuit 10.

[0048] The first reset signal CLR can be a high-level signal VGH. A low-level trace can provide a low-level signal VSS.

[0049] In one embodiment, the gate drive circuit 10 further includes a pull-up circuit 600, a second voltage node PUn, and a third voltage node Tn.

[0050] The drive switch circuit 100 is connected to the second voltage node PUn and the third voltage node Tn, respectively, and the pull-up circuit 600 is connected to the high-level trace and the second voltage node PUn, respectively. The third voltage node Tn-a of the na-th stage gate drive circuit 10 is connected to the control terminal of the pull-up circuit 600 of the n-th stage gate drive circuit 10.

[0051] The drive switch circuit 100 is used to generate and output a gate drive signal Gn based on the clock signal CK under the control of the voltage of the second voltage node PUn, and to generate and output a cascade trigger signal based on the clock signal CK. The cascade trigger signal is output through the third voltage node Tn. Here, n and a are both positive integers, and the specific value of a is determined according to the timing requirements of the specific cascade trigger signal. For example, a=4 can be taken.

[0052] The drive switch circuit 100 is used to generate and output a gate drive signal Gn based on a clock signal CK under the control of the voltage of the second voltage node PUn, and to generate and output a cascade trigger signal to the third voltage node Tn based on the clock signal CK.

[0053] It should be noted that, taking the gate drive circuit 10 of the nth stage as an example, when the pull-up circuit 600 is turned on, the voltage of the second voltage node PUn is pulled up by the high-level trace. The drive switch circuit 100 can be specifically configured to generate and output the gate drive signal Gn and the cascade trigger signal based on the clock signal CK when the voltage of the second voltage node PUn reaches the set threshold.

[0054] Please see Figure 3 , Figure 3 A detailed circuit diagram of the gate drive circuit 10 provided in this embodiment is shown.

[0055] In one embodiment, please refer to Figure 3 The gate drive circuit 10 also includes a fourth switch circuit 700. The first end of the fourth switch circuit 700 is connected to the second voltage node PUn, the second end of the fourth switch circuit 700 is connected to the drive switch circuit 100, and the fourth switch circuit 700 is also connected to the partition control module 200. The fourth switch circuit 700 is used to control the second voltage node PUn to conduct with the drive switch circuit 100 when a high-level control signal CTL is received.

[0056] The fourth switching circuit 700 can control the on / off state between the second voltage node PUn and the driving switching circuit 100. When the second voltage node PUn and the driving switching circuit 100 are on, the driving switching circuit 100 can respond to the clock signal CK to synchronously output the gate driving signal Gn and the cascade trigger signal. When the second voltage node PUn and the driving switching circuit 100 are off, the driving switching circuit 100 stops outputting the gate driving signal Gn, ensuring that the pixels in that row retain the display content of the previous frame, thus achieving partitioned refresh.

[0057] The fourth switching circuit 700 may include one or more transistors. Specifically, the fourth switching circuit 700 may include a sixth transistor MD. The first terminal of the sixth transistor MD is connected to the second voltage node PUn, the second terminal of the sixth transistor MD is connected to the drive switching circuit 100, and the control terminal of the sixth transistor MD is connected to the partition control module 200 to realize on / off switching in response to the control signal CTL.

[0058] In one embodiment, please refer to Figure 3 The fourth switch circuit 700 is also connected to the low-level trace. The fourth switch circuit 700 is also used to control the second terminal of the fourth switch circuit 700 to be connected to the low-level trace when the first reset signal CLR is received, and to control the second terminal of the fourth switch circuit 700 to be disconnected from the low-level trace when the first reset signal CLR is not received.

[0059] The fourth switch circuit 700 provides a direct discharge path in the reset or shutdown scenario of the display panel 20, eliminating the possibility of a white screen during shutdown or random output abnormalities during the next power-on caused by residual charge.

[0060] Specifically, the fourth switching circuit 700 may include a seventh transistor ME. The first terminal of the seventh transistor ME is connected to the driving switching circuit 100, and the second terminal of the seventh transistor ME is connected to a low-level trace. The control terminal of the seventh transistor ME is used to receive a first reset signal CLR. The seventh transistor ME can be turned on when the first reset signal CLR is received and turned off when the first reset signal CLR is not received, thereby ensuring that the driving switching circuit 100 is not interfered with by the low-level trace during normal operation.

[0061] In some embodiments, the gate drive circuit 10 further includes a pull-down reset module, which is at least connected to the second voltage node PUn. The pull-down reset module is used to control the second voltage node PUn to conduct with the low-level trace upon receiving a second reset signal, thereby quickly pulling the second voltage node PUn low during the reset phase. The second reset signal can be a cascaded trigger signal Tn-b provided by another gate drive circuit 10, where b is a positive integer. The specific value of b is determined according to the timing requirements of the specific cascaded trigger signal; for example, b=6.

[0062] The fourth switching circuit 700 may also include an eighth transistor MF, the first terminal of which is connected to the drive switching circuit 100, the second terminal of which is connected to a low-level trace, and the control terminal of which is used to receive a second reset signal.

[0063] The eighth transistor MF can work with the pull-down reset module to pull the first and second terminals of the sixth transistor MD low simultaneously, thereby releasing charge during the reset phase.

[0064] Please see Figure 4 , Figure 4 Another structural schematic diagram of the display panel provided in this embodiment is shown.

[0065] Furthermore, to better implement the gate driving circuit 10 in any of the above embodiments, based on the gate driving circuit 10 described above, this application embodiment also provides a display panel 20, which includes a pixel array and the gate driving circuit 10 as described above. The gate driving circuit 10 is connected to the pixel array.

[0066] The display panel 20 can specifically be an LCD panel.

[0067] In one embodiment, the display panel 20 includes a plurality of gate driving circuits 10, which are cascaded in sequence.

[0068] The pixel array includes multiple sub-pixels. The gate driving circuit 10 is connected to each row of scan lines in the pixel array in a one-to-one correspondence. It is used to output gate driving signals Gn row by row to achieve precise control of the charging and discharging process of each sub-pixel row by row.

[0069] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0070] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0071] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0072] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0073] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, The device is used in a display panel, which includes a partition control module. The gate driving circuit includes a drive switch circuit, which is used to output a gate driving signal based on a clock signal. The gate driving circuit also includes a first switch circuit, a first voltage node, and a second switch circuit. The first switching circuit includes a first transistor and a first capacitor. The first terminal of the first transistor is connected to the clock trace, the second terminal of the first transistor is connected to the clock input terminal of the driving switching circuit, the control terminal of the first transistor is connected to the first voltage node, the first terminal of the first capacitor is connected to the first terminal of the first transistor, and the second terminal of the first capacitor is connected to the control terminal of the first transistor. The second switching circuit is connected between the partition control module and the first voltage node, and the partition control module is used to output control signals; The second switching circuit is configured to precharge the first voltage node based on the control signal when the control signal is high and the clock signal is low. The second switching circuit is also used to disconnect the partition control module from the first voltage node when the clock signal is high.

2. The gate driving circuit according to claim 1, characterized in that, The second switching circuit includes a second transistor, a third transistor, and a second capacitor; The first terminal of the second transistor is connected to the partition control module and the first terminal of the third transistor respectively, for receiving the control signal. The second terminal of the second transistor is connected to the first terminal of the second capacitor and the control terminal of the third transistor. The control terminal of the second transistor is connected to the high-level trace. The second terminal of the third transistor and the second terminal of the second capacitor are both connected to the first voltage node.

3. The gate driving circuit according to claim 2, characterized in that, The second switching circuit further includes a fourth transistor, the first terminal of which is connected to the high-level trace, the second terminal of which is connected to the first terminal of the second transistor, and the control terminal of which is connected to the first terminal of the fourth transistor.

4. The gate driving circuit according to claim 1, characterized in that, The gate drive circuit further includes a third switching circuit, which is connected between the first voltage node and the low-level trace. The third switching circuit is used to control the first voltage node to be connected to the low-level trace when a first reset signal is received, and to control the first voltage node to be disconnected from the low-level trace when the first reset signal is not received.

5. The gate driving circuit according to claim 4, characterized in that, The third switching circuit includes a fifth transistor, the first terminal of which is connected to the first voltage node, the second terminal of which is connected to the low-level trace, and the control terminal of which is used to receive the first reset signal.

6. The gate driving circuit according to any one of claims 1 to 5, characterized in that, The gate drive circuit further includes a pull-up circuit, a second voltage node, and a third voltage node; The drive switch circuit is connected to the second voltage node and the third voltage node respectively, and the pull-up circuit is connected to the high-level trace and the second voltage node respectively; the third voltage node of the gate drive circuit of the na-th stage is connected to the control terminal of the pull-up circuit of the gate drive circuit of the n-th stage. The drive switch circuit is used to generate and output a gate drive signal based on a clock signal under the control of the voltage of the second voltage node, and to generate and output a cascade trigger signal based on the clock signal, the cascade trigger signal being output through the third voltage node.

7. The gate driving circuit according to claim 6, characterized in that, The gate drive circuit further includes a fourth switch circuit. The first terminal of the fourth switch circuit is connected to the second voltage node, and the second terminal of the fourth switch circuit is connected to the drive switch circuit. The fourth switch circuit is also connected to the partition control module. The fourth switch circuit is used to control the second voltage node to conduct with the drive switch circuit when a high-level control signal is received.

8. The gate driving circuit according to claim 7, characterized in that, The fourth switching circuit is also connected to a low-level trace. The fourth switching circuit is also used to control the second terminal of the fourth switching circuit to be connected to the low-level trace when a first reset signal is received, and to control the second terminal of the fourth switching circuit to be disconnected from the low-level trace when no first reset signal is received.

9. A display panel, characterized in that, The display panel includes a gate driving circuit as described in any one of claims 1 to 8, and further includes a pixel array, wherein the gate driving circuit is connected to the pixel array.

10. The display panel according to claim 9, characterized in that, The display panel includes multiple gate driving circuits, which are cascaded in sequence.

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