A method and device for detecting leakage of a DRAM adjacent capacitor

Abstract

The present disclosure relates to the technical field of semiconductor memory testing, and particularly relates to a method and device for detecting leakage of adjacent capacitors of DRAM. By constructing a mechanism for keeping a target word line activated and keeping a corresponding first sense amplifier in an enabled state, a constant voltage output is continuously provided to the high potential capacitor during a long static period, thereby effectively solving the problem of test pressure difference attenuation caused by static charge loss in traditional leakage detection, and improving the limit detection coverage of weak leakage defects. By applying the physical isolation characteristics of the high and low level data distribution and the sense amplifier alternately arranged to the static voltage maintaining process, only a single data write is required to accurately construct and maintain the static maximum voltage difference between adjacent capacitors during the entire test cycle, thereby improving the judgment accuracy and overall execution efficiency of the dynamic random access memory leakage detection scheme in the production test scene.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory testing technology, and specifically to a method and apparatus for detecting leakage current in adjacent capacitors of DRAM. Background Technology

[0002] When performing leakage detection on adjacent capacitors, Dynamic Random Access Memory (DRAM) often uses a method of writing high and low levels to adjacent capacitors respectively, then turning off the word lines and waiting to observe the leakage failure.

[0003] However, there are two main problems with current leakage detection of adjacent capacitors in DRAM: First, during the resting period when the word line (WL) is off, capacitor leakage will cause the test voltage difference to continuously decrease over time, making it impossible to maintain the extreme stress environment, which makes it easy to miss weak leakage defects; Second, if charge compensation is performed by repeatedly switching the word line on and off, additional dynamic noise and other leakage effects will be introduced, making the failure mode of the test results unclear.

[0004] Therefore, how to address the issues of differential voltage decay and low efficiency in existing DRAM leakage detection, and implement a constant differential voltage leakage detection mechanism that continuously and actively maintains the voltage of the capacitor during the resting period, thereby improving the ultimate coverage and execution efficiency of leakage detection, has become an urgent problem to be solved. Summary of the Invention

[0005] In view of this, this disclosure provides a method and apparatus for detecting leakage current of adjacent capacitors in DRAM, in order to solve the problem of how to achieve a constant voltage difference leakage current detection mechanism that continuously and actively maintains the voltage of capacitors during the resting period, thereby improving the limit coverage and execution efficiency of leakage current detection, in order to address the voltage difference decay and low efficiency of existing DRAM leakage current detection.

[0006] This disclosure provides a method for detecting leakage current in adjacent capacitors of a DRAM, the method comprising: High-level data is written to the memory cell connected to the first bit line in the target memory array, and low-level data is written to the memory cell connected to the second bit line, with the first bit line and the second bit line arranged alternately; wherein, the memory cell includes a capacitor for storing charge, so that after writing high-level data and low-level data, the capacitors in adjacent memory cells are at high potential and low potential respectively; Activate the target word line in the target memory array and enable the first sense amplifier corresponding to the first bit line; During the preset rest period, the target word line is kept in the active state, and the first readout amplifier is kept in the enabled state to continuously provide a high potential to the capacitor connected to the first word line. After the rest period ends, the second sense amplifier corresponding to the second bit line is enabled to read the data of the capacitor connected to the second bit line in order to determine whether there is leakage between the capacitors in adjacent memory cells.

[0007] This disclosure also provides a leakage current detection device for adjacent capacitors in a DRAM, the device comprising: The data writing module is used to write high-level data to the memory cell connected to the first bit line in the target memory array and write low-level data to the memory cell connected to the second bit line. The first bit line and the second bit line are arranged alternately. The memory cell includes a capacitor for storing charge, so that after writing high-level data and low-level data, the capacitors in adjacent memory cells are at high potential and low potential, respectively. The activation enable module is used to activate the target word line in the target memory array and enable the first sense amplifier corresponding to the first bit line; An active hold module is used to keep the target word line in an active state and keep the first sense amplifier in an enabled state for a preset rest period of time so as to continuously provide a high potential to the capacitor connected to the first word line. The leakage detection module is used to enable the second readout amplifier corresponding to the second bit line after the resting time ends, and read the data of the capacitor connected to the second bit line to determine whether there is leakage between the capacitors in adjacent memory cells.

[0008] This disclosure also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the leakage detection method for any of the above-described DRAM adjacent capacitors when executing the computer program.

[0009] This disclosure also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described methods for detecting leakage current in adjacent capacitors of a DRAM.

[0010] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described methods for detecting leakage current in adjacent capacitors of a DRAM.

[0011] In the DRAM adjacent capacitor leakage detection method and apparatus of the above embodiments of this disclosure, firstly, by constructing an active voltage holding mechanism that keeps the target word line active and keeps the corresponding first sense amplifier continuously enabled, a constant voltage output that continuously provides charge compensation to the high-potential capacitor during long-term static periods is realized. This effectively solves the problem of test voltage difference attenuation caused by static charge loss in traditional leakage detection, maintains the ultimate voltage stress environment between adjacent capacitors, and significantly improves the ultimate detection coverage of weak leakage defects. Secondly, by applying the alternating high and low level data distribution and the physical isolation characteristics of the sense amplifier to the static voltage holding process, the maximum static voltage difference between adjacent capacitors can be accurately constructed and maintained throughout the entire test cycle with only a single data write. This eliminates the dynamic switching noise interference and timing overhead introduced by repeatedly switching word lines to compensate for voltage difference attenuation in the prior art, thereby improving the decision accuracy and overall execution efficiency of the dynamic random access memory leakage detection scheme in mass production testing scenarios. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A schematic flowchart illustrating a method for detecting leakage current in adjacent capacitors of a DRAM provided in an embodiment of this disclosure; Figure 2 A schematic diagram of a memory cell structure for a method of detecting leakage current of adjacent capacitors in DRAM provided in an embodiment of this disclosure; Figure 3 A schematic diagram of the physical architecture of the target memory array and SA for a DRAM adjacent capacitor leakage detection method provided in an embodiment of this disclosure; Figure 4 A schematic diagram of the full array data graphic configuration for a leakage detection method for adjacent capacitors in a DRAM provided in an embodiment of this disclosure; Figure 5 A schematic diagram of a leakage current detection device for adjacent capacitors in a DRAM provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0014] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this disclosure.

[0015] As the core data throughput hub of modern computing systems, DRAM, with its high-density physical layout and high-reliability data retention capability under advanced processes, is the core foundation for achieving high-performance computing and improving the overall system stability.

[0016] However, in existing DRAM memory systems based on very large-scale capacitor arrays, the tiny physical spacing between adjacent memory cells (capacitors) easily triggers lateral charge leakage. Existing leakage detection mechanisms typically rely on writing high and low levels to adjacent capacitors, followed by shutting down word lines and allowing the system to remain stationary for an extended period to induce leakage failure. In such scenarios, the voltage holding state of the capacitor array is highly coupled with the test stress to its own static physical characteristics, and traditional testing methods struggle to flexibly inject continuous external compensation charges into the micro-memory cells within the chip.

[0017] Relying solely on the capacitor's static charge retention capability in the off state to apply leakage stress results in several limitations of existing technologies: 1. Existing conventional leakage current testing requires a purely static wait after the word lines are turned off. In this passive state, the capacitors continuously lose charge as leakage occurs, causing the physical voltage difference (test stress) between high and low potential capacitors to decay exponentially over time. In extremely demanding mass production testing scenarios, this voltage drop severely weakens the ability to apply extreme stress to weak leakage defects, easily leading to the missed detection of edge-failure cells. Because weak leakage paths are amplified over time, this can cause reliability issues in the long-term use of the memory system. 2. To compensate for the voltage drop attenuation caused by static storage, some existing technologies attempt to refresh and compensate the charge by repeatedly turning word lines on and off during the storage period. However, high-frequency word line switching not only significantly increases the testing time and computing power consumption, but also introduces a large amount of dynamic switching coupling noise into the extremely sensitive memory array. This high-frequency interference disrupts the pure static leakage current observation environment, making the leakage current judgment results highly susceptible to interference from dynamic noise and leading to rigid misjudgments. 3. When attempting to maintain capacitor potential using the DRAM's internal sense amplifier (SA), without effective bit-line interleaving mapping rules and strong underlying timing constraints, conventional SA enable operations can easily rely on their differential amplification nature to forcibly charge adjacent capacitors simultaneously. That is, a capacitor written to 0 is continuously charged to 0 by its corresponding SA, and a capacitor written to 1 is continuously charged to 1 by its corresponding SA. Thus, even if leakage exists between adjacent capacitors, this leakage effect cannot change the state of their respective capacitors. Existing technology lacks the ability to utilize the physical isolation characteristics of the sense amplifier to construct an asymmetric test environment of "single-sided continuous power supply and single-sided static leakage," making it impossible to spontaneously generate a constant limit leakage detection stress within the chip purely through native logic. This results in severely distorted objective yield indicators for leakage detection. 4. In the static leakage mode of traditional word line shutdown, the drop of high-potential capacitors to low-potential states is often the result of a combination of multiple leakage mechanisms. The charge loss path includes not only lateral leakage between adjacent capacitors, but also a significant amount of vertical leakage, such as subthreshold leakage from access switching devices and junction leakage towards the substrate. Current technologies can only determine cell failure by observing the overall charge reduction, but cannot isolate the interference of these other leakage mechanisms at the physical and electrical level. In other words, the leakage measured by current technologies cannot accurately determine that the leakage originates solely from leakage between capacitors, resulting in measurement results that cannot be 100% accurately attributed to damage to the physical insulation between adjacent capacitors. This mixed leakage effect severely masks the true lateral physical failure boundary between capacitors, leading to a lack of precise data guidance for evaluating the process yield of adjacent capacitor spacing in high-density arrays.

[0018] To address the aforementioned problems, various embodiments of this disclosure provide a method for detecting leakage current in adjacent capacitors of a DRAM. The method includes: writing high-level data to a memory cell connected to a first bit line in a target memory array and writing low-level data to a memory cell connected to a second bit line, with the first and second bit lines arranged alternately; wherein each memory cell includes a capacitor for storing charge, such that after writing high-level and low-level data, the capacitors in adjacent memory cells are at high and low potentials, respectively; activating a target word line in the target memory array and enabling a first sense amplifier corresponding to the first bit line; maintaining the target word line in an activated state and continuously enabling the first sense amplifier for a preset rest period to continuously provide a high potential to the capacitor connected to the first bit line; after the rest period ends, enabling a second sense amplifier corresponding to the second bit line and reading data from the capacitor connected to the second bit line to determine whether leakage current exists between capacitors in adjacent memory cells.

[0019] It should be noted that, in the description of this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this disclosure are used to distinguish similar objects and are not used to describe a particular order or sequence.

[0020] To enable those skilled in the art to better understand the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a method for detecting leakage current in adjacent capacitors of a DRAM, provided in an embodiment of this disclosure. The method may include the following steps: Step S101: Write high-level data to the memory cell connected to the first bit line in the target memory array, and write low-level data to the memory cell connected to the second bit line. The first bit line and the second bit line are arranged alternately.

[0022] In this embodiment, the storage cell includes a capacitor for storing charge, so that after writing high-level data and low-level data, the capacitors in adjacent storage cells are at high potential and low potential, respectively.

[0023] For example, please refer to Figure 2 , Figure 2 This is a schematic diagram of a memory cell structure for a DRAM adjacent capacitor leakage detection method provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, in addition to the aforementioned capacitor, the memory cell also includes an access switch device (e.g., a transistor). The control terminal of the access switch device (e.g., the gate of the transistor) is electrically coupled to a word line in the target memory array to receive an on or off command sent from the word line. The first conducting terminal of the access switch device (e.g., one of the source or drain of the transistor) is electrically connected to one plate of the capacitor, and the second conducting terminal of the access switch device (e.g., the other of the source or drain of the transistor) is electrically connected to the corresponding bit line (BitLine, BL, such as the first bit line or the second bit line mentioned above). Furthermore, the other plate of the capacitor is connected to a preset reference voltage (e.g., plate voltage Vplate).

[0024] It is understandable that when an activation voltage is applied to the target word line, the control terminal of the access switch device responds and makes the first conducting terminal and the second conducting terminal conduct, thereby establishing a physical conduction path between the bit line and the capacitor plate; at this time, the high-level data or low-level data carried by the bit line can be converted into the corresponding charge flow, injected through the conducting access switch device and reside in the capacitor.

[0025] Specifically, the target memory array can refer to a physical array block in DRAM that is composed of multiple word lines and multiple bit lines interwoven for storing data. The aforementioned alternating arrangement of the first and second bit lines can refer to a structural topology in which the two types of bit lines are adjacent and spaced apart on the physical array block.

[0026] High-level data (represented by "1") corresponds to a physical state of full charge or high voltage, while low-level data (represented by "0") corresponds to a physical state of empty charge or low voltage.

[0027] During the execution of step S101 above, based on the hardware connection mechanism of the above-mentioned storage cell, complementary high-level data and low-level data are written to the alternately arranged first bit line and second bit line respectively, so that the capacitors in two physically adjacent storage cells are charged to high potential and discharged to low potential respectively.

[0028] It is understandable that by performing the above-mentioned alternating write operations, a charge residence mode with alternating high and low potentials is formed in the physical space of the target memory array. Through this alternating high and low potential distribution, a maximum physical potential difference is built across the insulating medium of adjacent capacitors, thereby providing the most stringent initial limit voltage stress environment at the microscopic physical level for subsequently exciting and observing the lateral charge leakage phenomenon between adjacent capacitors.

[0029] Step S102: Activate the target word line in the target memory array and enable the first read amplifier corresponding to the first bit line.

[0030] In this embodiment, activating a target word line can mean applying an enable level to the word line of a specific row address, causing the transistor on that word line to be in a conducting state.

[0031] Specifically, when the word line is enabled, the charge inside the capacitor shares charge with the bit line. Since only the first sense amplifier (hereinafter referred to as SA) is enabled at this time, the first SA amplifies the potential signal on the first bit line it is connected to.

[0032] Combined with the logic "1" initially written in step S101, the first SA amplifies the tiny positive potential difference on the first bit line to a stable high voltage state and maintains a continuous high voltage charge on the first bit line, thereby forcing the capacitor connected to the first bit line to be maintained in a high voltage state; while the second SA corresponding to the second bit line remains in an disabled state at this time.

[0033] In step S103, the target word line is kept in an active state for a preset rest period, and the first readout amplifier is kept in an enabled state to continuously provide a high potential to the capacitor connected to the first word line.

[0034] In this embodiment, the preset resting time can refer to a waiting period that is artificially set according to the chip's physical characteristics or test coverage requirements, used to fully excite and accumulate the charge leakage effect.

[0035] Keeping the target word line active can mean that during the aforementioned waiting period, the system does not send a shutdown command to the target word line, so that the corresponding transistor remains on.

[0036] Specifically, during the aforementioned rest period, since the first SA remains in an enabled state, as an active driving circuit, it can continuously provide charge compensation to the capacitor storing logic "1" through the first bit line.

[0037] For example, continuing the test scenario of the aforementioned 0th row word line, if the capacitor connected to the first word line on the 0th row is initially locked to logic "1", during the waiting process, even if the capacitor itself has a tiny leakage channel that causes the internal charge to leak outward, the continuously powered first readout amplifier will immediately sense it and re-inject charge into the capacitor, so that its physical potential is anchored at the highest bias level corresponding to logic "1".

[0038] Understandably, the aforementioned active voltage compensation mechanism completely breaks through the physical limitations of traditional testing, where the charge gradually decreases and the test voltage difference gradually decays as the word line is turned off after data is written. By constructing a stringent and constant limiting voltage difference that does not decay over time throughout the entire testing cycle, the ability to induce and expose weak leakage defects can be effectively improved.

[0039] Step S104: After the resting time ends, enable the second readout amplifier corresponding to the second bit line, read the data of the capacitor connected to the second bit line, and determine whether there is leakage between the capacitors in adjacent memory cells.

[0040] In this embodiment, the end of the settling time means that the long-term physical stress application stage is completed, and the test process enters the data verification and failure determination stage.

[0041] Reading data can refer to activating the second SA, which is responsible for controlling the second bit line, to sense and extract the current true charge residence state of the capacitor that was initially in a low potential state.

[0042] Specifically, determining whether leakage exists can be done by comparing the current logic state of the capacitor connected to the second bit line with the logic "0" initially written in step S101. If an abnormal transition deviates from the initial logic characteristics, it is determined that a leakage path exists.

[0043] For example, still taking the aforementioned 0th row word line as an example, since the capacitor connected to the second bit line initially stores logic "0", under normal circumstances without leakage, after the resting time ends and the second SA is turned on, the weak potential of this capacitor should be amplified and pulled down to logic "0". However, if there is a physical leakage path between adjacent capacitors, the capacitor on the first bit line (logic "1"), which has always been in a stable high voltage state, will cause the potential of the capacitor on the second bit line to be abnormally pulled up during this resting period. Therefore, when the preset delayed resting time is passed and the second SA is turned on, the SA will amplify the potential that has been pulled up by leakage; if the capacitor that was originally supposed to be amplified to logic "0" is ultimately amplified to logic "1" by the second SA, the system can accurately determine that there is a physical leakage failure between these two adjacent capacitors.

[0044] Furthermore, the single-sided voltage holding and failure locking actions involved in steps S102 to S104 above are executed cyclically line by line in the specific test procedure. Starting from the first row, activation commands are issued sequentially to activate the target word line, then the first SA is enabled, and after a period of rest, the second SA is enabled to lock the final potential of the drain terminal. Finally, a precharge command (e.g., PRE command) is issued to close the word line of that row, and the process is repeated for the next row until the leakage test of all rows in the target memory array is completed.

[0045] It is understandable that by using the above-mentioned mechanism of continuous power supply and pressure application on one side and verification after leakage on one side, it is possible to accurately intercept and efficiently screen leakage current of adjacent capacitors in high-density DRAM arrays without increasing additional circuit hardware overhead or introducing high-frequency dynamic switching noise.

[0046] In the DRAM adjacent capacitor leakage detection method and apparatus of the above embodiments of this disclosure, firstly, by constructing an active voltage holding mechanism that keeps the target word line active and keeps the corresponding first sense amplifier continuously enabled, a constant voltage output that continuously provides charge compensation to the high-potential capacitor during long-term static periods is realized. This effectively solves the problem of test voltage difference attenuation caused by static charge loss in traditional leakage detection, maintains the ultimate voltage stress environment between adjacent capacitors, and significantly improves the ultimate detection coverage of weak leakage defects. Secondly, by applying the alternating high and low level data distribution and the physical isolation characteristics of the sense amplifier to the static voltage holding process, the maximum static voltage difference between adjacent capacitors can be accurately constructed and maintained throughout the entire test cycle with only a single data write. This eliminates the dynamic switching noise interference and timing overhead introduced by repeatedly switching word lines to compensate for voltage difference attenuation in the prior art, thereby improving the decision accuracy and overall execution efficiency of the dynamic random access memory leakage detection scheme in mass production testing scenarios. Finally, by constructing an asymmetric testing mechanism of continuous high-potential holding on one side and static low-potential holding on the adjacent side, accurate physical attribution of transverse leakage failure between adjacent capacitors was achieved. Since unrelated failures in DRAM are all manifested as potential drops caused by charge loss, and in this scheme, the drain capacitor is initially at a low potential, if it undergoes an abnormal flip to a high level, the injected charge can only come from the transverse leakage of the adjacent high-potential capacitor, thus eliminating interference from other downward leakage paths at the underlying logic level, and providing a precise root cause analysis basis for locating micro-defects.

[0047] In one possible implementation of the above embodiments, the first bit line is an even-numbered column bit line in the target memory array, and the second bit line is an odd-numbered column bit line in the target memory array; The first and second sense amplifiers are respectively located on opposite sides of the target memory array to control the even-numbered and odd-numbered column lines, respectively.

[0048] In this embodiment, multiple bit lines in the target memory array are alternately divided into odd-numbered and even-numbered bit lines according to their physical arrangement. To adapt to the layout requirements of high-density memory arrays and achieve independent electrical control, this embodiment adopts an interleaved underlying physical architecture in which adjacent memory regions share a read amplifier.

[0049] For example, please refer to the reference Figure 3 , Figure 3 This is a schematic diagram of the physical architecture of the target memory array and SA provided in an embodiment of the present disclosure for a method for detecting leakage current of adjacent capacitors in DRAM. Figure 3 As shown, in the target memory array (e.g., region 2 or region 3 in the figure), multiple rows (word lines WL) and multiple columns (bit lines BL) interweave and connect the memory cells shown in the circles.

[0050] Specifically, the bit lines of one memory region share a single SA module with the bit lines of another adjacent memory region; and the bit lines of even-numbered rows (Even BL, i.e., the aforementioned first bit line) and odd-numbered rows (Odd BL, i.e., the aforementioned second bit line) within the target storage array extend in opposite directions and connect to two SAs located on different sides of the array. Under this physical connection, the SA connected to Even BL is defined as the even-numbered read amplifier (Even SA, i.e., the aforementioned first read amplifier), and the SA connected to Odd BL is defined as the odd-numbered read amplifier (Odd SA, i.e., the aforementioned second read amplifier).

[0051] In terms of specific microscopic physical connections, taking region 2 as an example, its odd-numbered column lines (Odd BL) extend to one side, sharing an Odd SA module with the even-numbered column lines of the adjacent region 1; while its even-numbered column lines (Even BL) extend to the opposite side, sharing an Even SA module with the odd-numbered column lines of the adjacent region 3. That is, for adjacent memory regions, their even-numbered BLs share an SA with the odd-numbered BLs of their adjacent memory regions, and their odd-numbered BLs share an SA with the even-numbered BLs of their adjacent memory regions.

[0052] Understandably, the open architecture design, which uses adjacent areas for sharing and separate odd and even bit lines, allows for complete separation of the control ports for odd and even bit lines. During testing, when one side's Even SA is enabled to apply a continuous high-potential to the even bit lines, the other side's Odd SA remains off. This allows the odd bit lines to remain suspended due to complete physical pin isolation, thus receiving leakage charge. This fundamentally eliminates the signal crosstalk and potential contention issues that are extremely common in traditional same-side SA architectures.

[0053] In the DRAM adjacent capacitor leakage detection method and apparatus of the above embodiments of this disclosure, by mapping the first bit line and the second bit line to the even-numbered column and odd-numbered column in the physical array respectively, and strictly defining the independent SAs located on both sides of the array according to the actual connection assignment of the bit lines, the decoupling of stress application to adjacent capacitors and leakage observation at the physical hardware level is achieved. This not only effectively reuses the original regional shared SA staggered layout inside the DRAM, without adding additional test circuit area overhead to achieve read-write separation, but also more effectively eliminates the problem of adjacent bit line state crosstalk that is easily caused by the traditional SA architecture during continuous voltage holding, ensuring the reliability of the final leakage test results under extreme voltage difference test environment.

[0054] In one possible implementation of the above embodiments, the method further includes a reverse testing step: Write low-level data to the memory cell connected to the first bit line, and write high-level data to the memory cell connected to the second bit line; Activate the target word line and enable the second sense amplifier corresponding to the second bit line; During the preset rest period, the target word line is kept in the active state, and the second sense amplifier is kept in the enabled state to continuously provide a high potential to the capacitor connected to the second bit line. After the rest period of the reverse test step is completed, the first readout amplifier is enabled to read the data of the capacitor connected to the first bit line in order to determine whether there is leakage between the capacitors in adjacent memory cells.

[0055] In this embodiment, considering that during the actual manufacturing process of DRAM, due to factors such as photolithography deviation, the physical defects formed between adjacent capacitors often have structural directionality or electrical asymmetry.

[0056] This means that the ease of conduction of the leakage path may differ significantly in the direction from the first line side to the second line side, and from the second line side to the first line side. If only constant voltage leakage detection in one direction is performed during mass production testing, it is very easy to miss weak leakage defects with unidirectional conduction characteristics.

[0057] Therefore, this embodiment can introduce a reverse testing step.

[0058] Specifically, in the reverse testing step, the test roles of the first bit line (as mentioned above, even-numbered column bit lines) and the second bit line (as mentioned above, odd-numbered column bit lines) and their corresponding amplifiers can be swapped at the physical mechanism level.

[0059] First, by writing low-level data (i.e. logic "0") to the memory cell connected to the first bit line and high-level data (i.e. logic "1") to the memory cell connected to the second bit line, the initial limiting physical potential difference that is completely opposite to the forward test direction is reconstructed across the insulating medium of the adjacent capacitors.

[0060] Subsequently, after activating the target word line and establishing a physical conduction path, the system switches to enabling only the second SA (Odd SA) controlling the second bit line, and keeps it continuously on for the entire preset rest period. During this stage, the second SA acts as a reverse constant active drive circuit, continuously replenishing the charge to the capacitor in the high-potential state, anchoring its physical potential at the highest bias level; while the first bit line and its corresponding first SA (Even SA) remain in an unenabled isolated floating state.

[0061] Furthermore, after the rest period of the reverse test step, the first SA is activated to sense the current real potential of the capacitor on the first bit line. If the capacitor receives leakage charge from the second bit line, causing its read logic state to abnormally flip from the initially written low level to a high level (i.e., from logic "0" to logic "1"), it can be accurately determined that there is a reverse physical leakage failure between the two adjacent capacitors.

[0062] In the DRAM adjacent capacitor leakage detection method and apparatus of the above embodiments of this disclosure, by introducing a reverse testing step on the basis of forward leakage detection, bidirectional full-coverage screening of leakage paths in the physical space of adjacent memory cells is realized, thereby effectively making up for the detection blind spot of unidirectional testing when facing asymmetric semiconductor manufacturing defects, ensuring that effective testing can be obtained no matter what physical direction the leakage channel is biased towards, thereby improving the weak defect interception rate of DRAM and the mass production reliability of the final chip product.

[0063] In one possible implementation of step S101 above, writing high-level data to the memory cell connected to the first bit line and writing low-level data to the memory cell connected to the second bit line in the target memory array includes cyclically executing the following instruction operations according to a preset address traversal order: Send a line activation command to open the word line corresponding to the currently traversed line address; With the word line kept open, the column address is cyclically stepped and write instructions are sent sequentially to alternately write high-level data and low-level data to the memory cells connected to the first and second bit lines. After all column addresses corresponding to the current row address have been written with data, send a row precharge command to close the word line; Step to the next row address and repeat the above instruction operation until the global data writing of the target storage array is completed; wherein, the address traversal order is to traverse the column address first and then the row address, or to traverse the row address first and then the column address.

[0064] In the memory test control algorithm of this embodiment, a series of standard memory operation instructions can be predefined. For example, the ACT instruction can be defined as a row activation instruction to open a row at a specified address; the WRITE instruction can be defined as a write instruction to write data to a specified column address; the READ instruction can be defined as a read instruction to read data from a specified column address; and the PRE instruction can be defined as a row precharge instruction to close a row at a specified address.

[0065] Furthermore, in order to build an initial potential difference for leakage detection in the target storage array, high and low level data need to be alternately written to the corresponding storage cells.

[0066] Specifically, a row activation instruction (such as an ACT instruction) is first sent to the target row address being traversed, causing the transistor on that row word line to turn on.

[0067] Next, within the time window during which the current word line remains open, the system cyclically steps the column address according to the preset traversal logic (e.g., incrementing the column address by a step of 1) and continuously sends write instructions (e.g., WRITE instructions). During this writing process, the system writes logic "1" to the first bit line (such as the even-numbered column bit line mentioned above) and logic "0" to the second bit line (such as the odd-numbered column bit line mentioned above).

[0068] Here, because the column address is switched continuously in a single-row open state, complementary high and low level data can be quickly and alternately injected into the capacitors adjacent to that row.

[0069] Once all target columns of a row have been written, the system immediately issues a precharge instruction (such as a PRE instruction) for that row to close the current word line, independently lock the injected charge inside their respective capacitors, and restore the internal bit lines to their initial equilibrium potential, preparing for the operation of the next row.

[0070] Then, the row address is stepped to the next row, and the activation, alternating write, and precharge operation loop described above is repeated in its entirety. Regardless of whether the column-first, row-first or column-first traversal order is used, this loop process will continue until all capacitors in the entire target memory array have been alternately written with logic "1" and logic "0".

[0071] In the above embodiments of this disclosure, by strictly following the activation, write and precharge operation timing of the memory standard, the initial data loading of the entire array is completed in a nested loop traversal manner, and the physical differential pressure environment for subsequent leakage current excitation is efficiently constructed without adding additional complex control logic.

[0072] Building upon this, to more intuitively demonstrate the final data distribution state formed in the macroscopic physical array by the aforementioned address traversal write operations, please refer to the following example: Figure 4 , Figure 4 This is a schematic diagram of the full array data pattern configuration for a DRAM adjacent capacitor leakage detection method provided in an embodiment of this disclosure, as shown below. Figure 4 As shown, based on Figure 3 In the open interleaved SA architecture shown, the storage cells of the entire array are written with interleaved logical data "0" and logical "1", thereby constructing a data pattern background of bit line stripes in the macroscopic physical array.

[0073] Specifically, such as Figure 4As shown, in the target array, from region 1 to region N, all capacitors on the same bit line along the horizontal direction maintain the same logic polarity, and the polarities of adjacent bit lines are strictly complementary. Combining the aforementioned separate control of even-numbered and odd-numbered bit lines, logic "1" is globally written to all capacitors connected to even-numbered bit lines through the corresponding Even SA, and logic "0" is globally written to all capacitors connected to odd-numbered bit lines through the corresponding Odd SA.

[0074] Understandably, through the aforementioned global write operation, a physical spatial distribution with alternating data polarity along the row direction (WL) and constant data polarity along the column direction (BL) is ultimately formed across all capacitor nodes in the entire target storage array. This globally uniform striped extreme alternating data background ensures that, during the subsequent single-sided sustained voltage holding phase, the physical side of each drain-side capacitor (i.e., the capacitor containing logic "0") in the array is adjacent to the attack source capacitor (i.e., the capacitor containing logic "1") at the highest bias voltage level, thus achieving seamless global coverage of the lateral leakage current limit test stress in physical space.

[0075] In one possible implementation of step S104 above, reading the data of the capacitor connected to the second bit line to determine whether there is leakage between capacitors in adjacent memory cells includes: if the data read by the second read amplifier is flipped from the initially written low-level data to high-level data, then it is determined that there is leakage failure between adjacent capacitors connected to the first bit line and the second bit line.

[0076] In this embodiment, this step establishes specific physical failure logic judgment criteria in forward testing.

[0077] Specifically, since the capacitor connected to the second bit line (i.e. the odd-numbered column bit line) was written with a logic "0" representing low-level data in the initial stage, and its corresponding Odd SA was in an disabled state during the rest period, the capacitor should have remained in a low-voltage state.

[0078] If there is a leakage path between adjacent capacitors, the capacitor on the first bit line (logic "1"), which is always in a stable high voltage charging state, will continuously leak charge to the capacitor on the second bit line, causing the actual physical potential of the capacitor on the second bit line to be gradually pulled up.

[0079] When the resting time ends and the Odd SA is opened for data reading, the Odd SA differentially amplifies the tiny potentials on the bit lines. A capacitor that was originally supposed to be amplified to a low level because it contained a logic "0" is instead abnormally pulled high due to leakage, exceeding the SA's decision toggling threshold, and is ultimately incorrectly amplified to a logic "1".

[0080] The aforementioned data reading and judgment process can be executed through an independent instruction loop. After completing the static holding and pre-charging instruction to close the row, the outer loop controls the row address stepping again, sequentially issuing activation instructions to open each row word line. Simultaneously, while maintaining a single row open state, the inner loop controls the column address stepping, and the column address step size of this inner loop is specifically set to 2. Through this skip-step loop mechanism, the system specifically issues read instructions (e.g., READ instructions) to the target bit lines (e.g., odd-numbered column bit lines) where the leaky end is located for reading tests, while skipping the attack bit lines that are in a high-potential state, thereby significantly saving test time while ensuring detection coverage.

[0081] By capturing this clear data flip from logic "0" to logic "1" (i.e., if the read result of the read instruction is logic "1", it is determined to be a failure), it is possible to directly confirm at the digital logic level that a lateral charge leakage has occurred between adjacent capacitors.

[0082] In the DRAM adjacent capacitor leakage detection method and apparatus of the above embodiments of this disclosure, by accurately mapping the charge leakage phenomenon at the microscopic physical level to the unidirectional state flip of low level to high level in macroscopic digital logic, a very clear failure judgment basis is provided for the test equipment. This mechanism eliminates the hardware overhead of performing complex analog quantity measurement on weak leakage current, and greatly improves the speed and accuracy of automatic identification of leakage defects by mass production test equipment.

[0083] In one possible implementation of the above embodiment, reading the data of the capacitor connected to the first bit line to determine whether there is leakage between capacitors in adjacent memory cells includes: if the data read by the first read amplifier flips from the initially written low-level data to high-level data, then it is determined that there is leakage failure between adjacent capacitors connected to the first bit line and the second bit line.

[0084] In this embodiment, this step establishes the physical failure logic judgment criteria corresponding to the reverse testing step.

[0085] Specifically, in the reverse test scenario, the roles are completely reversed with those in the forward test. The capacitor connected to the first bit line (i.e., the even-numbered column bit line) is written with logic "0" representing low-level data in the initial stage and is in an unenabled floating and leaky state during the rest period; while the capacitor connected to the second bit line (i.e., the odd-numbered column bit line) is written with logic "1" representing high-level data and is maintained by Odd SA with a stable high voltage charge.

[0086] If there is a reverse physical leakage path between capacitors, the odd-numbered column line capacitors under high voltage will cause the potential of the even-numbered column line capacitors to be abnormally pulled up.

[0087] After the reverse rest period ends, Even SA is activated to differentially amplify the current potential of the even-numbered column line capacitors. Similarly, if a capacitor that was originally to be amplified to logic "0" is incorrectly amplified to logic "1" by Even SA, the system can accurately determine that a leakage failure has occurred between adjacent capacitors from the odd-numbered column line to the even-numbered column line.

[0088] Similarly, in the reverse testing process, the system can also implement the traversal writing of reverse data through a completely symmetrical instruction loop operation. In the reverse reading stage, a nested loop mechanism with a column address step of 2 is used to specifically issue read instructions to the first line (i.e., the even-numbered column bit line) in the leakage state. If the read data is a logic "1", then the reverse leakage is determined to be a failure.

[0089] In the DRAM adjacent capacitor leakage detection method and apparatus of the above embodiments of this disclosure, by using the same failure judgment criterion of abnormal flipping from logic "0" to logic "1" in reverse testing, the test system can complete bidirectional leakage coverage screening with a highly unified digital logic closed loop. This mechanism not only simplifies the development complexity of automatic test programs, but also ensures a high degree of consistency in defect judgment boundaries under bidirectional stress testing.

[0090] In one embodiment, please refer to Figure 5 , Figure 5 This is a schematic diagram of a leakage current detection device for adjacent capacitors in a DRAM provided in an embodiment of the present disclosure, as shown below. Figure 5 As shown, the device may include: The data writing module 51 is used to write high-level data to the memory cell connected to the first bit line in the target memory array and write low-level data to the memory cell connected to the second bit line. The first bit line and the second bit line are arranged alternately. The memory cell includes a capacitor for storing charge, so that after writing high-level data and low-level data, the capacitors in adjacent memory cells are at high potential and low potential, respectively. Activate enable module 52 to activate the target word line in the target memory array and enable the first read amplifier corresponding to the first bit line; The active hold module 53 is used to keep the target word line in an active state and keep the first read amplifier in an enabled state for a preset rest time so as to continuously provide a high potential to the capacitor connected to the first word line. The leakage detection module 54 is used to enable the second readout amplifier corresponding to the second bit line after the resting time ends, and read the data of the capacitor connected to the second bit line to determine whether there is leakage between the capacitors in adjacent memory cells.

[0091] In one embodiment, the first bit line is an even-numbered column bit line in the target memory array, and the second bit line is an odd-numbered column bit line in the target memory array; The first and second sense amplifiers are respectively located on opposite sides of the target memory array to control the even-numbered and odd-numbered column lines, respectively.

[0092] In one embodiment, the apparatus further includes a reverse test module for writing low-level data to a memory cell connected to the first bit line and writing high-level data to a memory cell connected to the second bit line. Activate the target word line and enable the second sense amplifier corresponding to the second bit line; During the preset rest period, the target word line is kept in the active state, and the second sense amplifier is kept in the enabled state to continuously provide a high potential to the capacitor connected to the second bit line. After the rest period of the reverse test phase ends, the first readout amplifier is enabled to read the data of the capacitor connected to the first bit line in order to determine whether there is leakage between the capacitors in adjacent memory cells.

[0093] In one embodiment, when the data writing module 51 writes high-level data to the memory cell connected to the first bit line and low-level data to the memory cell connected to the second bit line in the target memory array, it is specifically used to cyclically execute the following instruction operations according to a preset address traversal order: Send a line activation command to open the word line corresponding to the currently traversed line address; With the word line kept open, the column address is cyclically stepped and write instructions are sent sequentially to alternately write high-level data and low-level data to the memory cells connected to the first and second bit lines. After all column addresses corresponding to the current row address have been written with data, send a row precharge command to close the word line; Step to the next row address and repeat the above instruction operation until the global data writing of the target storage array is completed; wherein, the address traversal order is to traverse the column address first and then the row address, or to traverse the row address first and then the column address.

[0094] In one embodiment, when the leakage detection module 54 reads the data of the capacitor connected to the second bit line to determine whether there is leakage between the capacitors in adjacent memory cells, it is specifically used to determine that there is leakage failure between the adjacent capacitors connected to the first bit line and the second bit line if the data read by the second read amplifier flips from the initially written low-level data to high-level data.

[0095] In one embodiment, when the reverse test module reads the data of the capacitor connected to the first bit line to determine whether there is leakage between capacitors in adjacent memory cells, it is specifically used to determine that there is leakage failure between adjacent capacitors connected to the first bit line and the second bit line if the data read by the first read amplifier flips from the initially written low-level data to high-level data.

[0096] It should be noted that the DRAM adjacent capacitor leakage detection device provided in the above embodiments is only illustrated by the division of the above program modules when implementing the corresponding DRAM adjacent capacitor leakage detection method. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the above device can be divided into different program modules to complete all or part of the processing described above. In addition, the device provided in the above embodiments and the corresponding Figure 1 The embodiments of the methods shown belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0097] This disclosure also provides an electronic device having the above-described features. Figure 5 The leakage detection device for adjacent capacitors of the DRAM is shown.

[0098] Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure.

[0099] The following is a detailed reference. Figure 6 This diagram illustrates a suitable structural schematic for implementing an electronic device according to embodiments of the present disclosure. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 602 or a program loaded from memory 608 into random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the electronic device. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0100] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0101] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 609, or installed from a memory 608, or installed from a ROM 602. When the computer program is executed by the processor 601, it performs the functions defined in the DRAM adjacent capacitor leakage detection method of embodiments of this disclosure.

[0102] Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0103] This disclosure also provides a computer-readable storage medium in which the methods described in this disclosure can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded via a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the leakage detection method for adjacent capacitors of DRAM shown in the above embodiments is implemented.

[0104] A portion of this disclosure can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide methods and / or technical solutions according to this disclosure through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, and installation package files. Accordingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions; the computer compiling the instructions and then executing the corresponding compiled program; the computer reading and executing the instructions; or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0105] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for detecting leakage current in adjacent capacitors of a DRAM, characterized in that, The method includes: High-level data is written to a memory cell connected to the first bit line in the target memory array, and low-level data is written to a memory cell connected to the second bit line, with the first bit line and the second bit line arranged alternately; wherein, the memory cell includes a capacitor for storing charge, so that after the high-level data and the low-level data are written, the capacitors in adjacent memory cells are at high potential and low potential, respectively; Activate the target word line in the target memory array and enable the first sense amplifier corresponding to the first bit line; During a preset rest period, the target word line is kept in an active state, and the first sense amplifier is kept in an enabled state to continuously provide the high potential to the capacitor connected to the first bit line. After the resting time ends, the second sense amplifier corresponding to the second bit line is enabled to read the data of the capacitor connected to the second bit line in order to determine whether there is leakage between the capacitors in the adjacent memory cells; if the data read by the second sense amplifier is flipped from the initially written low-level data to high-level data, it is determined that there is leakage failure between the adjacent capacitors connected to the first bit line and the second bit line.

2. The method according to claim 1, characterized in that, The first bit line is an even-numbered column bit line in the target storage array, and the second bit line is an odd-numbered column bit line in the target storage array; The first sense amplifier and the second sense amplifier are respectively disposed on opposite sides of the target memory array to control the even-numbered column bit lines and the odd-numbered column bit lines respectively.

3. The method according to claim 1 or 2, characterized in that, The method also includes a reverse testing step: Write low-level data to the memory cell connected to the first bit line, and write high-level data to the memory cell connected to the second bit line; Activate the target word line and enable the second sense amplifier corresponding to the second bit line; During a preset rest period, the target word line is kept in an active state, and the second sense amplifier is kept in an enabled state to continuously provide the high potential to the capacitor connected to the second bit line. After the rest period of the reverse test step is completed, the first sense amplifier is enabled to read the data of the capacitor connected to the first bit line in order to determine whether there is leakage between the capacitors in the adjacent memory cells.

4. The method according to claim 1, characterized in that, The step of writing high-level data to the memory cell connected to the first bit line and low-level data to the memory cell connected to the second bit line in the target memory array includes cyclically executing the following instruction operations according to a preset address traversal order: Send a line activation command to open the word line corresponding to the currently traversed line address; With the word line kept open, the column address is cyclically stepped and write instructions are sent sequentially to alternately write the high-level data and the low-level data to the memory cells connected to the first bit line and the second bit line; After all column addresses corresponding to the current row address have completed data writing, a row precharge instruction is sent to shut down the word line; Step to the next row address and repeat the above instruction operation until the global data writing of the target storage array is completed; wherein, the address traversal order is to traverse the column address first and then the row address, or to traverse the row address first and then the column address.

5. The method according to claim 3, characterized in that, The step of reading data from the capacitor connected to the first bit line to determine whether there is leakage between the capacitors in the adjacent memory cells includes: if the data read by the first sense amplifier flips from the initially written low-level data to high-level data, then it is determined that there is leakage failure between the adjacent capacitors connected to the first bit line and the second bit line.

6. A leakage current detection device for adjacent capacitors in a DRAM, characterized in that, The device includes: A data writing module is used to write high-level data to a memory cell connected to the first bit line in the target memory array and to write low-level data to a memory cell connected to the second bit line, wherein the first bit line and the second bit line are arranged alternately; wherein, the memory cell includes a capacitor for storing charge, so that after the high-level data and the low-level data are written, the capacitors in adjacent memory cells are at high potential and low potential respectively; The activation enable module is used to activate the target word line in the target memory array and enable the first sense amplifier corresponding to the first bit line; An active hold module is used to keep the target word line in an active state and keep the first sense amplifier in an enabled state for a preset rest period of time, so as to continuously provide the high potential to the capacitor connected to the first bit line. The leakage detection module is used to enable the second sense amplifier corresponding to the second bit line after the resting time ends, and read the data of the capacitor connected to the second bit line to determine whether there is leakage between the capacitors in the adjacent memory cells; if the data read by the second sense amplifier flips from the initially written low-level data to high-level data, it is determined that there is leakage failure between the adjacent capacitors connected to the first bit line and the second bit line.

7. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the leakage detection method for adjacent capacitors of DRAM as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the leakage detection method for adjacent capacitors of DRAM as described in any one of claims 1-5.

9. A computer program product, characterized in that, Includes computer instructions for causing a computer to perform the leakage detection method for adjacent capacitors of DRAM as described in any one of claims 1-5.

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