Power switch tube driving circuit, battery management system and battery assembly

Abstract

Embodiments of the present application provide a power switch tube driving circuit, a battery management system and a battery assembly. The power switch tube driving circuit comprises a bleeder tube, a discharge circuit and a control circuit; the bleeder tube is used to be turned on after a turn-off signal is input at a driving signal end, so that the gate of the power switch tube is discharged through the discharge circuit; the control circuit is used to control the bleeder tube to be in a saturation state in a first stage and to be in an amplification state in a second stage after the first stage, so that the bleeder tube is in the amplification state when the gate voltage of the power switch tube drops to a Miller plateau voltage; wherein in the saturation state, the gate of the power switch tube is discharged at a first discharge rate, and in the amplification state, the gate of the power switch tube is discharged at a second discharge rate, and the first discharge rate is greater than the second discharge rate. The driving circuit is used to reduce the turn-off power consumption while suppressing the turn-off overshoot voltage, and to ensure the safe turn-off of the power switch tube.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a power switch driver circuit, a battery management system, and a battery assembly. Background Technology

[0002] In battery pack short-circuit testing and practical applications of medium- and high-voltage (such as 64V / 72V) battery management system (BMS) protection boards, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) generate induced electromotive force spikes at the moment of turn-off. When the induced electromotive force spike exceeds the withstand voltage of the MOSFET, it is very easy to cause the MOSFET to overvoltage breakdown, resulting in MOSFET failure.

[0003] Current conventional MOSFET turn-off control typically employs either a fast turn-off scheme or a slow turn-off scheme to suppress induced electromotive force (EMF) spikes. The fast turn-off scheme requires additional parallel connection of absorption devices such as a TVS diode (Transient Voltage Suppressor) and a transient suppression capacitor to suppress the EMF spike. This approach not only significantly increases hardware costs, but also, in high-voltage scenarios such as 72V, the induced EMF spike suppression effect is still very limited due to the inherent voltage margin of the MOSFET itself, failing to fundamentally avoid the risk of overvoltage failure. The slow turn-off scheme, in order to suppress induced EMF spikes, significantly prolongs the time the MOSFET remains in the linear region, leading to a sharp increase in turn-off losses. Other power switches with similar MOSFETs and Miller plateau voltages also suffer from the same problems.

[0004] Therefore, the turn-off control process of power switches in the prior art cannot simultaneously suppress overshoot voltage and reduce turn-off losses. Summary of the Invention

[0005] This application provides a power switch driving circuit, a battery management system, and a battery module to reduce turn-off power consumption while suppressing turn-off overshoot voltage, achieving a balance between saving hardware costs and reducing turn-off losses.

[0006] In a first aspect, embodiments of this application provide a power switch driving circuit. One end of the power switch driving circuit is connected to the driving signal terminal of the power switch, and the other end is connected to the gate of the power switch. The power switch driving circuit includes: a bleeder T1, a discharge circuit 101, and a control circuit 102. The first end of the bleeder T1 is connected to the gate of the power switch, and the second end of the bleeder T1 is connected to the discharge circuit 101. The bleeder T1 is turned on after a turn-off signal is input to the driving signal terminal, so that the gate of the power switch discharges through the discharge circuit 101. The control circuit 102 is connected to the third end of the bleeder T1 and is used to control the bleeder T1 to be in a saturated state in a first stage and to control the bleeder T1 to be in an amplified state in a second stage after the first stage, so that when the gate voltage of the power switch drops to the Miller plateau voltage, the bleeder T1 is in an amplified state. In the saturated state, the gate of the power switch discharges at a first discharge rate, and in the amplified state, the gate of the power switch discharges at a second discharge rate, wherein the first discharge rate is greater than the second discharge rate.

[0007] In one possible implementation, the control circuit 102 includes: a first control circuit connected between the third terminal of the bleed tube T1 and the drive signal terminal, used to control the bleed tube T1 to enter a saturation state after a turn-off signal is input to the drive signal terminal, until the first stage ends; and a second control circuit connected between the third terminal of the bleed tube T1 and the drive signal terminal, used to control the bleed tube T1 to enter an amplification state in the second stage.

[0008] In one possible implementation, the first control circuit includes a first resistor R1 and a first capacitor C1 connected in series; the second control circuit includes a second resistor R2; wherein the resistance of the second resistor R2 is greater than the resistance of the first resistor R1.

[0009] In one possible implementation, the discharge circuit 101 includes a third resistor R3.

[0010] In one possible implementation, the control circuit 102 further includes an adjustment circuit, connected in parallel with the discharge circuit 101, for adjusting the current flowing through the discharge circuit 101 to adjust the discharge rate so that the gate voltage of the power switch drops to the Miller plateau voltage at the beginning of the second stage or between the second stages.

[0011] In one possible implementation, the regulating circuit includes at least one of the following: a second capacitor C2 and a Zener diode Z1.

[0012] In one possible implementation, the control circuit 102 further includes a fourth resistor R4, one end of which is connected to the third terminal of the bleeder T1 and the other end is grounded, for providing the base bias voltage of the bleeder T1.

[0013] In one possible implementation, it further includes: a transmission circuit, one end of which is connected to a drive signal terminal and the other end of which is connected to the gate of a power switch transistor, for being turned on when an enable signal is input to the drive signal terminal to connect the gate of the power switch transistor to the drive signal terminal, and turned off when an disable signal is input to the drive signal terminal to disconnect the gate of the power switch transistor from the drive signal terminal.

[0014] Secondly, embodiments of this application provide a battery management system, including: a main control board, the main control board including a power switch transistor and a power switch transistor drive circuit as described above.

[0015] Thirdly, embodiments of this application provide a battery assembly, including a battery cell and a battery management system as described above.

[0016] The power switch driving circuit, battery management system, and battery module provided in this application adjust the gate discharge rate of the power switch by controlling the operating state of the bleeder. The gate of the power switch first discharges at a first discharge rate, entering the first stage, i.e., the fast discharge stage. Then, it discharges at a second discharge rate, entering the second stage, i.e., the slow discharge stage. When the gate voltage of the power switch drops to the Miller plateau voltage, the bleeder is in an amplification state, i.e., the gate of the power switch is in the slow discharge stage. This slow discharge suppresses overshoot voltage and prevents overvoltage failure of the power switch. Through these two stages, the power switch is finally completely turned off, thus achieving staged turn-off of the power switch. The above-described power switch turn-off method combines fast and slow turn-off to achieve a complete turn-off process. It significantly reduces the turn-off overshoot voltage generated during the turn-off process with minimal power consumption, avoiding the problem in existing technologies where the power switch turn-off control process cannot simultaneously suppress overshoot voltage and reduce turn-off losses. This reduces turn-off power consumption while suppressing turn-off overshoot voltage, ensuring safe turn-off of the power switch. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] Figure 1 The circuit for the MOSFET driving circuit provided in this application Figure 1 ;

[0019] Figure 2 The circuit for the MOSFET driving circuit provided in this application Figure 2 ;

[0020] Figure 3 The circuit for the MOSFET driving circuit provided in this application Figure 3 ;

[0021] Figure 4 The circuit for the MOSFET driving circuit provided in this application Figure 4 ;

[0022] Figure 5 The circuit for the MOSFET driving circuit provided in this application Figure 5 ;

[0023] Figure 6 The circuit for the MOSFET driving circuit provided in this application Figure 6 ;

[0024] Figure 7 The simulation waveform diagram of the MOSFET switching process provided in this application;

[0025] Figure 8 This is a schematic diagram of the battery management system provided in this application;

[0026] Figure 9 This is a schematic diagram of the battery assembly provided in this application.

[0027] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0029] First, let me explain the terms used in this application:

[0030] Power switching transistors (PSTs) are a class of power switching devices that use voltage or current control to control the on / off state of a circuit. They are characterized by fast switching speed, high input impedance, and low conduction loss, and are widely used in power conversion and switching control circuits such as battery management systems. The core of a power switching transistor is an insulated-gate field-effect transistor, such as a MOSFET (e.g., NMOS, PMOS, SiC-MOSFET). In addition, other power switching transistors exhibiting the Miller plateau voltage effect are also included.

[0031] Battery Management System (BMS): As the core control unit of power batteries and energy storage battery systems, the BMS is mainly used for real-time monitoring, safety protection, state estimation, and charge / discharge control of the battery pack. By collecting operating parameters such as individual battery cell voltage, total voltage, charge / discharge current, and temperature, the BMS determines the battery's operating status in real time and implements functions such as overcharge protection, over-discharge protection, overcurrent protection, over-temperature protection, and short-circuit protection to prevent battery damage or safety accidents caused by abnormal operation. Simultaneously, the BMS manages the on / off state of the battery charging and discharging circuit by controlling the switching on and off of power switching devices (such as MOSFETs), ensuring the battery operates within a safe and efficient operating range, thereby improving battery reliability and cycle life.

[0032] Power switching transistors such as MOSFETs generate an induced electromotive force (EMF) spike upon turn-off, resulting in a turn-off overshoot voltage. Current conventional MOSFET turn-off control typically employs either a fast turn-off scheme or a slow turn-off scheme to suppress this EMF spike and reduce the turn-off overshoot voltage. While the fast turn-off scheme can quickly turn off the MOSFET, it requires additional parallel connection of absorption devices such as TVS diodes and transient suppression capacitors to suppress the EMF spike. This approach not only significantly increases hardware costs, but also, in high-voltage scenarios such as 72V, the induced EMF spike suppression effect is still very limited due to the inherent voltage margin of the MOSFET itself, failing to fundamentally avoid the risk of overvoltage failure. The slow turn-off scheme, in order to suppress the induced EMF spike, significantly extends the turn-off time, leading to a sharp increase in turn-off power consumption. Therefore, current technologies cannot simultaneously suppress turn-off overshoot voltage and reduce turn-off power consumption during the turn-off process of power switching transistors such as MOSFETs.

[0033] The power switch driving circuit provided in this application discharges the gate of the power switch through a discharge circuit during the power switch turn-off process, reducing the gate voltage of the power switch to turn it off. During the discharge process, the gate discharge rate of the power switch is controlled by a control circuit to control the gate voltage drop rate. The gate voltage first drops rapidly at a first drop rate, entering the first turn-off sequence, and then drops slowly at a second drop rate, entering the second turn-off sequence, until the cutoff voltage is reached, ultimately completely turning off the power switch. This achieves staged turn-off of the power switch. When the gate voltage of the power switch drops to the Miller plateau voltage, slow discharge suppresses overshoot voltage, preventing overvoltage failure of the power switch. The aforementioned power switch turn-off method combines fast turn-off and slow turn-off to achieve a complete turn-off process for the power switch. Fast turn-off enables a rapid response to the turn-off signal of the power switch, followed by slowing down the discharge rate and slow turn-off to reduce the overshoot voltage during the Miller plateau period and avoid excessive overshoot voltage. This solves the problems of excessive overshoot voltage during fast turn-off in existing technologies, which require additional hardware to suppress overshoot voltage, and excessive power consumption during slow turn-off.

[0034] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0035] The following example uses a MOSFET as a power switch; the principle is the same for other types of power switches.

[0036] Figure 1 The circuit for the MOSFET driving circuit provided in this application Figure 1 ,like Figure 1 As shown, one end of the MOSFET driving circuit is connected to the drive signal terminal (DSG) of the MOSFET, and the other end is connected to the gate of the MOSFET (T2). The MOSFET driving circuit includes:

[0037] The discharge tube T1, the discharge circuit 101, and the control circuit 102;

[0038] The first end of the bleeder T1 is connected to the gate of the MOSFET, and the second end of the bleeder T1 is connected to the discharge circuit 101. The bleeder T1 is used to turn on after a turn-off signal is input at the drive signal terminal, so that the gate of the MOSFET discharges through the discharge circuit 101.

[0039] The control circuit 102 is connected to the third terminal of the bleeder T1 and is used to control the bleeder T1 to be in a saturated state in the first stage and to control the bleeder T1 to be in an amplification state in the second stage after the first stage, so that the bleeder T1 is in an amplification state when the gate voltage of the MOSFET drops to the Miller plateau voltage; wherein, in the saturated state, the gate of the MOSFET discharges at a first discharge rate, and in the amplification state, the gate of the MOSFET discharges at a second discharge rate, and the first discharge rate is greater than the second discharge rate.

[0040] In a preferred embodiment of the present invention, the vent pipe T1 can be a transistor, such as... Figure 1 As shown. In addition to transistors, other types of field-effect transistors can be used to control the gate discharge of the MOSFET and regulate the discharge rate.

[0041] In one possible implementation, the driving circuit of the present invention further includes: a transmission circuit, one end connected to a driving signal terminal and the other end connected to the gate of a MOSFET, for conducting when an enable signal is input to the driving signal terminal to connect the gate of the MOSFET to the driving signal terminal, and disengaging when an disable signal is input to the driving signal terminal to disconnect the gate of the MOSFET from the driving signal terminal. Figure 1 As shown, the transmission circuit is located between the gate of the MOSFET and the drive signal terminal DSG. It can be implemented using a unidirectional conducting diode D1. When the drive signal terminal DSG outputs an enable signal, i.e., a high-level signal, diode D1 conducts. When the drive signal terminal DSG outputs a disable signal, i.e., a low-level signal, diode D1 is turned off.

[0042] As illustrated in the example, when the MOSFET is normally turned on, the drive signal is input from the drive signal terminal DSG, and then... Figure 1 The signal transmission path containing diode D1, as shown, provides power to the MOSFET gate to drive the MOSFET to conduct. At this time, under the control of the control module, the discharge tube T1 is in the off state, and the discharge path has not yet been formed.

[0043] When it is necessary to turn off the MOSFET, the drive signal is no longer input through the drive signal terminal. The voltage on the MOSFET gate does not disappear immediately; it needs to discharge until the voltage at the gate drops below the cutoff voltage, thus achieving turn-off. In this scenario, combined with... Figure 1The circuit structure controls the discharge transistor T1 to operate in the saturation region, i.e., in a fully conducting state. Charge at the MOSFET gate flows through the conducting discharge transistor T1 to the discharge circuit for discharge, accompanied by a rapid drop in gate voltage. This is the first stage. In the first stage, because of the saturation state and full conduction, the discharge rate is relatively high, and the gate voltage drops rapidly. After the MOSFET gate begins to discharge, the MOSFET gate voltage begins to decrease. After the gate voltage drops to a certain level, it remains essentially constant, forming a flat plateau region. This voltage is the turn-off plateau voltage, i.e., the Miller plateau voltage. This application found that the overshoot voltage reaches its maximum during the Miller plateau period, making the MOSFET most susceptible to overvoltage failure. That is, the problem of excessive MOSFET overshoot mainly occurs near the Miller plateau voltage. Therefore, this invention employs rapid discharge in the first stage before reaching the Miller plateau voltage to reduce turn-off losses.

[0044] As the gate voltage decreases, approaching the Miller plateau voltage, which can be understood as the end of the first stage, the control circuit controls the bleeder diode T1 to enter the amplification state. This ensures that the MOSFET is in slow discharge when the Miller plateau voltage is reached, thus avoiding excessive overshoot voltage. Specifically, when the bleeder diode T1 switches to the amplification state (not fully open), the current flowing through it is relatively small, achieving slow discharge.

[0045] When the MOSFET enters the Miller plateau period, the discharge transistor T1 is in the second stage, namely the amplification state. The amplification state can start before entering the Miller plateau period or when entering the Miller plateau period. It is preferable to start when entering the Miller plateau period. That is, when the MOSFET gate voltage drops to the Miller plateau voltage at the first decreasing rate, it is a fast turn-off stage. When the MOSFET gate voltage drops to the cutoff voltage at the second decreasing rate, it is a slow turn-off stage. That is, the MOSFET is turned off quickly before the overshoot voltage reaches its maximum and slowly when the overshoot voltage reaches its maximum. This minimizes the turn-off power consumption and suppresses the turn-off overshoot voltage, ensuring the safe turn-off of the MOSFET.

[0046] In the above implementation, by setting up a discharge tube T1, two discharge processes, fast discharge and slow discharge, are achieved for the MOSFET. There is no need to set up two discharge paths. The working state of the discharge tube T1 can be controlled by the control circuit, which simplifies the circuit structure and saves circuit hardware costs.

[0047] Figure 2 The circuit for the MOSFET driving circuit provided in this application Figure 2 ,like Figure 2 As shown, the control circuit 102 includes:

[0048] The first control circuit is connected between the third terminal of the bleed tube T1 and the drive signal terminal. It is used to control the bleed tube T1 to enter the saturation state after a turn-off signal is input at the drive signal terminal, until the first stage ends.

[0049] The second control circuit is connected between the third terminal of the bleeder tube T1 and the drive signal terminal, and is used to control the bleeder tube T1 to enter the amplification state in the second stage.

[0050] The control circuit 102 uses the first control circuit and the second control circuit to make the discharge tube T1 work in saturation state and amplification state respectively, so as to adjust the discharge rate of the MOSFET gate and realize the staged turn-off of the MOSFET.

[0051] When the MOSFET needs to be turned off and the drive signal is no longer input through the drive signal terminal, the first control circuit is activated. Through the control of the first control circuit, the discharge tube T1 enters saturation and is fully turned on. The MOSFET gate discharges rapidly, ensuring the MOSFET turn-off speed while avoiding MOSFET mis-turn-on and energy loss during turn-off. This is the first stage. Until the end of the first stage, the first control circuit is used to control the discharge tube T1 to remain in saturation to ensure rapid MOSFET turn-off.

[0052] After the first stage ends, the second control circuit is activated. The second control circuit controls the discharge tube T1 to enter the amplification state, and the MOSFET gate begins to discharge slowly, entering the second stage. The second control circuit ensures that the MOSFET is in slow discharge when the MOSFET gate voltage drops to the Miller plateau voltage to avoid excessive overshoot voltage, until the MOSFET gate voltage drops to the cutoff voltage and the MOSFET is completely turned off.

[0053] This phased turn-off control, which first accelerates and then slows down, resolves the contradiction between overshoot from excessively fast turn-off and excessive losses from excessively slow turn-off, while also adapting to the turn-off characteristics of MOSFETs and improving the reliability and stability of the circuit. Simultaneously, the first and second control circuits work in a time-sharing coordinated manner to achieve precise switching of the operating state of the bleeder tube T1.

[0054] Figure 3 The circuit for the MOSFET driving circuit provided in this application Figure 3 The first and second control circuits can employ various control methods. In a preferred embodiment of the present invention, such as... Figure 3 As shown, the first control circuit includes a first resistor R1 and a first capacitor C1 connected in series; the second control circuit includes a second resistor R2; wherein the resistance value of the second resistor R2 is greater than the resistance value of the first resistor R1.

[0055] like Figure 3As shown, T1 is a PNP transistor. The core voltage condition for PNP transistor saturation is that the emitter voltage is higher than the base voltage, and the saturation conduction voltage threshold is met, i.e., V1. EB ≥0.7V. Optionally, the resistance of the first resistor R1 can be selected as 1kΩ, and the resistance of the second resistor R2 can be selected as 47kΩ.

[0056] In this circuit, when the drive signal terminal DSG receives a turn-off signal (i.e., suddenly changes from high to low), C1 begins to charge due to the voltage change across it. Since the resistance of the second resistor R2 is greater than that of the first resistor R1, the base charge of the transistor enters the DSG terminal through the path of R1 and C1, activating the first control circuit (first resistor R1 + first capacitor C1). Because the drive signal terminal is low, the base voltage of T1 drops rapidly. However, due to the cutoff effect of D1, the emitter voltage of T1 does not drop immediately. The emitter and base voltages of T1 meet the transistor saturation condition, and T1 enters saturation, becoming fully conductive. The MOSFET gate discharges rapidly until the first stage ends, and C1 is fully charged (equivalent to the first resistor R1 + first capacitor C1 path being disconnected), at which point the first control circuit ceases operation.

[0057] After C1 is fully charged and the first control circuit exits operation, the second control circuit containing R2 begins operation. The base charge of the transistor enters the DSG terminal through the path containing R2. At this time, because the resistance of the second resistor R2 is greater than the resistance of the first resistor R1, the base current decreases significantly. Due to the effect of the base current, T1 is removed from the saturation condition and meets the amplification condition. T1 switches from the saturation state to the amplification state, realizing the slow discharge of the MOSFET gate and entering the second turn-off stage.

[0058] The first and second control circuits described above can automatically control the state switching of the transistor without the need for additional switching devices, such as controllers or active switches, to achieve the control process of the transistor's saturation and amplification states, saving hardware costs and simplifying the circuit structure.

[0059] Figure 4 The circuit for the MOSFET driving circuit provided in this application Figure 4 .like Figure 4 As shown, in another possible implementation, the discharge circuit 101 includes a third resistor R3.

[0060] The discharge circuit 101 can use a discharge resistor for discharge, or other forms of discharge devices can be used, as long as they can safely and stably discharge the MOSFET gate. The control circuit 102 can control the discharge rate of the MOSFET gate, such as using... Figure 1When the discharge resistor is used for discharge, the control circuit 102 mainly adjusts the gate discharge current of the MOSFET. By grounding the discharge resistor, the charge on the gate of the MOSFET is released, thereby reducing the gate voltage of the MOSFET and realizing the phased turn-off of the MOSFET.

[0061] Figure 5 The circuit for the MOSFET driving circuit provided in this application Figure 5 .like Figure 5 As shown, preferably, the control circuit 102 further includes: an adjustment circuit, which is arranged in parallel with the discharge circuit 101, for adjusting the current flowing through the discharge circuit 101 to adjust the discharge rate so that the gate voltage of the MOSFET drops to the Miller plateau voltage at the beginning of the second stage or between the second stages.

[0062] To prevent the MOSFET gate voltage from dropping to the Miller plateau voltage in the first stage, thus failing to effectively suppress overshoot voltage, the control circuit 102 of this invention also includes an adjustment circuit. For example... Figure 5 As shown, the regulating circuit and the discharge circuit are connected in parallel. The regulating circuit can adjust the discharge current of the third resistor R3, thereby adjusting the gate discharge rate of the MOSFET. This causes the gate voltage of the MOSFET to drop to the Miller plateau voltage at the beginning of the second stage or between the second stages, so as to suppress the overshoot voltage by slow discharge and ensure the safe turn-off of the MOSFET.

[0063] Figure 6 The circuit for the MOSFET driving circuit provided in this application Figure 5 .like Figure 6 As shown, in an optional embodiment of the present invention, the regulating circuit includes at least one of the following: a second capacitor C2 and a Zener diode Z1.

[0064] like Figure 6 As shown, the regulating circuit includes a second capacitor C2 and a Zener diode Z1. Both have similar functions, adjusting the gate discharge rate of the MOSFET by absorbing the discharge current of the discharge circuit 101. The second capacitor C2 and the Zener diode Z1 are absorption devices used to absorb current. The regulating circuit can also incorporate other types of absorption devices, or more absorption devices can be connected in parallel to achieve a better regulating effect.

[0065] Preferably, the selection parameters of the second capacitor C2 and the Zener diode Z1 are related to those of the first capacitor C1. To ensure that the MOSFET gate voltage drops to the Miller plateau voltage just as the bleeder diode T1 enters the second state after the first capacitor C1 is fully charged, achieving optimal energy consumption and overshoot suppression, the second capacitor C2 and the Zener diode Z1, in conjunction with the first resistor R1 and the first capacitor C1, enable the first stage of MOSFET turn-off to rapidly approach the Miller plateau voltage Vp at which conduction occurs. After the first capacitor C1 is fully charged, the second stage of MOSFET turn-off is achieved. At this point, the bias current of the bleeder diode T1 decreases, thus slowing down the MOSFET turn-off speed and reducing the MOSFET turn-off induced electromotive force spike.

[0066] like Figure 6 As shown, the control circuit 102 also includes a fourth resistor R4, one end of which is connected to the third terminal of the bleeder T1 and the other end is grounded, for providing the base bias voltage of the bleeder T1 to prevent the bleeder T1 from being mis-biased.

[0067] In addition, such as Figure 6 As shown, the driving circuit of the present invention also includes a fifth resistor R5, one end of which is connected to the driving signal terminal DSG, and the other end is connected to the control circuit. A sixth resistor R6 is connected at one end to the emitter of the bleeder T1, and at the other end to the gate of the MOSFET. Both the fifth resistor R5 and the sixth resistor R6 are used to achieve stable current and anti-interference effects.

[0068] Figure 7 The diagram shows a simulation waveform of an optional MOSFET switching process using the drive circuit of the present invention. Figure 7 This diagram illustrates the dynamic changes of three key electrical quantities during the turn-off process of a MOSFET: the horizontal axis represents time, measured in seconds (s), with a time range of 500 μs to 1.5 ms. The vertical axes represent: drain current Id (A), drain voltage Vds (V), and gate voltage Vgs (V).

[0069] This period includes three phases:

[0070] Stage 1: On-state steady state (500μs-1ms), Vgs rises slowly and stabilizes at around 15V, and the MOSFET is fully turned on.

[0071] Phase 2: Turn-off Transition (approximately 1ms-1.05ms). Vgs rapidly drops from its steady-state value, and the MOSFET begins to turn off. Id momentarily spikes (peak value approximately 280-300A), then begins to decay. Vds rapidly rises from 0V, entering the voltage ramp-up phase. This phase corresponds to the core stage of the MOSFET gate starting to discharge and entering turn-off, and is the critical period of the discharge process. Specifically, the gate-source voltage Vgs rapidly drops from its steady-state 15V, corresponding to the input of a turn-off signal at the drive signal terminal. The bleeder diode T1 enters saturation, the MOSFET gate begins to discharge rapidly, the gate voltage drops rapidly, triggering the MOSFET to start turning off, entering the first phase. The drain current Id momentarily spikes to a peak value of approximately 280-300A, then begins to decay. This phenomenon is due to the MOSFET switching from conduction to turn-off during rapid gate discharge, releasing the energy stored in the parasitic inductance and capacitance of the circuit, generating a transient current surge. The drain-source voltage Vds rises rapidly from 0V, entering the voltage ramp-up phase. This corresponds to the MOSFET turn-off transition process, during which the conduction capability gradually weakens, and the voltage between the drain and source begins to rise again. This is a direct waveform representation of the MOSFET turn-off caused by gate discharge.

[0072] Phase 3: Steady-state after turn-off (1.05ms-1.5ms), Vgs stabilizes at approximately 8~10V, and the MOSFET gate remains in turn-off bias. Vds rises to approximately 60V and then remains stable, and the MOSFET enters the off state, bearing the full bus voltage. Id gradually decays from its peak value, slowly decreasing over time.

[0073] These waveforms, through smooth current spikes, gradual voltage rises, and oscillating gate voltage changes, intuitively demonstrate the effective suppression of overshoot during MOSFET switching by the drive circuit. This not only improves the MOSFET turn-off speed but also ensures the safe turn-off of the MOSFET.

[0074] For example, the power transistor turn-off process adjusted by a two-stage circuit may include: In the first stage, by using a first capacitor C1 biased by the bleeder, combined with a second capacitor C2 and a Zener diode Z1, the clamping voltage is adjusted to a suitable Miller plateau of the power transistor, thereby limiting the continued rise of the current. Here, the first capacitor C1 can be an accelerating capacitor, and the second capacitor C2 can be a bleeder circuit capacitor.

[0075] In the second stage, after the first capacitor C1 is fully charged, the circuit enters a slow discharge phase, thereby suppressing the voltage spike when the power transistor is turned off. The formula is Vds = L di / dt. In normal applications, the value of L remains constant, and di corresponds to the peak current. In the first stage, current ramp-up is suppressed, and dt corresponds to the time from the Miller plateau to the power transistor's turn-off. In the second stage, dt is increased to achieve a comprehensive effect that reduces Vds.

[0076] like Figure 7 As shown in the waveform diagram, the simulation settings are as follows: the short circuit is applied at 1ms, and the system response time is approximately 10us. 1. The waveform shows the power transistor turn-off process. In the first stage, the power transistor control voltage drops rapidly to the power transistor Miller plateau, at which point the current no longer rises.

[0077] 2. After the first capacitor C1 is fully charged, the circuit enters the second stage of slow discharge, which prolongs the time from the Miller plateau to the complete cutoff of the power transistor, thereby reducing di / dt and achieving the effect of suppressing the Vds peak voltage.

[0078] In summary, the power switch driving circuit provided by this invention adopts a combination of fast turn-off and slow turn-off to realize the complete turn-off process of the power switch. It significantly reduces the turn-off overshoot voltage generated during the turn-off process with a small amount of power consumption, avoiding the problem in the prior art that the turn-off control process of the power switch cannot simultaneously suppress overshoot voltage and reduce turn-off losses. It reduces turn-off power consumption while suppressing turn-off overshoot voltage, ensuring the safe turn-off of the power switch.

[0079] This application also provides a battery management system. Figure 8 A schematic diagram of the battery management system provided in this application is shown below. Figure 8 As shown, the battery management system includes a main control board 80, which includes a power switch transistor 801 and a power switch transistor drive circuit 802 as described above in this invention.

[0080] This application also provides a battery assembly. Figure 9 The schematic diagram of the battery assembly provided in this application is as follows: Figure 9 As shown, the battery assembly includes a battery cell 901 and a battery management system 902 as described above.

[0081] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A power switch driving circuit, characterized in that, One end of the power switch driving circuit is connected to the driving signal terminal of the power switch, and the other end is connected to the gate of the power switch; the power switch driving circuit includes: a discharge tube T1, a discharge circuit (101), and a control circuit (102). The first end of the bleed tube T1 is connected to the gate of the power switch tube, and the second end of the bleed tube T1 is connected to the discharge circuit (101). The bleed tube T1 is used to conduct after a turn-off signal is input at the drive signal terminal, so that the gate of the power switch tube discharges through the discharge circuit (101). The control circuit (102) is connected to the third terminal of the bleeder T1 and is used to control the bleeder T1 to be in a saturated state in the first stage and to control the bleeder T1 to be in an amplification state in the second stage after the first stage, so that the bleeder T1 is in an amplification state when the gate voltage of the power switch drops to the Miller plateau voltage; wherein, in the saturated state, the gate of the power switch discharges at a first discharge rate, and in the amplification state, the gate of the power switch discharges at a second discharge rate, the first discharge rate being greater than the second discharge rate; the control circuit (102) includes: The first control circuit is connected between the third end of the venting tube T1 and the drive signal end, and is used to control the venting tube T1 to enter the saturation state after the turn-off signal is input at the drive signal end, until the first stage ends. The second control circuit is connected between the third end of the bleed tube T1 and the drive signal end, and is used to control the bleed tube T1 to enter the amplification state in the second stage.

2. The power switch driving circuit according to claim 1, characterized in that, The first control circuit includes: a first resistor R1 and a first capacitor C1 connected in series; The second control circuit includes a second resistor R2; wherein the resistance value of the second resistor R2 is greater than the resistance value of the first resistor R1.

3. The power switch driving circuit according to claim 1, characterized in that, The discharge circuit (101) includes a third resistor R3.

4. The power switch driving circuit according to claim 1, characterized in that, The control circuit (102) also includes: An adjustment circuit, connected in parallel with the discharge circuit (101), is used to adjust the current flowing through the discharge circuit (101) to adjust the discharge rate so that the gate voltage of the power switch drops to the Miller plateau voltage at the beginning of the second stage or between the second stages.

5. The power switch driving circuit according to claim 4, characterized in that, The regulating circuit includes at least one of the following: a second capacitor C2 and a Zener diode Z1.

6. The power switch driving circuit according to claim 1, characterized in that, The control circuit (102) also includes: The fourth resistor R4 is connected at one end to the third terminal of the bleeder T1 and at the other end to ground, and is used to provide the base bias voltage of the bleeder T1.

7. The power switch driving circuit according to claim 1, characterized in that, Also includes: The transmission circuit has one end connected to the drive signal terminal and the other end connected to the gate of the power switch. It is used to turn on when an enable signal is input to the drive signal terminal to connect the gate of the power switch to the drive signal terminal, and to turn off when the disable signal is input to the drive signal terminal to disconnect the gate of the power switch from the drive signal terminal.

8. A battery management system, characterized in that, include: The main control board includes a power switching transistor and a power switching transistor drive circuit as described in any one of claims 1 to 7.

9. A battery assembly, characterized in that, Includes battery cells and the battery management system as described in claim 8.

Images