A DCM and CCM mode fast switching circuit

Abstract

The application discloses a DCM and CCM mode fast switching circuit, and relates to the technical field of peak current mode control, which comprises a fast error amplifier, a negative end of the error amplifier is used for receiving a feedback voltage, a positive end of the error amplifier receives a reference voltage, the error amplifier is used for outputting a COMP signal, a fast comparator unit in the error amplifier outputs an FB_HI signal, the FB_HI signal is high when the feedback voltage is greater than the reference voltage, and the FB_HI signal is low when the feedback voltage is less than the reference voltage; a fast comparator, a positive end of the fast comparator is used for receiving a low reference voltage, a negative end of the fast comparator is used for receiving the COMP signal, and the fast comparator is used for outputting a Comp_Low signal; a NAND gate group, the NAND gate group comprises a first NAND gate and a second NAND gate, the first NAND gate and the second NAND gate are used for receiving the Comp_Low signal and the FB_HI signal respectively; a delay unit; and a flip-flop group. The application can effectively reduce the number of PWM in the CCM mode, so that the output voltage ripple is reduced.

Description

Technical Field

[0001] This invention relates to the field of peak current mode control technology, and in particular to a fast switching circuit for DCM and CCM modes. Background Technology

[0002] Traditional asynchronous peak current mode controlled Buck converter, see Figure 1 There is no switching transistor between SW and ground (GND), only a freewheeling diode. When the load current decreases from large to small until it reaches 0, and the upper transistor is turned off, the inductor current becomes less than 0. Because there is no switching transistor between SW and ground (GND), the SW node will be charged by the reverse inductor current. Once the SW voltage is greater than the VOUT voltage, the inductor current will increase from negative to positive. Once the inductor current becomes positive again, the SW node charges VOUT through the inductor. Because the upper transistor is turned off, the SW node voltage will quickly discharge and become less than the VOUT voltage again. Then the inductor current becomes negative again, repeating the above periodic oscillation process. Therefore, in an asynchronous BUCK converter, when the load current is very small, once the upper transistor is turned off, once the inductor current crosses 0, the inductor current will oscillate near the 0 current, causing the average current of the inductor throughout the entire cycle to be much greater than the 0 current. Therefore, once the load current is 0, for the asynchronous BUCK to stabilize, it needs to enter DCM (Discontinuous Conduction Mode), skipping a certain number of switching cycles, so that the average current of the inductor equals the output current, reaching a steady state. Once the load current starts to increase, the number of skipped switching cycles in DCM mode is reduced, and the load current continues to increase until it returns to CCM (Continuous Conduction Mode) mode from DCM mode. Therefore, asynchronous BUCK converters need to be designed with CCM and DCM mode switching circuits to switch back and forth between the two modes according to the load conditions.

[0003] Therefore, a circuit for fast switching between DCM and CCM modes was developed to solve the above problems. Summary of the Invention

[0004] This invention proposes a fast switching circuit for DCM and CCM modes to solve the problem that the slow switching speed of existing peak current mode controlled Buck converters leads to delayed mode switching and large voltage ripple in the final output.

[0005] The present invention achieves the above objectives through the following technical solutions:

[0006] This invention provides a fast switching circuit for DCM and CCM modes, comprising:

[0007] The error amplifier has a negative terminal for receiving the feedback voltage and a positive terminal for receiving the reference voltage. It outputs the COMP signal and the fast comparator unit in the error amplifier outputs the FB_HI signal. When the feedback voltage is greater than the reference voltage, the FB_HI signal is high; when the feedback voltage is less than the reference voltage, the FB_HI signal is low.

[0008] The fast comparator has its positive terminal used to receive a low reference voltage, its negative terminal used to receive the COMP signal, and its output is the Comp_Low signal.

[0009] The NAND gate group includes a first NAND gate and a second NAND gate, which are used to receive the Comp_Low signal and the FB_HI signal, respectively.

[0010] The delay unit's input is connected to the output of the first NAND gate.

[0011] The trigger group includes a first trigger and a second trigger. The CLK terminal of the first trigger is connected to the output terminal of the delay unit, the RST_N terminal of the first trigger is connected to the output terminal of the second NAND gate, and the QN terminal of the first trigger is connected to the RST_N terminal of the second trigger through an inverter.

[0012] Furthermore, the error amplifier includes a bias current source, MP1, MP2, MP3, MP4, MP5, MP6, MP7, MN1, MN2, MN3, MN4, MN5, resistor R1, capacitor C1, and a hysteresis comparator. The bias current source is connected to the drain of MP1, the drain of MP1 is connected to its gate, the source of MP1 is connected to the power rail VDD, the gate of MP1 is connected to the gate of MP3, and the source of MP3 is connected to the power supply. The power rail VDD is used as the connection point. The drain of MP3 is connected to the source of MP4 and the source of MP5. The source of MP2 is connected to the power rail VDD. The drain and gate of MP2 are connected together. The gate of MP2 is connected to the gate of MP6. The gate of MP2 is connected to the gate of MP7. The drain of MP2 is connected to the drain of MN1. The gate of MP4 is connected to the feedback voltage. The drain of MP4 is connected to the drain of MN2. The gate of MP5 is connected to the reference voltage. The drain of MP5 is connected to the drain of MN3. The source of transistor MP6 is connected to the power rail VDD. The drain of transistor MP6 is connected to the input of the hysteresis comparator. The drain of transistor MP6 is also connected to the drain of transistor MN4. The source of transistor MP7 is connected to the power rail VDD. The drain of transistor MP7 is connected to the output node COMP. The drain of transistor MP7 is also connected to the drain of transistor MN5. The drain of transistor MP7 is also connected to the upper end of resistor R1. The gate of transistor MN1 is connected to the gate of transistor MN2. The source of transistor MN1 is connected to GND. The gate and drain of transistor MN2 are connected together. The source of transistor MN2 is connected to GND. The gate and drain of transistor MN3 are connected to ND. The gate of transistor MN3 is connected to the gate of transistor MN4. The gate of transistor MN3 is connected to the gate of transistor MN5. The source of transistor MN3 is connected to GND. The drain of transistor MN4 is connected to the input of the hysteresis comparator. The source of transistor MN4 is connected to GND. The source of transistor MN5 is connected to GND. The upper end of resistor R1 is connected to the output node COMP. The lower end of resistor R1 is connected to the upper end of capacitor C1. The lower end of capacitor C1 is connected to GND. The output of the hysteresis comparator is the signal FB_HI.

[0013] Furthermore, when the feedback voltage is higher than the reference voltage, the gate potential of MP4 is higher than that of MP5. MP3 mirrors the current obtained by MP1. At this time, the current obtained by MP4 is less than that obtained by MP5. The current in the branch where MP4 is located is mirrored to the branch where MN1 is located through the current mirror composed of MN2 and MN1. The current in the branch where MN1 is located is mirrored to the branch where MP6 is located by MP2 and MP6. The current in the branch where MP5 is located is mirrored to the branch where MN4 is located by the current mirror composed of MN3 and MN4. When the current of MP4 is less than the current of MP5, the current of MP6 is less than the current of MN4. At this time, the input potential of the hysteresis comparator is pulled low. After passing through the hysteresis comparator, the output signal FB_HI is high. Conversely, when the feedback voltage is lower than the reference voltage, the output of FB_HI is low.

[0014] Similarly, when the feedback voltage is higher than the reference voltage, the current received by MP4 is less than that received by MP5. The current in the branch where MP4 is located is mirrored to the branch where MN1 is located through the current mirror composed of MN2 and MN1. The current in the branch where MN1 is located is then mirrored to the branch where MP7 is located by MP2 and MP7. The current in the branch where MP5 is located is mirrored to the branch where MN5 is located by the current mirror composed of MN3 and MN5. When the current of MP4 is less than the current of MP5, the current of MP7 is less than the current of MN5. At this time, the output Comp_Low signal decreases. Conversely, when the feedback voltage is lower than the reference voltage, the output Comp_Low signal increases.

[0015] Furthermore, when the operating mode is DCM mode, the Comp_Low signal is 1 and FB_HI is 1. When the feedback voltage drops below the reference voltage, FB_HI quickly switches to 0 through the fast comparator unit in the error amplifier. At this time, the second NAND gate outputs 1, the first flip-flop is no longer set, the first NAND gate outputs 1, and the rising edge of the output signal of the delay unit sets the QN terminal of the first flip-flop to 0. The inverter obtains the EN_PWM signal to 1. At this time, the RST_N terminal of the second flip-flop is no longer set, and the rising edge of the clock signal of the second flip-flop sets the PWM signal to 1. At this time, the Comp_Low signal is 1 and has switched to CCM mode. When the charging is sufficient, both Comp_Low and FB_HI are 1. At this time, charging stops, the CLK signal is blocked, and DCM mode is entered.

[0016] Furthermore, the fast comparator unit in the error amplifier shares an input pair of transistors with the error amplifier connected in parallel with its input terminal. The input pair of transistors includes MP4 transistors and MP5 transistors.

[0017] Furthermore, the gain expression for the fast comparator unit in the error amplifier is:

[0018] ;

[0019] in, The transconductance of the MP5 transistor is equal to ΔIdmp5 / ΔVGSmp5, where ΔIdmp5 is the small-signal value of the channel current of the MP5 transistor, and ΔVGSmp5 is the small-signal value of the voltage difference between the gate and source of the MP5 transistor. This represents a coefficient obtained by dividing the width-to-length ratio of tube MN4 by the width-to-length ratio of tube MN3. It is a constant; This represents the output impedance of the MP6 transistor. The output impedance of the MP6 transistor is equal to ΔVdsmp6 / ΔIdmp6, where ΔVdsmp6 ​​is the small-signal value of the difference between the drain voltage and the source voltage of the MP6 transistor, and ΔIdmp6 is the small-signal value of the channel current of the MP6 transistor. This represents the output impedance of transistor MN4. The output impedance of transistor MN4 is equal to ΔVdsmn4 / ΔIdmn4, where ΔVdsmn4 is the small-signal value of the difference between the drain voltage and the source voltage of transistor MN4, and ΔIdmn4 is the small-signal value of the channel current of transistor MN4.

[0020] Furthermore, the hysteresis comparator is a Schmitt trigger.

[0021] The beneficial effects of this invention are as follows:

[0022] The present invention proposes a fast switching circuit for DCM and CCM modes. By introducing a new control signal, it enables fast switching between DCM and CCM modes in a Buck converter controlled by peak current mode. This can effectively reduce the number of PWM signals in CCM mode, thereby reducing output voltage ripple. Attached Figure Description

[0023] Figure 1 It is a traditional asynchronous peak current mode controlled Buck converter;

[0024] Figure 2 This is a schematic diagram of the structure of the DCM and CCM mode fast switching circuit in the embodiments of this application;

[0025] Figure 3 This is a schematic diagram of the circuit structure of the error amplifier in an embodiment of this application;

[0026] Figure 4 This is a graph showing the relationship between the Comp_low signal, FB_HI signal, clock signal CLK, inductor current IL, feedback voltage FB, reference voltage, and time t in the embodiments of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0029] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0030] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0031] like Figure 2 As shown, this patent introduces a new signal, FB_HI, to control the switching between DCM and CCM modes. FB_HI is generated by an error amplifier EA, which outputs two signals: a COMP signal and an FB_HI signal. The COMP signal is an analog signal output after amplifying the voltage difference between the FB signal and the Vref_EA signal. The FB_HI signal is a digital signal output after the FB signal and the Vref_EA signal pass through a fast comparator unit. When the feedback voltage is greater than the reference voltage, the FB_HI signal is high, equal to the power supply voltage; when the feedback voltage is less than the reference voltage, the FB_HI signal is low, equal to 0.

[0032] This invention discloses a fast switching circuit for DCM and CCM modes, comprising an error amplifier, a fast comparator, two NAND gates (NAND1 and NAND2), a delay unit (delay), an inverter (INV1), and two flip-flops (DFF1 and DFF2), enabling fast mode switching. The positive terminal of the error amplifier is connected to the feedback voltage FB, and the negative terminal is connected to the reference voltage Vref_EA.

[0033] Error amplifier EA receives the feedback voltage FB at its negative terminal and the reference voltage Vref_EA at its positive terminal. It outputs the COMP and FB_HI signals. The COMP signal is an analog signal amplified by the error amplifier from the difference between the FB and Vref_EA signals. The FB_HI signal is a digital signal output from the fast comparator unit after the FB and Vref_EA signals pass through it. When the feedback voltage is greater than the reference voltage, the FB_HI signal is high (equal to the power supply voltage); when the feedback voltage is less than the reference voltage, the FB_HI signal is low (equal to 0). The COMP signal, the output of the error amplifier, is connected to an external compensation circuit with R1 and C1 to stabilize the BUCK controller loop.

[0034] The fast comparator's positive terminal receives a low reference voltage, vref_low. When the COMP voltage is lower than vref_low, a low-voltage clamping circuit for COMP pulls COMP up to approximately equal to (slightly lower than) the voltage vref_low. The fast comparator's negative terminal receives the COMP signal and outputs the Comp_Low signal. When the COMP signal is lower than vref_low, the Comp_Low signal is high; when the COMP signal is greater than vref_low, the Comp_Low signal is low. The NAND gate group includes a first NAND gate and a second NAND gate, which receive the Comp_Low signal and the FB_HI signal, respectively.

[0035] The delay unit's input is connected to the output of the first NAND gate.

[0036] The trigger group includes a first trigger and a second trigger. The CLK terminal of the first trigger is connected to the output terminal of the delay unit, the RST_N terminal of the first trigger is connected to the output terminal of the second NAND gate, and the QN terminal of the first trigger is connected to the RST_N terminal of the second trigger through an inverter.

[0037] In DCM mode, Comp_Low=1, FB_HI=1. When the feedback voltage FB drops below the reference voltage Vref_EA, FB_HI quickly switches to 0 due to the rapid judgment of the fast comparator unit in the error amplifier. At this time, NAND2 outputs 1, and DFF1 is no longer set. NAND1 outputs 1, and through the delay unit delay, the rising edge of the delay output signal sets the QN terminal of DFF1 to 0. The EN_PWM signal is obtained as 1 through the inverter INV1. At this time, the RST_N terminal of DFF2 is no longer set, and the rising edge of the CLK signal sets the PWM signal to 1. At this time, although the Comp_Low signal is 1, it has already switched to DCM mode. This loop exits DCM mode without waiting for the Comp_Low signal to slowly decrease. When charging is sufficient, both Comp_Low and FB_HI are 1. At this time, charging stops, the CLK signal is disabled, and DCM mode is entered again.

[0038] This invention introduces a new control signal FB_HI. When the feedback voltage FB is lower than the reference voltage Vref_EA, the fast comparator unit outputs FB_HI=0, and the loop immediately switches to CCM mode. At this time, the Comp_Low signal is still 1, but the loop has already completed the mode switch, effectively reducing the number of PWM signals during charging and thus reducing the output voltage ripple.

[0039] like Figure 4As shown, Figure 4 The diagram illustrates the Comp_low signal, FB_HI signal, clock signal CLK, inductor current IL, feedback voltage FB, input reference voltage Vref_EA of error amplifier EA, and the switching between DCM and CCM modes. Starting from the zero point on the X-axis, Comp_low and FB_HI are both high, indicating the Buck converter is operating in DCM mode. With zero inductor current and no energy supplied to the output, the Buck output voltage is gradually reduced by the output load current, and FB also decreases accordingly. When the FB voltage drops below Vref_EA, the fast comparator unit in the error amplifier rapidly changes the output FB_HI from high to low, and the Buck converter immediately switches from DCM to CCM mode. The Buck converter then charges the output through the inductor current, and the FB signal gradually increases.

[0040] When the FB signal is higher than Vref_EA, the FB_HI signal changes from low to high again. This is because the COMP node has compensation circuits R1 and C1 present (see...). Figure 3 COMP voltage changes very slowly and is less than Vref_Low (see...) Figure 2 Therefore, the Comp_Low signal has not yet turned high, and the Buck converter remains in CCM mode. As FB continues to rise, the Comp_Low signal turns high, at which point the Buck converter switches from CCM mode back to DCM mode, skipping subsequent switching cycles. The inductor current is 0, and the FB signal begins to fall again, returning to the zero point on the X-axis. This mode switching process repeats thereafter.

[0041] like Figure 3As shown, the error amplifier includes a bias current source, MP1, MP2, MP3, MP4, MP5, MP6, MP7, MN1, MN2, MN3, MN4, MN5, resistor R1, capacitor C1, and a hysteresis comparator. The bias current source is connected to the drain of MP1, and the drain and gate of MP1 are connected together. The source of MP1 is connected to the power rail VDD, the gate of MP1 is connected to the gate of MP3, and the source of MP3 is connected to the power rail VDD. VDD, the drain of MP3 is connected to the source of MP4 and the source of MP5. The source of MP2 is connected to the power rail VDD. The drain and gate of MP2 are connected together. The gate of MP2 is connected to the gate of MP6. The gate of MP2 is connected to the gate of MP7. The drain of MP2 is connected to the drain of MN1. The gate of MP4 is connected to the feedback voltage. The drain of MP4 is connected to the drain of MN2. The gate of MP5 is connected to the reference voltage. The drain of MP5 is connected to the drain of MN3. MP6... The source of transistor MP6 is connected to the power rail VDD. The drain of transistor MP6 is connected to the input of the hysteresis comparator. The drain of transistor MP6 is also connected to the drain of transistor MN4. The source of transistor MP7 is connected to the power rail VDD. The drain of transistor MP7 is connected to the output node COMP. The drain of transistor MP7 is also connected to the drain of transistor MN5. The drain of transistor MP7 is also connected to the upper end of resistor R1. The gate of transistor MN1 is connected to the gate of transistor MN2. The source of transistor MN1 is connected to GND. The gate and drain of transistor MN2 are connected together. The source of transistor MN2 is connected to GN. D. The gate and drain of transistor MN3 are connected together. The gate of transistor MN3 is connected to the gate of transistor MN4. The gate of transistor MN3 is connected to the gate of transistor MN5. The source of transistor MN3 is connected to GND. The drain of transistor MN4 is connected to the input of the hysteresis comparator. The source of transistor MN4 is connected to GND. The source of transistor MN5 is connected to GND. The upper end of resistor R1 is connected to the output node COMP. The lower end of resistor R1 is connected to the upper end of capacitor C1. The lower end of capacitor C1 is connected to GND. The output of the hysteresis comparator is the signal FB_HI. The hysteresis comparator is a Schmitt trigger (SMIT1).

[0042] Among them, MP1, MP2, MP3, MP4, MP5, MP6, and MP7 are all PMOS transistors, while MN1, MN2, MN3, MN4, and MN5 are all NMOS transistors. The transistors MP1, MP2, MP3, MP4, MP5, and MP6 are respectively... Figure 2 The MP1, MP2, MP3, MP4, MP5, MP6, and MP7 tubes, and the MN1, MN2, MN3, MN4, and MN5 tubes are respectively Figure 2 MN1, MN2, MN3, MN4, and MN5 are specified. Resistor R1 and capacitor C1 are... Figure 2 R1 and C1 in the example.

[0043] The error amplifier operates as follows: The input signals at the two ends of the error amplifier are the negative input signal feedback voltage FB and the positive input signal reference voltage Vref_EA. When the FB signal is slightly higher than the reference voltage Vref_EA, the gate potential of transistor MP4 is higher than that of transistor MP5. Since transistors MP4 and MP5 share the same branch bias current (i.e., transistor MP3 mirrors the current received by transistor MP1), the current received by transistor MP4 is less than that received by transistor MP5. The current in the branch containing transistor MP4 is mirrored back to the branch containing transistor MN1 through a current mirror composed of transistors MN2 and MN1. The current in the branch containing transistor MN1 is then mirrored back to the branch containing transistor MP6 by transistors MP2 and MP6. The current in the branch containing transistor MP5 is mirrored back to the branch containing transistor MN4 by a current mirror composed of transistors MN3 and MN4. Since MP6 and MN4 are in the same branch, when the current of MP4 is less than the current of MP5, the current of MP6 will be less than the current of MN4. At this time, the input potential of the hysteresis comparator SMIT1 will be pulled low. After passing through the hysteresis comparator SMIT1, the output signal FB_HI will be high. Conversely, when the feedback voltage FB is lower than the reference voltage Vref_EA, the output of FB_HI will be low.

[0044] Similarly, the current in the branch containing MP4 is mirrored back to the branch containing MN1 through the current mirror formed by transistors MN2 and MN1. The current in the branch containing MN1 is then mirrored back to the branch containing MP7 by transistors MP2 and MP7. The current in the branch containing MP5 is mirrored back to the branch containing MN5 by the current mirror formed by transistors MN3 and MN5. Since transistors MP7 and MN5 are in the same branch, when the current in MP4 is less than the current in MP5, the current in MP7 will be less than the current in MN5. At this time, capacitor C1 discharges, and the voltage value of COMP equals the sum of the voltage across the upper plate of capacitor C1 and the voltage drop across R1, so the voltage value of COMP decreases. Conversely, when the feedback voltage FB is lower than the reference voltage Vref_EA, the voltage value of COMP increases.

[0045] The input transistor pair of the fast comparator unit in the error amplifier, i.e., the comparator stage, is shared with the input transistor pair of the error amplifier EA, and the gain is also shared. Therefore, the fast comparator unit in the error amplifier and the error amplifier EA have the same offset.

[0046] The gain expression for the fast comparator unit in the error amplifier is: ;

[0047] in, The transconductance of the MP5 transistor is equal to ΔIdmp5 / ΔVGSmp5, where ΔIdmp5 is the small-signal value of the channel current of the MP5 transistor, and ΔVGSmp5 is the small-signal value of the voltage difference between the gate and source of the MP5 transistor. This represents a coefficient obtained by dividing the width-to-length ratio of tube MN4 by the width-to-length ratio of tube MN3. It is a constant; This represents the output impedance of the MP6 transistor. The output impedance of the MP6 transistor is equal to ΔVdsmp6 / ΔIdmp6, where ΔVdsmp6 ​​is the small-signal value of the difference between the drain voltage and the source voltage of the MP6 transistor, and ΔIdmp6 is the small-signal value of the channel current of the MP6 transistor. This represents the output impedance of transistor MN4. The output impedance of transistor MN4 is equal to ΔVdsmn4 / ΔIdmn4, where ΔVdsmn4 is the small-signal value of the difference between the drain voltage and the source voltage of transistor MN4, and ΔIdmn4 is the small-signal value of the channel current of transistor MN4.

[0048] The present invention proposes a fast switching circuit for DCM and CCM modes. By introducing a new control signal, it enables fast switching between DCM and CCM modes in a Buck converter controlled by peak current mode. This can effectively reduce the number of PWM signals in CCM mode, thereby reducing output voltage ripple.

[0049] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A circuit for fast switching between DCM and CCM modes, characterized in that, include: The error amplifier has a negative terminal for receiving the feedback voltage and a positive terminal for receiving the reference voltage. It outputs the COMP signal and the fast comparator unit in the error amplifier outputs the FB_HI signal. When the feedback voltage is greater than the reference voltage, the FB_HI signal is high; when the feedback voltage is less than the reference voltage, the FB_HI signal is low. The fast comparator has its positive terminal used to receive a low reference voltage, its negative terminal used to receive the COMP signal, and its output is the Comp_Low signal. The NAND gate group includes a first NAND gate and a second NAND gate, which are used to receive the Comp_Low signal and the FB_HI signal, respectively. The delay unit has its input connected to the output of the first NAND gate. The trigger group includes a first trigger and a second trigger. The CLK terminal of the first trigger is connected to the output terminal of the delay unit, the RST_N terminal of the first trigger is connected to the output terminal of the second NAND gate, and the QN terminal of the first trigger is connected to the RST_N terminal of the second trigger through an inverter. When the operating mode is DCM mode, the Comp_Low signal is 1 and FB_HI is 1. When the feedback voltage drops below the reference voltage, FB_HI quickly switches to 0 through the fast comparator unit in the error amplifier. At this time, the second NAND gate outputs 1, the first flip-flop is no longer set, and the first NAND gate outputs 1. The rising edge of the output signal of the delay unit sets the QN terminal of the first flip-flop to 0. The inverter obtains the EN_PWM signal as 1. At this time, the RST_N terminal of the second flip-flop is no longer set, and the rising edge of the clock signal of the second flip-flop sets the PWM signal to 1. At this time, the Comp_Low signal is 1 and has switched to CCM mode. When the charge is sufficient, both Comp_Low and FB_HI are 1. At this time, charging stops, the CLK signal is blocked, and DCM mode is entered.

2. The DCM and CCM mode fast switching circuit according to claim 1, characterized in that, The error amplifier includes a bias current source, MP1, MP2, MP3, MP4, MP5, MP6, MP7, MN1, MN2, MN3, MN4, and MN5 transistors, resistor R1, capacitor C1, and a hysteresis comparator. The bias current source is connected to the drain of MP1, and the drain and gate of MP1 are connected together. The source of MP1 is connected to the power rail VDD, the gate of MP1 is connected to the gate of MP3, and the source of MP3 is connected to the power rail VDD. The drain of MP3 is connected to the source of MP4 and the source of MP5. The source of MP2 is connected to the power rail VDD. The drain and gate of MP2 are connected together. The gate of MP2 is connected to the gate of MP6. The gate of MP2 is connected to the gate of MP7. The drain of MP2 is connected to the drain of MN1. The gate of MP4 is connected to the feedback voltage. The drain of MP4 is connected to the drain of MN2. The gate of MP5 is connected to the reference voltage. The drain of MP5 is connected to the drain of MN3. The drain of MP6... The source of transistor MP6 is connected to the power rail VDD. The drain of MP6 is connected to the input of the hysteresis comparator. The drain of MP6 is also connected to the drain of transistor MN4. The source of MP7 is connected to the power rail VDD. The drain of MP7 is connected to the output node COMP. The drain of MP7 is also connected to the drain of transistor MN5. The drain of MP7 is also connected to the upper end of resistor R1. The gate of transistor MN1 is connected to the gate of transistor MN2. The source of MN1 is connected to GND. The gate and drain of transistor MN2 are connected together. The source of MN2 is connected to GND. The gate and drain of transistor MN3 are connected together. The gate of transistor MN3 is connected to the gate of transistor MN4. The gate of transistor MN3 is connected to the gate of transistor MN5. The source of transistor MN3 is connected to GND. The drain of transistor MN4 is connected to the input of the hysteresis comparator. The source of transistor MN4 is connected to GND. The source of transistor MN5 is connected to GND. The upper end of resistor R1 is connected to the output node COMP. The lower end of resistor R1 is connected to the upper end of capacitor C1. The lower end of capacitor C1 is connected to GND. The output of the hysteresis comparator is the output signal FB_HI.

3. The DCM and CCM mode fast switching circuit according to claim 2, characterized in that, When the feedback voltage is higher than the reference voltage, the gate potential of MP4 is higher than that of MP5. MP3 mirrors the current obtained by MP1. At this time, the current obtained by MP4 is less than that obtained by MP5. The current in the branch where MP4 is located is mirrored to the branch where MN1 is located through the current mirror composed of MN2 and MN1. The current in the branch where MN1 is located is then mirrored to the branch where MP6 is located by MP2 and MP6. The current in the branch where MP5 is located is mirrored to the branch where MN4 is located by the current mirror composed of MN3 and MN4. When the current of MP4 is less than the current of MP5, the current of MP6 is less than the current of MN4. At this time, the input potential of the hysteresis comparator is pulled low. After passing through the hysteresis comparator, the output signal FB_HI is high. Conversely, when the feedback voltage is lower than the reference voltage, the output of FB_HI is low. When the feedback voltage is higher than the reference voltage, the current received by MP4 is less than that received by MP5. The current in the branch containing MP4 is mirrored to the branch containing MN1 through the current mirror formed by MN2 and MN1. The current in the branch containing MN1 is then mirrored to the branch containing MP7 by MP2 and MP7. The current in the branch containing MP5 is mirrored to the branch containing MN5 by the current mirror formed by MN3 and MN5. When the current of MP4 is less than the current of MP5, the current of MP7 is less than the current of MN5. At this time, the output Comp_Low signal decreases. Conversely, when the feedback voltage is lower than the reference voltage, the output Comp_Low signal increases.

4. The DCM and CCM mode fast switching circuit according to claim 2, characterized in that, The fast comparator unit in the error amplifier shares an input pair of transistors with the error amplifier connected in parallel with its input terminal. The input pair of transistors includes MP4 and MP5 transistors.

5. The DCM and CCM mode fast switching circuit according to claim 4, characterized in that, The gain expression for the fast comparator unit in the error amplifier is: ； in, The transconductance of the MP5 transistor is equal to ΔIdmp5 / ΔVGSmp5, where ΔIdmp5 is the small-signal value of the channel current of the MP5 transistor, and ΔVGSmp5 is the small-signal value of the voltage difference between the gate and source of the MP5 transistor. This represents a coefficient obtained by dividing the width-to-length ratio of tube MN4 by the width-to-length ratio of tube MN3. It is a constant; This represents the output impedance of the MP6 transistor. The output impedance of the MP6 transistor is equal to ΔVdsmp6 / ΔIdmp6, where ΔVdsmp6 ​​is the small-signal value of the difference between the drain voltage and the source voltage of the MP6 transistor, and ΔIdmp6 is the small-signal value of the channel current of the MP6 transistor. This represents the output impedance of transistor MN4. The output impedance of transistor MN4 is equal to ΔVdsmn4 / ΔIdmn4, where ΔVdsmn4 is the small-signal value of the difference between the drain voltage and the source voltage of transistor MN4, and ΔIdmn4 is the small-signal value of the channel current of transistor MN4.

6. The DCM and CCM mode fast switching circuit according to claim 2, characterized in that, The hysteresis comparator is a Schmitt trigger.

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