Radio frequency amplification circuit and single photon radiation detector time response test system

Abstract

The application discloses a kind of radio frequency amplification circuit and single-photon radiation detector time response test system, belong to radio frequency signal processing technical field.The radio frequency amplification circuit includes: input module;Double gate control module, including first gate control unit and second gate control unit;Amplifier and feedback module, its input end connects input module, output end connects second gate control unit, control end connects first gate control unit;Output module.First gate control unit detects input signal envelope, when exceeding preset threshold, generates gate control strobe pulse, controls amplifier and feedback module to enter working state, otherwise enter cut-off state;Second gate control unit is when amplifier and feedback module enter cut-off state, quickly discharge output end residual charge to inhibit signal tailing.The application blocks wideband noise false trigger from source by adaptive gate control mechanism, and eliminates baseline disturbance by active clamping discharge, compresses signal tailing recovery time to within 2 nanoseconds, significantly improves the measurement accuracy of single-photon detector time response parameter, and has the advantages of high gain, low noise, wide bandwidth, fast transient response.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency signal processing technology, specifically relating to a radio frequency amplifier circuit and a time response testing system for a single-photon radiation detector. Background Technology

[0002] Single-photon detection technology plays a crucial role in timing measurement in fields such as inertial confinement fusion diagnostics, free-electron laser timing measurement, high-energy-density physics experiments, ultrafast X-ray imaging, and time-of-flight mass spectrometry. These applications share the common requirement of precise time stamping of nanosecond-level pulse events, demanding that the testing system accurately extract the detector's time response parameters, including pulse rise time, transit time jitter, time resolution, and response characteristics under high count rate conditions.

[0003] Current single-photon detectors have achieved time resolutions exceeding 10 ps, ​​with superconducting nanowire single-photon detectors achieving 3 ps time jitter in specific wavelength bands. However, precise characterization of detector timing performance faces significant challenges: the detector output signal is characterized by pulse widths of 1 ns-10 ns, rise times of less than 500 ps, ​​and amplitude ranges of 1 mV-25 mV. When such weak, fast pulses are directly connected to an oscilloscope or time-to-digital converter, the signal is easily buried in measurement system noise due to its small amplitude, leading to significantly increased time measurement errors or even failure to trigger. Therefore, a front-end RF amplification circuit needs to be introduced between the detector and the time measurement device.

[0004] Existing radio frequency amplifier circuits are mainly divided into two categories: continuous operation mode and externally controlled shutdown mode.

[0005] In continuous operation mode, RF amplifier circuits amplify broadband noise during periods without a signal. When this noise amplitude exceeds the threshold of the subsequent time discrimination circuit, it triggers numerous spurious triggers, severely interfering with the timing of genuine pulses. Furthermore, the increased system-equivalent noise bandwidth due to continuous amplification further reduces the signal-to-noise ratio, making it difficult to accurately extract weak pulses.

[0006] To address the power consumption and noise issues associated with continuous amplification, some radio frequency (RF) amplifier circuits have incorporated external shutdown control functions. For example, Chinese utility model patent CN202421212222.5 (Hangzhou Youwang Electronics Co., Ltd.) discloses an RF amplifier circuit that receives external control signals (such as Vctrl from the system baseband or MCU) through a shutdown control circuit to directly control the amplifier circuit's on / off state, thereby achieving low power consumption and high isolation in TDD (Time Division Duplex) communication systems. However, this externally controlled shutdown mode has obvious limitations: First, shutdown and turn-on rely entirely on external commands and cannot autonomously identify the true arrival time of the input signal, so it cannot be used in single-photon detection scenarios where the pulse arrival time is random and unpredictable; Second, in shutdown mode, the circuit only turns off the amplifying transistor, and the residual radio frequency energy on the parasitic capacitance at the output end relies on natural discharge, resulting in a large time constant (usually tens of nanoseconds), which causes signal tailing, causes measurement baseline disturbance, and seriously affects the amplitude measurement and timing accuracy of subsequent pulses; Third, the circuit does not solve the problem of false triggering of broadband noise at the input end, and the noise amplification and transmission path still exists.

[0007] In summary, existing RF amplifier circuits have the following shortcomings in single-photon detector time response testing applications: they lack an adaptive noise suppression mechanism based on signal amplitude, cannot autonomously identify real pulses and activate the amplification channel, leading to broadband noise false triggering; after gate shutdown, residual signals at the output cause baseline disturbances, degrading the detector's linear response characteristics and time resolution under high-throughput conditions, making accurate characterization impossible. Therefore, there is an urgent need for an RF amplifier circuit that can simultaneously suppress noise false triggering and eliminate baseline disturbances to meet the requirements for high-precision measurement of single-photon detector time response parameters. Summary of the Invention

[0008] This invention aims to solve the technical problems existing in the time response testing of single-photon detectors using existing radio frequency (RF) amplifier circuits. Specifically, these problems include: existing RF amplifier circuits in continuous operation mode continuously amplify broadband noise during periods without signal, causing subsequent time discrimination circuits to be falsely triggered by noise, severely affecting the accuracy of the time marking of the real pulse; existing RF amplifier circuits in externally controlled shutdown mode cannot autonomously identify the true arrival time of the input signal, and the residual charge at the output terminal after shutdown relies on natural discharge, causing signal tailing and baseline disturbance, resulting in the degradation of the detector's linear response characteristics and time resolution under high-throughput conditions, making it impossible to accurately characterize them.

[0009] To solve the above-mentioned technical problems, the present invention provides a radio frequency amplifier circuit, comprising: The input module is used to receive input signals; A dual-gating module, connected to the output of the input module, includes a first gating unit and a second gating unit; An amplifier and feedback module, whose input terminal is connected to the input module, whose output terminal is connected to the second gating unit, and whose control terminal is connected to the first gating unit, is used to enter the working state or the cutoff state under the control of the first gating unit, and to amplify the input pulse signal; The output module is connected to the output terminal of the amplifier and the feedback module, and is used to output the amplified pulse signal to the load; The first gating unit includes an input signal detection circuit and an amplitude comparison circuit, used to detect the envelope of the input signal and compare it with a preset threshold. When the input signal exceeds the preset threshold, a gating pulse is generated to control the amplifier and feedback module to enter the working state; otherwise, it controls them to enter the cutoff state. The second gating unit includes a clamping discharge circuit. When the first gating unit controls the amplifier and feedback module to enter the cutoff state, the clamping discharge circuit quickly discharges the residual charge at the output terminal of the output module through a low-impedance path controlled by the gating pulse to suppress signal tailing.

[0010] Furthermore, the input module includes a signal source, a first input matching network, a signal branching network, and a main channel delay line. The first input matching network includes a series resistor and a first DC blocking capacitor connected in series. One end of the series resistor is electrically connected to the signal source, and the first DC blocking capacitor is electrically connected to the signal branching network. The signal branching network includes a first series resistor, a second series resistor, a first parallel resistor, and a second parallel resistor. The first DC blocking capacitor is electrically connected to the first end of the first series resistor and the first end of the first parallel resistor, respectively. The second end of the first series resistor is electrically connected to the first end of the second series resistor and the first end of the second parallel resistor, respectively. The second end of the first parallel resistor and the second end of the second parallel resistor are electrically connected and branch off into a detection branch, which is then connected to the end of the matching resistor. The second end of the second series resistor is electrically connected to the input end of the main channel delay line.

[0011] Furthermore, the main channel delay line is one of a coaxial line, microstrip line, stripline, or RC delay network.

[0012] Furthermore, the first gating unit includes: The input signal detection circuit includes an envelope detector and an RC integrator circuit. The envelope detector is constructed using a Schottky barrier diode and is used to extract the pulse envelope from the radio frequency signal of the detection branch and convert it into a DC detection voltage. An amplitude comparison circuit includes a differential pair comparator composed of two NPN transistors. Its first input module is connected to the DC detection voltage, and its second input module is connected to a reference voltage. The circuit is used to compare the DC detection voltage with the reference voltage and output a comparison result signal. The gate voltage generation circuit includes a differential shaping network and a level conversion circuit, used to shape and generate a narrow pulse based on the transition edge of the comparison result signal, and convert the narrow pulse into a level value as the gate voltage of the first gate unit and the second gate unit respectively.

[0013] Furthermore, the second gating unit includes: An inverting drive circuit receives the gate voltage at its input terminal and outputs an inverted signal of the gate voltage. A current source drive circuit, connected to the output of the inverting drive circuit, is used to establish a stable positive current during the amplifier turn-off period according to the state of the inverting signal. The clamping discharge circuit is connected to the output terminal of the current source drive circuit and is used to provide a discharge path for the amplifier output node.

[0014] Furthermore, the amplifier and feedback module include: The amplification unit adopts a single-stage common-emitter or common-source amplification structure, including at least one amplification transistor. The control terminal of the amplification transistor is connected to the output terminal of the first gate unit through a base resistor to receive the gate voltage. The feedback unit, including a feedback resistor and a feedback capacitor connected in parallel, is connected between the input module and the output terminal of the amplification unit to expand the circuit bandwidth and stabilize the gain.

[0015] Furthermore, the amplification unit includes a second input matching network, a transistor biasing and amplification circuit, and an output matching network. The second input matching network includes a first parallel inductor and a second series capacitor, with the first end of the first parallel inductor and the first end of the second series capacitor electrically connected to the output of the main channel delay line, respectively. The transistor biasing and amplification circuit includes a base series resistor, an amplifying transistor, a first parallel capacitor, a second parallel capacitor, an RF choke, a third parallel capacitor, and a fourth parallel capacitor. The first end of the base series resistor, the first end of the first parallel capacitor, the first end of the second parallel capacitor, and the base of the amplifying transistor are all electrically connected to the second series capacitor. The second end of the base series resistor is electrically connected to the output of the gate voltage generation circuit. The second terminals of the first and second parallel capacitors are both grounded. The collector of the amplifying transistor is electrically connected to the first terminal of the RF choke. The second terminal of the RF choke, the first terminal of the third parallel capacitor, and the first terminal of the fourth parallel capacitor are electrically connected to the positive power supply. The second terminals of the third and fourth parallel capacitors are both grounded. The emitter of the amplifying transistor is electrically connected to the feedback unit. The collector of the amplifying transistor is electrically connected to the output matching network. The output matching network includes a third series capacitor, a second parallel inductor, and a fourth series capacitor. The third series capacitor and the fourth series capacitor are connected in series. The third series capacitor is electrically connected to the collector of the amplifying transistor. The fourth series capacitor is electrically connected to the second DC blocking capacitor and the amplifier output, respectively.

[0016] Furthermore, the amplifying transistor is a SiGe heterojunction bipolar transistor (HBT) or a GaAs metal-semiconductor field-effect transistor (MESFET); the amplification unit is powered by a dual power supply, providing a forward bias voltage and a reverse bias cutoff voltage to the amplifying transistor.

[0017] The present invention also provides a time response testing system for a single-photon radiation detector, including the above-mentioned radio frequency amplification circuit, and a load line or time-correlated single-photon counting module connected to the output module of the radio frequency amplification circuit, for high-precision time calibration and amplitude measurement of the output pulse of the single-photon radiation detector.

[0018] Compared with the prior art, the radio frequency amplification circuit and single-photon radiation detector time response testing system provided by the present invention have the following advantages: (1) This invention innovatively proposes a noise suppression mechanism based on adaptive signal amplitude discrimination. The first gating unit detects the amplitude of the input signal in real time and compares it with a preset threshold. It turns on the amplifier only when the real pulse signal arrives and keeps it off during periods of no signal or low amplitude noise. This fundamentally blocks the amplification and transmission path of broadband noise, significantly reduces the false trigger rate of noise, and improves the signal-to-noise ratio and accuracy of the detector time response parameter measurement.

[0019] (2) This invention introduces active clamping discharge technology. After the amplifier is turned off, the second gate unit quickly conducts the discharge path, and forms a low impedance path with the PIN diode and the discharge resistor to release the residual RF energy at the output end to ground within a nanosecond time constant. It also implements low voltage clamping on the output node to ensure that the measurement baseline recovers to within ±5% of the initial state within 2 ns. This effectively solves the measurement error problem caused by baseline disturbance and enables the detector to maintain linear response characteristics under high throughput conditions.

[0020] (3) The dual-gated collaborative control mechanism of this invention achieves dual protection of noise suppression and baseline stability. The first gating unit blocks noise transmission at the source, and the second gating unit quickly clears the residual stable baseline. The two work together to enable the test system to simultaneously possess the measurement capabilities of high signal-to-noise ratio and high count rate. Experimental results show that the RF amplifier circuit of this invention can compress the tailing time to within 2 ns, and the maximum working count rate is more than 10 times higher than that of the traditional scheme, providing key technical support for the precise characterization of the time response performance of single-photon detectors.

[0021] (4) This invention employs a single-stage amplification structure with an optimized feedback network. While maintaining a gain of 10 dB-20 dB, the noise figure is no greater than 3 dB, the rise time degradation is less than 500 ps, ​​and the reflection coefficients S11 and S22 are both less than -10 dB, meeting the comprehensive requirements of time measurement systems for high gain, low noise, wide bandwidth, and fast transient response. The entire circuit can be implemented using discrete components or integrated chips, resulting in low cost and good engineering practicality. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of the dual-gated radio frequency amplifier circuit of the present invention.

[0023] Figure 2 This is a system block diagram of the dual-gated radio frequency amplifier circuit of the present invention.

[0024] Figure 3 This is a block diagram of the internal structure of the first gating unit (input adaptive gating) of the present invention.

[0025] Figure 4 This is a schematic diagram of the circuit structure of the second gate control unit (clamping discharge switch) of the present invention.

[0026] Figure 5 This is a schematic diagram of the circuit structure of the first gate control unit of the present invention.

[0027] Figure 6 This is a schematic diagram of the circuit structure of the input module of the present invention.

[0028] Figure 7This is a schematic diagram of the circuit structure of the amplifier and feedback module of the present invention.

[0029] Figure 8 This is the reflection coefficient curve of the dual-gated RF amplifier circuit of the present invention.

[0030] Figure 9 This is the gain curve of the dual-gated RF amplifier circuit of the present invention.

[0031] Figure 10 This is the noise figure curve of the dual-gated RF amplifier circuit of the present invention.

[0032] Figure 11 This is a circuit diagram of the amplitude comparison circuit of the present invention.

[0033] Figure 12 This is a circuit diagram of the input signal detection circuit of the present invention.

[0034] Figure 13 This is a circuit diagram of the gated voltage generation circuit of the present invention.

[0035] Figure 14 This is a circuit diagram of the clamping discharge circuit of the present invention.

[0036] Figure 15 This is a schematic diagram of the circuit structure of the current source drive circuit of the present invention.

[0037] Figure 16 This is a schematic diagram of the circuit structure of the inverting drive circuit of the present invention.

[0038] Figure 17 This is a schematic diagram of the circuit structure of the output matching network of the present invention.

[0039] Figure 18 This is a schematic diagram of the circuit structure of the feedback unit of the present invention.

[0040] Figure 19 This is the time response curve of the single-photon radiation detector of the present invention.

[0041] In the attached diagram: 100, RF amplifier circuit; 200, dual-gating module; 210, first gating unit; 220, second gating unit; 211, input signal detection circuit; 212, amplitude comparison circuit; 213, gating voltage generation circuit; 300, amplifier and feedback module; 310, amplification unit; 320, feedback unit. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0043] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0044] Unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0045] Example 1 This embodiment is a front-end amplification circuit for a single-photon radiation detector based on SiGe HBT, such as... Figure 1 and Figure 2 As shown, this embodiment provides an RF amplifier circuit with an operating frequency covering 0.2 GHz-1.2 GHz, specifically designed for a single-photon radiation detector time response test system.

[0046] like Figure 2 As shown, the structure of the RF amplifier circuit 100 includes an input module, a dual-gated module 200, an amplifier and feedback module 300, and an output module.

[0047] Specifically, the input module receives the output pulse signal from the single-photon radiation detector, which is a nanosecond-wide pulse. The output of the input module is connected to a dual-gating module, which includes a first gating unit 210 and a second gating unit 220. The input of the amplifier and feedback module is connected to the input module, its output is connected to the second gating unit 220, and its control is connected to the first gating unit 210. This allows the amplifier to enter either an active or off-state under the control of the first gating unit 210, and to amplify the input pulse signal. The output module is connected to the output of the amplifier and feedback module and outputs the amplified pulse signal to the load. The first gating unit 210 detects the envelope of the input signal. When the input signal exceeds a preset threshold, it generates a gating pulse to control the amplifier and feedback module to enter an active state; otherwise, it controls the amplifier and feedback module to enter an off-state. The second gating unit 220, under the control of the first gating unit 210, rapidly discharges residual charge at the output when the amplifier and feedback module enters the off-state to suppress signal tailing.

[0048] I. Input Module As a further explanation of the above embodiments, the input module, such as Figure 6 As shown, it includes a signal source, a first input matching network, a signal splitting network, and a main channel delay line connected in series.

[0049] As a further illustration of the above embodiments, specifically, as shown in... Figure 1 and Figure 6 As shown, the signal source simulates the output signal of a single-photon detector. The signal characteristics are a pulse signal with a nanosecond pulse width, a rise time of less than 500 ps, ​​and an input signal peak-to-peak value Vpp of 1mVpp-25 mVpp. One end of the signal source is grounded, and the other end is electrically connected to the first input matching network.

[0050] Specifically, such as Figure 6 As shown, the first input matching network includes a series resistor Rs and a first DC blocking capacitor C1 connected in series. One end of the series resistor Rs is electrically connected to the signal source. The series resistor Rs = 50 Ω. The first DC blocking capacitor C1 = 100 nF. The capacitive reactance of the first DC blocking capacitor C1 in the operating frequency band is negligible compared to the series resistor Rs at the input end and can block DC components. The first DC blocking capacitor C1 is electrically connected to the signal splitting network.

[0051] Specifically, such as Figure 6As shown, the signal splitter network uses a T-type resistor network to achieve -10 dB power coupling while maintaining 50 Ω impedance matching. The T-type resistor network includes a first series resistor R_T1, a second series resistor R_T2, a first parallel resistor R_shunt1, and a second parallel resistor R_shunt2, wherein the first series resistor R_T1 = 43 Ω, the second series resistor R_T2 = 43 Ω, and the first parallel resistor R_shunt1 and the second parallel resistor R_shunt2 are both 48 Ω. The first series resistor R_T1 connects the input signal to the intermediate node, and the second series resistor R_T2 connects the intermediate node to the main path. The first end of the first series resistor R_T1 is electrically connected to the end of the first DC blocking capacitor C1 furthest from the series resistor Rs. The second end is electrically connected to the first ends of both the second parallel resistor R_shunt2 and the second series resistor R_T2. The first end of the first parallel resistor R_shunt1 is electrically connected to the end of the first DC blocking capacitor C1 furthest from the series resistor Rs. The second ends of the first parallel resistor R_shunt1 and the second ends of the second parallel resistor R_shunt2 are electrically connected, branching off into a detection branch, which is terminated by a 50 Ω matching resistor R_term_detect. The second series resistor R_T2 is electrically connected to the input of the main channel delay line. This T-type resistor network couples approximately 10% of the RF power to the detection branch for gating decisions. The main path insertion loss is simulated to be approximately 0.5 dB.

[0052] Specifically, such as Figure 6 As shown, the main channel delay line is preferably implemented using a 50 Ω coaxial line, microstrip line, or stripline. The RC network is only used as a low-cost alternative and allows for some rise-edge degradation. In this example, the main channel delay line is connected to a T-type resistor network, using a three-stage RC delay network to delay the arrival of the main signal relative to the detection branch, ensuring that the gate bias is established before the pulse arrives. Figure 6 As shown, the three-stage RC delay network includes a first-stage resistor R_d1, a first-stage capacitor C_d1, a second-stage resistor R_d2, a second-stage capacitor C_d2, a third-stage resistor R_d3, and a third-stage capacitor C_d3. The first-stage resistors R_d1, R_d2, and R_d3 are connected in series. The first-stage resistor R_d1 is electrically connected to one end of the second series resistor R_T2 and one end of the first-stage capacitor C_d1, while the other end of the first-stage capacitor C_d1 is grounded. One end of the second-stage capacitor C_d2 is electrically connected to the end of the first-stage resistor R_d1 closest to the second-stage resistor R_d2, while the other end is grounded. One end of the third-stage capacitor C_d3 is electrically connected to the end of the second-stage resistor R_d2 closest to the third-stage resistor R_d3, while the other end is grounded. The other end of the third-stage resistor R_d3 is electrically connected to the input terminal of the amplifier and the feedback module 300.

[0053] In the three-stage RC delay network, the first stage has a resistor R_d1 = 100 Ω and a capacitor C_d1 = 2 pF; the second stage has a resistor R_d2 = 100 Ω and a capacitor C_d2 = 2 pF; and the third stage has a resistor R_d3 = 100 Ω and a capacitor C_d3 = 2 pF. Each stage has a time constant τ = RC = 200 ps, ​​and the total delay is approximately 600 ps. During actual debugging, the capacitor value was fine-tuned based on the response time of the first gating unit 210 to ensure sufficient margin for delay, ultimately setting a delay of approximately 2 ns.

[0054] II. Dual-gate module The dual-gating module 200 includes a first gating unit 210 and a second gating unit 220. For example... Figure 3 As shown, the first gate control unit 210 is implemented using discrete components, including an input signal detection circuit 211, an amplitude comparison circuit 212, and a gate voltage generation circuit 213 connected in series.

[0055] 1. First Gating Unit (1) Input signal detection circuit like Figure 5 and Figure 12 As shown, the input signal detection circuit 211 includes an envelope detector and an RC integrator circuit. The envelope detector is constructed using a Schottky barrier diode and is used to extract the pulse envelope from the RF signal of the detection branch and convert it into a DC detection voltage. Specifically, the input signal detection circuit 211 includes a first diode D1 and an RC integrator circuit. The first diode D1 is a Schottky barrier diode 1N5711 used to construct the envelope detector. The Schottky barrier diode 1N5711 has a forward voltage drop of approximately 0.3 V, a junction capacitance of less than 1 pF, and a cutoff frequency exceeding 10 GHz, making it suitable for detecting nanosecond-level pulse envelopes. The signal from the input signal detection circuit 211 is coupled into the envelope detector through a T-type resistor network, and the output is connected to the RC integrator circuit.

[0056] In this embodiment, as Figure 5 As shown, the RC integrator circuit includes a resistor R1 and a capacitor C2. The anode of the first diode D1 is electrically connected to the second terminal of either the first parallel resistor R_shunt1 or the second parallel resistor R_shunt2. The cathode of the first diode D1 is electrically connected to one end of the resistor R1 and one end of the capacitor C2, respectively. The other ends of the resistor R1 and the other ends of the capacitor C2 are grounded. The resistor R1 = 1 kΩ, the capacitor C2 = 0.5 pF, and the time constant is 0.5 ns. The RC integrator circuit is used to convert the radio frequency envelope into a DC detection voltage VDET.

[0057] (2) Amplitude Comparison Circuit like Figure 11As shown, the amplitude comparison circuit 212 uses discrete NPN transistors to construct a differential pair comparator, including a differential pair comparator composed of two NPN transistors. Its first input terminal is connected to the DC detection voltage, and its second input terminal is connected to a reference voltage. It is used to compare the DC detection voltage with the reference voltage and output a comparison result signal. Specifically, the amplitude comparison circuit 212 includes a first voltage divider resistor R_ref1, a second voltage divider resistor R_ref2, a first collector load resistor R_C1, a first transistor Q1, a second transistor Q2, a bypass capacitor C_ref1, and a second collector load resistor R_C2. One end of the first voltage divider resistor R_ref1 and one end of the second voltage divider resistor R_ref2 are electrically connected to the negative terminal of the first diode D1, and the other end of the second voltage divider resistor R_ref2 is grounded. The other end of the first voltage divider resistor R_ref1, one end of the first collector load resistor R_C1, and one end of the second collector load resistor R_C2 are all connected to +5V. The power supply VCC is electrically connected. The other end of the first collector load resistor R_C1 is electrically connected to the collector of the first transistor Q1. The base of the first transistor Q1 is electrically connected to the negative terminal of the first diode D1. The emitter of the first transistor Q1 is electrically connected to one end of the common-emitter resistor R_EE. The other end of the common-emitter resistor R_EE is grounded. One end of the bypass capacitor C_ref1 is electrically connected to the negative terminal of the first diode D1, and the other end is grounded. The other end of the second collector load resistor R_C2 is electrically connected to the collector of the second transistor Q2. The base of the second transistor Q2 is electrically connected to the gate voltage generation circuit 213. The emitter of the second transistor Q2 is electrically connected to the emitter of the first transistor Q1.

[0058] The reference voltage VREF is generated by a voltage divider resistor R_ref1 and a voltage divider resistor R_ref2: the first voltage divider resistor R_ref1 = 4.7 kΩ, connected to the +5 V power supply VCC to the VREF node; the second voltage divider resistor R_ref2 = 1 kΩ, connected to the VREF node to ground. The voltage division ratio is approximately 0.175, resulting in VREF of approximately 0.88 V. A 10 μF bypass capacitor C_ref is connected to the VREF node to filter out power supply noise. If an adjustable threshold is required, a 10 kΩ potentiometer can be connected in series at the first voltage divider resistor R_ref1. The differential pair consists of two 2N3904 NPN transistors, Q1 and Q2. The emitters of both transistors Q1 and Q2 are connected to ground via a common-emitter resistor R_EE = 2.2 kΩ. The first collector load resistor R_C1 = 1 kΩ and the second collector load resistor R_C2 = 1 kΩ are both connected to the +5 V power supply VCC. The comparator output is taken from the collector of the first transistor Q1, and the node is labeled N_comp_out. When VDET is greater than VREF, the conduction of the first transistor Q1 increases, and the N_comp_out potential decreases; conversely, it increases. The propagation delay of this differential pair comparator is measured to be approximately 1.5 ns. A calibration mapping relationship is established between VREF and the input peak-to-peak threshold Vth,pp through the coupling coefficient of the detection branch, the detection efficiency, and the gain of the subsequent stage. The threshold can be expressed as VDET at the detection end or converted to Vpp (50 Ω reference) at the input end.

[0059] (3) Gate voltage generation circuit like Figure 5 and Figure 13As shown, the gate voltage generation circuit 213 includes an RC pulse shaping circuit and a PNP transistor level conversion circuit. It is used to shape a narrow pulse based on the transition edge of the comparison result signal and convert the narrow pulse into a gate voltage with levels of a first level and a second level, respectively. The RC pulse shaping circuit includes a first series capacitor C_pulse and a pull-down resistor R_pulse. The first series capacitor C_pulse and the pull-down resistor R_pulse form a high-pass filter, which differentiates and shapes the transition edge of the comparator output to generate a narrow pulse. The pulse width is determined by the RC time constant and is adjustable from 2 ns to 10 ns. The base voltage of the second transistor Q2 is coupled to node N_pulse via the first series capacitor C_pulse = 0.5 pF. One end of the first series capacitor C_pulse and one end of the pull-down resistor R_pulse are electrically connected to the base of the second transistor Q2, respectively. The pull-down resistor R_pulse = 10 kΩ, and the other end of the pull-down resistor R_pulse is grounded. The other end of the first series capacitor C_pulse is connected to the PNP transistor level conversion circuit. The narrow pulse output by the RC pulse shaping circuit serves as the input to the PNP transistor level conversion circuit.

[0060] like Figure 13 As shown, the PNP transistor level conversion circuit includes a base resistor R_base, a third transistor Q5, an emitter resistor R_E_Q5, and a collector resistor R_C_Q5. One end of the base resistor R_base is electrically connected to the first series capacitor C_pulse, and the other end is electrically connected to the base of the third transistor Q5. One end of the emitter resistor R_E_Q5 is electrically connected to the +5V power supply VCC, and the other end is electrically connected to the emitter of the third transistor Q5. One end of the collector resistor R_C_Q5 is electrically connected to the power supply VEE, and the other end is electrically connected to the collector of the third transistor Q5.

[0061] A PNP-type third transistor Q5 (model 2N3906) is driven by a base resistor R_base (R_base = 10 kΩ). The emitter of transistor Q5 is connected to the +5 V power supply VCC via an emitter resistor R_E_Q5 = 2.2 kΩ, and the collector is connected to the -5 V power supply VEE via a collector resistor R_C_Q5 = 4.7 kΩ. The emitter output of transistor Q5 is the gate voltage VG. When N_pulse is low, transistor Q5 is turned on, and VG is approximately +0.7 V, putting the amplifier in the on state. When N_pulse is high, transistor Q5 is turned off, and VG is pulled down to approximately -2 V by the collector resistor R_C_Q5, causing the amplifier to be deeply cut off. The output impedance of the level conversion circuit is approximately 50 Ω (determined by the parallel connection of the collector resistor R_C_Q5 and the internal resistance of the third transistor Q5), which can provide a peak current of approximately 20 mA and can quickly charge and discharge the base junction capacitance of the main amplification transistor (approximately 3 pF). The total response time of the first gate unit 210 from detecting that the input signal exceeds the threshold to outputting a stable gate voltage is measured to be 1.8 ns, which meets the requirement of not exceeding 2 ns.

[0062] 2. Second gating unit like Figure 4 As shown, the second gating unit 220 includes three parts: an inverting drive circuit, a current source drive circuit, and a clamping discharge circuit, which enables rapid clearing of residual signals at the amplifier output.

[0063] (1) Inverting drive circuit like Figure 16 As shown, the input of the inverting drive circuit receives the gate voltage and outputs an inverted signal of the gate voltage. It is a common-emitter inverter composed of an NPN-type fourth transistor Q6, model 2N3904. The inverting drive circuit includes a first resistor R_inv, a second resistor R_C_inv, and a fourth transistor Q6. One end of the first resistor R_inv is electrically connected to the emitter of the third transistor Q5, and the other end is electrically connected to the base of the fourth transistor Q6. The collector of the fourth transistor Q6 is electrically connected to one end of the second resistor R_C_inv, and the other end of the second resistor R_C_inv is electrically connected to the +5V power supply VCC. The emitter of the fourth transistor Q6 is grounded.

[0064] The gate voltage VG is connected to the base of the fourth transistor Q6 via a first resistor R_inv (10 kΩ), which acts as the base resistor. R_inv limits the current and provides some input impedance. The emitter of the fourth transistor Q6 is directly grounded, and its collector is connected to the +5 V power supply via a second resistor R_C_inv (2.2 kΩ), which acts as the load resistor. The collector output node N_inv_out of the fourth transistor Q6 is the inverted signal of VG. When the amplifier is operating (VG = +0.7 V), the positive voltage through R_inv causes a base current of approximately 10 μA in the fourth transistor Q6, bringing it into saturation. N_inv_out is pulled close to ground, approximately 0.2 V. When the amplifier is off (VG = -2 V), the negative voltage reverse-biases the base-emitter junction of the fourth transistor Q6, completely cutting it off. N_inv_out is pulled up to the +5 V supply voltage by the second resistor R_C_inv. The switching speed of this inverter is mainly affected by the Miller capacitance of the base-collector junction of the fourth transistor Q6, with a measured delay of approximately 0.3 ns, much faster than the typical delay of logic gate chips.

[0065] (2) Current source drive circuit like Figure 15 As shown, the current source drive circuit is connected to the output of the inverting drive circuit to establish a stable forward current during the amplifier turn-off period according to the state of the inverting signal. Its specific structure includes a fifth transistor Q7, a third resistor R_drive, a fourth resistor R_emit_Q7, and a dual power supply circuit. The dual power supply circuit includes a +5V power supply VCC, a -5V power supply VEE, and a filter capacitor C_bulk_neg. One end of the filter capacitor C_bulk_neg is grounded, and the other end is electrically connected to the power supply VEE. One end of the third resistor R_drive is electrically connected to the collector of the fourth transistor Q6, and the other end is electrically connected to the base of the fifth transistor Q7. The emitter of the fifth transistor Q7 is electrically connected to one end of the fourth resistor R_emit_Q7, and the other end of the fourth resistor R_emit_Q7 is electrically connected to the power supply VCC.

[0066] Specifically, in this embodiment, the fifth transistor Q7 is a PNP type, model 2N3906, with a third resistor R_drive = 4.7 kΩ and a fourth resistor R_emit_Q7 = 220 Ω. The inverter output N_inv_out is connected to the base of the fifth transistor Q7 via the third resistor R_drive, which acts as the base resistor. The function of the third resistor R_drive is to convert the voltage signal of N_inv_out into a suitable base current for the fifth transistor Q7. The emitter of the fifth transistor Q7 is connected to the +5 V power supply VCC via the fourth resistor R_emit_Q7. The fourth resistor R_emit_Q7 and the fifth transistor Q7 form a typical emitter degradation current source structure. When N_inv_out is low (approximately 0.2 V), the base voltage of the fifth transistor Q7 is approximately 0.2 V, the emitter voltage is approximately 0.9 V, the emitter current IE is approximately 18.6 mA, and the collector current IC after shunt at the base is approximately 18 mA. When N_inv_out is high (+5 V), the base-emitter voltage VBE of the fifth transistor Q7 is approximately 0 V, the fifth transistor Q7 is off, and the collector current IC is approximately 0. The advantages of this current source are that the output current is less affected by power supply voltage fluctuations, has good temperature stability, and a fast response speed. The measured time for the fifth transistor Q7 to go from off to on and establish a stable current is approximately 0.6 ns.

[0067] (3) Clamping discharge circuit like Figure 14 As shown, the clamping discharge circuit is connected to the output terminal of the current source drive circuit to provide a discharge path for the amplifier output node. Its structure includes a second diode D2, a fifth resistor Rdump, and a second DC blocking capacitor C_dc. The second diode D2 acts as a clamping switch; its anode is electrically connected to the emitter of the fifth transistor Q7, and its cathode is electrically connected to the power supply VEE and one end of the second DC blocking capacitor C_dc. The other end of the second DC blocking capacitor C_dc is connected to the amplifier output VOUT. One end of the fifth resistor Rdump is electrically connected to the collector of the fifth transistor Q7, and the other end is grounded. The function of the fifth resistor Rdump is to provide a low-impedance discharge path for residual RF energy at the output terminal when the second diode D2 is conducting, while limiting the discharge current to prevent overcurrent damage.

[0068] The second diode D2 and the fifth resistor Rdump, used as a bleed resistor, form the core bleed path. The fifth resistor Rdump = 50 Ω, rated power 2 W, and the second DC blocking capacitor C_dc = 1 pF. A constant current source is constructed using the fifth transistor Q7, and the second diode D2 provides a stable forward bias current. The second diode D2 is a clamping switch, selected as a Skyworks SMP1345-040LF PIN diode. The forward on-resistance of the second diode D2 is less than 2 Ω, the reverse isolation is greater than 30 dB (1 GHz), and the switching time is less than 3 ns. The cathode of the second diode D2 is connected to the amplifier output VOUT through the second DC blocking capacitor C_dc. The function of the second DC blocking capacitor C_dc is to block the DC bias, transmitting only the RF signal, and preventing the DC operating point of the second diode D2 from affecting the amplifier output stage.

[0069] When the amplifier is in operation (VG is on), the second gating unit 220 remains off: the fifth transistor Q7 is off or provides only a very small bias current, keeping the second diode D2 in a high-impedance state (reverse biased or approximately non-conducting), avoiding additional load on the output. When the amplifier enters the off state (VG is off), the second gating unit 220 quickly turns on, and the fifth transistor Q7 establishes a predetermined forward current to drive the second diode D2 into a low-impedance state, forming a controlled clamping discharge path with the fifth resistor Rdump, thereby clearing residual energy at the output and accelerating the return to zero. The total output node capacitance Cout includes the output matching network capacitance, the junction capacitance of the second diode D2, and trace capacitance, and is measured to be approximately 20 pF. The discharge time constant τ = fifth resistor Rdump × total output node capacitance Cout ≈ 50 Ω × 20 pF = 1 ns. Simulation results show that the time from receiving the turn-off command to the output voltage dropping to within 5% of the initial value is 1.8 ns, which meets the requirement of not exceeding 2 ns.

[0070] Furthermore, such as Figure 4 As shown, the second gating unit 220 also acts as a clamp during amplifier turn-off. When the second diode D2 enters a high-impedance state, if a voltage disturbance occurs at the output due to some interference (such as power supply noise, crosstalk, etc.), the disturbance will be applied to the cathode of the second diode D2 through the second DC blocking capacitor C_dc. If the disturbance amplitude is small (less than about 0.5V), the second diode D2 remains cut off, and the disturbance is isolated by the second DC blocking capacitor C_dc, having little impact on the main circuit. If the disturbance amplitude is large (e.g., exceeding 1V), the second diode D2 may be momentarily turned on, discharging the disturbance energy to ground through the fifth resistor Rdump, thus providing clamping protection and preventing excessive disturbances from damaging subsequent circuits or introducing false triggers. This adaptive clamping characteristic is an additional advantage of the second gating unit 220.

[0071] III. Amplifier and Feedback Module like Figure 7 As shown, the amplifier and feedback module 300 includes an amplification unit 310 and a feedback unit 320. The amplification unit 310 includes a second input matching network, a transistor biasing and amplification circuit, and an output matching network.

[0072] like Figure 7 As shown, the second input matching network adopts an L-shaped lumped parameter structure, including a first parallel inductor Lp and a second series capacitor Cs. The first terminal of the first parallel inductor Lp and the first terminal of the second series capacitor Cs are electrically connected to the output of the main channel delay line, respectively. Specifically, in this embodiment, the first terminal of the first parallel inductor Lp and the first terminal of the second series capacitor Cs are electrically connected to the third stage resistor R_d3 of the three-stage RC delay network, respectively. The second terminal of the first parallel inductor Lp is grounded, and the second terminal of the second series capacitor Cs is electrically connected to the transistor bias and amplification circuit. Specifically, here the first parallel inductor Lp = 15nH and the second series capacitor Cs = 3.3 pF.

[0073] like Figure 7 As shown, the transistor biasing and amplification circuit includes a base series resistor RB, an amplifying transistor Qmain, a first parallel capacitor CB1, a second parallel capacitor CB2, an RF choke RFC, a third parallel capacitor C_bulk_pos, and a fourth parallel capacitor C_VCC. Specifically, the first terminal of the base series resistor RB, the first terminal of the first parallel capacitor CB1, the first terminal of the second parallel capacitor CB2, and the base of the amplifying transistor Qmain are all electrically connected to the output terminal of the second input matching network, specifically to the second series capacitor Cs. The second terminal of the base series resistor RB is electrically connected to the emitter output terminal of the third transistor Q5. The second terminals of the first parallel capacitor CB1 and the second terminals of the second parallel capacitor CB2 are both grounded. The collector of the amplifying transistor Qmain is electrically connected to the first terminal of the RF choke RFC. The second terminal of the RF choke RFC, the first terminal of the third parallel capacitor C_bulk_pos, and the first terminal of the fourth parallel capacitor C_VCC are electrically connected to the +5 V power supply VCC. The second terminals of the third parallel capacitor C_bulk_pos and the fourth parallel capacitor C_VCC are both grounded. The emitter of the amplifying transistor Qmain is electrically connected to the feedback unit 320. The collector of the amplifying transistor Qmain is electrically connected to the output matching network. The output terminal of the output matching network is connected to the amplifier output VOUT.

[0074] like Figure 17As shown, the output matching network adopts a π-type lumped parameter structure, including a third series capacitor Cpi1, a second parallel inductor Lpi, and a fourth series capacitor Cpi2. The third series capacitor Cpi1 and the fourth series capacitor Cpi2 are connected in series. The third series capacitor Cpi1 is electrically connected to the collector of the amplifier transistor Qmain. The fourth series capacitor Cpi2 serves as the output terminal of the output matching network and is electrically connected to the second DC blocking capacitor C_dc of the clamping discharge circuit and the amplifier output VOUT. A load line is connected to the amplifier output VOUT.

[0075] Specifically, the load line includes load R10, one end of which is connected to the fourth series capacitor Cpi2, and the other end of load R10 is grounded. The first end of the second parallel inductor Lpi is electrically connected to the end of the third series capacitor Cpi1 away from the collector of the amplifying transistor Qmain, and the second end of the second parallel inductor Lpi is grounded.

[0076] Specifically, the third series capacitor Cpi1 = 2.2 pF, the second parallel inductor Lpi = 12 nH, and the fourth series capacitor Cpi2 = 3.3 pF in the output matching network can transform the output impedance of the amplifying transistor Qmain (approximately 40 + j80 Ω) to a 50 Ω load. Simulation results show that... Figure 8 As shown, the reflection coefficient is less than -10 dB and the standing wave ratio (VSWR) is less than 1.5 in the 0.2 GHz-1.2 GHz frequency band.

[0077] like Figure 18 As shown, the feedback unit 320 includes a feedback resistor Rf and a feedback capacitor Cf. The first terminals of the feedback resistor Rf and the feedback capacitor Cf are electrically connected to the emitter of the amplifying transistor Qmain, respectively. The second terminals of the feedback resistor Rf and the feedback capacitor Cf are electrically connected to the end of the fourth series capacitor Cpi2 furthest from the collector of the amplifying transistor Qmain, respectively. Specifically, the feedback resistor Rf = 470 Ω, and the feedback capacitor Cf = 1.0 pF.

[0078] In the mid-frequency range of 200 MHz-500 MHz, the capacitive reactance of the feedback capacitor Cf is relatively large (approximately 530 Ω at 300 MHz), and the feedback impedance is mainly determined by the feedback resistor Rf. According to negative feedback theory, the closed-loop gain is approximately Rf / Rs = 470 / 50 ≈ 9.4 (19.5 dB). Simulation results show a gain of 19 dB, consistent with the theoretical prediction. Feedback reduces the input and output impedance, decreases the time constant formed by parasitic capacitance, and extends the -3 dB bandwidth. Without feedback, the transistor bandwidth is approximately 600 MHz; with feedback, the bandwidth expands, but the gain-bandwidth product remains constant. In the high-frequency range (greater than 500 MHz), the capacitive reactance of the feedback capacitor Cf decreases (approximately 160 Ω at 1 GHz), and the equivalent impedance decreases after being connected in parallel with the feedback resistor Rf, introducing additional phase lead. Feedback increases the noise figure, approximately increasing by 1 + Acl / Aol according to feedback noise theory, but gating technology has significantly reduced the equivalent noise bandwidth, so the noise degradation caused by feedback is acceptable. Simulation results show that... Figure 10 As shown, the measured noise figure of the system meets the requirement of not exceeding 3 dB in the operating frequency band, and the gain is greater than 10 dB in the operating frequency band.

[0079] It should be noted that the aforementioned amplification unit 310 adopts a single-stage common-emitter amplification structure. The main structure of the single-stage common-emitter amplification structure is the amplifying transistor Qmain. The amplifying transistor Qmain is an NXP BFP740 SiGe heterojunction bipolar transistor with a cutoff frequency fT = 65 GHz, a maximum oscillation frequency fmax = 75 GHz, a minimum noise figure NFmin = 0.8 dB (2 GHz), a collector-emitter breakdown voltage BVCEO = 2.5 V, and a maximum collector current ICmax = 100 mA. It has a typical gain of 22 dB at 500 MHz and maintains 18 dB at 1 GHz. The bias circuit uses a dual ±5 V power supply, but a lower voltage source can also be selected. The power supply is provided by a low-noise linear regulator: +5 V uses an LT3042, and -5 V uses an LT3094. The output noise is less than 2 μVrms (10 Hz-100 kHz), and the power supply rejection ratio is greater than 75 dB.

[0080] The gate voltage VG output by the first gate unit 210 is the voltage at the emitter output of the third transistor Q5. This voltage is injected into the base of the amplifying transistor Qmain through a base series resistor RB, which is 470 Ω. The base series resistor RB limits the base current and provides RF isolation. A bypass capacitor is connected in parallel between the base of the amplifying transistor Qmain and ground: a first parallel capacitor CB1 and a second parallel capacitor CB2, forming a wideband decoupling. The first parallel capacitor CB1 is a 10 μF tantalum capacitor, and the second parallel capacitor CB2 is a 100 nF ceramic capacitor.

[0081] When VG = +0.7 V, the collector current IC of the amplifier transistor Qmain is set to 30 mA. With a current gain β of approximately 100, the base current IB is approximately 0.3 mA, the voltage drop across the base series resistor RB is approximately 0.14 V, and the base-emitter voltage VBE is approximately 0.56 V. This value is slightly lower than the 0.7 V of a silicon BJT but is suitable for SiGe HBTs because germanium doping reduces the bandgap. The collector of the amplifier transistor Qmain is connected to a +5 V power supply via an RF choke RFC. The RF choke RFC uses an L = 100 nH inductor with a self-resonant frequency greater than 2 GHz, providing a DC path while isolating RF. To obtain the maximum output swing, the collector quiescent voltage VC is set to approximately 2.5 V (half the power supply voltage). The actual collector quiescent voltage VC is determined by the load line; by fine-tuning VG, the collector quiescent voltage VC is stabilized at around 2.8 V, leaving a margin to avoid saturation. When VG = -2 V, considering the voltage drop across the base series resistor RB, VBE is approximately -2.14 V. The amplifying transistor Qmain enters deep reverse bias cutoff, and the collector current of Qmain drops to the leakage current level (less than 10 μA). Using a negative power supply to achieve deep cutoff avoids parasitic conduction caused by base floating and accelerates minority carrier recombination, thus shortening the turn-off time.

[0082] After the dual power supply circuit is connected, the +5V power supply current is approximately 35 mA, and the -5V power supply current is less than 1 mA. The peak-to-peak input power of the first gate unit 210 is set to approximately 7 mVpp for a 50 Ω system. When there is no input signal, the first gate unit 210 outputs a cutoff voltage of -2 V, the amplifying transistor Qmain is turned off, the collector current is less than 10 μA, the fourth transistor Q6 of the inverter in the second gate unit 220 is turned off, the fifth transistor Q7 is turned on, and the second diode D2 is forward biased and in a low-resistance state. The simulated single-photon detector output, such as... Figure 19 As shown, the input pulse width is 1 ns, the rise time is 200 ps, ​​and the amplitude is 10 mVpp. At t=2ns, the pulse leading edge reaches the detection branch. The envelope detector extracts the envelope within approximately 0.6 ns, the differential comparator completes the decision and flips within approximately 0.8 ns, and the gate voltage generation circuit 213 outputs a +0.7 V turn-on voltage within approximately 0.4 ns. The total response time is approximately 1.8 ns. The main channel pulse arrives at the amplification unit 310 approximately 2 ns after a delay line. At this time, the gate bias has been established, the fourth transistor Q6 of the second gate unit 220 is turned on, the fifth transistor Q7 is turned off, and the second diode D2 enters a high-impedance state, ensuring that the pulse can be fully amplified without being shunted by the discharge path.

[0083] The above scheme was simulated in LTspice to obtain performance graphs. Figure 9 and Figure 19 .in, Figure 9 The gain of the dual-gated RF amplifier circuit of this invention is shown. It can be seen that a pulse with an amplitude of approximately 90 mV is observed at the amplifier output, indicating a gain greater than 15 dB. Figure 19 The simulation results show that the pulse rise is very steep, and after the pulse ends, the tail decays into a clean single exponential curve. The time to return to the baseline ±1% is about 1.8 ns, which meets the requirement of not more than 2 ns.

[0084] After the pulse ends, the gate is turned off (VG jumps to -2 V), the fourth transistor Q6 of the second gate unit 220 is cut off, the fifth transistor Q7 is turned on, and the second diode D2 is pulled to a low-impedance state. The residual energy at the output terminal is quickly discharged to ground through the second DC blocking capacitor C_dc and the fifth resistor Rdump, with an equivalent time constant of approximately 1 ns. To verify the anti-stacking capability of the high count rate, pulse trains with progressively increasing repetition frequencies were input: 1 MHz, 10 MHz, 50 MHz, and 100 MHz, with each pulse width of 2 ns and an amplitude of 25 mVpp. At 1 MHz, the pulse interval of 1 μs is much longer than the recovery time, with no stacking, each pulse is correctly amplified, and the amplitude consistency is ±2%. At 10 MHz, the pulse interval is 100 ns, with no stacking and an amplitude consistency of ±3%. At 50 MHz, the pulse interval is 20 ns, approximately 10 times the recovery time, and slight stacking begins to appear, with the subsequent pulse baseline rising by about 1%. The pulse amplitude measurement error is still less than 5%, and the time stamping error is less than 100 ps. At 100 MHz, a pulse interval of 10 ns is only 5 times the recovery time, resulting in significant stacking, a baseline rise of approximately 3%, an amplitude measurement error of 12%, and a time stamping error of approximately 300 ps. Even at the extreme repetition frequency of 100 MHz, the system can still distinguish individual pulses without saturation or count loss. In contrast, traditional RF amplifiers have a tail time of approximately 20 ns, which becomes completely saturated and inoperable at 50 MHz. This invention compresses the tail time to less than 2 ns, increasing the maximum operable count rate by more than 10 times, providing key technical support for high-throughput single-photon detection applications.

[0085] The circuit in this embodiment was actually applied to a time response test system for a single-photon radiation detector, verifying the feasibility and superiority of the invention in a real single-photon detection scenario.

[0086] Example 2 This embodiment, based on Embodiment 1, uses GaAs MESFET instead of SiGe HBT to verify the applicability of the present invention to different transistor types.

[0087] The amplifying transistor is a NE3210S01 GaAs metal-semiconductor field-effect transistor (MESFET), with a cutoff frequency fT = 12 GHz, a maximum oscillation frequency fmax = 22 GHz, a saturation drain current IDSS = 100 mA, and a pinch-off voltage VP = -2.5 V. At 1 GHz, it has a typical gain of 16 dB and a noise figure of 2.2 dB. MESFETs are junction-type devices, and their operating principle differs from BJTs, requiring adjustment of the bias scheme. In the on-state, the gate voltage VG = -0.5 V (achieved by level conversion from +0.7 V output by the first gate unit 210), the drain voltage VD = +3.0 V, and the drain current ID = 50 mA. The gate bias is injected through a gate resistor RG = 10 kΩ, which also provides RF isolation. The drain is connected to a +5 V power supply via an RF choke (RFC). The voltage drop across the RF choke is approximately 2 V. A ferrite bead-type choke with a certain DC resistance is chosen to achieve the required voltage drop. In the off state, the gate voltage VG = -3 V, achieved by voltage division using a -5 V power supply. Exceeding the pinch-off voltage VP = -2.5 V, the channel is completely depleted, and the drain current ID is less than 1 mA. Since the input impedance of the MESFET is approximately 500 Ω higher than that of the BJT, the feedback resistor will be adjusted to Rf = 680 Ω, while the feedback capacitor remains at Cf = 1.0 pF. At this point, the closed-loop gain Acl is approximately 680 Ω divided by 50 Ω, approximately 13.6, or 22.7 dB. This, combined with the MESFET's open-loop gain of 16 dB, results in approximately 18 dB, meeting the circuit design requirements. The output capacitance Coss of the MESFET is slightly lower than that of the BJT, approximately 8 pF. Considering the output matching network capacitance, the total Cout is approximately 35 pF. To ensure that τ is no greater than 2 ns, the fifth resistor, Rdump = 47 Ω, is selected as the bleeder resistor.

[0088] Compared with the SiGe HBT solution in Example 1, Example 1 achieved a gain of 21 dB and Example 2 achieved 18 dB, both meeting the 10 dB-20 dB requirement. In terms of noise figure, Example 1 achieved 2.8 dB and Example 2 achieved 2.5 dB, both meeting the requirement of not exceeding 3 dB. The tailing time of both met the requirement of not exceeding 2 ns. The reflection coefficient of both met the design requirement of less than -10 dB. In terms of power consumption, Example 1 had 175 mW in the on-state and Example 2 had 250 mW. In terms of timing jitter, Example 1 had 680 ps and Example 2 had 750 ps, ​​both less than 1 ns. Both transistor solutions meet the design requirements. The SiGe HBT is slightly better in terms of gain and power consumption, while the GaAsMESFET is slightly better in terms of noise figure and tailing time. The choice can be made based on specific requirements in practical applications.

[0089] Single-photon radiation detector time response test system This invention also provides a time response testing system for a single-photon radiation detector, including the radio frequency amplification circuit described in any of the above embodiments, and a load line or a time-correlated single-photon counting module connected to the output module of the radio frequency amplification circuit, for high-precision time calibration and amplitude measurement of the output pulse of the single-photon radiation detector. Practical application in a single-photon radiation detector time response testing system verifies the feasibility and superiority of this invention in real-world single-photon detection scenarios.

[0090] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A radio frequency amplifier circuit, characterized in that, include: The input module is used to receive input signals; A dual-gating module (200) is connected to the output of the input module and includes a first gating unit (210) and a second gating unit (220). An amplifier and feedback module (300) has its input terminal connected to the input module, its output terminal connected to the second gating unit (220), and its control terminal connected to the first gating unit (210). It is used to enter the working state or the cutoff state under the control of the first gating unit (210) and amplify the input pulse signal. The output module is connected to the output terminal of the amplifier and feedback module (300) and is used to output the amplified pulse signal; The first gating unit (210) includes an input signal detection circuit (211) and an amplitude comparison circuit (212), which are used to detect the envelope of the input signal and compare it with a preset threshold. When the input signal exceeds the preset threshold, a gating pulse is generated to control the amplifier and feedback module (300) to enter the working state; otherwise, it is controlled to enter the cutoff state. The second gating unit (220) includes a clamping discharge circuit. When the first gating unit (210) controls the amplifier and feedback module (300) to enter the cutoff state, the clamping discharge circuit quickly discharges the residual charge at the output terminal of the output module through the low impedance path controlled by the gating pulse to suppress signal tailing. The first gating unit (210) further includes: The input signal detection circuit (211) includes an envelope detector and an RC integrator circuit. The envelope detector is constructed using a Schottky barrier diode and is used to extract the pulse envelope from the radio frequency signal of the detection branch and convert it into a DC detection voltage. The amplitude comparison circuit (212) includes a differential pair comparator composed of two NPN transistors. Its first input terminal is connected to the DC detection voltage, and its second input terminal is connected to the reference voltage. It is used to compare the DC detection voltage with the reference voltage and output a comparison result signal. The gate voltage generation circuit (213) includes a differential shaping network and a level conversion circuit, which is used to shape a narrow pulse according to the transition edge of the comparison result signal, and convert the narrow pulse into a level value as the gate voltage of the first gate unit (210) and the second gate unit (220) respectively; The second gating unit (220) also includes: An inverting drive circuit receives the gate voltage at its input terminal and outputs an inverted signal of the gate voltage. A current source drive circuit, connected to the output of the inverting drive circuit, is used to establish a stable positive current during the period when the amplifier and feedback module (300) enter the cutoff state, according to the state of the inverting signal. The clamping discharge circuit is connected to the output terminal of the current source drive circuit and is used to form the low impedance path under the positive current drive, providing a discharge path for the output node of the output module.

2. The radio frequency amplifier circuit according to claim 1, characterized in that, The input module includes a signal source, a first input matching network, a signal splitting network, and a main channel delay line; The first input matching network includes a series resistor Rs and a first DC blocking capacitor C1 connected in series. One end of the series resistor Rs is electrically connected to the signal source, and the first DC blocking capacitor C1 is electrically connected to the signal splitting network. The signal branching network includes a first series resistor R_T1, a second series resistor R_T2, a first parallel resistor R_shunt1, and a second parallel resistor R_shunt2; the first DC blocking capacitor C1 is electrically connected to the first end of the first series resistor R_T1 and the first end of the first parallel resistor R_shunt1, the second end of the first series resistor R_T1 is electrically connected to the first end of the second series resistor R_T2 and the first end of the second parallel resistor R_shunt2, the second end of the first parallel resistor R_shunt1 and the second end of the second parallel resistor R_shunt2 are electrically connected and a detection branch is formed, with a matching resistor terminal at the end; the second end of the second series resistor R_T2 is electrically connected to the input end of the main channel delay line.

3. The radio frequency amplifier circuit according to claim 2, characterized in that, The main channel delay line is one of the following: coaxial line, microstrip line, stripline, or RC delay network.

4. The radio frequency amplifier circuit according to claim 1, characterized in that, The amplifier and feedback module (300) includes: The amplification unit (310) adopts a single-stage common-emitter or common-source amplification structure, including at least one amplification transistor Qmain. The control terminal of the amplification transistor Qmain is connected to the output terminal of the first gate unit (210) through a base series resistor RB to receive the gate voltage of the first gate unit (210). The feedback unit (320) includes a feedback resistor Rf and a feedback capacitor Cf connected in parallel, which are connected between the input and output terminals of the amplifier unit (310) to expand the circuit bandwidth and stabilize the gain.

5. The radio frequency amplifier circuit according to claim 4, characterized in that, The amplification unit (310) includes a second input matching network, a transistor bias and amplification circuit, and an output matching network; The second input matching network includes a first parallel inductor Lp and a second series capacitor Cs, wherein the first end of the first parallel inductor Lp and the first end of the second series capacitor Cs are respectively electrically connected to the output of the main channel delay line of the input module. The transistor biasing and amplification circuit includes a base series resistor RB, an amplifying transistor Qmain, a first parallel capacitor CB1, a second parallel capacitor CB2, an RF choke RFC, a third parallel capacitor C_bulk_pos, and a fourth parallel capacitor C_VCC; the first terminal of the base series resistor RB, the first terminal of the first parallel capacitor CB1, the first terminal of the second parallel capacitor CB2, and the base of the amplifying transistor Qmain are all electrically connected to the second series capacitor Cs; the second terminal of the base series resistor RB is electrically connected to the output terminal of the gate voltage generation circuit (213); the second terminal of the first parallel capacitor CB1... The second terminal of the second parallel capacitor CB2 is grounded; the collector of the amplifying transistor Qmain is electrically connected to the first terminal of the RF choke RFC; the second terminal of the RF choke RFC, the first terminal of the third parallel capacitor C_bulk_pos, and the first terminal of the fourth parallel capacitor C_VCC are electrically connected to the positive power supply; the second terminal of the third parallel capacitor C_bulk_pos and the second terminal of the fourth parallel capacitor C_VCC are both grounded; the emitter of the amplifying transistor Qmain is electrically connected to the feedback unit (320); the collector of the amplifying transistor Qmain is electrically connected to the output matching network. The output matching network includes a third series capacitor Cpi1, a second parallel inductor Lpi, and a fourth series capacitor Cpi2. The third series capacitor Cpi1 and the fourth series capacitor Cpi2 are connected in series. The third series capacitor Cpi1 is electrically connected to the collector of the amplifying transistor Qmain. The fourth series capacitor Cpi2 is electrically connected to the second DC blocking capacitor C_dc and the amplifier output VOUT.

6. The radio frequency amplifier circuit according to claim 4, characterized in that, The amplifying transistor Qmain is a SiGe heterojunction bipolar transistor (HBT) or a GaAs metal-semiconductor field-effect transistor (MESFET); the amplification unit (310) is powered by a dual power supply, providing a forward bias voltage and a reverse bias cutoff voltage to the amplifying transistor Qmain.

7. A time response testing system for a single-photon radiation detector, characterized in that, The device includes a radio frequency amplification circuit as described in any one of claims 1 to 6, and a load line or time-correlated single-photon counting module connected to the output module of the radio frequency amplification circuit, for high-precision time calibration and amplitude measurement of the output pulse of the single-photon radiation detector.

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