Data encryption method and device based on target processor architecture, and embedded device

Abstract

The application discloses a data encryption method and device based on a target processor architecture, and an embedded device, and relates to the field of data encryption or other related technical fields, and the method comprises the following steps: receiving plaintext data to be encrypted, and transmitting the plaintext data to a hardware acceleration unit asynchronously; reading extended key data in a first data cache according to an encryption algorithm type, and mapping the extended key data to a key register of the hardware acceleration unit; based on the extended key data, controlling the hardware acceleration unit to perform encryption operation on the plaintext data, and interrupting a designated general register group in a core processor to notify that ciphertext data obtained through encryption is obtained. The application solves the technical problem of low execution efficiency when an encryption algorithm is implemented on a processor architecture in the related art.

Description

Technical Field

[0001] This invention relates to the field of data encryption technology or other related fields. Specifically, it relates to a data encryption method and apparatus, and an embedded device based on a target processor architecture. Background Technology

[0002] With the rapid development of information technology, cryptographic algorithms are increasingly being used in security-critical areas such as financial transactions, IoT devices, and smart cards, placing higher demands on computational efficiency and energy consumption control. The SM algorithm, as a domestically designed commercial cryptographic standard, has become a core component of information security infrastructure due to its high security and policy compliance.

[0003] In related technologies, the implementation of the SM algorithm on various processor architectures generally adopts a "general software porting" approach, that is, directly migrating the SM algorithm code applicable to other general-purpose processors to the processor platform without modification. This implementation method has significant drawbacks, resulting in low algorithm performance and energy efficiency. The main disadvantages include: 1) Reliance on software loop instructions, leading to low computational efficiency. In related technologies, the core operations of the SM algorithm are mainly completed through software loops and general instructions, rather than utilizing the dedicated computing units of the processor architecture. This requires the introduction of additional instruction decoding and branch prediction overhead, resulting in long instruction execution paths and large clock cycle consumption, significantly extending the computation cycle. For example, in the SM2 key exchange operation, the software loop method may increase the clock cycle by more than 30%, which cannot meet the real-time requirements. 2) Excessive system energy consumption. The existing SM algorithm implementation relies entirely on the general-purpose core processor CPU to perform all operations, which not only keeps the energy consumption high (for example, in low-power embedded devices, the power consumption of SM4 encryption and decryption operations may exceed the budget by 25%), but also fails to meet the strict energy efficiency requirements of battery-powered devices (such as smart wearable devices).

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This invention provides a data encryption method and apparatus, and an embedded device based on a target processor architecture, to at least solve the technical problem of low execution efficiency when implementing encryption algorithms on a processor architecture in related technologies.

[0006] To achieve the above objectives, according to one aspect of this application, a data encryption method based on a target processor architecture is provided, applied to a controller in the target processor architecture. The target processor architecture includes an embedded processor architecture running on a domestically produced reduced instruction set computer. The target processor architecture includes at least the controller, a hardware acceleration unit, and a core processor. The data encryption method based on the target processor architecture includes: receiving plaintext data to be encrypted and asynchronously transmitting the plaintext data to the hardware acceleration unit; reading extended key data from a first data cache according to an encryption algorithm type and mapping the extended key data to a key register of the hardware acceleration unit; controlling the hardware acceleration unit to perform encryption operations on the plaintext data based on the extended key data; and interrupting the encrypted ciphertext data to notify a designated general-purpose register group in the core processor.

[0007] Optionally, the step of asynchronously transmitting the plaintext data to the hardware acceleration unit includes: loading the plaintext data into a designated general-purpose register group in the core processor; and asynchronously transmitting the plaintext data from the designated general-purpose register group to the hardware acceleration unit using dedicated instructions.

[0008] Optionally, before loading the plaintext data into a designated general-purpose register set in the core processor, the method further includes: parsing the architecture parameters of the currently running target processor architecture to obtain the parameters of the designated general-purpose register set, the cache bit length of the first data cache, the cache bit length of the second data cache, the encryption algorithm type supported by the hardware acceleration unit, and the controller type; determining the input-output characteristics of the encryption algorithm based on the encryption algorithm type supported by the hardware acceleration unit, wherein the input-output characteristics are used to determine the bit length of the extended key data, the bit length of the plaintext data to be encrypted, and the bit length of the ciphertext data output after encryption; and compiling the underlying driver function to encapsulate multiple dedicated instructions into the core processing unit.

[0009] Optionally, before loading the plaintext data into a designated general-purpose register group in the core processor, the method further includes: initializing the extended key array of the encryption algorithm; locking the initialized extended key array in the key storage area of ​​the first data cache using a specified function, wherein the extended key array locked in the first data cache includes multiple sets of extended key data; and configuring the address of the key register of the hardware acceleration unit according to the cache bit width of the first data cache.

[0010] Optionally, after controlling the hardware acceleration unit to perform encryption operations on the plaintext data based on the extended key data, the method further includes: writing back the encrypted ciphertext data to the first data cache; or writing back the encrypted ciphertext data to main memory.

[0011] Optionally, the core processor includes: the register group, which includes multiple registers, wherein a first register among the multiple registers is used to store the encrypted ciphertext data; an instruction decoder, which is used to extract pre-configured special instructions based on the plaintext data to be encrypted, and send the special instructions to the hardware acceleration unit; and an arithmetic logic unit, which is used to perform basic arithmetic and logical operations of the encryption algorithm.

[0012] Optionally, the hardware acceleration unit includes: a hardware acceleration engine for performing encryption operations on the plaintext data based on the extended key data; a key expansion module for determining multiple sets of extended key data based on the algorithm characteristics of the encryption algorithm; and an algorithm module for accelerating the execution process of the encryption algorithm.

[0013] According to another aspect of the present invention, an embedded device is also provided, running an embedded processor architecture of a domestically produced reduced instruction set computer, comprising: a memory hierarchy including: main memory, a first data cache, and a second data cache, wherein the main memory is used to provide a cache range, and the first data cache is used to store an extended key array; a hardware acceleration unit, including at least: a hardware acceleration engine, a key expansion module, and an algorithm module, used to perform encryption operations on received plaintext data based on the extended key data, and to interrupt and notify a designated general-purpose register group in the core processor of the encrypted ciphertext data; a core processor, including at least: a register group and an instruction decoder, used to preload the extended key data and transmit the plaintext data and dedicated instructions to the hardware acceleration unit; and a direct memory controller, used to execute the data encryption method based on the target processor architecture described in any one of the above embodiments.

[0014] According to another aspect of the present invention, a data encryption device based on a target processor architecture is also provided, applied to a controller in the target processor architecture. The target processor architecture includes: an embedded processor architecture running on a domestically produced reduced instruction set computer, and the target processor architecture includes at least: the controller, a hardware acceleration unit, and a core processor. The data encryption device based on the target processor architecture includes: a data transmission unit, used to receive plaintext data to be encrypted and asynchronously transmit the plaintext data to the hardware acceleration unit; a key mapping unit, used to read extended key data from a first data cache according to the encryption algorithm type and map the extended key data to the key register of the hardware acceleration unit; and a data encryption unit, used to control the hardware acceleration unit to perform encryption operations on the plaintext data based on the extended key data, and to interrupt and notify a designated general-purpose register group in the core processor of the encrypted ciphertext data.

[0015] Optionally, the data transmission unit includes: a data loading module for loading the plaintext data into a designated general-purpose register group in the core processor; and a data transmission module for asynchronously transmitting the plaintext data from the designated general-purpose register group to the hardware acceleration unit via dedicated instructions.

[0016] Optionally, the data encryption device based on the target processor architecture further includes: a processor architecture parsing unit, configured to parse the architecture parameters of the currently running target processor architecture before loading the plaintext data into a designated general-purpose register group in the core processor, to obtain the parameters of the designated general-purpose register group, the cache bit length of the first data cache, the cache bit length of the second data cache, the encryption algorithm type supported by the hardware acceleration unit, and the controller type; an encryption algorithm feature determination unit, configured to determine the input-output features of the encryption algorithm based on the encryption algorithm type supported by the hardware acceleration unit, wherein the input-output features are used to determine the bit length of the extended key data, the bit length of the plaintext data to be encrypted, and the bit length of the ciphertext data output after encryption; and an instruction encapsulation unit, configured to compile low-level driver functions and encapsulate multiple dedicated instructions into the core processing unit.

[0017] Optionally, the data encryption device based on the target processor architecture further includes: an initialization unit, configured to initialize an extended key array of the encryption algorithm before loading the plaintext data into a designated general-purpose register group in the core processor; a key locking unit, configured to lock the initialized extended key array in the key storage area of ​​the first data cache using a specified function, wherein the extended key array locked in the first data cache includes multiple sets of extended key data; and an address configuration unit, configured to configure the address of the key register of the hardware acceleration unit according to the cache bit width of the first data cache.

[0018] Optionally, the data encryption device based on the target processor architecture further includes: a write-back unit, configured to write back the encrypted ciphertext data to the first data cache after controlling the hardware acceleration unit to perform encryption operations on the plaintext data based on the extended key data; or, to write back the encrypted ciphertext data to main memory.

[0019] Optionally, the core processor includes: the register group, which includes multiple registers, wherein a first register among the multiple registers is used to store the encrypted ciphertext data; an instruction decoder, which is used to extract pre-configured special instructions based on the plaintext data to be encrypted, and send the special instructions to the hardware acceleration unit; and an arithmetic logic unit, which is used to perform basic arithmetic and logical operations of the encryption algorithm.

[0020] Optionally, the hardware acceleration unit includes: a hardware acceleration engine for performing encryption operations on the plaintext data based on the extended key data; a key expansion module for determining multiple sets of extended key data based on the algorithm characteristics of the encryption algorithm; and an algorithm module for accelerating the execution process of the encryption algorithm.

[0021] According to another aspect of the present invention, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to execute any of the above-described data encryption methods based on a target processor architecture.

[0022] According to another aspect of the present invention, an electronic device is also provided, including one or more processors and a memory, the memory being used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the data encryption method based on the target processor architecture described above.

[0023] According to another aspect of the present invention, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps of the data encryption method based on the target processor architecture described in any one of the above embodiments.

[0024] In this disclosure, plaintext data to be encrypted is received and asynchronously transmitted to the hardware acceleration unit; extended key data in the first data cache is read according to the encryption algorithm type and mapped to the key register of the hardware acceleration unit; based on the extended key data, the hardware acceleration unit is controlled to perform encryption operation on the plaintext data, and the encrypted ciphertext data is interrupted to notify a designated general-purpose register group in the core processor.

[0025] Based on the above disclosure, the key required by the encryption algorithm and the plaintext data to be encrypted can be directly mapped to the hardware acceleration unit. Then, the encryption operation is performed by the hardware acceleration unit in the target processor architecture, and the operation result is directly written back to the register group. This hardware acceleration unit has the ability to complete one round of encryption in a single cycle. Compared with the path delay caused by the frequent exchange and transfer of parameters between memory and registers and memory access delay in traditional software, it can greatly improve the system's computing efficiency, thereby solving the technical problem of low execution efficiency when implementing encryption algorithms on processor architecture in related technologies. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0027] Figure 1 A hardware structure block diagram of a computer terminal (or mobile device) for implementing a data encryption method based on a target processor architecture is shown.

[0028] Figure 2 This is a flowchart of an optional data encryption method based on a target processor architecture according to an embodiment of the present invention;

[0029] Figure 3 This is a flowchart illustrating an accelerated optimization of the SM algorithm based on the CSKY architecture according to an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram showing the connection between a Crypto unit and an SM4 algorithm module in an optional CSKY architecture according to an embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram illustrating the collaborative operation of various components in an optional processor architecture according to an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of an optional data encryption device based on a target processor architecture according to an embodiment of the present invention;

[0033] Figure 7This is a structural block diagram of an electronic device that performs a data encryption method based on a target processor architecture according to an embodiment of this application. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] To facilitate understanding of the present invention by those skilled in the art, some terms or nouns involved in the various embodiments of the present invention are explained below:

[0037] The SM algorithm, or State Cryptography Algorithm for short, refers to domestically developed commercial cryptographic standard algorithms, including SM2, SM3, and SM4, used to ensure the confidentiality, integrity, and authentication of information. It should be noted that this application uses the SM4 block cipher algorithm for illustrative purposes, which achieves data encryption through 32 rounds of iterative computation.

[0038] The CSKY architecture, Chengdu Sunway Kernal Architecture, or CSKY for short, is a 32-bit / 64-bit Reduced Instruction Set Computer (RISC) processor architecture optimized for embedded systems, IoT terminals, and industrial control equipment. It is the underlying hardware platform for implementing this invention.

[0039] The ALU (Arithmetic Logic Unit) is the core component of the CPU that performs basic arithmetic operations (such as addition and subtraction) and logical operations (such as XOR and shift). In the SM4 software implementation, it is responsible for the step-by-step calculation of round functions.

[0040] A Direct Memory Access Controller (DMA) is a CPU-independent hardware module that enables high-speed data transfer between memory, cache, and peripherals without CPU intervention.

[0041] The hardware acceleration unit, or Crypto unit for short, is a dedicated cryptographic coprocessor integrated into the CSKY architecture.

[0042] Cache locking, or cache pinning, refers to the process of forcing specific data (such as SM4 extended keys) to reside in the L1 cache through hardware instructions or system interfaces, preventing it from being replaced or evicted by other data, and ensuring that frequently accessed data is always in a high-speed access state. This is the key mechanism of this invention to achieve a stable high cache hit rate and low access latency.

[0043] The round function refers to the core operation module in the SM4 algorithm that is executed 32 times repeatedly. Each round includes XOR, S-box substitution and linear transformation operations. This invention solidifies the entire round operation into a single hardware instruction through a dedicated instruction, realizing the efficient execution of "1 instruction = 1 round", and completely changing the inefficient mode of traditional software looping.

[0044] It should be noted that the data encryption method and apparatus based on the target processor architecture in this disclosure can be used in the field of data encryption technology when the encryption algorithm is accelerated and optimized based on the processor architecture, and can also be used in any field other than the field of data encryption technology when the encryption algorithm is accelerated and optimized based on the processor architecture. This disclosure does not limit the application field of the data encryption method and apparatus based on the target processor architecture.

[0045] It should be noted that the information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, and displayed data, etc.) collected in this public disclosure are information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, storage, use, processing, transmission, provision, disclosure, and application of related data are handled with corresponding access points, allowing users to choose to authorize or refuse. For example, this system has interfaces with relevant users or organizations. Before obtaining relevant information, a request to obtain the information needs to be sent to the aforementioned user or organization through the interface, and the relevant information is obtained only after receiving consent from the aforementioned user or organization.

[0046] It should be noted that in this disclosure, customer information is collected and analyzed, and users are provided with corresponding operation entry points to choose whether to agree to or reject the automated decision results; if the user chooses to reject, the process will proceed to the expert decision-making process.

[0047] The following embodiments of the present invention can be applied to various data encryption systems / applications / devices based on the target processor architecture. The present invention can be applied to various resource-constrained embedded information security devices using domestically produced processor architectures (such as the CSKY architecture processor), and is particularly suitable for domestically produced trusted security application scenarios with stringent requirements for computing performance, real-time performance, and power consumption. Examples include IoT security chips (in massive edge devices such as smart meters, industrial sensors, and vehicle networking terminals, real-time SM4 encryption is required to ensure data transmission security), smart card security devices (such as financial payment cards, security tokens, etc.), industrial control systems, and trusted execution environments for mobile terminals (such as mobile phones or tablets equipped with the CSKY processor).

[0048] This invention breaks through the performance constraints of the traditional "software porting" model through a four-fold systematic optimization of "hardware adaptation, instruction optimization, memory layout, and heterogeneous collaboration." It achieves a comprehensive leap in the SM algorithm in terms of computational efficiency, memory access, system energy consumption, and real-time performance on domestic processor architectures. It can significantly reduce memory access latency, significantly reduce system energy consumption, significantly reduce CPU utilization, enhance execution time stability, and is fully compatible with national cryptographic standards. It also has good portability and scalability.

[0049] The present invention will now be described in detail with reference to various embodiments.

[0050] Example 1

[0051] According to an embodiment of the present invention, an embodiment of a data encryption method based on a target processor architecture is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0052] The data encryption method based on the target processor architecture provided in Embodiment 1 of this application can be executed in a mobile terminal, computer terminal, or similar computing device. Figure 1 A hardware block diagram of a computer terminal (or mobile device) for implementing a data encryption method based on a target processor architecture is shown. Figure 1 As shown, computer terminal 10 (or mobile device) may include one or more ( Figure 1 The processor 102 (which may include, but is not limited to, a microprocessor MCU (Microcontroller Unit) or a programmable gate array (FPGA)) is shown as 102a, 102b, ..., 102n. It also includes a memory 104 for storing data and a transmission device 106 for communication functions. In addition, it may include: a display, an input / output interface (I / O interface), a Universal Serial Bus (USB) port (which may be included as one of the ports of a BUS bus), a network interface, a power supply, and / or a camera. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned electronic device. For example, computer terminal 10 may also include... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0053] It should be noted that the aforementioned one or more processors 102 and / or other data processing circuits are generally referred to herein as "data processing circuits". These data processing circuits may be embodied, in whole or in part, in software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuits may be a single, independent processing module, or may be integrated, in whole or in part, into any other element within the computer terminal 10 (or mobile device). As involved in the embodiments of this application, the data processing circuits serve as a processor control mechanism (e.g., selection of a variable resistor termination path connected to an interface).

[0054] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the data encryption method based on the target processor architecture in this embodiment. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, thereby implementing the aforementioned data encryption method based on the target processor architecture. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0055] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of the computer terminal 10. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0056] The display can be, for example, a touchscreen liquid crystal display (LCD), which allows the user to interact with the user interface of the computer terminal 10 (or mobile device).

[0057] To achieve the above objectives, according to one aspect of this application, a data encryption method based on a target processor architecture is provided, which is applied to a controller in the target processor architecture. The target processor architecture includes: an embedded processor architecture running on a domestically produced reduced instruction set computer, and the target processor architecture includes at least: a controller, a hardware acceleration unit, and a core processor.

[0058] This invention constructs a heterogeneous collaborative encryption architecture for domestic embedded platforms, rather than a general-purpose computing platform. It comprises three key functional modules: a controller, a hardware acceleration unit, and a core processor, which together form a unified encryption execution system of "control-computation-transfer". The target processor architecture serves as the underlying hardware platform of this invention. The processor architecture type can include, but is not limited to, the CSKY architecture. The CSKY architecture possesses typical Reduced Instruction Set Computing (RISC) characteristics such as a reduced instruction set, rich registers, efficient pipeline, and low power consumption, adapting to the resource-constrained requirements of embedded scenarios. The controller's responsibilities include: initializing encryption parameters, configuring the DMA controller, triggering the hardware acceleration unit, responding to interrupts, and managing the task queue. It does not directly perform intensive encryption operations but achieves system-level parallelism by coordinating other hardware units. The hardware acceleration unit refers to a dedicated cryptographic coprocessor integrated into the target processor architecture, such as the Crypto unit. Internally, it contains hardware circuitry for cryptographic operations like the SM4 round function and the SM3 compression function, and can execute dedicated instructions such as sm4_round and sm3_compress. This hardware acceleration unit is capable of completing one round of encryption in a single cycle, achieving an order-of-magnitude improvement in computational efficiency compared to traditional software implementations. It is the "computing engine" that enables the performance leap in this invention. The core processor, the core of the target processor architecture, is responsible for executing general computing tasks such as the main control program, operating system scheduling, and user logic processing. In this invention, its role changes from a full-stack executor to a lightweight controller, responsible for configuration, triggering, and response. It no longer participates in high-overhead operations such as data rotation and S-box lookup, thereby significantly improving system efficiency.

[0059] Optionally, the core processor includes: a register set, comprising multiple registers, wherein a first register among the multiple registers is used to store the encrypted ciphertext data; an instruction decoder, used to extract pre-configured special instructions based on the plaintext data to be encrypted, and send the special instructions to the hardware acceleration unit; and an arithmetic logic unit, used to perform basic arithmetic and logical operations of the encryption algorithm.

[0060] In this embodiment, the final output of the encryption operation is directly written to a designated register in the register group (such as the first register r0). This register has a hardware-level mapping relationship with the output port of the hardware acceleration unit. In addition, after the encrypted data is encrypted by the hardware acceleration unit, it is directly written back to this register through the internal data path, avoiding intermediate writing to memory or cache. This helps to shorten the result return path, reduce memory access latency during subsequent data reading, and make the encrypted data available to the controllable logic access state earlier.

[0061] Furthermore, this embodiment identifies cryptographic-specific instructions (such as sm4_enc) called by the software layer through an instruction decoder. During the instruction decoding stage, it identifies the source of the opcode and operands, and directly routes the instruction's control signals and data source address information to the input interface of the hardware acceleration unit. This process does not rely on software drivers or interrupt handling, enabling transparent conversion of instructions from general instruction sets to hardware-accelerated paths. This helps eliminate the additional overhead introduced by function calls or system calls in traditional solutions, allowing encryption requests to be triggered at near-hardware response speeds.

[0062] In this embodiment, the arithmetic logic unit undertakes lightweight computational tasks not covered by the acceleration unit in the encryption process, including basic operations such as the initial XOR of the round key, address offset calculation, loop counter control, and status flag updates. This helps to rationally distribute the computational load between general-purpose and special-purpose modules, allowing the core processor to maintain lightweight control over the system process. The coordinated configuration of the register set, instruction decoder, and arithmetic logic unit allows the core processor to focus on control, guidance, and auxiliary computation in the encryption process. The hardware acceleration unit handles intensive computation, and the instruction decoder implements hardware-level distribution of special instructions. The whole system forms an integrated processing path of instruction triggering, data pass-through, and result write-back, which helps to improve the determinism of instruction execution and the continuity of data flow. This allows the encryption operation to maintain architectural integrity while having a clearer division of labor among modules and a lower frequency of software intervention.

[0063] Optionally, the hardware acceleration unit includes: a hardware acceleration engine for performing encryption operations on plaintext data based on extended key data; a key expansion module for determining multiple sets of extended key data based on the algorithmic characteristics of the encryption algorithm; and an algorithm module for accelerating the execution process of the encryption algorithm.

[0064] The hardware acceleration engine in this embodiment includes combinational logic circuits for encryption algorithms (such as the SM4 algorithm). Its input is connected to the register set and key expansion module, and its output is directly connected to a designated register of the core processor. After receiving plaintext data and the corresponding round key, the hardware acceleration engine can independently complete all 32 rounds of round function operations, including but not limited to: S-box permutation, row shifting, column mixing, and round key addition operations. Its operation process is controlled by a fixed timing sequence and does not require the core processor to participate in intermediate state management.

[0065] The key expansion module in this embodiment can use the hardware-implemented SM key scheduling algorithm. Based on the nonlinear transformation and cyclic shift rules defined by the algorithm, the received initial key is expanded in parallel. For example, for the SM4 algorithm, 32 round keys can be generated. The pre-calculation of the expanded key is completed before the encryption process starts, and the result is directly written into the internal cache or latch register for the hardware acceleration engine to call in the order of rounds. This helps to avoid the delay caused by the core processor dynamically calculating the key during the encryption process, reduces the memory access dependency in the key acquisition path, and enables the key supply and data encryption process to achieve time decoupling.

[0066] In this embodiment, the algorithm module is a control logic unit integrated within the hardware acceleration unit. Its functions include coordinating the timing synchronization of the hardware acceleration engine and the key expansion module, managing the triggering conditions for data input and output, responding to start instructions from the core processor, and generating an interrupt signal after the operation is completed. Through the layered design of the hardware acceleration engine, key expansion module, and algorithm module, the computation, key generation, and flow control of the encryption operation are handled by independent hardware subunits. This helps reduce the complexity of the core processor's involvement in the encryption process, improves the parallelism of the operation and the predictability of the execution, and enables the overall encryption process to achieve high throughput, low latency, and deterministic hardware autonomous completion after the instruction is triggered.

[0067] Under the aforementioned operating environment, this application provides the following: Figure 2 The data encryption method shown is based on the target processor architecture. Figure 2 This is a flowchart of an optional data encryption method based on a target processor architecture according to an embodiment of the present invention, such as... Figure 2 As shown, the method includes the following steps S201 to S203. The present invention will be described in detail below with reference to each implementation step.

[0068] Step S201: Receive the plaintext data to be encrypted and asynchronously transmit the plaintext data to the hardware acceleration unit.

[0069] This embodiment decouples the transmission of plaintext data from the computational tasks of the core processor, achieving non-blocking execution of the data transfer process. After being received, the plaintext data does not rely on the core processor's continued participation in subsequent transmission processes; instead, the hardware mechanism autonomously completes the directed transfer from registers to the hardware acceleration unit. This approach helps reduce the load on the core processor during the data transfer phase, enabling it to process other control tasks in parallel, thereby improving the overall concurrency capability of the system.

[0070] Optionally, the step of asynchronously transmitting plaintext data to the hardware acceleration unit includes: loading the plaintext data into a designated general-purpose register set in the core processor; and asynchronously transmitting the plaintext data from the designated general-purpose register set to the hardware acceleration unit using dedicated instructions.

[0071] In this embodiment, the plaintext data to be encrypted is preloaded into a predefined general-purpose register set (such as r0–r3) in the core processor using standard load instructions. This register set has a direct mapping relationship with the input ports of the hardware acceleration unit. This design avoids the plaintext data passing through the memory buffer during transmission, reduces cache misses and bus access latency, helps shorten the path latency in the data preparation stage, and makes the data more quickly ready to be read by the hardware acceleration unit.

[0072] Furthermore, plaintext data is asynchronously transferred from a designated general-purpose register set to the hardware acceleration unit via dedicated instructions. This embodiment utilizes cryptographically specific instructions (such as sm4_enc) natively supported by the CSKY architecture. When the core processor executes this instruction, it triggers the input registers within the hardware acceleration unit to automatically read data from the designated general-purpose register set. The execution of this instruction does not block the core processor; after completion, the core processor can immediately proceed to subsequent operations, while data transmission is completed independently by the hardware path. This mechanism enables parallelism between instruction issuance and data transfer, helping to reduce software-level polling overhead and interrupt frequency, making the encryption process closer to the low-latency mode of native hardware execution.

[0073] Plaintext data is transmitted to the hardware acceleration unit via register pass-through and dedicated instruction triggering, eliminating the need for continuous core processor intervention in the data transfer process. The system separates the control flow and data flow in the unit data encryption task, which helps improve instruction pipeline efficiency, reduce processor idle cycles caused by waiting for data, and reduce memory access frequency and bus contention, making the overall response of encryption operations more predictable.

[0074] Step S202: Read the extended key data in the first data cache according to the encryption algorithm type, and map the extended key data to the key register of the hardware acceleration unit.

[0075] In this embodiment, based on the algorithm type (e.g., SM4, SM3) corresponding to the current encryption task, a pre-locked extended key array is located from the first data cache. This extended key array has been configured to reside in a specific physical area of ​​the cache during the initialization phase. The extended key data is directly transferred from the cache address to the dedicated key register inside the hardware acceleration unit via a controller (e.g., a direct memory controller, DMA). This process is completed automatically by the hardware without the core processor's involvement in data transfer, which helps avoid the key being transferred through main memory during transmission. This reduces bus occupancy and cache pollution, allowing the key data to enter the input path of the encryption operation with minimal latency.

[0076] Step S203: Based on the extended key data, control the hardware acceleration unit to perform encryption operations on the plaintext data, and interrupt the notification of the encrypted ciphertext data to the designated general-purpose register group in the core processor.

[0077] In this embodiment, after the hardware acceleration unit completes one or more rounds of encryption operations, it detects the completion flag through an internal state machine and triggers an interrupt signal to the interrupt controller of the core processor. This interrupt is only used to notify that the operation result is ready. The encrypted data itself has already been written to the designated general-purpose register group of the core processor (such as the first register r0) through a hardware direct connection, without the need for additional read or copy operations. This helps to achieve synchronous perception of computation completion and result readiness, reduces the execution gap caused by software polling or delayed response, and allows the control logic to directly access the registers to obtain the result in the interrupt service routine, improving the continuity of the process.

[0078] Optionally, after controlling the hardware acceleration unit to perform encryption operations on the plaintext data based on the extended key data, the method further includes: writing back the encrypted ciphertext data to the first data cache; or writing back the encrypted ciphertext data to the main memory.

[0079] In this embodiment, after the hardware acceleration unit completes the encryption operation, the output ciphertext data can be directly written to the pre-allocated cache area in the first data cache through the internal data path. This cache area is configured as a temporary storage area for the encryption result during the system initialization phase. Its address space is adjacent to the key data area, and a latching mechanism is used to prevent it from being overwritten by other data. This helps to shorten the access path of the ciphertext data from the hardware unit to the cache, which can reduce the number of main memory accesses when the core processor reads the ciphertext later, so that the data can be transferred within the cache level.

[0080] In this embodiment, after the hardware acceleration unit completes the encryption operation, the encrypted data can be directly transferred from the designated register group of the core processor to the target address in the main memory through the controller. It should be noted that the transmission process is autonomously scheduled by the hardware controller, without the core processor participating in address calculation or data transfer. The target address is configured by the software and written to the register before the task starts, which helps to support continuous output in large-scale data encryption scenarios and can avoid write-back blocking caused by cache capacity limitations.

[0081] Therefore, the encrypted data in this embodiment can be selectively written back to the first data cache or main memory, allowing the system to flexibly adapt to the data access mode according to the application scenario. Cache write-back helps improve the continuous processing efficiency of small data blocks after encryption, while main memory write-back supports long data streams or batch processing requirements. Both modes are completed through hardware channels, which helps reduce the burden of core processor participation in the result writing stage.

[0082] Through the above steps, plaintext data to be encrypted can be received and asynchronously transmitted to the hardware acceleration unit. Extended key data is read from the first data cache according to the encryption algorithm type and mapped to the key register of the hardware acceleration unit. Based on the extended key data, the hardware acceleration unit is controlled to perform encryption operations on the plaintext data, and the encrypted ciphertext data is interrupted to notify the designated general-purpose register group in the core processor. In this embodiment, the key required by the encryption algorithm and the plaintext data to be encrypted can be directly mapped to the hardware acceleration unit. Then, the encryption operation is performed by the hardware acceleration unit in the target processor architecture, and the operation result is directly written back to the register group. This hardware acceleration unit has the ability to complete one round of encryption in a single cycle. Compared with the path latency caused by frequent parameter exchange and transfer between memory and registers and memory access latency in traditional software, this can greatly improve the system's computing efficiency, thereby solving the technical problem of low execution efficiency when implementing encryption algorithms on processor architectures in related technologies.

[0083] Optionally, before loading plaintext data into a designated general-purpose register set in the core processor, the method further includes: parsing the architecture parameters of the currently running target processor architecture to obtain the parameters of the designated general-purpose register set, the cache bit length of the first data cache, the cache bit length of the second data cache, the encryption algorithm type supported by the hardware acceleration unit, and the controller type; determining the input-output characteristics of the encryption algorithm based on the encryption algorithm type supported by the hardware acceleration unit, wherein the input-output characteristics are used to determine the bit length of the extended key data, the bit length of the plaintext data to be encrypted, and the bit length of the ciphertext data output after encryption; and compiling the underlying driver function to encapsulate multiple dedicated instructions into the core processing unit.

[0084] It should be noted that in this embodiment, during the system initialization phase, the hardware description information of the target processor architecture chip is read, including the register file number and width, the capacity and line size of the first and second data caches, the set of algorithms supported by the hardware acceleration unit (such as SM4 and SM3), and the channel configuration of the controller. This parsing process is completed by reading the chip's internal registers or device tree information, without relying on external configuration files, which helps to build an execution environment that is precisely matched with the current hardware platform.

[0085] Subsequently, based on the algorithm type identified by the hardware acceleration unit, this embodiment extracts the corresponding data format specifications from a preset algorithm feature table. For example, the plaintext and ciphertext of the SM4 algorithm are both 128 bits, the extended key is 32 groups of 32-bit words, and both input and output are 4-byte aligned structures. This feature information is used to constrain the boundary conditions of subsequent data loading, cache allocation, and register mapping, helping to ensure that the data structure and hardware interface are fully compatible in terms of bit width, alignment, and byte order. This can avoid abnormal encryption results or instruction execution failures caused by format mismatches.

[0086] Furthermore, this embodiment can utilize a cross-compilation toolchain to encapsulate dedicated instructions supported by the hardware acceleration unit (such as sm4_enc and sm4_round) into inline functions or assembly wrapper functions during the compilation phase, generating low-level interfaces that can be called by high-level languages. These functions are directly mapped to their corresponding machine code after compilation, without introducing function call overhead or stack frame operations. This makes software-level calls equivalent to direct hardware instruction issuance, facilitating transparent invocation of cryptographic operation instructions in high-level language environments, eliminating intermediate layer scheduling delays, and fully integrating the triggering of encryption operations into the program control flow.

[0087] Optionally, before loading plaintext data into a designated general-purpose register set in the core processor, the method further includes: initializing an extended key array for the encryption algorithm; locking the initialized extended key array in the key storage area of ​​a first data cache using a specified function, wherein the extended key array locked in the first data cache includes multiple sets of extended key data; and configuring the address of the key register of the hardware acceleration unit according to the cache bit width of the first data cache.

[0088] In this embodiment, during system startup or encryption task preparation, a one-time key expansion operation is performed by the core processor according to the key scheduling rules of the SM algorithm. For example, for the SM4 algorithm, 32 sets of 32-bit round key sequences can be generated and stored in a memory buffer in a fixed byte order. This initialization process is independent of the encryption execution flow and is triggered only during the first call or key change. This helps to decouple the highly complex key derivation operation from the real-time encryption path, allowing subsequent encryption operations to rely only on pre-computed key data, thus reducing computational load fluctuations during the encryption process.

[0089] Furthermore, this embodiment uses a cache locking instruction (such as Cache Lock / Pin) to migrate the initialized extended key array from main memory to a specified physical region of the first data cache. This ensures that the key data always resides in the cache throughout the entire encryption task cycle, avoiding access loss due to cache replacement strategies. This helps to achieve deterministic access latency for key data and ensures that the hardware acceleration unit can obtain a high-speed supply with zero waiting time when calling the key in any round.

[0090] Furthermore, in this embodiment, based on the row size, group-associative structure, and address mapping rules of the first data cache, the physical address range of the extended key array in the cache is calculated, and this address range is written into the key source address register of the hardware acceleration unit. This configuration process is completed during the initialization phase, ensuring that the controller can directly locate the locked area within the cache when transmitting the key, without the need for dynamic software addressing. This facilitates direct hardware-to-hardware transmission of key data from the cache to the acceleration unit, eliminates address translation overhead, and allows the key loading path to be completely controlled by hardware, improving the determinism and efficiency of data transfer.

[0091] The following describes in detail another optional implementation method.

[0092] This invention aims to address the technical problems of low computational efficiency, high memory access latency, and high power consumption in the implementation of the SM algorithm on processor architectures (this invention uses the CSKY architecture as an example). This invention accelerates the SM algorithm through a four-step optimization process: hardware adaptation design, instruction optimization, memory layout optimization, and hardware resource allocation. It leverages the characteristics of the processor architecture's registers, dedicated instructions, cache, and hardware acceleration units through a combination of hardware and software optimization. This invention proposes a systematic, multi-layered optimization method that breaks away from the conventional thinking of "general software porting," starting from the hardware characteristics of the processor architecture and performing top-down algorithm reconstruction and adaptation.

[0093] In this embodiment of the invention, taking SM4 on CK860 as an example, the hardware adaptation design, focusing on "software-hardware collaboration" and "bottlenecks elimination," eliminates memory transfer overhead through register remapping (mapping the input parameters and round keys of SM4 to the r0-r4 registers of CK860) and hardware acceleration unit calls (calling hardware acceleration instructions through inline assembly or driver functions). It replaces the traditional software loop with dedicated instructions (such as sm4_round), reducing the number of instructions from 256 to 32 and the number of cycles from 256 to 32, achieving extremely low overhead hardware acceleration. "Memory layout optimization" is crucial for system-level performance. The extended key array is locked in the L1 cache (corresponding to the first data cache mentioned above), and a DMA-driven data pipeline is introduced. During this process, CPU computing resources are released, allowing the CPU to process other tasks in parallel, achieving overlap between computation and data transfer, maximizing system efficiency. Hardware resource coordination involves calling the hardware acceleration unit (illustrated in this embodiment as the Crypto unit) for SM4 encryption, transferring data via DMA to reduce CPU load, and notifying the CPU via an interrupt after computation is complete. Ultimately, the entire system forms a highly efficient collaborative model of "CPU (control and scheduling) + DMA controller (data pipeline) + Crypto unit (hardware acceleration)". The CPU acts as an intelligent controller, the DMA as an efficient data transfer agent, and the Crypto unit as a dedicated computing engine. The three perform their respective functions in parallel without conflict, together forming a highly efficient execution architecture with pipelined parallelism and hardware acceleration, thereby achieving dual optimization of computing performance and energy efficiency at the system level.

[0094] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, taking the encryption operation of the SM4 block cipher algorithm on the CSKY CK860 processor as an example. Figure 3 This is a flowchart illustrating an accelerated optimization of the SM algorithm based on the CSKY architecture according to an embodiment of the present invention, such as... Figure 3As shown, the optimization process includes: inputting plaintext / data to be encrypted; the algorithm module determining which encryption algorithm is used (e.g., using SM4 for encryption / decryption, SM2 for signature / verification, or SM3 for hash calculation); hardware adaptation design – precise register mapping + hardware instruction calls, eliminating memory transfer overhead; instruction-level optimization – identifying core loops and replacing software loops with dedicated instructions (87.5% efficiency improvement), zero-overhead hardware acceleration calls; memory layout optimization – cache locking (preloading high-frequency data such as keys into the L1 cache) + DMA pipeline parallelism (configuring DMA and building a DMA-driven data pipeline), freeing up CPU computing resources; hardware resource collaborative calls – sending the data to be encrypted to the Crypto unit via DMA, with the CPU and DMA / Crypto working in parallel to obtain hardware-accelerated results; system effects – dual optimization of performance and energy consumption, ensuring data access efficiency. Finally, outputting the ciphertext / result encrypted with the high-performance, low-energy SM algorithm.

[0095] Figure 4 This is a schematic diagram illustrating the connection between the Crypto unit and the SM4 algorithm module in an optional CSKY architecture according to an embodiment of the present invention, as shown below. Figure 4 As shown, the CSKY CK860 chip displays the connections and data flow between the SM4 algorithm module, Crypto unit, DMA controller, cache, and register group.

[0096] like Figure 4 As shown, the CSKY architecture includes: a memory hierarchy (including main memory, L1 cache (32kb) and L2 cache (256kb)), a dedicated hardware acceleration unit (including a round function processing unit, Crypto engine and key expansion module), a DMA controller and a CPU core processing unit (including register sets r0-r15, instruction decoder and ALU arithmetic unit).

[0097] Combination Figure 4 The following explains the data flow of each module in the CSKY architecture, specifically including:

[0098] Step a. The extended key array is locked in the L1 data cache.

[0099] Step b. The DMA controller reads the extended key from the L1 data cache and transfers it to the key register of the Crypto unit.

[0100] Step c. Plaintext data is loaded into registers r0-r3 by the CPU core, and then sent to the Crypto unit by a special instruction (such as sm4_enc).

[0101] Step d. The Crypto unit performs the encryption operation and outputs the ciphertext data to register r0.

[0102] Step e. The encrypted data is written back to the L1 data cache or memory.

[0103] The following describes the implementation process and steps of the technical solution of this invention, using a specific CSKY architecture model (such as CSKY CK803, CK860), a specific SM algorithm module (such as SM2 signature, SM4 encryption), and specific optimization parameters:

[0104] Step 1), prepare the hardware and software environment (taking SM4 on CK860 as an example).

[0105] Hardware environment: Specify the specific parameters of the CSKY architecture, such as "based on the CSKY CK860 architecture chip, which includes a 32-bit register group, L1 data cache (32KB), L2 cache (256KB), dedicated Crypto hardware acceleration unit (supporting SM4 / SM3 algorithm acceleration), and DMA controller".

[0106] Software environment: such as "the compilation tool is CSKY GNU Compiler Collection (csky-gcc 9.3.0), and the operating system is an embedded system, etc."

[0107] Step 2), hardware adaptation design (taking SM4 on CK860 as an example), accurately matches the high-level logic of the algorithm with the underlying hardware resources.

[0108] The register remapping process includes: analyzing the 32-bit input-output characteristics of the SM4 round function F(Xi,Ki), accurately mapping its four 32-bit input parameters (Xi,Xi+1,Xi+2,Xi+3) and round key Ki to the CK860's general-purpose registers r0-r4, and directly writing the output back to the first register r0. Compared to the frequent parameter passing via the memory stack in general-purpose implementations, this eliminates the frequent memory overflows in general-purpose implementations. Reduce register data transfer overhead and minimize parameter interaction latency.

[0109] Seamless Hardware Acceleration Unit Invocation: Beyond simply enabling the Crypto hardware acceleration unit, the key aspect is defining a hardware / software interface protocol and designing a zero-overhead hardware / software invocation interface. For example, by writing inline assembly or low-level driver functions to encapsulate the calls to the sm4_enc r0,r1 instructions, and then calling this interface function in a high-level language (such as C), the compiler can directly generate the corresponding machine instructions, enabling high-level languages ​​(such as C) to invoke hardware acceleration functions seamlessly and with zero overhead.

[0110] Step 3) Instruction optimization (quantization comparison): Use the dedicated instructions provided by the architecture to "harden" the core computation of the algorithm.

[0111] Traditional implementation (software loop): Number of instructions, 32 rounds × (8 instructions / round for loading data, XOR, S-box lookup, linear transformation, storing results, etc.) ≈ 256 instructions.

[0112] Clock cycle: Assuming 1 cycle per instruction, at least 256 clock cycles are required (excluding jump and memory latency).

[0113] Optimized implementation of the present invention (dedicated instructions): Dedicated instructions replace software loops.

[0114] Number of instructions: 32 rounds × 1 instruction, sm4_round instruction = 32 instructions.

[0115] Clock cycle: Ideally, only 32 clock cycles are required.

[0116] Optimization results: Instruction count reduced by 87.5%, core operation cycle reduced by 87.5%.

[0117] Step 4) Memory layout optimization (system-level optimization) to resolve data supply bottlenecks and ensure that computing units can continuously obtain high-speed data streams.

[0118] Cache-friendly data structure: After initialization, the 128-bit extended key array (rk

[32] ) of SM4 is locked (Lock / Pin) in a specific area of ​​the L1 data cache using a dedicated function (such as memcpy with cache operation instructions). This prevents the critical data from being swapped out by ordinary data and ensures an access hit rate of >90%.

[0119] DMA-driven asynchronous data pipeline: Traditional path, CPU loads key → CPU transfers to Crypto unit, which involves CPU usage and access latency. Figure 5 This is a schematic diagram illustrating the collaborative operation of various components in an optional processor architecture according to an embodiment of the present invention, such as... Figure 5 As shown, the system comprises three main parts: a computing unit, a control and data transfer unit, and a memory subsystem. The invention's process is as follows: the CPU pre-places the key in the L1 cache → configures the DMA source address (L1 cache key area) and target address (Crypto unit key register) → triggers DMA transfer to the Crypto unit. During this process, the CPU can perform other preparatory work. To further free up the CPU and allow overlapping operations, this invention introduces a direct memory access controller for data transfer, achieving overlap between computation and data transfer, thus maximizing system efficiency.

[0120] Optionally, the SM algorithm acceleration optimization path based on the CSKY architecture of this invention includes:

[0121] Sub-step 1. CPU initialization: Lock the key in the L1 cache and place the data to be encrypted in memory.

[0122] Sub-step 2. CPU configure DMA: Set the source address (key in L1 cache or data block in memory) and the target address (data input register of Crypto unit).

[0123] Sub-step 3. The CPU triggers a DMA transfer and immediately returns to perform other tasks (such as preparing the next data block).

[0124] Sub-step 4. The DMA controller independently and efficiently completes the data transfer to the Crypto unit.

[0125] Sub-step 5. Once the Crypto unit completes its calculation, it notifies the CPU via an interrupt.

[0126] Advantages: This design achieves parallelization of computation (Crypto unit) and data transfer (DMA), freeing the CPU from tedious I / O operations and greatly improving the overall system throughput and efficiency.

[0127] Step 5) Coordinated use of hardware resources.

[0128] Combining the above steps, a highly efficient collaborative process is achieved at runtime: the CPU acts as the controller and task scheduler, the DMA acts as an efficient data transporter, and the Crypto hardware acceleration unit acts as the core computing engine. The parallel operation of these three components transforms the SM4 encryption operation from the traditional "CPU serial execution" mode to a highly efficient "pipeline parallel, hardware accelerated" mode.

[0129] This invention is applicable to different CSKY architecture processors (such as CK803 and CK860) and different SM algorithms (such as SM2, SM3, and SM4). During implementation, it is necessary to determine the specific chip's datasheet, register file, cache configuration, whether it integrates a Crypto unit, and the specific instructions it supports. The register mapping scheme, cache lock size, and DMA transfer configuration parameters should be adjusted accordingly. In terms of software implementation, a corresponding cross-compilation toolchain (such as csky-gcc) should be used for compilation, and the invention should be able to run in an operating system or bare-metal environment.

[0130] Through the above embodiments, this invention achieves significant advantages over existing "general software porting" technologies. By employing hardware adaptation design, instruction-level optimization, memory subsystem reconstruction, and heterogeneous resource collaborative scheduling, it achieves full-stack acceleration of the SM algorithm on the CSKY architecture. Specifically, this invention can improve computing performance. For example, the number of instructions for SM4 encryption operations is reduced from approximately 256 in traditional software implementations to 32 dedicated instructions, resulting in an 87.5% reduction in core operation cycles. On the CSKY CK860 platform, the encryption time for 1GB of data is shortened from 11.2 seconds to 5.6 seconds, significantly improving computational efficiency.

[0131] Furthermore, this invention can reduce memory access latency. The extended key array is locked in the L1 data cache, increasing the cache hit rate from 50% to over 90%. The key and plaintext data are directly connected to the hardware acceleration unit via DMA, avoiding main memory access and reducing memory access latency by 40%–60%. Simultaneously, this invention can reduce system power consumption. Due to the shortened computation cycle and the hardware acceleration unit replacing the general-purpose CPU to perform intensive computations, the power consumption per KB of encrypted data is reduced from 5mJ to 3.2–3.8mJ, resulting in an overall power consumption reduction of 25%–35%. In addition, this invention can reduce CPU utilization. Data transfer is independently completed by the DMA controller, and encryption operations are autonomously executed by the hardware acceleration engine. The core processor only participates in task initiation and interrupt response, significantly reducing CPU utilization and freeing up computing power for parallel task processing.

[0132] Furthermore, this invention can enhance execution time stability, replace software loops with hardware pipelines, eliminate cycle jitter caused by branch prediction failures and cache misses, significantly reduce computation time jitter, and meet the deterministic requirements of demanding real-time scenarios such as industrial control.

[0133] Scalable and adaptable architecture: By parsing CSKY chip parameters, binding algorithm features and compiling dedicated instruction interfaces, a standardized optimization template is formed, which can be adapted to different processors such as CK803 and CK860 and other national cryptographic algorithms such as SM2 and SM3, supporting cross-platform reuse.

[0134] According to another aspect of the present invention, an embedded device is also provided, which runs an embedded processor architecture of a domestically produced reduced instruction set computer, including: a memory hierarchy including: main memory, a first data cache and a second data cache, wherein the main memory is used to provide a cache area and the first data cache is used to store an extended key array; a hardware acceleration unit including at least: a hardware acceleration engine, a key expansion module and an algorithm module, used to perform encryption operations on received plaintext data based on the extended key data, and to interrupt and notify a designated general-purpose register group in the core processor of the encrypted ciphertext data; a core processor including at least: a register group and an instruction decoder, used to preload the extended key data and transmit the plaintext data and dedicated instructions to the hardware acceleration unit; and a direct memory controller used to execute the data encryption method based on the target processor architecture of any one of the above.

[0135] This embodiment adopts a multi-level caching architecture. The main memory serves as the final storage medium for system data, carrying the data blocks to be encrypted, the initial key, and intermediate state buffers. The first data cache can be understood as an L1-level data cache, whose capacity and access latency are adapted to the real-time requirements of the CSKY architecture. It is used to hold the extended key array of the SM algorithm and prevents it from being replaced by other data through a cache locking mechanism. The second data cache serves as an L2 cache, used to temporarily store large-scale plaintext data or intermediate outputs, forming a transition buffer between cache levels. This helps to achieve high-frequency, low-latency access to key data, supports continuous and stable reading of keys by hardware acceleration units, and avoids pipeline stalls caused by cache misses.

[0136] The hardware acceleration unit in this embodiment integrates a dedicated encryption engine, containing a round function operation circuit, an S-box lookup network, and a linear transformation logic module that matches the SM4 algorithm, supporting a single-cycle completion of one round of encryption operation. The key expansion module is a read-only register set used to receive pre-computed key data transmitted by DMA and distribute it to the input port of the algorithm module. After receiving the plaintext data and key, the algorithm module starts the encryption pipeline. After the operation is completed, the interrupt controller of the core processor is triggered through a hardware interrupt signal. The ciphertext result is directly written to the designated general-purpose register set without software intervention, which helps to realize the complete hardware execution of encryption operations, eliminates software polling overhead, and improves the determinism and response speed of the operation.

[0137] The core processor in this embodiment can adopt a 32-bit general-purpose register set based on the CSKY architecture, such as... Figure 4As shown in the diagram, r0–r4 are designated for plaintext input, intermediate state transmission, and result output. The instruction decoder identifies and parses dedicated encryption instructions (such as sm4_enc) encapsulated in a high-level language, translating them into control signals recognizable by the hardware acceleration unit. Before the encryption task starts, the core processor directly loads plaintext data through registers and triggers the hardware acceleration unit by calling dedicated instructions through inline assembly, completing a seamless switch from software control to hardware execution. This helps to achieve transparent embedding of encryption instructions in the program flow, reduces the jump overhead of the control path, and enables high coordination between encryption operations and the main logic flow.

[0138] The direct memory controller in this embodiment has independent channel and address mapping capabilities, which are used to complete the operation of transferring the extended key from the first data cache to the hardware acceleration unit key register, transferring plaintext data from main memory to the encryption engine input register, and writing the encryption result back from the output register to the first data cache or main memory without the intervention of the core processor. The source address and target address of the DMA controller are configured by the core processor during the task initialization phase, and the transfer is triggered by a dedicated instruction or event signal. The whole process does not occupy the core processor cycle, which helps to realize the parallelization of computation and data transfer, freeing up the core processor for task scheduling and context switching, and improving the overall concurrency capability of the system.

[0139] The aforementioned embedded device plane can construct a complete data flow closed loop of "key cache locking - transparent instruction triggering - autonomous data transfer - result interruption feedback" through the collaborative design of memory hierarchy, hardware acceleration unit, core processor and direct memory controller. This helps to eliminate latency fluctuations and resource contention caused by software participation, and can realize high-performance, low-power, and highly deterministic execution of the SM algorithm in resource-constrained environments. This allows the system to achieve hardware-native cryptographic computing capabilities while maintaining compatibility with domestic architecture.

[0140] The following is a detailed description with reference to another embodiment.

[0141] Example 2

[0142] The data encryption device based on the target processor architecture provided in this embodiment includes multiple implementation units, each of which corresponds to a specific implementation step in the above embodiment one. The specific implementation method and beneficial effects can be referred to the foregoing method embodiment, and will not be repeated here.

[0143] According to another aspect of the present invention, a data encryption device based on a target processor architecture is also provided, which is applied to a controller in the target processor architecture. The target processor architecture includes: an embedded processor architecture running on a domestically produced reduced instruction set computer, and the target processor architecture includes at least: a controller, a hardware acceleration unit, and a core processor.

[0144] Figure 6 This is a schematic diagram of an optional data encryption device based on a target processor architecture according to an embodiment of the present invention, such as... Figure 6 As shown, the data encryption device based on the target processor architecture may include: a data transmission unit 61, a key mapping unit 62, and a data encryption unit 63.

[0145] The data transmission unit 61 is used to receive plaintext data to be encrypted and asynchronously transmit the plaintext data to the hardware acceleration unit.

[0146] The key mapping unit 62 is used to read the extended key data in the first data buffer according to the encryption algorithm type, and map the extended key data to the key register of the hardware acceleration unit.

[0147] The data encryption unit 63 is used to control the hardware acceleration unit to perform encryption operations on plaintext data based on the extended key data, and to interrupt the notification of the encrypted ciphertext data to a designated general-purpose register group in the core processor.

[0148] The aforementioned data encryption device based on the target processor architecture can receive plaintext data to be encrypted through the data transmission unit 61 and asynchronously transmit the plaintext data to the hardware acceleration unit. The key mapping unit 62 reads extended key data from the first data cache according to the encryption algorithm type and maps the extended key data to the key register of the hardware acceleration unit. The data encryption unit 63, based on the extended key data, controls the hardware acceleration unit to perform encryption operations on the plaintext data and sends the encrypted ciphertext data to a designated general-purpose register group in the core processor. In this embodiment, the key required by the encryption algorithm and the plaintext data to be encrypted can be directly mapped to the hardware acceleration unit. The encryption operation is then performed by the hardware acceleration unit in the target processor architecture, and the operation result is directly written back to the register group. This hardware acceleration unit has the ability to complete one round of encryption in a single cycle. Compared to traditional software, which suffers from path latency due to frequent parameter exchange and transfer between memory and registers and memory access delays, this significantly improves system efficiency, thus solving the technical problem of low execution efficiency when implementing encryption algorithms on processor architectures in related technologies.

[0149] Optionally, the data transmission unit includes: a data loading module for loading plaintext data into a designated general-purpose register group in the core processor; and a data transmission module for asynchronously transmitting plaintext data from the designated general-purpose register group to the hardware acceleration unit via dedicated instructions.

[0150] Optionally, the data encryption device based on the target processor architecture further includes: a processor architecture parsing unit, used to parse the architecture parameters of the currently running target processor architecture before loading plaintext data into a specified general-purpose register group in the core processor, to obtain the parameters of the specified general-purpose register group, the cache bit length of the first data cache, the cache bit length of the second data cache, the encryption algorithm type supported by the hardware acceleration unit, and the controller type; an encryption algorithm feature determination unit, used to determine the input and output features of the encryption algorithm based on the encryption algorithm type supported by the hardware acceleration unit, wherein the input and output features are used to determine the bit length of the extended key data, the bit length of the plaintext data to be encrypted, and the bit length of the ciphertext data output after encryption; and an instruction encapsulation unit, used to compile the underlying driver functions and encapsulate multiple dedicated instructions into the core processing unit.

[0151] Optionally, the data encryption device based on the target processor architecture further includes: an initialization unit, used to initialize the extended key array of the encryption algorithm before loading plaintext data into a specified general-purpose register group in the core processor; a key locking unit, used to lock the initialized extended key array in the key storage area of ​​the first data cache using a specified function, wherein the extended key array locked in the first data cache includes multiple sets of extended key data; and an address configuration unit, used to configure the address of the key register of the hardware acceleration unit according to the cache bit width of the first data cache.

[0152] Optionally, the data encryption device based on the target processor architecture further includes: a write-back unit, used to write back the encrypted ciphertext data to the first data cache after controlling the hardware acceleration unit to perform encryption operations on the plaintext data based on the extended key data; or, to write back the encrypted ciphertext data to the main memory.

[0153] Optionally, the core processor includes: a register set, comprising multiple registers, wherein a first register among the multiple registers is used to store the encrypted ciphertext data; an instruction decoder, used to extract pre-configured special instructions based on the plaintext data to be encrypted, and send the special instructions to the hardware acceleration unit; and an arithmetic logic unit, used to perform basic arithmetic and logical operations of the encryption algorithm.

[0154] Optionally, the hardware acceleration unit includes: a hardware acceleration engine for performing encryption operations on plaintext data based on extended key data; a key expansion module for determining multiple sets of extended key data based on the algorithmic characteristics of the encryption algorithm; and an algorithm module for accelerating the execution process of the encryption algorithm.

[0155] The aforementioned data encryption device based on the target processor architecture may further include a processor and a memory. The aforementioned data transmission unit 61, key mapping unit 62, data encryption unit 63, etc., are all stored in the memory as program units, and the processor executes the aforementioned program units stored in the memory to realize the corresponding functions.

[0156] The aforementioned processor contains a kernel, which retrieves the corresponding program units from memory. One or more kernels can be configured, and the encryption algorithm optimization based on the target processor architecture can be achieved by adjusting kernel parameters.

[0157] The aforementioned memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0158] Example 3

[0159] Embodiments of this application may provide an electronic device. Figure 7 This is a structural block diagram of an electronic device that implements a data encryption method based on a target processor architecture, according to an embodiment of this application. Figure 7 As shown, the electronic device may include: one or more ( Figure 7 (Only one is shown) processor 702, memory 704, memory controller, and peripheral interface, wherein the peripheral interface is connected to the radio frequency module, audio module and display.

[0160] The memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the data encryption method and apparatus based on the target processor architecture in the embodiments of this application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby realizing the aforementioned data encryption method based on the target processor architecture. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0161] The processor can call the information and application stored in the memory through the transmission device to perform the following steps: receive plaintext data to be encrypted and asynchronously transmit the plaintext data to the hardware acceleration unit; read the extended key data in the first data cache according to the encryption algorithm type and map the extended key data to the key register of the hardware acceleration unit; control the hardware acceleration unit to perform encryption operation on the plaintext data based on the extended key data; and interrupt the notification of the encrypted ciphertext data to the designated general-purpose register group in the core processor.

[0162] Those skilled in the art will understand that Figure 7 The structure shown is for illustrative purposes only. Electronic devices can also be smartphones, tablets, handheld computers, mobile internet devices (MIDs), PADs, and other terminal devices. Figure 7 This does not limit the structure of the aforementioned electronic device. For example, electronic devices may also include components that are more... Figure 7 The more or fewer components shown (such as network interfaces, display devices, etc.), or having the same Figure 7 The different configurations shown.

[0163] Those skilled in the art will understand that all or part of the steps in the various data encryption methods based on the target processor architecture in the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0164] Example 4

[0165] Embodiments of this application also provide a storage medium. Optionally, in this embodiment, the storage medium can be used to store the program code executed by the data encryption method based on the target processor architecture provided in Embodiment 1.

[0166] According to another aspect of the present invention, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored computer program, wherein, when the computer program is running, it controls the device where the computer-readable storage medium is located to execute any of the data encryption methods based on the target processor architecture described in Embodiment 1 above.

[0167] Optionally, in this embodiment, the storage medium may be located in any computer terminal in a group of computer terminals in a computer network, or in any mobile terminal in a group of mobile terminals.

[0168] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data encryption method based on the target processor architecture described in various embodiments of this application.

[0169] This application also provides a computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the data encryption method based on the target processor architecture described in various embodiments of this application.

[0170] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0171] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0172] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0173] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0174] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0175] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0176] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A data encryption method based on a target processor architecture, characterized in that, A controller applied in the target processor architecture, the target processor architecture including: an embedded processor architecture running on a reduced instruction set computer, the target processor architecture including at least: the controller, a hardware acceleration unit, and a core processor, and a data encryption method based on the target processor architecture including: Receiving plaintext data to be encrypted and asynchronously transmitting the plaintext data to the hardware acceleration unit includes: loading the plaintext data into a designated general-purpose register group in the core processor; and asynchronously transmitting the plaintext data from the designated general-purpose register group to the hardware acceleration unit using dedicated instructions. Before loading the plaintext data into the designated general-purpose register group in the core processor, the method further includes: parsing the architecture parameters of the currently running target processor architecture to obtain the parameters of the designated general-purpose register group, the cache bit width of the first data cache, the cache bit width of the second data cache, the encryption algorithm type supported by the hardware acceleration unit, and the controller type; determining the input-output characteristics of the encryption algorithm based on the encryption algorithm type supported by the hardware acceleration unit, wherein the input-output characteristics are used to determine the bit width of the extended key data, the bit width of the plaintext data to be encrypted, and the bit width of the encrypted ciphertext data; compiling the underlying driver function and encapsulating multiple dedicated instructions into the core processor; initializing the extended key array of the encryption algorithm; locking the initialized extended key array in the key storage area of ​​the first data cache using a designated function, wherein the extended key array locked in the first data cache includes multiple sets of extended key data; and configuring the address of the key register of the hardware acceleration unit according to the cache bit width of the first data cache. Read the extended key data from the first data cache according to the encryption algorithm type, and map the extended key data to the key register of the hardware acceleration unit; Based on the extended key data, the hardware acceleration unit is controlled to perform encryption operations on the plaintext data, and the encrypted ciphertext data is interrupted to notify the designated general-purpose register group in the core processor.

2. The data encryption method according to claim 1, characterized in that, After controlling the hardware acceleration unit to perform encryption operations on the plaintext data based on the extended key data, the method further includes: Write the encrypted ciphertext data back to the first data cache; or... The encrypted ciphertext data is written back to main memory.

3. The data encryption method according to claim 1, characterized in that, The core processor includes: The register group includes multiple registers, wherein the first register among the multiple registers is used to store the encrypted ciphertext data; An instruction decoder is used to extract pre-configured special instructions based on the plaintext data to be encrypted, and send the special instructions to the hardware acceleration unit; Arithmetic logic unit (ALU) is used to perform basic arithmetic and logical operations for encryption algorithms.

4. The data encryption method according to claim 1, characterized in that, The hardware acceleration unit includes: A hardware acceleration engine is used to perform encryption operations on the plaintext data based on the extended key data; The key expansion module is used to determine multiple sets of expanded key data based on the algorithmic characteristics of the encryption algorithm; The algorithm module is used to accelerate the execution process of encryption algorithms.

5. An embedded device, characterized in that, Embedded processor architectures that run reduced instruction set computers include: The memory hierarchy includes: main memory, a first data cache, and a second data cache, wherein the main memory is used to provide a cache range, and the first data cache is used to store an extended key array; The hardware acceleration unit includes at least a hardware acceleration engine, a key expansion module, and an algorithm module, which are used to perform encryption operations on received plaintext data based on the expanded key data, and to interrupt and notify a designated general-purpose register group in the core processor of the encrypted ciphertext data. The core processor includes at least: a register set and an instruction decoder, used to preload extended key data and transmit plaintext data and special instructions to the hardware acceleration unit; A direct memory controller for executing the data encryption method based on the target processor architecture as described in any one of claims 1 to 4.

6. A data encryption device based on a target processor architecture, characterized in that, A controller applied in the target processor architecture, the target processor architecture including: an embedded processor architecture running on a reduced instruction set computer, the target processor architecture including at least: the controller, a hardware acceleration unit, and a core processor, and a data encryption device based on the target processor architecture including: A data transmission unit is used to receive plaintext data to be encrypted and asynchronously transmit the plaintext data to the hardware acceleration unit; the data transmission unit includes: a data loading module, used to load the plaintext data into a designated general-purpose register group in the core processor; and a data transmission module, used to asynchronously transmit the plaintext data from the designated general-purpose register group to the hardware acceleration unit through dedicated instructions. The data encryption device based on the target processor architecture further includes: a processor architecture parsing unit, configured to parse the architecture parameters of the currently running target processor architecture before loading the plaintext data into a designated general-purpose register group in the core processor, to obtain the parameters of the designated general-purpose register group, the cache bit length of the first data cache, the cache bit length of the second data cache, the encryption algorithm type supported by the hardware acceleration unit, and the controller type; and an encryption algorithm feature determination unit, configured to determine the input-output features of the encryption algorithm based on the encryption algorithm type supported by the hardware acceleration unit, wherein the input-output features are used to determine the bit length of the extended key data, the bit length of the plaintext data to be encrypted, and so on. The system includes: a bit depth of the encrypted ciphertext data; an instruction encapsulation unit for compiling low-level driver functions and encapsulating multiple dedicated instructions into the core processor; an initialization unit for initializing the extended key array of the encryption algorithm before loading the plaintext data into a specified general-purpose register group in the core processor; a key locking unit for locking the initialized extended key array in the key storage area of ​​the first data cache using a specified function, wherein the extended key array locked in the first data cache includes multiple sets of extended key data; and an address configuration unit for configuring the address of the key register of the hardware acceleration unit according to the cache bit depth of the first data cache. A key mapping unit is used to read extended key data from the first data cache according to the encryption algorithm type, and map the extended key data to the key register of the hardware acceleration unit; The data encryption unit is used to control the hardware acceleration unit to perform encryption operations on the plaintext data based on the extended key data, and to interrupt the notification of the encrypted ciphertext data to a designated general-purpose register group in the core processor.

7. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the data encryption method based on the target processor architecture as described in any one of claims 1 to 4.

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