A load and power consumption adjustable comparator and image sensor

Abstract

The application discloses a comparator and an image sensor with adjustable load and power consumption, and relates to the technical field of image sensors.The comparator can select between a high dynamic range and a high signal-to-noise ratio according to a gain condition.In a low gain condition, the circuit of the comparator can process a larger range of pixel signals, effectively retains a high light scene, restores a real scene as seen by the human eye, and avoids picture distortion.In a high gain condition, a higher signal-to-noise ratio can be provided, which means that the proportion of effective signals in the image is larger, and there are fewer interference signals such as noise points.Therefore, the restoration capability for dark details is stronger, and details in the dark part are prevented from being lost due to coverage by noise points.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and more specifically, to a comparator and image sensor with adjustable load and power consumption. Background Technology

[0002] Traditional SDR (Standard Dynamic Range) mode typically achieves this by reducing pixel exposure time and lowering system gain when the image sensor is capturing bright scenes. In this case, the image sensor needs a larger dynamic range to accurately reproduce bright scenes. For dark details, it is generally achieved by increasing pixel exposure time and increasing gain. Therefore, a higher signal-to-noise ratio is required in low-light conditions to prevent pixel signals from being overwhelmed by noise.

[0003] However, in traditional SDR mode, under conditions of large differences in brightness or complex lighting, the image sensor often suffers from insufficient dynamic range, resulting in overexposure in bright areas and severe noise in dark areas. Therefore, existing technologies have developed HDR (High Dynamic Range) mode, such as... Figure 1 As shown, by reading the dark and bright information separately or simultaneously, the final output image can simultaneously restore the bright and dark information in a single image. Generally, HDR effects are achieved by controlling the pixel readout method or using pixels with different sensitivities. In the pixel signal readout circuit, the comparator is a crucial module reflecting light intensity; therefore, the comparator's input range determines the sensor's dynamic range to a certain extent, playing a vital role in the final imaging effect. However, the input range of a traditional comparator is only related to its own structure and does not change with different gain conditions. In other words, the comparator does not adjust the balance between its input upper limit and signal-to-noise ratio according to the characteristics of the HDR mode, leading to distortion or loss of detail in the image sensor's imaging effect in HDR mode. Summary of the Invention

[0004] The purpose of this invention is to provide a comparator and image sensor with adjustable load and power consumption, which solves the problem that the comparators provided by the prior art do not adjust the balance between their input upper limit and signal-to-noise ratio according to the characteristics of HDR mode, resulting in the image sensor's imaging effect in HDR mode being distorted or losing details.

[0005] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0006] A first aspect of the present invention provides a comparator with adjustable load and power consumption, the comparator including a differential amplifier, the differential amplifier comprising:

[0007] The first input transistor includes a gate connected to the reference ramp signal input node;

[0008] The second input transistor includes a gate connected to the pixel voltage signal input node;

[0009] The first load transistor includes a drain connected to the drain of the first input transistor;

[0010] The fourth load transistor includes a drain connected to the drain of the second input transistor;

[0011] The second load transistor includes a drain connected to the source of the first load transistor;

[0012] The third load transistor includes the drain connected to the source of the fourth load transistor;

[0013] The first switching transistor includes a drain connected to the source of the second load transistor;

[0014] The second switching transistor includes a drain connected to the source of the third load transistor;

[0015] The third switching transistor includes a source connected to the source of the first switching transistor and a drain connected to the drain of the second load transistor.

[0016] The fourth switching transistor includes a source connected to the source of the second switching transistor and a drain connected to the drain of the third load transistor.

[0017] The fifth switching transistor includes a source connected to the source of the second load transistor and a drain connected to the drain of the first load transistor; and

[0018] The sixth switching transistor includes a source connected to the source of the third load transistor and a drain connected to the drain of the fourth load transistor.

[0019] In one implementation, the differential amplifier further includes a current adjustment circuit, the current adjustment circuit comprising:

[0020] A first current-adjusting transistor includes a drain connected to the source of a first input transistor and a second input transistor; and

[0021] The second current-adjusting transistor includes a drain connected to the source of the first input transistor and the second input transistor.

[0022] In one implementation, the comparator further includes a second-stage amplifier, which includes:

[0023] The fifth load transistor includes a gate connected to the drain of the second input transistor;

[0024] The sixth load transistor includes a gate connected to the drain of the second input transistor and a drain connected to the source of the fifth load transistor;

[0025] The seventh switching transistor includes a drain connected to the source of the sixth load transistor;

[0026] The eighth switching transistor includes a drain connected to the drain of the fifth load transistor and a source connected to the source of the sixth load transistor.

[0027] The ninth switching transistor includes a source connected to the source of the seventh switching transistor and a drain connected to the drain of the sixth load transistor; and

[0028] The third input transistor includes a drain connected to the drain of the fifth load transistor.

[0029] In one implementation, the comparator further includes an inverter, the inverter comprising:

[0030] The seventh load transistor includes a drain connected to the signal output node and a gate connected to the drain of the fifth load transistor; and

[0031] The eighth load transistor includes a drain connected to the signal output node and a gate connected to the drain of the fifth load transistor.

[0032] In one implementation, the comparator is configured to operate between high dynamic range and high signal-to-noise ratio based on a gain condition;

[0033] Wherein, when the gain condition is a low gain condition, the third, fourth, fifth and sixth switching transistors are turned on, and the first switching transistor and the second shift transistor are turned off, so that the first load transistor and the second load transistor are connected in parallel, and the third load transistor and the fourth load transistor are connected in parallel.

[0034] The seventh switching transistor is turned off, and the eighth and ninth switching transistors are turned on, so that the fifth load transistor is connected in parallel with the sixth load transistor.

[0035] In one implementation, the first current-adjusting transistor is turned on, and the second current-adjusting transistor is turned off.

[0036] In one implementation, the comparator is configured to operate between high dynamic range and high signal-to-noise ratio based on a gain condition;

[0037] When the gain condition is a high gain condition, the third, fourth, fifth, and sixth switching transistors are turned off, and the first and second shift transistors are turned on, so that the first load transistor and the second load transistor are connected in series, the third load transistor and the fourth load transistor are connected in series, and both the first and second current adjustment transistors are turned on.

[0038] The seventh switching transistor is turned on, and the eighth and ninth switching transistors are turned off, so that the fifth load transistor is connected in series with the sixth load transistor.

[0039] In one implementation, the first current-adjusting transistor is turned on, and the second current-adjusting transistor is turned on.

[0040] In one implementation, the comparator further includes:

[0041] The first zero-adjustment switch can connect the reference ramp signal input node to the drain of the first input transistor;

[0042] The second zero-adjustment switch can connect the pixel voltage signal input node to the drain of the second input transistor; and

[0043] The third zero-adjustment switch can connect the gate of the third input transistor to the drain.

[0044] A second aspect of the present invention provides an image sensor, comprising:

[0045] A pixel array is configured to output pixel signals;

[0046] The pixel driver module is configured to control the movement of the pixel array;

[0047] The load current source module is configured to process the pixel signals output by the pixel array to generate pixel voltage signals;

[0048] A ramp generator is configured to generate a reference ramp signal;

[0049] As provided in the first aspect of the invention, a comparator with adjustable load and power consumption is configured to compare a pixel voltage signal and a reference ramp signal under different gain conditions and generate different output signals based on the comparison results.

[0050] A counter is configured to count different output signals to obtain a counting result; and

[0051] The signal processing module is configured to perform digital processing on the counting results and output image data.

[0052] Compared with the prior art, the present invention has the following beneficial effects:

[0053] 1. The comparator with adjustable load and power consumption provided by this invention, compared to the fixed input range of traditional comparators, can select between high dynamic range and high signal-to-noise ratio based on gain conditions. Under low gain conditions, the comparator circuit can process a wider range of pixel signals, effectively preserving highlight scenes, restoring the realistic scene seen by the human eye, and avoiding image distortion. Under high gain conditions, it can provide a higher signal-to-noise ratio, which means a larger proportion of effective signal in the image and less noise and other interference signals. Therefore, it has a stronger ability to restore details in dark areas, avoiding the loss of details in dark areas due to noise coverage.

[0054] 2. The comparator with adjustable load and power consumption provided by the present invention can also dynamically adjust the size of the tail current according to different gain conditions, thereby reducing the power consumption of the comparator. Attached Figure Description

[0055] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0056] Figure 1 A schematic diagram of the SDR mode provided for existing technology;

[0057] Figure 2 A schematic diagram of a comparator with adjustable load and power consumption provided in an embodiment of the present invention;

[0058] Figure 3 This is a schematic diagram of a multi-exposure HDR mode provided in an embodiment of the present invention;

[0059] Figure 4 This is a timing diagram of the signal control of the comparator in HDR mode provided in an embodiment of the present invention;

[0060] Figure 5 This is a schematic diagram illustrating a comparator-based HDR mode for multiple exposures, provided in an embodiment of the present invention.

[0061] Figure 6 This is a schematic diagram of a comparator with a dual-input structure in DCG-HDR mode provided by an embodiment of the present invention;

[0062] Figure 7 The signal control timing diagram of the comparator with a dual-input structure in DCG-HDR mode provided in the embodiments of the present invention;

[0063] Figure 8 This is a schematic diagram of the structure of an image sensor provided in an embodiment of the present invention.

[0064] Figure labels and descriptions:

[0065] MN_RAMP, First Input Transistor; MN_Vpix, Second Input Transistor; MP1, First Load Transistor; MP2, Second Load Transistor; MP3, Third Load Transistor; MP4, Fourth Load Transistor; MP5, First Switch Transistor; MP6, Second Switch Transistor; MP7, Third Switch Transistor; MP8, Fifth Switch Transistor; MP9, Fourth Switch Transistor; MP10, Sixth Switch Transistor; TAILSW_0, First Current Adjustment Transistor; TAILSW_1, Second Current Adjustment Transistor; MP11, Fifth Load Transistor; MP13, Sixth Load Transistor; MP14, Seventh Switch Transistor; MP12, Eighth Switch Transistor; MP15, Ninth Switch Transistor; MN_1, Third Input Transistor; MP16, Seventh Load Transistor; MN_2, Eighth Load Transistor; MP_RST_0, First Zero Switch; MP_RST_1, Second Zero Switch; MN_RST, Third Zero Switch. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0067] It should be noted that the terms "comprising" or "may include" used in the various embodiments of this application indicate the presence of the claimed function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in the various embodiments of this application, the terms "comprising," "having," and their cognates are intended only to indicate a specific feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or adding one or more combinations of the foregoing.

[0068] It should be understood that terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0069] Image sensors can be mounted on electronic devices that have image or light sensing capabilities. For example, image sensors can be mounted on electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, tablet PCs, personal digital assistants (PDAs), portable multimedia players (PMPs), or navigation devices. Furthermore, image sensors can be mounted as components in electronic devices included in vehicles, furniture, manufacturing equipment, doors, or various measuring instruments.

[0070] Figure 8 This is a schematic diagram of the structure of an image sensor provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the image sensor includes: a pixel array configured to output pixel signals; a pixel driving module configured to control the operation of the pixel array; a load current source module configured to process the pixel signals output by the pixel array to generate pixel voltage signals; a ramp generator configured to generate a reference ramp signal; a load and power adjustable comparator configured to compare the pixel voltage signal and the reference ramp signal under different gain conditions and generate different output signals based on the comparison results; a counter configured to count different output signals to obtain counting results; and a signal processing module configured to digitally process the counting results and output image data.

[0071] Specifically, the pixel array includes multiple pixels connected to multiple row lines and multiple column lines and arranged in a matrix. Each pixel includes a light-sensing element. For example, the light-sensing element may include a photodiode, phototransistor, photogate, pinned photodiode, etc. Each pixel may include at least one light-sensing element, and in embodiments, each pixel may include multiple light-sensing elements. Pixels can sense light using the light-sensing elements and convert the sensed light into pixel signals as electrical signals. Pixel signals may include reset signals generated according to reset operations of individual pixels and image signals generated according to light-sensing operations of individual pixels. Each pixel can sense light in a specific spectral band. For example, a pixel may include a red pixel that converts light in the red spectral band into an electrical signal, a green pixel that converts light in the green spectral band into an electrical signal, and a blue pixel that converts light in the blue spectral band into an electrical signal. Color filters for transmitting light in specific spectral bands may be arranged above the pixels respectively.

[0072] A ramp generator can generate a reference ramp signal in response to a ramp control signal. The ramp control signal may include a ramp enable signal, a mode signal, etc. When the ramp enable signal is activated, the ramp generator can generate a ramp signal with a gradient set based on the mode signal. For example, the ramp generator can generate a reference ramp signal with a specific gradient and a downward slope.

[0073] There can be multiple counters, each connected to the output node of a comparator, and each counter can perform counting based on the output signal of its respective comparator. Counter control signals may include a counter clock signal, a counter reset signal controlling the reset operation of the counter, and an inverting signal that inverts the internal bits of each counter. The counter counts the comparison result signal according to the counter clock signal and outputs the counted comparison result signal as a digital signal. For example, the counter may include an up / down counter, a bit-by-bit inverting counter, etc. In this case, the bit-by-bit inverting counter can perform operations similar to the up / down counter. For example, a bit-by-bit inverting counter can perform only up counting and invert all bits of the counter when a certain signal is input, changing the bit to its two's complement of 1. A bit-by-bit inverting counter can perform a reset count and invert it to change the reset count to its two's complement of 1, i.e., a negative value.

[0074] Finally, the signal processing module performs digital signal processing steps such as noise reduction, white balance, and color correction on the output counting result of the counter (the counting result is a digital signal), which can improve the image quality of the final output data image.

[0075] Currently, comparators generally consist of a differential amplifier, a second-stage amplifier, and an inverter. The difference between the load- and power-adjustable comparator provided in this invention and traditional comparators lies mainly in the differential amplifier section. Please refer to [link / reference needed]. Figure 2The comparator includes a differential amplifier comprising: a first input transistor MN_RAMP, including a gate connected to a reference ramp signal input node; a second input transistor MN_Vpix, including a gate connected to a pixel voltage signal input node; a first load transistor MP1, including a drain connected to the drain of the first input transistor MN_RAMP; a fourth load transistor MP4, including a drain connected to the drain of the second input transistor MN_Vpix; a second load transistor MP2, including a drain connected to the source of the first load transistor MP1; a third load transistor MP3, including a drain connected to the source of the fourth load transistor MP4; and a first switching transistor MP5, including a switch connected to the second load transistor MP2. The first load transistor MP1 has a source and a drain; the second switching transistor MP6 includes a source and a drain connected to the source of the third load transistor MP3; the third switching transistor MP7 includes a source connected to the source of the first switching transistor MP5 and a drain connected to the drain of the second load transistor MP2; the fourth switching transistor MP9 includes a source connected to the source of the second switching transistor MP6 and a drain connected to the drain of the third load transistor MP3; the fifth switching transistor MP8 includes a source connected to the source of the second load transistor MP2 and a drain connected to the drain of the first load transistor MP1; and the sixth switching transistor MP10 includes a source connected to the source of the third load transistor MP3 and a drain connected to the drain of the fourth load transistor MP4.

[0076] like Figure 2 As shown, the reference ramp signal can be transmitted to the comparator's reference ramp signal input node RAMP as the first input signal, and the pixel voltage signal can be transmitted to the comparator's pixel voltage signal input node Vpix as the second input signal. The comparator can compare the reference ramp signal transmitted through capacitor C_RAMP and the pixel voltage signal transmitted through capacitor C_PIX, and can output the comparison result as the output signal. Since the comparison process is common knowledge well known to those skilled in the art, this embodiment will not provide further description of the comparator's comparison process.

[0077] In traditional SDR (Standard Dynamic Range) mode, when image sensors capture bright scenes, this is typically achieved by reducing pixel exposure time and lowering system gain. In this case, the image sensor needs a wider dynamic range to accurately reproduce bright scenes. For dark details, this is generally achieved by increasing pixel exposure time and increasing gain. Therefore, a higher signal-to-noise ratio is required in low-light conditions to prevent pixel signals from being overwhelmed by noise.

[0078] However, in traditional SDR mode, under conditions of large differences in brightness or complex lighting, the image sensor often suffers from insufficient dynamic range, resulting in overexposure in bright areas and severe noise in dark areas. Therefore, existing technologies have developed HDR (High Dynamic Range) mode, such as... Figure 1 As shown, by reading the dark and bright information separately or simultaneously, the final output image can simultaneously restore the bright and dark information in a single image. Generally, HDR effects are achieved by controlling the pixel readout method or using pixels with different sensitivities. In the pixel signal readout circuit, the comparator is a crucial module reflecting light intensity; therefore, the comparator's input range determines the sensor's dynamic range to a certain extent, playing a vital role in the final imaging effect. However, the input range of a traditional comparator is only related to its own structure and does not change with different gain conditions. In other words, the comparator does not adjust the balance between its input upper limit and signal-to-noise ratio according to the gain characteristics of the HDR mode, which can lead to distortion or loss of detail in the image sensor's imaging effect in HDR mode.

[0079] To address the technical shortcomings of the image sensor described above, embodiments of the present invention provide an image sensor including a comparator with adjustable load and power consumption. For HDR mode, under low gain conditions, this comparator provides a wider input range for pixel readout, thus mitigating image distortion caused by overexposure in bright areas. Under high gain conditions, it reduces noise, improves the signal-to-noise ratio, and mitigates image detail loss due to noise in dark areas.

[0080] In HDR mode, by changing the load MOS of the differential amplifier of the comparator ( Figure 2 The connection method of P-type transistors MP1, MP2, MP3 and MP4 in the PMOS is used to change the equivalent transconductance Gmp and load impedance of the load PMOS. The tail current of the differential pair is adjusted through the TAIL_ADJ signal to achieve a larger input range, that is, a larger range of pixel signal processing, while reducing circuit power consumption and better noise suppression. This can significantly improve the imaging effect of HDR mode while reducing the power consumption of the image sensor.

[0081] Specifically, when shooting in bright environments, if the image sensor gain condition is low (or during short exposure), then SWB / C=Low and SWA=High are controlled. The third switching transistor MP7, the fourth switching transistor MP9, the fifth switching transistor MP8, and the sixth switching transistor MP10 of the differential amplifier are turned on, while the first switching transistor MP5 and the second shift transistor are turned off. This causes the first load transistor MP1 and the second load transistor MP2 to be connected in parallel, and the third load transistor MP3 and the fourth load transistor MP4 to be connected in parallel. Furthermore, the seventh switching transistor MP14 of the second-stage amplifier is turned off, while the eighth switching transistor MP12 and the ninth switching transistor MP15 are turned on, causing the fifth load transistor MP11 and the sixth load transistor MP13 to be connected in parallel.

[0082] Based on the on / off control described above, the total load impedance of the differential amplifier is reduced, the tail current of the differential amplifier is decreased, the load voltage division is reduced, and the comparator input range is increased. This increases the range of pixel signals that can be processed while reducing power consumption. However, the aspect ratio of the load transistor increases, the equivalent transconductance Gm increases, and the noise generated by the comparator also increases. But under low-gain conditions, the pixel voltage amplitude is larger, resulting in a high system signal-to-noise ratio. When shooting in bright environments, the image has higher requirements for dynamic range, while the impact of noise on the image is negligible. Therefore, using the control method provided in this solution under low-gain conditions can effectively reduce overexposure.

[0083] Specifically, the input common-mode voltage V of the differential amplifier is calculated using the formula... ic（最大） =VDD-V gs（load） -V th1 Where VDD is the power supply voltage, V gs（load） V is the gate-source voltage of the load MOSFET above. th1 This is the threshold voltage of the MOSFET at the input of the differential amplifier. The power supply calculation formula for the saturation region transistor is (I=1 / 2*μ). p C ox Substituting (W / L)(Vgs-Vth)² into the above voltage calculation formula yields V. ic（最大） =VDD-V gs（load） -V th1 = VDD- -V th1 When the transistors in the load cell are in parallel, due to the increase in the equivalent width-to-length ratio (W / L) of the transistors in the load cell, the upper limit of the input common-mode voltage V is limited for the range of input common-mode voltage. ic（最大） This can improve the image. Therefore, when shooting images with bright areas, it can reduce the occurrence of overexposure.

[0084] In one embodiment, the differential amplifier further includes a current adjustment circuit, which includes: a first current adjustment transistor TAILSW_0, including a drain connected to the source of the first input transistor MN_RAMP and the second input transistor MN_Vpix; and a second current adjustment transistor TAILSW_1, including a drain connected to the source of the first input transistor MN_RAMP and the second input transistor MN_Vpix.

[0085] The Tail_ADJ signal adjusts the magnitude of the tail current source current in the differential amplifier. Under low gain conditions, the first current adjustment transistor (TAILSW_0) is turned on (Tail_ADJ_0 = High), and the second current adjustment transistor (TAILSW_1) is turned off (Tail_ADJ_1 = Low). This reduces the tail current of the differential amplifier, placing the comparator circuit in a low-current state. This reduces power consumption and increases the comparator's input range. Therefore, it reduces overexposure when capturing images with bright areas.

[0086] From the input common-mode voltage of the differential amplifier, we can know that V ic（最小） =V ds(tail) +V gs1 , where V ds(tail) V represents the source-drain voltage of the MOSFET in the lower current mirror. gs1 This is the gate-source voltage of the MOSFET at the input of the differential amplifier. It is calculated using the power supply formula for a saturated NMOS transistor (I = 1 / 2 * μ). n C ox (W / L)(Vgs-Vth) ² Substituting into the voltage calculation formula above, we can obtain V ic（最小） =V ds(tail) +V gs1 V ds(tail) =V ds(tail) + When the current decreases, the lower limit of the differential amplifier's input common-mode voltage is even lower. Therefore, the input common-mode voltage range of the differential amplifier is:

[0087] V ds(tail) + ≤Input Voltage≤VDD- -V th1 .

[0088] When shooting in low-light environments, if the image sensor is in high-gain condition (or under long exposure), the third switching transistor MP7, the fourth switching transistor MP9, the fifth switching transistor MP8, and the sixth switching transistor MP10 are turned off, while the first switching transistor MP5 and the second shift transistor are turned on. This causes the first load transistor MP1 and the second load transistor MP2 to be connected in series, and the third load transistor MP3 and the fourth load transistor MP4 to be connected in series. The first current adjustment transistor TAILSW_0 and the second current adjustment transistor TAILSW_1 are both turned on. The seventh switching transistor MP14 is turned on, while the eighth switching transistor MP12 and the ninth switching transistor MP15 are turned off, causing the fifth load transistor MP11 and the sixth load transistor MP13 to be connected in series.

[0089] The reduced equivalent transconductance of the transistors in the load unit of the differential amplifier helps suppress noise generation, thereby improving the signal-to-noise ratio.

[0090] When the transistors in the load unit of a differential amplifier are connected in series, the effective width-to-length ratio (W / L) of the load transistors decreases. The relationship between the output impedance and the width-to-length ratio is as follows: R OUT =1 / Gm= From the relationship between gain and noise, we know that gain * noise bandwidth = constant (GBW), and gain Av = gm1 * R OUT (gm1 is the transconductance of the input MOSFET), 3dB bandwidth f_3dB = 1 / 2ΠR*C, noise bandwidth NB = (Π / 2)*f_3dB, gain-bandwidth product GBW = Av*f_3dB. Combining the above formulas, the final formula for calculating noise bandwidth is:

[0091] NB = (Π / 2) * =(Π / 2)* As can be seen, a decrease in the width-to-length ratio (W / L) of the load MOS leads to a decrease in noise bandwidth and noise. Therefore, connecting the transistors in the load unit in series can suppress noise generation. Furthermore, an increase in total load results in a higher gain for the differential amplifier, while simultaneously reducing the noise bandwidth. Thus, this series structure not only effectively suppresses its own noise but also limits noise generated by the preceding circuitry. However, the increased total load impedance leads to a greater voltage division by the transistors in the load unit, reducing the comparator's input range. However, under high-gain conditions, the voltage fluctuation of the pixel signal is relatively small, so the input range requirement for the comparator is not high. But when shooting dark scenes, system noise has a greater impact on the image. Therefore, under high-gain conditions, this series structure can effectively improve the signal-to-noise ratio and reduce image noise.

[0092] When shooting in low-light environments (system high gain), the current adjustment signal Tail_ADJ_0 / 1 = High, and both the first current adjustment transistor TAILSW_0 and the second current adjustment transistor TAILSW_1 are turned on. The comparator current returns to normal, which can speed up the comparator's switching speed and improve the margin during the signal reset phase.

[0093] In some embodiments, the comparator further includes a second-stage amplifier comprising: a fifth load transistor MP11, including a gate connected to the drain of the second input transistor MN_Vpix; a sixth load transistor MP13, including a gate connected to the drain of the second input transistor MN_Vpix and a drain connected to the source of the fifth load transistor MP11; a seventh switching transistor MP14, including a drain connected to the source of the sixth load transistor MP13; an eighth switching transistor MP12, including a drain connected to the drain of the fifth load transistor MP11 and a source connected to the source of the sixth load transistor MP13; a ninth switching transistor MP15, including a source connected to the source of the seventh switching transistor MP14 and a drain connected to the drain of the sixth load transistor MP13; and a third input transistor MN_1, including a drain connected to the drain of the fifth load transistor MP11.

[0094] like Figure 2 As shown, the comparator provided in this embodiment of the invention further includes an inverter, which includes: a seventh load transistor MP16, including a drain connected to the signal output node and a gate connected to the drain of the fifth load transistor MP11; and an eighth load transistor MN_2, including a drain connected to the signal output node and a gate connected to the drain of the fifth load transistor MP11.

[0095] like Figure 2 As shown, the comparator provided in this embodiment of the invention further includes: a first zero-adjustment switch MP_RST_0, which can connect the reference ramp signal input node to the drain of the first input transistor MN_RAMP; a second zero-adjustment switch MP_RST_1, which can connect the pixel voltage signal input node to the drain of the second input transistor MN_Vpix; and a third zero-adjustment switch MN_RST, which can connect the gate of the third input transistor MN_1 to its drain.

[0096] It should be noted that without the switching transistors MP5 / MP6 (which are equivalent to the source of load transistors MP2 / MP3 being connected to the power supply), there is no impact on the series connection characteristics. In the parallel connection state, load transistors MP2 / MP3 will be short-circuited. The same applies to the switching transistor MP14 (without the switching transistor MP14, load transistor MP13 will be short-circuited).

[0097] From a practical perspective, assuming the width-to-length ratio of load transistors MP1 / MP2 / MP3 / MP4 is W / L, then when connected in series, the total width-to-length ratio of the load is W / 2L; when connected in parallel, the total width-to-length ratio of the load is 2W / L. Therefore, in the series-parallel connection state, the width-to-length ratio changes by a factor of 4. However, as mentioned above, if there are no switching transistors MP5 / MP6: when connected in series, the total width-to-length ratio of the load is W / 2L; when connected in parallel, since load transistors MP2 / MP3 are short-circuited, the total width-to-length ratio of the load is W / L (only load transistors MP1 / MP4 are working), and in the series-parallel connection state, the width-to-length ratio changes by a factor of 2.

[0098] Specifically, at the start of the operation cycle, the RST (automatic zeroing) signal (RST1 / RST2) starts to operate, performing zeroing operations on the differential amplifier and the second stage amplifier respectively. This is common knowledge in the technical field, and this embodiment will not elaborate further.

[0099] The comparator structure provided in this embodiment of the invention is applicable to multiple HDR modes, and the application methods in different HDR modes are as follows: Figure 3 As shown, in HDR mode based on multiple exposures, the sensor outputs multiple frames for wide dynamic range fusion. A short exposure frame focuses on capturing highlight information, while a long exposure frame focuses on capturing shadow information. After processing by a certain algorithm, a single output image is generated, capable of simultaneously restoring both highlight and shadow information. The principle is that, with an adjustable comparator, a wider input range and higher signal-to-noise ratio can be provided in HDR mode. The comparator's signal control timing in this HDR mode is as follows... Figure 4 As shown, when the structure is shooting bright environments in multi-frame synthesis HDR mode (system low gain), SWB / C=Low, SWA=High, the first load transistor MP1 of the differential amplifier is connected in parallel with the second load transistor MP2, and the third load transistor MP3 is connected in parallel with the fourth load transistor MP4; the fifth load transistor MP11 of the second stage amplifier is connected in parallel with the sixth load transistor MP13, which reduces the differential pair load impedance and helps to increase the input range of the comparator.

[0100] When the current adjustment signal Tail_ADJ_0 = High, TAILSW_0 is turned on; when Tail_ADJ_0 = Low, TAILSW_1 is turned off. The comparator circuit is in a low-current state, which reduces power consumption and also increases the comparator's input range. Therefore, when shooting images of bright areas, it can reduce overexposure.

[0101] At the start of the operation cycle, the RST (automatic zeroing) signal (RST1 / RST2) is activated, which performs zeroing operations on the differential amplifier and the second stage amplifier, respectively.

[0102] When shooting in low-light environments (system high gain), SWB / C = High, SWA = Low. The first load transistor MP1 of the differential amplifier is connected in series with the second load transistor MP2, and the third load transistor MP3 is connected in series with the fourth load transistor MP4. The fifth load transistor MP11 of the second-stage amplifier is connected in series with the sixth load transistor MP13. This reduces the equivalent transconductance of the load PMOS transistors in the differential amplifier, which helps suppress noise generation and thus improves the signal-to-noise ratio.

[0103] When the current adjustment signal Tail_ADJ_0 / 1=High, TAILSW_0 / 1 is turned on, the circuit current returns to normal, and the comparator's switching speed is accelerated. The zeroing action is the same as under low gain conditions. Automatic zeroing is performed at the beginning of the operation cycle. Signals RST1 and RST2 start to operate, respectively performing zeroing actions on the differential amplifier and the second stage amplifier.

[0104] like Figure 5 As shown, in DCG-HDR mode, since each pixel can be individually controlled with different gains, a pixel can undergo only one exposure, but with two readouts: one using HCG (high conversion gain) to capture dark information, and the other using LCG (low conversion gain) to capture bright information. The two parts are then combined to output the image. Therefore, this DCG-HDR mode typically requires a comparator with a dual-input structure. The comparator structure provided in this embodiment is still applicable to dual-input comparator structures, and its basic circuit structure is as follows: Figure 6 As shown, to simultaneously reflect results with different gains within one cycle, the comparator needs to employ a dual-input structure. One side inputs a high-gain pixel signal, and the other side inputs a low-gain pixel signal, processing the pixel signals with different gains separately. This dual-input comparator structure is controlled by the SEL_A / B signals to select the input branches of the comparator, choosing different branches for different gains within one operating cycle. Simultaneously, the zero-adjustment signals RST1_A / RST1_B perform zero-adjustment operations on the two input branches of the comparator. The TAIL_ADJ signal can adjust the current magnitude according to different gains to achieve low power consumption. Furthermore, to match the current of the differential amplifier after current switching, a current adjustment branch is added to the second-stage amplifier circuit to ensure normal operation of the circuit after the differential amplifier current switching. Ultimately, it outputs results with two different gains within one operating cycle, and its control timing is as follows. Figure 7 As shown below:

[0105] (1) Rs stage (LCG) comparator operation description: When the input selection switch signal SEL_A=High, SEL_B=Low, SELSW_A_0 / 1 is turned on, and SELSW_B_0 / 1 is turned off. At this time, the input branch on the A side of the comparator is connected, and the input branch on the B side is shielded. SWB / C=Low, SWA=High, the load transistors MP1 and MP2 of the differential amplifier are connected in parallel, and MP3 and MP4 are connected in parallel; MP11 and MP13 of the second stage amplifier are connected in parallel. The differential pair load impedance is reduced, which is beneficial to increasing the input range of the comparator.

[0106] When the current adjustment signal Tail_ADJ_0 = High, TAILSW_0 is turned on; when Tail_ADJ_0 = Low, TAILSW_1 is turned off. When 2ND_ADJ_0 = High, 2NDSW_0 is turned on; when 2ND_ADJ_1 = Low, 2NDSW_1 is turned off, and the circuit is in a low-power state. At the start of the Rs stage (LCG), RST1_A = Low, RST2 = High, and RST operation is performed on the input of comparator A and the second-stage amplifier.

[0107] (2) Rs Stage (HCG) Comparator Operation Description: When the input selection switch signal SEL_B=High, SEL_A=Low, SELSW_B_0 / 1 is turned on, and SELSW_A_0 / 1 is turned off. At this time, the input branch on the B side of the comparator is connected, and the input branch on the A side is shielded. SWA=Low, SWB / C=High, the load transistors MP1 and MP2 of the differential amplifier are connected in series, and MP3 and MP4 are connected in series; MP11 and MP13 of the second stage amplifier are connected in series. The equivalent transconductance of the differential-to-load PMOS is reduced, which suppresses noise generation and improves the system signal-to-noise ratio.

[0108] With the current adjustment signal Tail_ADJ_0 / 1 set to High, TAILSW_0 / 1 is turned on. The differential amplifier current returns to normal. This speeds up the switching speed of the high-gain conditional comparator output signal and improves the Rs stage margin.

[0109] At the initial moment of gain switching, RST1_B=Low performs an RST action on the input of the comparator B side. Since the differential amplifier currents of HCG and LCG are different, in order to match the current of the second-stage amplifier with the differential amplifier current during the HCG stage and ensure that the comparator circuit can operate normally, the current adjustment function of the second-stage amplifier is necessary. At this time, 2ND_ADJ_0 / 1=High, 2NDSW_0 / 1 is turned on, and the current of the second-stage amplifier also increases synchronously.

[0110] (3) Ss stage (HCG) comparator operation description: Except for the RST signal, the other control signals are the same as those in the Rs stage (HCG). The circuit noise is reduced, resulting in a higher signal-to-noise ratio for the HCG pixel signal. The high-gain pixel signal is input through the B side of the comparator and finally outputs the result of the light intensity under the HCG condition.

[0111] (4) Ss Stage (LCG) Comparator Operation Description: Except for the RST signal, the other control signals are the same as in the Rs Stage (LCG). The comparator switches to A-side input, the load PMOS returns to parallel connection, the current of the differential amplifier and the secondary amplifier decreases, the circuit power consumption decreases, and the input range of the comparator increases. Large voltage fluctuations of low-gain pixel signals are processed through the A-side input of the comparator. The final output is the light intensity result under LCG conditions.

[0112] In LOFIC pixels, due to the larger pixel well capacity, more charges can be collected, thus effectively extending the dynamic range of the pixel under strong light. Correspondingly, the voltage input range of the pixel readout circuit also needs to be larger; therefore, the comparator circuit provided in this embodiment of the invention is more suitable for LOFIC pixel sensors.

[0113] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A comparator with adjustable load and power consumption, characterized in that, The comparator includes a differential amplifier, the differential amplifier comprising: The first input transistor includes a gate connected to the reference ramp signal input node; The second input transistor includes a gate connected to the pixel voltage signal input node; The first load transistor includes a drain connected to the drain of the first input transistor; The fourth load transistor includes a drain connected to the drain of the second input transistor; The second load transistor includes a drain connected to the source of the first load transistor; The third load transistor includes the drain connected to the source of the fourth load transistor; The first switching transistor includes a drain connected to the source of the second load transistor; The second switching transistor includes a drain connected to the source of the third load transistor; The third switching transistor includes a source connected to the source of the first switching transistor and a drain connected to the drain of the second load transistor. The fourth switching transistor includes a source connected to the source of the second switching transistor and a drain connected to the drain of the third load transistor. The fifth switching transistor includes a source connected to the source of the second load transistor and a drain connected to the drain of the first load transistor; and The sixth switching transistor includes a source connected to the source of the third load transistor and a drain connected to the drain of the fourth load transistor.

2. The comparator with adjustable load and power consumption according to claim 1, characterized in that, The differential amplifier further includes a current adjustment circuit, which comprises: A first current-adjusting transistor includes a drain connected to the source of a first input transistor and a second input transistor; and The second current-adjusting transistor includes a drain connected to the source of the first input transistor and the second input transistor.

3. The comparator with adjustable load and power consumption according to claim 1, characterized in that, The comparator further includes a second-stage amplifier, the second-stage amplifier comprising: The fifth load transistor includes a gate connected to the drain of the second input transistor; The sixth load transistor includes a gate connected to the drain of the second input transistor and a drain connected to the source of the fifth load transistor; The seventh switching transistor includes a drain connected to the source of the sixth load transistor; The eighth switching transistor includes a drain connected to the drain of the fifth load transistor and a source connected to the source of the sixth load transistor. The ninth switching transistor includes a source connected to the source of the seventh switching transistor and a drain connected to the drain of the sixth load transistor; and The third input transistor includes a drain connected to the drain of the fifth load transistor.

4. A comparator with adjustable load and power consumption according to claim 3, characterized in that, The comparator further includes an inverter, which includes: The seventh load transistor includes a drain connected to the signal output node and a gate connected to the drain of the fifth load transistor; and The eighth load transistor includes a drain connected to the signal output node and a gate connected to the drain of the fifth load transistor.

5. A comparator with adjustable load and power consumption according to claim 4, characterized in that, The comparator is configured to operate between high dynamic range and high signal-to-noise ratio based on a gain condition; Wherein, when the gain condition is a low gain condition, the third, fourth, fifth and sixth switching transistors are turned on, and the first switching transistor and the second shift transistor are turned off, so that the first load transistor and the second load transistor are connected in parallel, and the third load transistor and the fourth load transistor are connected in parallel. The seventh switching transistor is turned off, and the eighth and ninth switching transistors are turned on, so that the fifth load transistor is connected in parallel with the sixth load transistor.

6. A comparator with adjustable load and power consumption according to claim 5, characterized in that, The first current-adjusting transistor is turned on, and the second current-adjusting transistor is turned off.

7. A comparator with adjustable load and power consumption according to claim 4, characterized in that, The comparator is configured to operate between high dynamic range and high signal-to-noise ratio based on a gain condition; When the gain condition is a high gain condition, the third, fourth, fifth, and sixth switching transistors are turned off, and the first and second shift transistors are turned on, so that the first load transistor and the second load transistor are connected in series, the third load transistor and the fourth load transistor are connected in series, and both the first and second current adjustment transistors are turned on. The seventh switching transistor is turned on, and the eighth and ninth switching transistors are turned off, so that the fifth load transistor is connected in series with the sixth load transistor.

8. A comparator with adjustable load and power consumption according to claim 5, characterized in that, The first current-adjusting transistor is turned on, and the second current-adjusting transistor is turned on.

9. A comparator with adjustable load and power consumption according to claim 3, characterized in that, The comparator further includes: The first zero-adjustment switch can connect the reference ramp signal input node to the drain of the first input transistor; The second zero-adjustment switch can connect the pixel voltage signal input node to the drain of the second input transistor; and The third zero-adjustment switch can connect the gate of the third input transistor to the drain.

10. An image sensor, characterized in that, include: A pixel array is configured to output pixel signals; The pixel driver module is configured to control the movement of the pixel array; The load current source module is configured to process the pixel signals output by the pixel array to generate pixel voltage signals; A ramp generator is configured to generate a reference ramp signal; A load and power consumption adjustable comparator as described in any one of claims 1-9 is configured to compare a pixel voltage signal and a reference ramp signal under different gain conditions and generate different output signals based on the comparison results. The counter is configured to count different output signals to obtain the counting result; as well as The signal processing module is configured to perform digital processing on the counting results and output image data.

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