Pixel structure, control method and image sensor

Abstract

The application provides a pixel structure, a control method and an image sensor, and the pixel structure comprises: a photosensitive transmission unit for accumulating and driving charge transmission along a first direction; a charge transfer unit arranged at the output side of the photosensitive transmission unit; a shunt unit arranged at the output side of the charge transfer unit, comprising at least one level of shunt structure, each level of shunt structure being composed of a branch component and a control component, for providing multiple branch paths for the charge and realizing selective conduction; and multiple signal output units arranged at the output side of the last level of branch paths respectively for signal conversion. By introducing multiple levels of shunt structures and parallel readout circuits at the end of the charge transmission path, the application can alternately shunt the continuous charge to different branch paths, can reduce the conversion pressure of a single ADC, and can solve the problem that the readout speed of a single channel of a traditional TDI-CMOS sensor is limited, while maintaining high charge transfer efficiency, and greatly improving the line frequency and running speed of the image sensor.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, specifically to a pixel structure, control method, and image sensor. Background Technology

[0002] By embedding charge transport channels with a structure similar to a charge-coupled device (CCD) into the complementary metal-oxide-semiconductor (CMOS) process, this technology is called embedded CCD (eCCD). Time-delay integration (TDI) image sensors made using this technology are called TDI-CMOS image sensors. Currently, TDI-CMOS image sensors are widely used in fields such as industrial machine vision, semiconductor inspection, and earth observation.

[0003] In the detection of pattern defects in semiconductor photomasks and wafers, TDI-CMOS image sensors are typically required to possess ultra-high line rates (megahertz-level line frequencies) and ultra-high sensitivity to achieve higher detection efficiency. For traditional TDI-CMOS image sensors (such as the patent with publication number CN117832246A), the pixel array is read out serially, and the output speed of the entire column of pixels is limited by the sampling rate of the single analog-to-digital converter (ADC) at the back end; its maximum scan line frequency is typically only a few hundred kilohertz (kHz). Therefore, to realize the application of TDI-CMOS image sensors in semiconductor inspection, it is urgent to optimize the design of TDI-CMOS image sensors to further improve their operating speed. Summary of the Invention

[0004] The problem solved by this invention is that the operating speed of image sensors is limited by the single-channel readout rate.

[0005] To address the aforementioned problems, the present invention provides a pixel structure comprising: a photosensitive transmission unit configured to accumulate and drive charge transmission along a first direction under the action of a clock driving signal; a charge transfer unit disposed on the output side of the photosensitive transmission unit in the first direction, for receiving and transferring charge; a shunt unit disposed on the output side of the charge transfer unit, the shunt unit comprising at least one shunt structure sequentially adjacent to each other along the first direction; wherein each shunt structure comprises a branch component and a control component; the branch component is configured to provide multiple branch paths for charge transmission entering the shunt structure at that stage; the control component is configured to selectively conduct or block each of the branch paths; and multiple signal output units, each of the signal output units disposed on the output side of a branch path of the final stage shunt structure, for receiving charge from the corresponding branch path and performing signal conversion.

[0006] Optionally, the photosensitive transmission unit includes at least one level of pixel photosensitive units arranged along the first direction; wherein each level of the pixel photosensitive unit includes a substrate, a gate oxide layer disposed on the substrate, and a plurality of first gate electrodes disposed on the gate oxide layer and arranged along the first direction; the plurality of first gate electrodes are insulated from each other; the plurality of first gate electrodes are configured to integrate photogenerated charge and drive it to be transmitted along the first direction under the action of the clock drive signal.

[0007] Optionally, each pixel photosensitive unit includes M first gate electrodes arranged along the first direction, where M is an even number not less than 4; wherein the phase difference between the clock drive signals received by two adjacent first gate electrodes along the first direction is 1 / M of the clock drive signal period.

[0008] Optionally, the charge transfer unit includes the substrate, the gate oxide layer, and at least one transfer gate electrode disposed downstream of the photosensitive transmission unit along the first direction; the transfer gate electrode is disposed on the gate oxide layer and located between the photosensitive transmission unit and the shunt unit; along the first direction, the upstream end of the transfer gate electrode is disposed adjacent to the last first gate electrode in the photosensitive transmission unit, and the downstream end of the transfer gate electrode is disposed adjacent to the first-stage shunt structure in the shunt unit.

[0009] Optionally, when the charge transfer unit includes a plurality of transfer gate electrodes arranged along the first direction, each of the transfer gate electrodes receives a transmission control signal having a preset phase difference; wherein, the transmission control signal received by the first transfer gate electrode is used to control it to receive the charge when the photosensitive transmission unit outputs the charge; the start time of the effective level of the transmission control signal received by each subsequent transfer gate electrode is sequentially delayed relative to the start time of the effective level of the previous transfer gate electrode.

[0010] Optionally, the start time of the effective level of the transmission control signal applied to the first transfer gate electrode is earlier than the end time of the effective level of the clock drive signal applied to the last first gate electrode, and the end time of its effective level is later than the end time of the effective level of the clock drive signal applied to the last first gate electrode.

[0011] Optionally, the lateral width of the transfer gate electrode gradually narrows along the first direction to improve the charge shunting efficiency.

[0012] Optionally, the branching assembly includes the substrate, the gate oxide layer, and a plurality of shunt gate electrodes arranged along a second direction perpendicular to the first direction; the plurality of shunt gate electrodes are disposed on the gate oxide layer, and the proximal ends of the plurality of shunt gate electrodes of the first-stage branching assembly in the charge transport direction are arranged adjacent to the distal ends of the transfer gate electrode in the charge transport direction.

[0013] Optionally, the plurality of shunt gate electrodes are electrically connected to the shunt control signal; the plurality of shunt gate electrodes are configured to receive the charge output from the charge transfer unit under the action of the shunt control signal and shunt it to their respective corresponding branch paths.

[0014] Optionally, the timing of the shunt control signal is configured such that the start time of its effective level is no later than the start time of the effective level of the transmission control signal applied by the last transfer gate electrode, and the end time of its effective level lags behind the end time of the effective level of the transmission control signal, so that after the transmission control signal transitions to an invalid level, the shunt gate electrode continuously receives and temporarily stores the charge from the charge transfer unit.

[0015] Optionally, the shunt control signal includes independent drive signals applied to each of the shunt gate electrodes; after the transmission control signal is converted to an invalid level, the independent drive signal applied to the shunt gate electrode corresponding to the target branch path is converted to an invalid level at a time that lags behind the time when the independent drive signals applied to other shunt gate electrodes are converted to an invalid level.

[0016] Optionally, the control component includes the substrate, the gate oxide layer, and a plurality of control gate electrodes arranged along the second direction; the plurality of control gate electrodes are disposed on the gate oxide layer and are respectively disposed adjacent to the output side of the shunt gate electrode corresponding to the branch path.

[0017] Optionally, the plurality of control gate electrodes respectively receive a plurality of independent control drive signals; the effective level start time of each control drive signal is no later than the effective level end time of the corresponding shunt control signal, and its effective level end time lags behind the effective level end time of the corresponding shunt control signal; wherein, the effective levels of the control drive signals applied to different control gate electrodes do not overlap in time, so that each branch path is turned on in turn at different time periods.

[0018] Optionally, each of the signal output units includes a floating diffusion node disposed within the substrate; the floating diffusion node is disposed beside the output side of the final stage control component.

[0019] On the other hand, the present invention also provides a pixel structure control method, comprising the following steps: applying an M-phase clock drive signal to a plurality of first gate electrodes of the photosensitive transmission unit, such that the clock drive signal between adjacent first gate electrodes generates a phase lag of 1 / M period, so as to drive charge to be transmitted to the charge transfer unit along a first direction; when the charge transfer unit includes a plurality of transfer gate electrodes arranged along the first direction, applying a transmission control signal having a preset phase difference to the transfer gate electrodes respectively; wherein, the transmission control signal applied to the first transfer gate electrode is used to control it to receive the charge when the photosensitive transmission unit outputs charge; the start time of the effective level of the transmission control signal applied to each subsequent transfer gate electrode is sequentially delayed relative to the start time of the effective level of the previous transfer gate electrode; the start time of the effective level of the transmission control signal applied to the first transfer gate electrode is earlier than the end time of the effective level of the clock drive signal applied to the last first gate electrode, and the end time of the effective level of the transmission control signal applied to the last first gate electrode is later than the end time of the effective level of the clock drive signal applied to the last first gate electrode. A shunt control signal and a control drive signal are applied to the multiple shunt gate electrodes and control gate electrodes of the shunt unit, respectively; wherein, by alternately changing the level state of the control drive signal corresponding to different branch paths, the continuously transmitted charge packets are sequentially shunted to different branch paths; the multiple signal output units alternately convert the received charge into voltage signals and output them in parallel.

[0020] Optionally, when the charge needs to be output through a specific branch path, the control drive signal of the previous stage and the shunt control signal of the next stage are switched to active levels simultaneously, and the end time of the shunt control signal is kept lagging behind the end time of the transmission control signal.

[0021] On the other hand, the present invention also provides an image sensor, comprising: a pixel array composed of a plurality of the aforementioned pixel structures arranged in rows and columns; a driving circuit for generating the clock driving signal, the transmission control signal, the shunt control signal, and the control driving signal; and a readout circuit comprising multiple sets of parallel analog-to-digital converters (ADCs).

[0022] Optionally, in each column of the pixel array, adjacent pixel structures share the same substrate and charge transport channels are continuously arranged.

[0023] Compared with existing technologies, the technical solution of this invention has the following advantages: By adding a multi-stage shunt unit at the end of the charge transfer path, this invention achieves the transformation from single-channel line-by-line readout to multi-channel parallel processing, significantly improving the operating speed of the TDI-CMOS image sensor. Furthermore, by utilizing the gradually narrowing transfer gate, the delayed timing of the shunt control signal between the shunt gate electrodes, and combining it with timing-exclusive control drive signals, the charge transfer efficiency of the TDI-CMOS image sensor can be significantly improved. Attached Figure Description

[0024] Figure 1 The diagram shown is a cross-sectional view of a pixel structure according to the present invention. Figure 2 Shown is a top view of the pixel structure of the present invention; Figure 3 Shown as the present invention Figure 2 A timing diagram of the voltage signals applied to each electrode. Detailed Implementation

[0025] As can be seen from the background technology, in the existing TDI-CMOS pixel array, each column of pixels usually adopts a serial readout mode, which cannot achieve physical-level parallel processing within the pixel, and it is difficult to achieve high-density multi-channel parallel output within a limited pixel size.

[0026] To address the aforementioned technical problem, in one aspect, the present invention provides a pixel structure, comprising: a photosensitive transmission unit configured to accumulate and drive charge transmission along a first direction under the action of a clock driving signal; a charge transfer unit disposed on the output side of the photosensitive transmission unit in the first direction, for receiving and transferring charge; a shunt unit disposed on the output side of the charge transfer unit, the shunt unit comprising at least one shunt structure sequentially adjacent along the first direction; wherein each shunt structure comprises a branch component and a control component; the branch component is configured to provide multiple branch paths for charge transmission entering the shunt structure at that stage; the control component is configured to selectively conduct or block each of the branch paths; and multiple signal output units, each of the signal output units disposed on the output side of a branch path of the final shunt structure, for receiving charge from the corresponding branch path and performing signal conversion.

[0027] In this embodiment, the photosensitive transmission unit includes at least one level of pixel photosensitive units arranged along the first direction; wherein each level of the pixel photosensitive unit includes a substrate, a gate oxide layer disposed on the substrate, and a plurality of first gate electrodes disposed on the gate oxide layer and arranged along the first direction; the plurality of first gate electrodes are insulated from each other; the plurality of first gate electrodes are configured to integrate photogenerated charge and drive it to be transmitted along the first direction under the action of the clock driving signal.

[0028] like Figure 1 As shown, Figure 1 The diagram shows a cross-sectional view of a pixel structure according to the present invention; and in conjunction with Figure 2 , Figure 2 The diagram shows a top view of the pixel structure of the present invention. The photosensitive transmission unit includes at least one level of pixel photosensitive units arranged along a first direction (the charge transport direction from left to right in the diagram). Each level of the pixel photosensitive unit is located above the underlying structure, specifically including a substrate 11, a gate oxide layer 12 disposed on the substrate 11, and a plurality of first gate electrodes disposed on the gate oxide layer 12 and arranged sequentially along the first direction. In this embodiment, the plurality of first gate electrodes includes first gate electrode PH1, first gate electrode PH2, first gate electrode PH3, first gate electrode PH4, first gate electrode PH5, first gate electrode PH6, first gate electrode PH7, and first gate electrode PH8. These first gate electrodes are insulated from each other to ensure that each electrode can be controlled by an independent signal.

[0029] During operation, the plurality of first gate electrodes are configured to first integrate and accumulate the photogenerated charge generated by photosensitive substrate 11 under the action of the externally applied clock drive signal. Subsequently, by alternately changing the level state on adjacent first gate electrodes, the charge is driven to be transferred along the first direction to the downstream charge transfer unit. This charge transfer method based on the eCCD structure enables low noise and high integrity during high-speed charge transfer. It should be noted that... Figure 1 The number and arrangement of the first gate electrodes shown are merely examples. In actual applications, the total number of electrodes can be set according to the needs of the TDI integration stages, and the number M of the first gate electrodes contained in each pixel photosensitive unit can be determined according to the number of driving phases (such as four-phase, eight-phase, or...). Figure 1 (Multi-phase drive) can be flexibly configured.

[0030] In some embodiments, each pixel photosensitive unit includes M first gate electrodes arranged along the first direction, where M is an even number not less than 4; wherein the phase difference between the clock drive signals received by two adjacent first gate electrodes along the first direction is 1 / M of the clock drive signal period.

[0031] See Figures 1 to 3 Each level of the pixel photosensitive unit includes a region along the first direction X (e.g., along...). Figure 2 The first gate electrodes (e.g., PH1 to PH8) are arranged in a direction indicated by the X-axis, where M is an even number not less than 4. In this embodiment, M is 8, meaning it includes 8 first gate electrodes. In other embodiments, it can also be 4 or 10 first gate electrodes, etc.

[0032] See Figure 3 , Figure 3 Shown as the present invention Figure 2 A timing diagram of the voltage signals applied to each electrode. The plurality of first gate electrodes (such as first gate electrodes PH1 to first gate electrodes PH8) are configured to receive the clock drive signal. The phase difference between the clock drive signals received by two adjacent first gate electrodes along the first direction X is 1 / M of the clock drive signal period T. In this embodiment, the phase difference between the clock drive signals received by two adjacent first gate electrodes along the first direction X is 1 / 8 of the clock drive signal period T.

[0033] Specifically, with Figure 3 Taking the timing relationship shown as an example, if each stage of the photosensitive transmission unit is configured with multiple first gate electrodes, the driving clock signals between adjacent first gate electrodes are sequentially offset on the time axis. For example, the clock driving signal received by the first gate electrode PH1 is delayed in phase by T / 8 (T is the period) relative to the clock driving signal received by the first gate electrode PH2; similarly, the first gate electrode PH3 is delayed by T / 8 relative to the first gate electrode PH2, and so on.

[0034] This driving method with a fixed phase difference enables the potential well formed within the substrate 11 to move along the first direction at a stable step frequency. Since M is selected as an even number not less than 4, this ensures that at any given time, a sufficiently wide potential well region can be formed below the plurality of first gate electrodes to accommodate photogenerated charges, thereby optimizing the efficiency of charge transfer along the first direction from the front-end photosensitive transmission unit to the end-end charge transfer unit.

[0035] In this embodiment, the first gate electrodes (PH1-PH8) have a rectangular shape when viewed from above. In terms of arrangement, these multiple rectangular first gate electrodes (PH1-PH8) are arranged sequentially and at equal intervals along the first direction X on the gate oxide layer 12 on the substrate 11. The long side of each first gate electrode (PH1-PH8) extends perpendicular to the first direction, and an insulating gap is left between adjacent first gate electrodes (PH1-PH8) to achieve electrical insulation between them. This rectangular array arrangement is beneficial for the directional and efficient transport of photogenerated charges in the first direction.

[0036] Regardless of their shape, the plurality of first gate electrodes (PH1-PH8) must remain insulated from each other and receive the clock drive signal according to the aforementioned phase difference rule in order to integrate and drive the photogenerated charge.

[0037] A charge transfer unit is disposed on the output side of the photosensitive transmission unit in the first direction, and is used to receive and transfer charge. The charge transfer unit includes the substrate, the gate oxide layer, and at least one transfer gate electrode disposed downstream of the photosensitive transmission unit along the first direction; the transfer gate electrode is disposed on the gate oxide layer and located between the photosensitive transmission unit and the shunt unit; along the first direction, the upstream end of the transfer gate electrode is adjacent to the last first gate electrode in the photosensitive transmission unit, and the downstream end of the transfer gate electrode is adjacent to the first-stage shunt structure in the shunt unit.

[0038] like Figures 1 to 3 As shown, the charge transfer unit is disposed in the photosensitive transmission unit in the first direction (e.g., Figure 2 The output side (in the direction shown by the X-axis) (referring to the movement and output of charges in the first direction) is used to receive photogenerated charges transmitted from the photosensitive transmission unit of the preceding stage and further transfer them to the subsequent stage.

[0039] In this embodiment, as Figure 2 As shown, the charge transfer unit includes the substrate 11, the gate oxide layer 12 disposed on the substrate 11, and at least one transfer gate electrode PH9 disposed downstream of the photosensitive transmission unit along the first direction (referring to the output side of the photosensitive transmission unit in the first direction X). The transfer gate electrode PH9 is disposed on the gate oxide layer 12 and is located between the photosensitive transmission unit and the subsequent shunt unit in the first direction.

[0040] Along the first direction, the upstream end of the transfer gate electrode PH9 (referring to the input side of the charge transfer unit corresponding to the transfer gate electrode PH9 in the first direction X) is adjacent to the last first gate electrode PH8 in the photosensitive transmission unit, while the downstream end of the transfer gate electrode PH9 (the output side of the charge transfer unit corresponding to the transfer gate electrode PH9 in the first direction X) is adjacent to the first-stage shunt structure in the shunt unit (such as...). Figure 2 The layers containing PH10a and PH10b are arranged adjacent to each other. The transfer gate electrode PH9 is electrically insulated from the first gate electrode PH8 and the shunt structure in the subsequent stage.

[0041] In this embodiment, the charge transfer unit includes only one transfer gate electrode PH9. The transfer gate electrode PH9 serves as an intermediate bridge connecting the photosensitive transmission unit (including the first gate electrodes PH1 to PH8) and the shunt unit, enabling charge transfer from the preceding stage to the following stage. The transfer gate electrode receives a transmission control signal to control its reception of charge when the photosensitive transmission unit outputs charge. The effective start time of the transmission control signal for the transfer gate electrode is earlier than the effective end time of the clock drive signal applied to the last first gate electrode, and its effective end time is later than the effective end time of the clock drive signal applied to the last first gate electrode.

[0042] In other embodiments, the charge transfer unit may also be configured to include a plurality of the transfer gate electrodes arranged along the first direction, depending on requirements such as transmission distance (for example, one or more gate electrodes with similar structure and function to PH9 may be added sequentially after PH9 and before the shunt unit).

[0043] When the charge transfer unit includes a plurality of transfer gate electrodes, the plurality of transfer gate electrodes are all disposed on the gate oxide layer 12 and arranged sequentially along the first direction. The upstream transfer gate electrode is disposed adjacent to the last first gate electrode PH8 in the photosensitive transmission unit, and the downstream transfer gate electrode is disposed adjacent to the first-stage shunt structure in the shunt unit.

[0044] In this embodiment, the top-view geometry of the transfer gate electrode PH9 is the same as that of the first gate electrodes PH1-PH8 in the photosensitive transmission unit, which is rectangular. The long side of the transfer gate electrode PH9 extends perpendicular to the first direction (X-axis direction), and its width in the lateral direction (perpendicular to the first direction) is consistent with the lateral width of the first gate electrodes PH1-PH8. This ensures that the potential well has good continuity and matching in the lateral distribution during the charge transfer from the first gate electrode PH8 to the transfer gate electrode PH9.

[0045] In other embodiments, the lateral width of the transfer gate electrode gradually narrows along the first direction to improve charge shunting efficiency. To further optimize the directionality of charge transfer to subsequent shunting units and improve charge shunting efficiency, the lateral width of the transfer gate electrode PH9 can be designed to gradually narrow along the first direction. Specifically, the transfer gate electrode PH9 can adopt a trapezoidal structure or other structures with a converging tendency. When the transfer gate electrode PH9 adopts a trapezoidal structure, its end near the first gate electrode PH8 (upstream end) has a larger lateral width, while its end near the shunting unit (downstream end) has a smaller lateral width. In embodiments of the present invention, the lateral width of the transfer gate electrode is designed to be non-narrowing, and its lateral cross-sectional shape is rectangular.

[0046] By gradually reducing the lateral width of the transfer gate electrode PH9 along the first direction, a lateral edge electric field component can be generated within the substrate 11 in this region. This edge electric field exerts a squeezing effect on the charges, causing them to converge towards the central axis. This guides the charges to gradually converge in the lateral space as they move downstream, allowing them to enter the subsequent shunt unit more accurately and quickly. This geometry effectively reduces charge diffusion losses at the shunt interface, thereby improving the overall charge shunt efficiency of the device.

[0047] In some embodiments, when the charge transfer unit includes a plurality of transfer gate electrodes arranged along the first direction, each of the transfer gate electrodes receives a transmission control signal having a preset phase difference; wherein, the transmission control signal received by the first transfer gate electrode is used to control it to receive the charge when the photosensitive transmission unit outputs the charge; the start time of the effective level of the transmission control signal received by each subsequent transfer gate electrode is sequentially delayed relative to the start time of the effective level of the previous transfer gate electrode.

[0048] See Figures 1 to 3When the charge transfer unit includes a plurality of transfer gate electrodes arranged along the first direction (e.g., including the transfer gate electrode PH9 and subsequent transfer gate electrodes arranged sequentially downstream therefrom), each of the transfer gate electrodes receives a transmission control signal having a preset phase difference.

[0049] See Figure 3 The transmission control signal is a periodic pulse signal. In this embodiment, the "effective level" refers to a level state that enables the transfer gate electrode to form a potential well in the substrate 11 below it to accommodate charge. Figure 3 The waveform diagram of each clock signal is shown. When the signal is at a high level, a deep potential well is formed below the corresponding transmission gate electrode PH9, and the charge is attracted there. Therefore, in this embodiment, the effective level is a high level.

[0050] When the charge transfer unit includes a transfer gate electrode, the transfer control signal received by the transfer gate electrode is used to control it to receive the charge when the photosensitive transmission unit outputs charge (i.e., when the clock drive signal of the first gate electrode PH8 in the preceding stage becomes low).

[0051] When the charge transfer unit includes a plurality of transfer gate electrodes arranged along the first direction, the transmission control signal received by the first transfer gate electrode in the charge transfer unit is used to control it to receive the charge when the photosensitive transmission unit outputs charge (i.e., when the clock drive signal of the preceding first gate electrode PH8 becomes low). The start time of the effective level (i.e., high level) of the transmission control signal received by each subsequent transfer gate electrode is sequentially delayed relative to the start time of the effective level (i.e., high level) of the previous transfer gate electrode.

[0052] refer to Figure 3 In the time axis shown, in this embodiment, there is a preset time lag t between the clock drive signal corresponding to the first gate electrode PH8 and the transmission control signal corresponding to the transfer gate electrode PH9, which are adjacent to each other. In this embodiment, the time lag t and the signal period T satisfy a preset phase relationship (e.g., t=T / M, where M is the total number of drive phases). In this embodiment, the phase difference between the transfer gate electrode PH9 and the first gate electrode PH8 is consistent with the phase difference between two adjacent first gate electrodes (e.g., PH1 and PH2, or PH7 and PH8) in the photosensitive transmission unit. By keeping the drive phase difference constant throughout the transmission path, it can be ensured that the electric field driving force experienced by the charge packet is continuous when it enters the charge transfer unit from the photosensitive transmission unit, thereby ensuring the speed and efficiency of charge transfer.

[0053] In other embodiments, the time lag t of the transmission control signal received by the transfer gate electrode PH9 relative to the first gate electrode PH8 of the previous stage can also be adjusted according to actual needs, so that it is different from the phase difference between adjacent gates inside the photosensitive transmission unit.

[0054] For example, this lag time can be reduced to create a steeper potential gradient, thereby giving the charge a greater initial velocity as it enters the charge transfer unit. This tunability of the phase difference provides a larger process window for optimizing charge transfer between the photosensitive transmission unit and the shunt unit, allowing for flexible adjustment of the timing characteristics of charge transfer for different application scenarios.

[0055] In this embodiment, the effective level start time of the transmission control signal applied to the first transfer gate electrode is earlier than the effective level end time of the clock drive signal applied to the last first gate electrode, and the effective level end time is later than the effective level end time of the clock drive signal applied to the last first gate electrode.

[0056] like Figures 1 to 3 As shown, at the junction of the photosensitive transmission unit and the charge transfer unit, the timing logic of the driving signal is optimized to achieve efficient cross-unit charge transfer.

[0057] Specifically, the start time of the effective level (high level in this embodiment) of the transmission control signal applied to the first transfer gate electrode PH9 is earlier than the end time of the effective level (high level in this embodiment) of the clock drive signal applied to the last first gate electrode PH8. That is, the transfer gate electrode PH9 has already switched to a high level before the first gate electrode PH8 switches from a high level to a low level. And the end time of the effective level of the transmission control signal of the transfer gate electrode PH9, that is, the time when it switches from a high level to a low level, is later than the end time of the effective level of the clock drive signal of the first gate electrode PH8, that is, the time when it switches from a high level to a low level.

[0058] refer to Figure 3 As shown, this timing design creates a "level overlap region" between the first gate electrode PH8 and the transfer gate electrode PH9 on the time axis. Before the effective level of the first gate electrode PH8 has ended, the effective level of the transfer gate electrode PH9 has already been turned on. This means that during this period, the potential well below the first gate electrode PH8 and the potential well below the transfer gate electrode PH9 are simultaneously turned on and connected within the substrate 11.

[0059] By setting the above-mentioned level overlap relationship, the technical effects that can be achieved include: First, at the instant when the charge is transferred from the photosensitive transmission unit to the charge transfer unit, since the transfer gate electrode PH9 is turned on in advance, the charge can smoothly feel the attraction from the potential well below the transfer gate electrode PH9 under the drive of the first gate electrode PH8, thereby eliminating the potential barrier at the junction of the two units and preventing the charge from accumulating or flowing back at the junction of PH8 and PH9.

[0060] Secondly, the effective level end time of the transfer gate electrode PH9 is later than the effective level end time of the first gate electrode PH8. This ensures that when the signal of the first gate electrode PH8 changes from high level to low level, causing the potential well below it to become shallower and completely disappear, the charge has completely entered and is locked in the deep potential well below the transfer gate electrode PH9.

[0061] This overlapping drive method of "turning on first and then turning off" presents a dynamically changing potential well gradient in the first direction, allowing charge to be transferred between the first gate electrode PH8 and the transfer gate electrode PH9 in a "relay" manner. This greatly improves the charge transfer efficiency between different functional units, ensures the continuity of signal transmission, and thus enhances the charge transfer integrity of the device in high-speed image acquisition mode.

[0062] The pixel structure of the present invention further includes a shunt unit disposed on the output side of the charge transfer unit. The shunt unit includes at least one shunt structure sequentially adjacent to each other along the first direction. Each shunt structure includes a branch component and a control component. The branch component is configured to provide multiple branch paths for charge transport entering the shunt structure. The control component is configured to selectively conduct or block each branch path.

[0063] Combination Figures 1 to 3 As shown, the pixel structure in this embodiment also includes a current shunting unit, which is disposed on the output side of the charge transfer unit (i.e., Figure 2 The right side of the transfer gate electrode PH9 described in the text). The shunt unit includes components along the first direction ( Figure 2 At least one level of shunt structure that is sequentially adjacent in the X direction.

[0064] Specifically, in this embodiment, the shunt unit adopts a two-stage shunt structure. The first-stage shunt structure (initial shunt structure) consists of a branch assembly composed of shunt gate electrodes PH10a and PH10b, and a control assembly composed of adjacent control gate electrodes PH11a and PH11b, used to divide the single charge path from the transfer gate electrode PH9 into two parallel branch paths. The second-stage shunt structure is located on the output side of the first-stage shunt structure, and consists of a branch assembly composed of shunt gate electrodes PH12a, PH12b, PH12c, and PH12d, and a control assembly composed of adjacent control gate electrodes TXa, TXb, TXc, and TXd, used to further shunt the charge into four parallel branch paths.

[0065] Each stage of the shunt structure includes a branching component and a control component. The branching component is configured to provide multiple branch paths for charge transport into that stage of the shunt structure. In this embodiment, the branch paths refer to multiple potential well transport paths generated by the shunt gate electrodes within the substrate 11 and separated from each other in the second direction. For example, in the first-stage shunt structure, shunt gate electrodes PH10a and PH10b respectively form two parallel charge channels; in the second-stage shunt structure, shunt gate electrodes PH12a, PH12b, PH12c, and PH12d respectively form four parallel charge channels. The control component (such as PH11a and PH11b in the first stage and TXa-TXd in the second stage) is configured to selectively conduct or block each branch path by adjusting the voltage signal applied to each gate electrode, thereby realizing charge transport on different paths.

[0066] In this embodiment, the branching assembly includes the substrate, the gate oxide layer, and a plurality of shunt gate electrodes arranged along a second direction perpendicular to the first direction; the plurality of shunt gate electrodes are disposed on the gate oxide layer, and the proximal ends of the plurality of shunt gate electrodes in the charge transport direction of the first-stage branching assembly are commonly disposed adjacent to the distal ends of the transfer gate electrode in the charge transport direction. Figure 1 and Figure 2 As shown, the branching assembly includes the substrate 11, the gate oxide layer 12, and a plurality of shunt gate electrodes (e.g., PH10a, PH10b, etc.) arranged along a second direction (a longitudinal direction perpendicular to the first direction X). The plurality of shunt gate electrodes are disposed on the gate oxide layer 12. The proximal ends (PH10a, PH10b) of the plurality of shunt gate electrodes (PH10a, PH10b) in the charge transport direction of the first-stage branching assembly... Figure 2 The left side of PH10a and PH10b, together with the distal end of the transfer gate electrode PH9 in the charge transport direction ( Figure 2(Set adjacent to the right side of PH10a and PH10b).

[0067] Furthermore, in this embodiment, the plurality of shunt gate electrodes are electrically connected to the shunt control signal; the plurality of shunt gate electrodes are configured to receive the charge output from the charge transfer unit under the action of the shunt control signal and shunt it to their respective corresponding branch paths. The branch paths are structurally formed by a controlled potential well region below the shunt gate electrodes. By setting a plurality of mutually independent shunt gate electrodes in the second direction, the charge originally located in a single channel (below PH9) can be guided according to timing logic to multiple spatially independent sub-channels, realizing the spatial expansion and shunt of the charge.

[0068] Furthermore, in this embodiment, the timing of the shunt control signal is configured such that the start time of its effective level is no later than the start time of the effective level of the transmission control signal applied by the last transfer gate electrode, and the end time of its effective level lags behind the end time of the effective level of the transmission control signal, so that after the transmission control signal transitions to an inactive level, the shunt gate electrode continuously receives and temporarily stores the charge from the charge transfer unit. In this embodiment, the effective level refers to a high level that enables a charge retention potential well to be formed below the shunt gate electrode or the transfer gate electrode (e.g., ...). Figure 3 The potentials corresponding to the rising edges of the PH10a and PH10b signal waveforms), through this timing configuration, ensure that the transmission control signal PH9 transitions from a high level to an inactive level (i.e., ...). Figure 3 After the potential well disappears at a low level, the shunt gate electrode (such as PH10a, PH10b) remains at a high level, thereby continuously receiving and temporarily storing the charge from the charge transfer unit.

[0069] Furthermore, in this embodiment, the shunt control signal includes independent drive signals applied to each of the shunt gate electrodes; after the transmission control signal becomes inactive, the independent drive signal applied to the shunt gate electrode corresponding to the target branch path becomes inactive at a time lags behind the time when the independent drive signals applied to other shunt gate electrodes become inactive. The independent drive signal refers to a signal capable of individually switching the level of each shunt gate electrode (e.g., PH10a, PH10b) without interference. Figure 3As shown, after the transmission control signal PH9 transitions to an invalid level (low level), the independent drive signal applied to the shunt gate electrode corresponding to the target branch path transitions to an invalid level (low level) later than the independent drive signals applied to other shunt gate electrodes. The target branch path refers to a specific path (e.g., path A composed of PH10a, PH11a, PH12a, etc.) preset for receiving and further transmitting the batch of charges according to specific acquisition requirements. By making the drive signal of the target branch path (e.g., PH10a) transition to an invalid level later than that of non-target branch paths (e.g., PH10b), the charges can be guided precisely to converge towards the target branch path for subsequent transfer, storage, or readout.

[0070] like Figures 1 to 3 As shown, the control component in this embodiment further includes the substrate, the gate oxide layer, and a plurality of control gate electrodes arranged along the second direction; the plurality of control gate electrodes are disposed on the gate oxide layer and are respectively disposed adjacent to the output side of the shunt gate electrode corresponding to the branch path.

[0071] The control components of the first-stage shunt structure include the substrate 11, the gate oxide layer 12, and a plurality of first-stage control gate electrodes (i.e., PH11a, PH11b) arranged along the second direction. The first-stage control gate electrodes PH11a and PH11b are disposed on the gate oxide layer 12 and are respectively disposed adjacent to the output sides of the corresponding branch gate electrodes PH10a and PH10b. In this embodiment, by applying mutually exclusive control signals to the control gate electrodes PH11a and PH11b, the charge from the first-stage branch component can be selectively directed to the next-stage shunt structure.

[0072] The control component of the second-stage shunt structure also includes the substrate 11 and the gate oxide layer 12, and includes a plurality of second-stage control gate electrodes TXa, TXb, TXc, and TXd arranged along the second direction. The plurality of control gate electrodes TXa, TXb, TXc, and TXd are disposed on the gate oxide layer 12 and are respectively adjacent to the output side of the second-stage shunt gate electrodes PH12a, PH12b, PH12c, and PH12d corresponding to the branch paths. In this embodiment, each control gate electrode TXa, TXb, TXc, and TXd corresponds to one branch path, used to control the final output of the charge of that path to the corresponding subsequent floating diffusion regions FDa, FDb, FDc, and FDd.

[0073] Through the cooperation of the two-stage control components described above, this embodiment can achieve the step-by-step guidance and allocation of the charge transfer path in the second direction.

[0074] Furthermore, in this embodiment, the plurality of control gate electrodes respectively receive a plurality of independent control drive signals; the effective level start time of each control drive signal is no later than the effective level end time of the corresponding shunt control signal, and its effective level end time lags behind the effective level end time of the corresponding shunt control signal; wherein, the effective levels of the control drive signals applied to different control gate electrodes do not overlap in time, so that each branch path is turned on in turn at different time periods.

[0075] refer to Figure 3 The effective start time of each control drive signal is no later than the effective end time of the corresponding shunt control signal. Specifically, taking the first branch path as an example, the effective start time of the control drive signal applied to the control gate electrode TXa (e.g., high level) is earlier than or equal to the effective end time of the shunt control signal applied to its preceding corresponding shunt gate electrode PH12a. This timing setting ensures that the output-side control gate electrode TXa is already in the on state before the effective level of the shunt gate electrode PH12a ends, thereby eliminating the potential barrier during the charge transfer to the output end and ensuring that the charge temporarily stored below the shunt gate electrode can be completely transferred to the subsequent path.

[0076] Simultaneously, the effective level end time of each of the control drive signals lags behind the effective level end time of the corresponding shunt control signal. That is, when the shunt control signal of the shunt gate electrode PH12a changes from an effective level to an ineffective level (e.g., from a high level to a low level), the control gate electrode TXa still maintains an effective level. Through this timing difference, the residual charge below the shunt gate electrode PH12a can be completely transferred to the control gate electrode TXa, thereby improving the charge transfer efficiency.

[0077] Wherein, the effective levels of the control drive signals of the control gate electrodes (such as TXa and TXb, TXc and TXd) corresponding to the shunt paths applied to the same shunt gate electrode do not overlap in time, wherein the effective levels of the control drive signals of the control gate electrodes TXa and TXc, TXb and TXd are allowed to overlap in time. Reference Figure 3 The waveform distribution of the four control signals shows that the pulses of adjacent branch path signals are alternately arranged and separated from each other on the time axis. This configuration allows adjacent branch paths to be turned on in turn at different time periods; that is, at any given moment, two adjacent control gate electrodes will not be turned on simultaneously. Through this locally mutually exclusive time-division control, charges from different sampling periods are precisely allocated to the corresponding floating diffusion regions FDa, FDb, FDc, and FDd, avoiding crosstalk and aliasing of charges between different paths, thereby improving the accuracy of the shunt signal.

[0078] In this embodiment, each of the signal output units includes a floating diffusion node disposed within the substrate; the floating diffusion node is disposed beside the output side of the final stage control component.

[0079] like Figures 1-3 The floating diffusion nodes FDa, FDb, FDc, and FDd are respectively disposed beside the output side of the final-stage control component. Specifically, in the two-stage shunt structure of this embodiment, the final-stage control component is a component composed of multiple control gate electrodes TXa, TXb, TXc, and TXd. The floating diffusion nodes FDa, FDb, FDc, and FDd are located downstream of the control gate electrodes TXa, TXb, TXc, and TXd in the first direction (X direction), and are arranged one-to-one with each of the control gate electrodes in the second direction. Continuing with the aforementioned time-division control, when one of the control gate electrodes TXa, TXb, TXc, and TXd (e.g., TXa) receives a valid level signal and is turned on, the corresponding branch path is activated. Charge is transferred from below the corresponding shunt gate electrode PH12a, passes below the turned-on control gate electrode TXa, and is finally injected into the corresponding floating diffusion node FDa for storage, and is then converted into a voltage signal output by subsequent circuitry. By independently setting each of the floating diffusion nodes FDa, FDb, FDc, and FDd on the output side of each of the control gate electrodes TXa, TXb, TXc, and TXd, this embodiment can perform parallel and non-interfering charge-voltage conversion and reading of each charge signal after multi-stage shunting.

[0080] On the other hand, the present invention also provides a pixel structure control method, comprising the following steps: applying an M-phase clock drive signal to a plurality of first gate electrodes of the photosensitive transmission unit, causing a 1 / M-period phase lag in the clock drive signal between adjacent first gate electrodes, so as to drive charge to be transmitted along a first direction to the charge transfer unit; applying a transmission control signal to the transfer gate electrode of the charge transfer unit, so that it is turned on during the period when the photosensitive transmission unit outputs charge, and receives the charge; applying a shunt control signal and a control drive signal to a plurality of shunt gate electrodes and a control gate electrode of the shunt unit respectively; wherein, by alternately changing the level state of the control drive signal corresponding to different branch paths, the continuously transmitted charge packets are sequentially shunted to different branch paths; and the plurality of signal output units alternately convert the received charge into voltage signals and output them in parallel.

[0081] In this embodiment, an M-phase clock drive signal is applied to the plurality of first gate electrodes of the photosensitive transmission unit. In this embodiment, a control circuit causes the clock drive signal between adjacent first gate electrodes to have a phase lag of 1 / M period, thereby driving the photogenerated charge to be continuously transferred to the charge transfer unit along the first direction.

[0082] In this embodiment, a transfer control signal is applied to the transfer gate electrode of the charge transfer unit. (Reference) Figure 3 When the charge transfer unit includes a plurality of transfer gate electrodes arranged along the first direction, each transfer gate electrode is respectively applied with a transmission control signal having a preset phase difference; wherein, the transmission control signal applied to the first transfer gate electrode is used to control it to receive the charge when the photosensitive transmission unit outputs charge; the start time of the effective level of the transmission control signal applied to each subsequent transfer gate electrode is sequentially delayed relative to the start time of the effective level of the previous transfer gate electrode, and further, the start time of the effective level of the transmission control signal applied to the first transfer gate electrode is earlier than the end time of the effective level of the clock drive signal applied to the last first gate electrode, and the end time of its effective level is later than the end time of the effective level of the clock drive signal applied to the last first gate electrode.

[0083] In this embodiment, shunt control signals and control drive signals are applied to the multiple shunt gate electrodes and control gate electrodes of the shunt unit, respectively. Specifically, by alternately changing the level of the control drive signals corresponding to different branch paths, the charge continuously transmitted along the first direction is sequentially shunted to different branch paths in the second direction. For example, during a first time period, only the signal of the control gate electrode TXa corresponding to the first branch path is activated, and the charge enters the first branch path.

[0084] In this embodiment, multiple signal output units alternately convert the received charges into voltage signals and output them in parallel. Specifically, the charge packets entering each branch path are stored in the corresponding floating diffusion nodes FDa, FDb, FDc, and FDd. Since each path is turned on in turn in time, each node alternately completes charge accumulation and realizes parallel reading of multiple signals through its corresponding output circuit (such as a source follower, a selection transistor, etc.).

[0085] In this embodiment, when charge needs to be output via a specific branch path, the control drive signal of the previous stage and the shunt control signal of the next stage are simultaneously switched to an effective level, and the end time of the shunt control signal is kept lagging behind the end time of the transmission control signal. (Reference) Figure 3The logic relationship of each control signal is as follows: when charge needs to be output through a specific branch path (e.g., the path corresponding to TXa), timing control simultaneously switches the shunt control signal (e.g., PH12a) and the control drive signal (TXa) on that branch path to an active level. Furthermore, the end time of the shunt control signal (PH12a) is kept lagging behind the end time of the transmission control signal of the transfer gate electrode. This ensures that during the transfer of charge from the charge transfer unit to the shunt unit, the downstream shunt gate electrode PH12a maintains a low potential barrier or a deep potential well, using the potential gradient to drive the charge completely into the target branch path, avoiding charge backflow or residue at the transfer interface, and improving shunt efficiency.

[0086] Combination Figures 1 to 3 The control process is explained using the example of charge transport along the first direction (X direction) and readout via the control gate electrode TXc to the floating diffusion node FDc: In the photosensitive transmission unit, charge movement is driven by a multiphase clock. During the last pixel photosensitive cycle, the clock drive signal of the first gate electrode PH1 changes from high to low at time t1, while simultaneously, the clock drive signal of the first gate electrode PH5 changes from low to high at time t1, thus forming charge transport along the X direction. In the photosensitive transmission unit, the clock drive signal applied to the subsequent first gate electrode lags behind the previous first gate electrode by 1 / 8 period (i.e., M=8). For example, the first gate electrode PH2 is the electrode following PH1, and its drive voltage signal changes from high to low at time t2. Simultaneously, the first gate electrode PH6 is the electrode following PH5, and its drive voltage signal changes from low to high at time t2, satisfying t2-t1=T. 1 / 8, where T is the period of the driving voltage signal.

[0087] In the readout region formed by the charge transfer unit and subsequent shunt structure, the reference Figure 3 When the charge is transferred to the charge transfer unit at time t5, the shunt control signals of the transfer gate electrode and each shunt gate electrode of the first-stage shunt structure simultaneously change from low to high at time t5 to generate a sufficiently deep potential well to receive and guide the charge from the photosensitive transmission unit. If the charge ultimately needs to be read out to the floating diffusion node FDc via the control gate electrode TXc, then at time t6, the shunt control signals of the shunt gate electrodes PH12c and PH12d on this side of the second-stage shunt structure simultaneously change from low to high. At the same time, since the charge needs to be guided to the branch where the control gate electrode PH11b is located, the driving voltage signal applied to the control gate electrode PH11a on the other side of the first-stage shunt structure remains at a low level, thereby blocking the charge from entering the branch on that side.

[0088] To ensure efficient directional charge movement to the output, a timing gradient exists between the electrodes within the first-stage shunt structure. Since the charge needs to be transferred to the FDc via the channel region corresponding to the control gate electrode PH11b, the control drive signal for the control gate electrode PH11b lags behind the transfer control signal for the transfer gate electrode. (Refer to...) Figure 3 The transfer control signal for the gate electrode changes from high to low at time t7, while the control drive signal for the gate electrode PH11b changes from high to low at time t8. t8 - t7 = T 1 / 16, through the potential thrust generated by this step-by-step shutdown, drives the charge to transfer to the second-stage shunt structure.

[0089] In this embodiment, charge is transported along the X direction, read out through the control gate electrode TXc, and then to the floating diffusion node FDc. (Refer to...) Figure 3 Under similar timing control, charge can be transferred along the X direction and read out through the control gate electrodes TXa, TXb, and TXd to the floating diffusion nodes FDa, FDb, and FDd, respectively. It should be noted that the charge is read out alternately during shunt readout.

[0090] In practical implementation, the duration of the high-level pulse, the duration of the low-level pulse, and the slope of the rising and falling edges during level changes of the applied drive voltage signal can be adjusted according to actual usage. The readout pulse width of each control gate electrode TXa to TXd can also be set according to actual conditions, as long as it is ensured that the charge in the channel region corresponding to the last shunt gate electrode in the shunt unit can be completely transferred to the corresponding control gate electrode and floating diffusion node.

[0091] By using the aforementioned pixel structure and its control timing, the charge transfer speed within the pixel can be improved, enabling parallel processing of four branch paths, thereby significantly enhancing the image sensor's operating speed and charge transfer efficiency.

[0092] On the other hand, the present invention also provides an image sensor, comprising: a pixel array composed of a plurality of the aforementioned pixel structures arranged in rows and columns; a driving circuit for generating the clock driving signal, the transmission control signal, the shunt control signal, and the control driving signal; and a readout circuit comprising multiple sets of parallel analog-to-digital converters (ADCs).

[0093] A pixel array is composed of several pixel structures arranged in rows and columns. In this embodiment, the pixel array adopts a TDI (Time Delay Integration) structure, in which multiple photosensitive units of pixels in each column are arranged along the charge transfer direction (such as the X direction).

[0094] The driving circuit generates various logic signals involved in the control method described above, including: an M-phase clock driving signal (such as PH1 to PH8) applied to the photosensitive transmission unit, a transmission control signal applied to the charge transfer unit, and a shunt control signal applied to the shunt unit. The driving circuit ensures high-speed, residue-free, and directional charge transfer between each stage of the gate electrode through timing control.

[0095] In some embodiments, a readout circuit is connected to the output of the pixel array. The readout circuit includes multiple parallel analog-to-digital converters (ADCs). In the pixel structure, the signal output unit of each branch path includes a floating diffusion node (FD), a reset transistor, a source follower, and a selection transistor. Charge is converted into an analog voltage signal at the floating diffusion node, amplified and buffered by the source follower, and then transmitted to the readout bus under the control of the selection transistor.

[0096] In some embodiments, each group of ADCs corresponds to one or more branch paths of the pixel structure. Through these parallel ADCs, the analog voltage signals output by each path can be converted into digital signals in real time. This parallel readout matches the aforementioned multi-stage shunt structure, effectively alleviating the data processing pressure caused by the extremely high line frequency, thereby meeting the high bandwidth data output requirements brought about by high-speed charge shunt, and ensuring that the image sensor still has good linearity and dynamic range under high-speed operation.

[0097] Optionally, in each column of the pixel array, adjacent pixel structures share the same substrate and charge transport channels are continuously arranged. (Reference) Figure 1 Based on the TDI (Transmission Discharge) working principle, in each column of the pixel array, adjacent pixel structures share the same substrate and their charge transport channels are continuously arranged. Specifically, the charge generated by the photosensitive structure of the preceding pixel is transported along the channel to the following pixel structure under the action of a clock drive signal, and is superimposed with the charge generated by the photosensitive structure of the following pixel in the charge storage area, and so on. This continuously arranged channel structure enables the accumulation of photogenerated charge during the transport process.

[0098] In the image sensor provided in this embodiment of the invention, the problem of limited single-channel readout speed in traditional TDI-CMOS sensors is solved by introducing a multi-stage shunt structure and parallel readout circuits at the end of the TDI readout area. Since the continuous charge packets generated by each column of pixels are alternately shunt to four different branch paths (TXa~TXd), the conversion time pressure of a single-channel ADC is reduced to one-quarter of the original. This sensor maintains extremely high charge transfer efficiency while supporting higher line frequencies, meeting the needs of industrial inspection and other applications for ultra-high-speed, high-sensitivity imaging.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A pixel structure, characterized in that, include: The photosensitive transmission unit is configured to accumulate and drive charge to be transmitted along a first direction under the action of a clock drive signal; A charge transfer unit is disposed on the output side of the photosensitive transmission unit in the first direction, and is used to receive and transfer charge; A shunt unit is disposed on the output side of the charge transfer unit. The shunt unit includes at least one shunt structure sequentially adjacent to each other along the first direction. Each shunt structure includes a branch component and a control component. The branch component is configured to provide multiple branch paths for charge transport entering the shunt structure. The control component is configured to selectively conduct or block each branch path. Multiple signal output units are provided, each of which is disposed on the output side of the branch path of the final stage shunt structure, for receiving charge from the corresponding branch path and performing signal conversion.

2. The pixel structure according to claim 1, characterized in that, The photosensitive transmission unit includes at least one level of pixel photosensitive units arranged along the first direction; wherein each level of the pixel photosensitive unit includes a substrate, a gate oxide layer disposed on the substrate, and a plurality of first gate electrodes disposed on the gate oxide layer and arranged along the first direction; the plurality of first gate electrodes are insulated from each other; the plurality of first gate electrodes are configured to integrate photogenerated charge and drive it to be transmitted along the first direction under the action of the clock drive signal.

3. The pixel structure according to claim 2, characterized in that, Each pixel photosensitive unit includes M first gate electrodes arranged along the first direction, where M is an even number not less than 4; wherein the phase difference between the clock drive signals received by two adjacent first gate electrodes along the first direction is 1 / M of the clock drive signal period.

4. The pixel structure according to claim 3, characterized in that, The charge transfer unit includes the substrate, the gate oxide layer, and at least one transfer gate electrode disposed downstream of the photosensitive transmission unit along the first direction; the transfer gate electrode is disposed on the gate oxide layer and located between the photosensitive transmission unit and the shunt unit; along the first direction, the upstream end of the transfer gate electrode is disposed adjacent to the last first gate electrode in the photosensitive transmission unit, and the downstream end of the transfer gate electrode is disposed adjacent to the first-stage shunt structure in the shunt unit.

5. The pixel structure according to claim 4, characterized in that, When the charge transfer unit includes a plurality of transfer gate electrodes arranged along the first direction, each of the transfer gate electrodes receives a transmission control signal with a preset phase difference; wherein, the transmission control signal received by the first transfer gate electrode is used to control it to receive the charge when the photosensitive transmission unit outputs the charge; the start time of the effective level of the transmission control signal received by each subsequent transfer gate electrode is sequentially delayed relative to the start time of the effective level of the previous transfer gate electrode.

6. The pixel structure according to claim 5, characterized in that, The transmission control signal applied to the first of the transfer gate electrodes has an effective level start time earlier than the effective level end time of the clock drive signal applied to the last of the first gate electrodes, and its effective level end time is later than the effective level end time of the clock drive signal applied to the last of the first gate electrodes.

7. The pixel structure according to claim 6, characterized in that, The lateral width of the transfer gate electrode gradually narrows along the first direction to improve the charge shunting efficiency.

8. The pixel structure according to claim 5, characterized in that, The branching assembly includes the substrate, the gate oxide layer, and a plurality of shunt gate electrodes arranged along a second direction perpendicular to the first direction; the plurality of shunt gate electrodes are disposed on the gate oxide layer, and the proximal ends of the plurality of shunt gate electrodes in the charge transport direction of the first-stage branching assembly are disposed adjacent to the distal ends of the transfer gate electrode in the charge transport direction.

9. The pixel structure according to claim 8, characterized in that, The plurality of shunt gate electrodes are electrically connected to the shunt control signal; the plurality of shunt gate electrodes are configured to receive the charge output from the charge transfer unit under the action of the shunt control signal and shunt it to their respective corresponding branch paths.

10. The pixel structure according to claim 9, characterized in that, The timing of the shunt control signal is configured such that the start time of its effective level is no later than the start time of the effective level of the transmission control signal applied by the last transfer gate electrode, and the end time of its effective level lags behind the end time of the effective level of the transmission control signal, so that after the transmission control signal transitions to an invalid level, the shunt gate electrode continuously receives and temporarily stores the charge from the charge transfer unit.

11. The pixel structure according to claim 10, characterized in that, The shunt control signal includes independent drive signals applied to each of the shunt gate electrodes; after the transmission control signal is converted to an invalid level, the independent drive signal applied to the shunt gate electrode corresponding to the target branch path is converted to an invalid level at a time that lags behind the time when the independent drive signals applied to other shunt gate electrodes are converted to an invalid level.

12. The pixel structure according to claim 9, characterized in that, The control component includes the substrate, the gate oxide layer, and a plurality of control gate electrodes arranged along the second direction; the plurality of control gate electrodes are disposed on the gate oxide layer and are respectively disposed adjacent to the output side of the shunt gate electrode corresponding to the branch path.

13. The pixel structure according to claim 12, characterized in that, The plurality of control gate electrodes respectively receive a plurality of independent control drive signals; the effective level start time of each control drive signal is no later than the effective level end time of the corresponding shunt control signal, and the effective level end time lags behind the effective level end time of the corresponding shunt control signal; wherein, the effective levels of the control drive signals applied to different control gate electrodes do not overlap in time, so that each branch path is turned on in turn at different time periods.

14. The pixel structure according to claim 1, characterized in that, Each of the signal output units includes a floating diffusion node disposed within the substrate; the floating diffusion node is disposed beside the output side of the final stage control component.

15. A method for controlling a pixel structure as described in any one of claims 1 to 14, characterized in that, Includes the following steps: An M-phase clock drive signal is applied to a plurality of first gate electrodes of the photosensitive transmission unit, causing a 1 / M-period phase lag in the clock drive signal between adjacent first gate electrodes, so as to drive charge to be transferred to the charge transfer unit along the first direction. When the charge transfer unit includes a plurality of transfer gate electrodes arranged along the first direction, a transmission control signal with a preset phase difference is applied to each of the transfer gate electrodes; wherein, the transmission control signal applied to the first transfer gate electrode is used to control it to receive the charge when the photosensitive transmission unit outputs charge; the start time of the effective level of the transmission control signal applied to each subsequent transfer gate electrode is sequentially delayed relative to the start time of the effective level of the previous transfer gate electrode; the start time of the effective level of the transmission control signal applied to the first transfer gate electrode is earlier than the end time of the effective level of the clock drive signal applied to the last first gate electrode, and the end time of the effective level of the transmission control signal applied to the last first gate electrode is later than the end time of the effective level of the clock drive signal applied to the last first gate electrode; A shunt control signal and a control drive signal are applied to the multiple shunt gate electrodes and control gate electrodes of the shunt unit, respectively; wherein, by alternately changing the level state of the control drive signal corresponding to different branch paths, the continuously transmitted charge packets are sequentially shunted to different branch paths; The multiple signal output units alternately convert the received charges into voltage signals and output them in parallel.

16. The control method according to claim 15, characterized in that, When charge needs to be output through a specific branch path, the control drive signal of the previous stage and the shunt control signal of the next stage are switched to active levels simultaneously, and the end time of the shunt control signal is kept lagging behind the end time of the transmission control signal.

17. An image sensor, characterized in that, include: A pixel array, comprising a plurality of pixel structures as described in any one of claims 1 to 14 arranged in rows and columns; A driving circuit is used to generate the clock driving signal, the transmission control signal, the shunt control signal, and the control driving signal; The readout circuitry includes multiple sets of parallel-configured analog-to-digital converters (ADCs).

18. The image sensor according to claim 17, characterized in that, In each column of the pixel array, adjacent pixel structures share the same substrate and charge transport channels are continuously arranged.

Images