Image sensor and method of controlling the same, electronic device

Abstract

The application provides an image sensor and a control method thereof and an electronic device, wherein the control method of the image sensor comprises: acquiring an integral charge signal based on the image sensor; acquiring a reset signal based on the integral charge signal; acquiring a first image signal and a second image signal with different gains based on the integral charge signal, and acquiring a first quantization signal and a second quantization signal based on the reset signal and corresponding image signals; and acquiring an actual signal of an image based on the first quantization signal and the second quantization signal. Based on the above scheme, through the design of the image sensor and the control method thereof, based on single-frame HDR technology, the problems of difficulty in effectively implementing high dynamic range and existence of artifacts or ghosting in multi-frame HDR in the prior art can be solved.

Description

Technical Field

[0001] This invention belongs to the field of image acquisition technology, and in particular relates to an image sensor, its control method, and corresponding electronic equipment. Background Technology

[0002] Image sensors are a crucial component of digital cameras. Based on the different components, they can be divided into two main categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal-Oxide Semiconductor).

[0003] With the continuous development of CMOS integrated circuit manufacturing processes, especially the design and manufacturing processes of CMOS image sensors (CIS), CMOS image sensors have gradually replaced CCD image sensors as the mainstream. Compared with CCD, CMOS image sensors have advantages such as low voltage, low power consumption, low cost, and high integration, and have important application value in fields such as machine vision, consumer electronics, high-definition surveillance, and medical imaging.

[0004] To deliver good image quality in scenes with varying brightness, CMOS image sensors require high dynamic range (HDR). A common HDR implementation is time-domain multi-frame HDR, which involves capturing multiple underexposed to overexposed images of a specific scene with different exposure parameters, and then combining these images. Underexposure preserves detail in bright areas, while overexposure better restores detail in dark areas, resulting in a composite image that effectively captures the overall scene. However, because it combines images captured at different times, artifacts or ghosting are easily produced when photographing fast-moving subjects, which is an unacceptable drawback.

[0005] Therefore, it is essential to provide an image sensor and its control method, as well as an electronic device, to solve the problems of high dynamic range being difficult to achieve effectively and artifacts existing in multi-frame HDR in the prior art.

[0006] The above background information is provided solely for the purpose of clearly and completely explaining the technical solutions of this invention and facilitating understanding by those skilled in the art. It should not be assumed that these solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an image sensor, control method, and electronic device to solve the problem that the prior art is unable to effectively acquire high dynamic range images.

[0008] To achieve the above and other related objectives, the present invention provides a control method for an image sensor, the control method comprising:

[0009] Integrated charge signals are acquired using an image sensor;

[0010] The reset signal is obtained based on the integrated charge signal;

[0011] Based on the integrated charge signal, first image signals and second image signals with different gains are obtained, and based on the reset signal and the corresponding image signal, first quantization signal and second quantization signal are obtained;

[0012] The actual signal of the image is obtained based on the first quantization signal and the second quantization signal.

[0013] The present invention also provides an image sensor, which can be prepared using the control method described above. Of course, other control methods can also be used. The image sensor includes:

[0014] A pixel array includes pixel units arranged in an array, wherein the pixel units are used to acquire an integrated charge signal and output a corresponding pixel reset signal and a pixel image signal based on the integrated charge signal;

[0015] An analog-to-digital conversion circuit includes a comparator-counter circuit that receives a ramp signal and acquires a corresponding reset signal, a first image signal, and a second image signal based on the ramp signal, the pixel reset signal, and the pixel image signal; and...

[0016] The data processing circuit is used to obtain the actual signal for improving the dynamic range of the single frame corresponding to the integrated charge signal based on the reset signal, the first image signal and the second image signal.

[0017] The present invention also provides an electronic device including an image sensor as described in any of the above embodiments.

[0018] As described above, the image sensor and its control method and electronic device of the present invention have the following beneficial effects: Through the design of the image sensor and its control method, this application can solve the problems of high dynamic range being difficult to achieve effectively in the prior art and artifacts or ghosting in multi-frame HDR based on single-frame HDR technology. Attached Figure Description

[0019] Figure 1 The diagram shows the basic structure of an image sensor system.

[0020] Figure 2 The diagram shows a pixel circuit of an image sensor.

[0021] Figure 3 The flowchart shown is a process for controlling an image sensor in an embodiment of this application.

[0022] Figure 4 The diagram shown is a timing diagram of the control logic for an image sensor in an embodiment of this application.

[0023] Figure 5 The diagram shown is a schematic representation of an image sensor structure according to an embodiment of this application.

[0024] Figure 6 The diagram shown is a schematic of a ramp generation circuit for an image sensor in an embodiment of this application.

[0025] Figure 7 The diagram shown is a pixel circuit schematic of a pixel unit of an image sensor in an embodiment of this application.

[0026] Figure 8 This is shown as the quantization time required for a 10-bit ADC system in the control of a pair of proportional image sensors.

[0027] Figure 9 This is shown as the quantization time required for a 12-bit ADC system in the control of a pair of proportional image sensors.

[0028] Figure 10 The figure shows the quantization time required for a control logic of an image sensor according to an embodiment of this application.

[0029] Component designation explanation

[0030] 10 - Pixel unit; 20 - Analog-to-digital conversion circuit; 30 - Data processing circuit; 40 - Ramp generation circuit. Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0033] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments. For ease of explanation in the detailed description of embodiments of the invention, cross-sectional views illustrating device structures may be partially enlarged and not to scale; these schematic diagrams are merely examples and should not limit the scope of protection of the invention. In actual fabrication, three-dimensional spatial dimensions of length, width, and depth should be included.

[0034] For ease of description, spatial relation terms such as "below," "below," "lower than," "below," "above," and "above" may be used herein to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more layers in between. The described structure of a first feature "above" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0035] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] Figure 1 The diagram shows a basic block structure of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. A functional logic unit is connected to the readout circuit, and the readout circuit and control circuit are connected to a status register to control the pixel array. The pixel array includes multiple pixels (P1, P2, P3) arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). The pixel signals output by the pixel array are output to the readout circuit via column lines. In specific implementations, the readout circuit may include an analog-to-digital converter (ADC) and other circuits. In some applications, after the pixels acquire image data, they are read out using the readout mode specified by the status register and then transmitted to the functional logic unit.

[0037] In some applications, the status register may contain a programmed selection system to determine whether the readout system uses rolling shutter or global shutter exposure. The functional logic unit may store raw image data or image data after image processing. In some implementations, the readout circuitry may read one row of image data at a time along the readout column lines; other methods may also be used. The operation of the control circuitry can be determined by the current settings in the status register. For example, the control circuitry generates a shutter signal to control image acquisition. In some applications, this shutter signal may be a global shutter signal, allowing all pixels in the pixel array to acquire their image data simultaneously through a single acquisition window. In other applications, this shutter signal may be a rolling shutter signal, allowing pixels in each row of the pixel array to be continuously exposed and read through the acquisition window.

[0038] Figure 2 This diagram illustrates a pixel unit in an image sensor. As shown, each pixel unit includes a photoelectric conversion element (e.g., a photodiode) and pixel circuitry (shown as a transistor within the dashed box). The photodiode can be a buried photodiode (PPD) used in current image sensors. In one application example, the pixel circuitry includes a reset transistor (RST), a source follower transistor (SF), and a pixel select transistor (RS), connected to, for example... Figure 2 The diagram shows a transfer transistor (TX) and a photodiode. In some applications, the pixel circuitry is stacked, including a reset transistor, a source follower transistor, and a pixel select transistor on a first circuit chip, and a transfer transistor on a second circuit chip, where the photodiode is connected to other transistors on the first circuit chip via the transfer transistor. In further applications, the pixel circuitry may also include a gain control transistor (DCG) connected between the floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photocharge in response to incident light during exposure. The transfer transistor is connected to a transfer signal that controls the transfer transistor to transfer the accumulated charge in the photoelectric conversion element to the floating diffusion region. The reset transistor is connected between the power supply voltage and the floating diffusion region, and in response to a reset signal, resets the sensor pixel circuitry (e.g., discharges or charges the floating diffusion region and the photodiode to the current voltage). The floating diffusion region is connected to the gate of the source follower transistor, which is connected between the power supply voltage and the pixel select transistor, responding to and outputting the potential of the floating diffusion region. The pixel select transistor is connected to the source follower transistor and the bit line, and in response to a pixel select control signal, performs pixel selection readout and outputs it to the readout column.

[0039] To deliver superior image quality across varying brightness levels, CMOS image sensors require a high dynamic range. A common HDR implementation is time-domain multi-frame HDR, which involves capturing multiple underexposed to overexposed images of a specific scene with varying exposure parameters, then combining these images. Underexposure preserves detail in bright areas, while overexposure better restores detail in dark areas, resulting in a composite image that effectively captures the entire scene. However, because images captured at different times are combined, artifacts or ghosting are easily produced with fast-moving subjects, a significant drawback. This application addresses these issues by designing an image sensor and its control method, using single-frame HDR technology to solve the problems of achieving high dynamic range effectively and artifacts / ghosting in multi-frame HDR.

[0040] The following will describe the specific embodiments in detail.

[0041] Example 1:

[0042] Please see Figure 3 As shown, this embodiment provides a control method for an image sensor. Figure 3 The flowchart shown is for this control method, which includes the following steps:

[0043] S1: Acquire integrated charge signal based on image sensor;

[0044] S2: Obtain the corresponding reset signal based on the integrated charge signal;

[0045] S3: Based on the integrated charge signal, obtain a first image signal and a second image signal with different gains, and based on the first image signal and the second image signal, obtain a first quantization signal and a second quantization signal;

[0046] S4: Obtain the actual signal of the image based on the first quantization signal and the second quantization signal.

[0047] In the image sensor and its control in this embodiment, based on single-frame HDR technology, the first and second quantization signals corresponding to the integrated charge signal are acquired. This achieves high dynamic range without requiring multi-frame synthesis; a single frame can be output, effectively avoiding artifacts or ghosting issues in high-speed shooting. Furthermore, while achieving high dynamic range, it effectively reduces the additional quantization time and significantly reduces the additional power consumption. It should be noted that the existing operational sequence in the above steps can be changed according to actual needs without affecting the beneficial effects of this application.

[0048] The control method of the image sensor of this application will be described in detail below with reference to specific implementation methods.

[0049] First, step S1 is performed to acquire the integrated charge signal based on the image sensor.

[0050] Specifically, the integrated charge signal can refer to the charge signal representing the image to be captured, acquired by pixels in an image sensor based on photoelectric conversion. The image sensor can be a CMOS image sensor, comprising a pixel array. The pixel array includes pixel units arranged in an array. A pixel unit can be a non-shared unit consisting of a single photoelectric conversion element and its corresponding pixel circuit, or a shared unit consisting of at least two photoelectric conversion elements and their shared pixel circuits. During the operation of the image sensor, an exposure process occurs. Generally, a global reset process is performed before exposure. During this exposure process, the photoelectric conversion element in the pixel unit receives incident light and performs photoelectric conversion to generate a corresponding integrated charge signal. Furthermore, the pixel unit outputs a corresponding pixel reset signal and a pixel image signal based on the integrated charge signal. Both the pixel reset signal and the pixel image signal are analog voltage signals output by the pixel unit.

[0051] Next, proceed to step S2, where the corresponding reset signal is obtained based on the integrated charge signal.

[0052] Specifically, the operation of the image sensor includes a readout process, during which the reset signal corresponding to the integrated charge signal and the image signal are read, i.e., the pixel reset signal and the pixel image signal are read. In one implementation, the floating diffusion node FD of the pixel circuit is reset, and the self-output transistor SF outputs the reset signal corresponding to the integrated charge signal. Further, the integrated charge signal in the photoelectric conversion element PD is transferred to the floating diffusion node FD, and the self-output transistor SF outputs the image signal corresponding to the integrated charge signal. The transfer of the integrated charge signal can be controlled based on the transfer control transistor TX, and the transfer of the integrated charge signal in the photoelectric conversion element PD can be performed after the reset signal is read out.

[0053] In this process, after the pixel unit outputs the pixel reset signal, it is quantized to obtain a reset signal. The quantized reset signal can be a digital signal for subsequent acquisition of actual signals.

[0054] Next, step S3 is performed, where a first image signal and a second image signal with different gains are obtained based on the integrated charge signal, and a first quantization signal and a second quantization signal are obtained based on the first image signal and the second image signal. The first image signal and the second image signal with different gains can be obtained based on an analog-to-digital converter circuit. Similarly, the reset signal mentioned in the previous step can also be obtained based on an analog-to-digital converter circuit.

[0055] Specifically, during the readout process, the image signal corresponding to the integrated charge signal is read. In this step, two image signals are obtained based on the integrated charge signal. The first image signal is a signal obtained by quantizing the integrated charge signal at the first analog gain after it is transferred to the floating diffusion node and output through the output transistor. It can be a digital signal and represents the image information at the first analog gain. Similarly, the second image signal is a signal obtained by quantizing the integrated charge signal at the second analog gain after it is transferred to the floating diffusion node and output through the output transistor. It can be a digital signal and represents the image information at the second analog gain.

[0056] Furthermore, the first quantization signal is a signal corresponding to the first image signal used for subsequent actual signal acquisition of the image, and can be a subsequent first actual sub-signal. The second quantization signal is another signal corresponding to the second image signal used for subsequent actual signal acquisition of the image, and can be a subsequent second actual sub-signal. An actual signal is formed based on the first and second actual sub-signals. This actual signal is realized in a single frame relative to the integrated charge signal and has an improved dynamic range.

[0057] In this application, a high dynamic range (HDR) image is formed based on a single frame of data, corresponding to two images with different gains. The HDR image can then be synthesized from these two images. A single-frame HDR image can be achieved using analog dual-gain technology, where the quantization ADC uses two different gain conditions to quantize the signal; for example, low gain is used for bright areas, and high gain is used for dark areas. This achieves high dynamic range without requiring multi-frame synthesis; a single frame can be output, effectively mitigating artifacts or ghosting issues in high-speed shooting. Achieving high dynamic range based on the analog-to-digital conversion circuit avoids losses in pixel circuit area, further facilitating pixel miniaturization.

[0058] As an example, the first quantization signal corresponds to the first gain, which is the first analog gain, and the second quantization signal corresponds to the second gain, which is the second analog gain, wherein the magnitude of the second gain is smaller than the magnitude of the first gain; wherein the steps of obtaining the first quantization signal and the second quantization signal based on the integrated charge signal include: first obtaining the first image signal, then obtaining the second image signal, and / or, first obtaining the first quantization signal, then obtaining the second quantization signal.

[0059] In other words, in this example, the first image signal under high analog gain (HCG) is acquired first, followed by the second image signal under low analog gain (LCG). Furthermore, the first quantized signal corresponding to the first image signal under high analog gain is acquired first, followed by the second quantized signal corresponding to the second image signal under low analog gain. In this example, the acquisition order of the image signal and the quantized signal corresponds consistently, which helps improve data accuracy. In other examples, other correspondence methods can be used to acquire the signals.

[0060] As an example, the second gain is smaller than the first gain, and the analog gain of the reset signal is selected to be the same as that of the high-gain first image signal, which is beneficial to improve readout efficiency and optimize power consumption requirements.

[0061] Specifically, the reset signal is acquired at the first gain. That is, the data readout process corresponding to the integrated charge signal includes the reset signal at the first gain, the first image signal at the first gain, and the second image signal at the second gain. In a further optional example, the reset signal (rst) at the first gain, the first image signal (hcgsig) at the first gain, and the second image signal (lcg sig) at the second gain are read out sequentially, which facilitates gain adjustment. For the acquisition of the three signals, see [link to documentation]. Figure 4 As shown.

[0062] As an example, a reset signal is acquired before the first and second image signals are acquired.

[0063] In one implementation, the first quantized signal is the difference between the first image signal and the reset signal, and the second quantized signal is the difference between the second image signal and the reset signal. The reset signal can be acquired before the first and second image signals are acquired; that is, the actual signal is obtained by performing correlation double sampling on the corresponding image signal and the reset signal, thereby improving data accuracy.

[0064] As an example, the steps for obtaining first and second image signals with different gains include:

[0065] The first image signal and the second image signal are obtained based on the ramp signals with different slopes, so as to obtain the first quantization signal and the second quantization signal respectively.

[0066] As an example, ramp signals with different slopes are obtained based on a current source, and a comparison counting circuit is used to obtain a first image signal and a second image signal based on the ramp signal and the integrated charge signal.

[0067] Specifically, the analog-to-digital converter circuit 20 based on the image sensor acquires first and second image signals with different analog gains. The analog-to-digital converter circuit includes a comparator-counting circuit. This circuit receives a ramp signal and acquires the corresponding reset signal, first image signal, and second image signal based on the ramp signal, pixel reset signal, and pixel image signal. The comparator-counting circuit may include a comparator and a counter connected to each other. The comparator determines the signals at the two input terminals and flips the signal, while the counter counts based on the comparator's flip, thus quantizing the signals at the comparator's input terminals. For example, as... Figure 5 As shown, the comparator includes MOS transistors M1, M2, M3, and M4, and has an output terminal out1. Of course, both the comparator and the counter can adopt the circuit structure of the counter and comparator used in existing CMOS image sensors.

[0068] Specifically, a first image signal can be obtained by comparing and counting the analog signal output from the integrated charge signal transfer with the first quantization ramp signal, and a second image signal can be obtained by comparing and counting the analog signal output from the integrated charge signal transfer with the second quantization ramp signal. Optionally, the first quantization ramp signal has a first slope, such as K1, and the second quantization ramp signal has a second slope, such as K1, that is different from the first slope.

[0069] As an example, see Figure 6 As shown, the analog-to-digital converter circuit includes a ramp generator 40, and a comparator / counter circuit has a first input terminal and a second input terminal, wherein:

[0070] The first input of the comparator in the comparison counting circuit is coupled to the pixel array to receive the output signal bitline from the pixel array; the second input of the comparator in the comparison counting circuit is coupled to the ramp generation circuit to receive ramp signals vramp with different slopes provided by the ramp generation circuit, such as... Figure 5 As shown in K1 and K2, these are ramp signals with two different slopes.

[0071] In one example, ramp signals with different slopes are obtained based on current sources. The slope of the ramp signal can be adjusted by changing the number of switches that are turned on, thereby changing the current flowing from the current source to the resistor. Alternatively, the initial voltage of the ramp signal can be obtained based on the initial number of current sources turned on.

[0072] In one example, the ramp-generating circuit includes:

[0073] Multiple slope generating branches are provided, each slope generating branch including a first output terminal and a second output terminal. The first output terminals of each slope generating branch are connected to form a first slope signal, and the first output terminals of each slope generating branch are connected to form a second slope signal. The slope signals with different slopes are formed based on at least one of the first slope signal and the second slope signal.

[0074] Optionally, such as Figure 6 As shown, the ramp generation circuit generates and outputs a falling ramp voltage Vramp_F or a rising ramp voltage Vramp_R based on the ramp control signal. In one example, the ramp generator may contain a digital circuit that outputs a ramp control signal to control ramp generation. For example, it may control the opening / closing of switches Φa and Φb connected to the current source in the ramp generator to output a ramp signal with the corresponding slope. Of course, other methods of ramp generation in the prior art can also be used, and it is not limited to this.

[0075] Specifically, the ramp generation circuit is implemented using a current-steering digital-to-analog converter, including: multiple ramp generation branches, a first load RF, and a second load RR. Each ramp generation branch's circuit structure includes: a current source, a first switch Φa, and a second switch Φb. The current source's power supply terminal is connected to the power supply voltage, and its output terminal is connected to the first terminals of the first switches Φa and Φb. The second terminal of the first switch is grounded through the first load and generates a descending ramp voltage Vramp_F. The second terminal of the first switch serves as the first output terminal of the ramp generation branch. The first output terminals of each ramp generation branch are connected to the second load. The second terminal of the second switch is grounded through the second load and... A rising ramp voltage Vramp_R is generated. The second terminal of the second switch serves as the second output terminal of the ramp generation branch. The first output terminals of each ramp generation branch are connected. The first switch is controlled by a ramp control signal, and the second switch is controlled by the inverted signal of the ramp control signal. A first ramp signal (e.g., a falling ramp voltage Vramp_F) is generated corresponding to the first output terminal, and a second ramp signal (e.g., a rising ramp voltage Vramp_R) is generated corresponding to the second output terminal. Furthermore, a quantization ramp is generated through at least one of the two, such as a first quantization ramp signal corresponding to the first image signal and a first quantization ramp signal corresponding to the first image signal.

[0076] In one example, the circuit structures of multiple ramp branches are the same. Of course, in other implementations, they can be set differently according to actual needs.

[0077] As an example, the current sources of multiple ramp-generating branches have the same current magnitude. Of course, the current magnitudes of the current sources of multiple ramp-generating branches can also be set to be different. The specific magnitude settings can be determined according to actual needs. Optionally, the current source magnitudes of each ramp-generating branch in multiple ramp-generating branches can be a binary increasing ratio, such as I:2I:4I:8I:16I:32I:64I:128I; the current source magnitudes of each ramp-generating branch in multiple ramp-generating branches can also be a mixed ratio, such as I:2I:4I:8I:16I:16I:16I. Therefore, the current source magnitudes of each ramp-generating branch in multiple ramp-generating branches can be designed based on actual needs and are not limited here.

[0078] In this example, multiple first switches are controlled by a ramp control signal, and multiple second switches are controlled by the inverted signal of the ramp control signal. By controlling the number of closed first and second switches, the magnitude of the current flowing to the corresponding load resistor is controlled, thereby controlling the magnitude of the falling ramp voltage Vramp_F and the rising ramp voltage Vramp_R. For example, for a branch with 6 ramps, if the ramp control signal is 111111, then its inverted signal is 000000. At this time, all 6 first switches are closed, and all 6 second switches are open. The current flowing to the first load is the maximum, and the current flowing to the second load is the minimum. The falling ramp voltage Vramp_F is at its maximum value, and the rising ramp voltage Vramp_R is at its minimum value. Taking the initial state where the falling ramp signal Vramp_F is at its maximum value as an example, the closed first switches are gradually opened, one at a time, to form a falling ramp signal Vramp_F with one slope. In addition, the closed first switches are gradually opened, two at a time, to form a falling ramp signal Vramp_F with another slope. The voltage that can be connected to the comparator counting circuit can be either the falling ramp voltage Vramp_F or the rising ramp voltage Vramp_R, which can be selected by a selector switch.

[0079] As an example, the ramp generation circuit includes multiple ramp generation branches connected in parallel, wherein each ramp generation branch includes a branch output terminal, and the branch output terminals are connected to form a variable ramp signal, and ramp signals with different ramp rates are generated based on the variable ramp signal.

[0080] Specifically, in this example, the ramp-generating branch includes a current source and a ramp control switch. The power supply terminal of the current source is connected to the power supply voltage, and the output terminal is connected to the ramp control switch. The second terminal of the ramp control switch serves as the branch output terminal of the corresponding ramp-generating branch. The connection and operation of the ramp-generating circuit in this example are described above for the ramp-generating circuit including the first and second switches, and will not be repeated here.

[0081] As an example, the slope of the ramp signal corresponding to the first image signal is less than the slope of the ramp signal corresponding to the second image signal. Correspondingly, the analog gain corresponding to the first image signal is greater than the analog gain corresponding to the second image signal. The reset signals corresponding to both are acquired under high analog gain. Additionally, the initial voltage of the ramp signal corresponding to the second image signal is greater than ( Figure 4 (as shown by the dashed line) or equal to ( Figure 4 (As shown by the solid line in the middle) Obtain the initial voltage of the ramp signal corresponding to the first image signal. Raising the initial voltage of the ramp signal obtained at low analog gain is beneficial in this example when acquiring reset and image signals with different analog gains. This ensures that when the image sensor has zero input (i.e., the voltage value of the reset signal and the voltage value of the corresponding image signal are the same), the difference between the reset signal and the corresponding image signal (the result of correlated double sampling) is zero, thus optimizing signal deviation defects.

[0082] In one example, the initial voltage of the ramp signal can be obtained based on the number of initial current sources turned on, such as by changing the number of current sources initially connected in the ramp generation branch to form the ramp signal.

[0083] Finally, step S4 is performed to acquire the actual signal of the image based on the first quantized signal and the second quantized signal. The actual signal can be acquired using existing CIS processing methods.

[0084] As an example, after obtaining the corresponding reset signal based on the integrated charge signal, the following steps are also included:

[0085] The reset signal is stored to obtain the actual sub-signal based on the first image signal and the second image signal respectively, and the actual signal is obtained based on the actual sub-signal. The actual signal is realized in a single frame relative to the integrated charge signal and has an improved dynamic range.

[0086] As an example, the steps for obtaining the actual sub-signals based on the reset signal corresponding to the first image signal and the second image signal respectively include:

[0087] The corresponding reset signal is obtained based on the electrical integrated charge signal;

[0088] Store the reset signal to retrieve the multiplexed reset signal;

[0089] The first image signal is obtained based on the integrated charge signal;

[0090] Store the first image signal to obtain the first stored signal;

[0091] The second image signal is obtained based on the integrated charge signal;

[0092] Store the second image signal to obtain the second stored signal;

[0093] A first quantized signal is obtained based on the multiplexed reset signal and the first stored signal, and is used as the first actual sub-signal. A second quantized signal is obtained based on the multiplexed reset signal and the second stored signal, and is used as the second actual sub-signal. The actual signal of the image is obtained based on the first actual sub-signal and the second actual sub-signal.

[0094] Specifically, the first quantized signal and the second quantized signal can be obtained based on the data processing circuit 30 of the image sensor. See, for example... Figure 5 As shown, the data processing circuit 30 includes:

[0095] A reset memory unit is used to store a reset signal to obtain a multiplexed reset signal; the reset memory unit can be a memory, such as SRAM, as shown in the figure, where sram1 stores the reset signal rst;

[0096] Multiple image storage units are used to store a first image signal and a second image signal respectively, so as to obtain the first stored signal and the second stored signal; wherein, the image storage unit can be a memory, such as SRAM, and the figure shows that SRAM2 stores the first image signal hcg sig and SRAM3 stores the second image signal lcg sig;

[0097] The data computing circuit is coupled to each storage unit and is used to acquire a first quantized signal based on the stored multiplexed reset signal and the stored first image signal, i.e., the first storage signal, and to acquire a second quantized signal based on the stored multiplexed reset signal and the stored second image signal, i.e., the second storage signal.

[0098] The data calculation circuit may include a subtractor. The input terminal receives the stored multiplexed reset signal and the stored first image signal. The subtractor calculates the difference between the two and outputs the difference, which is the first quantized signal. Similarly, the stored multiplexed reset signal and the stored second image signal are calculated by the subtractor of the data calculation circuit to obtain the second quantized signal, thereby obtaining the actual image signal.

[0099] As an example, the quantization process of the second image signal and the acquisition process of the first quantized signal overlap. For instance, when the second image signal is quantized, the first quantized signal can be acquired based on the multiplexed reset signal and the first image signal. Similarly, in other implementations, the quantization process of the first image signal and the acquisition process of the second quantized signal may overlap. When the first image signal is quantized, the second quantized signal can be acquired based on the multiplexed reset signal and the second image signal, thereby improving quantization efficiency.

[0100] As an example, the method of obtaining first image signals and second image signals with different gains based on integrated charge signals includes: generating sub-integrated charge signals with different quantization capacities based on integrated charge signals, and generating at least one of the first image signal and the second image signal corresponding to different integrated charge signals.

[0101] In one example, the pixel unit includes a capacitive switch for forming integrated charge signals of different capacities.

[0102] Specifically, such as Figure 7 As shown, the pixel unit 10 includes a photosensitive module, a first capacitive control module 102, and a second capacitive control module 103. The photosensitive module has a photoelectric conversion element (PD) and a transmission transistor (TX). The first capacitive control module has a first capacitive control switch (DCG), and the second capacitive control module has a second capacitive control switch (OF_CTL) and an overflow capacitor (OF_Cap). The pixel unit also has an output transistor (SF), a selection transistor (SEL), and floating diffusion nodes (FD1 and FD2). The pixel unit can be implemented using existing LOFIC operation methods. The pixel unit can store overflow signals, thereby forming different capacities corresponding to the floating diffusion nodes FD1 and FD2 and the overflow capacitor (OF_Cap). Based on the three capacities, three sub-integrated charge signals can be generated from the integrated charge signal, thereby generating a first image signal and a second image signal respectively, enriching the details of high dynamic range imaging and improving image quality. Of course, the pixel unit can also be designed in other ways to form different quantization capacities.

[0103] Please see Figures 8 to 10 As shown, a comparative example is provided to further illustrate the effects of this application, such as... Figure 8 As shown, the quantization timing diagrams of the traditional reset signal rst and image signal sig are displayed, as follows: Figure 9 The diagram shows the quantization time required to achieve HDR by increasing the quantization bit depth of the ADC system in the CMOS image sensor readout circuit. It can be seen that increasing the quantization bit depth of the ADC system leads to an exponential increase in the required quantization time. Assuming that to achieve high dynamic range, the quantization bit depth of the ADC needs to be increased from 10 bits to 12 bits; taking a 10-bit ADC system as an example, the required quantization times for the rst and sig signals are t1_rst and t1_sig, respectively. Figure 8 As shown; however, in an ADC system with a 12-bit quantization bit, the quantization times required for the rst and sig signals are 4*t1_rst and 4*t1_sig, respectively. Figure 9As shown. Therefore, the time required to quantize one line with a 12-bit ADC will be four times that of a 10-bit ADC, thus reducing the frame rate of the entire CMOS image sensor to at least one-quarter of its original value; similarly, power consumption will also increase dramatically due to the significant increase in quantization time. In this application, the quantization time for the second image signal is added, and the quantization time required for the second image signal is close to or only slightly longer than that of the first image signal. The time required to quantize one line is approximately t1_rst + 2*t1_sig, which is much less than 4*(t1_rst + t1_sig). Figure 10 As shown, the frame rate will not decrease significantly, and the power consumption will not increase sharply due to the large increase in quantization time.

[0104] The signal generation logic proposed in this application implements a technical solution for HDR in CMOS image sensors. While achieving high dynamic range, it effectively reduces the additional quantization time, avoids a significant drop in frame rate, and greatly reduces additional power consumption. The reset signal and the corresponding image signal generation logic can significantly reduce the additional quantization time required to improve dynamic range. Specifically, a high-gain condition can be used to represent dark details, while a low-gain condition can represent bright details. Quantization of the same pixel's output voltage under two different gain conditions can be achieved by changing the slope of the ramp signal.

[0105] Example 2:

[0106] This application also provides an image sensor, which is applicable to the control method described in any of the above solutions. Related details can be found in the description of the control method, and will not be repeated here. Of course, in other embodiments, other control methods may also be applicable, wherein the image sensor includes:

[0107] A pixel array includes pixel units arranged in an array. The pixel units are used to acquire integrated charge signals and output corresponding pixel reset signals and pixel image signals based on the integrated charge signals.

[0108] The analog-to-digital conversion circuit includes a comparator-counter circuit that receives a ramp signal and acquires a corresponding reset signal, a first image signal, and a second image signal based on the ramp signal, a pixel reset signal, and a pixel image signal; and...

[0109] The data processing circuit is used to obtain the actual signal with improved dynamic range corresponding to a single frame of the integrated charge signal based on the reset signal, the first image signal, and the second image signal.

[0110] As an example, the analog-to-digital converter circuit includes a ramp generating circuit and a comparator counting circuit having a first input terminal and a second input terminal, wherein:

[0111] The first input terminal is coupled to the pixel array and is used to receive the output signal of the pixel array.

[0112] The second input terminal is coupled to the ramp generator circuit and is used to receive ramp signals with different slopes provided by the ramp generator circuit.

[0113] As an example, the ramp generation circuit includes: a plurality of ramp generation branches, each ramp generation branch including a first output terminal and a second output terminal, wherein the first output terminal of each ramp generation branch is connected to form a first ramp signal, and the first output terminal of each ramp generation branch is connected to form a second ramp signal, so as to form ramp signals with different slopes based on at least one of the first ramp signal and the second ramp signal.

[0114] As an example, the ramp-generating branch includes a current source and a first switch and a second switch, wherein:

[0115] The power supply terminal of the current source is connected to the power supply voltage, and the output terminal is connected to the first terminal of the first switch and the first terminal of the second switch. The second terminal of the first switch serves as the first output terminal of the corresponding ramp generation branch, and the second terminal of the second switch serves as the second output terminal of the corresponding ramp generation branch.

[0116] As an example, the ramp generation circuit includes: multiple ramp generation branches, each ramp generation branch including a branch output terminal, the branch output terminals being connected to form a variable ramp signal, and ramp signals with different slopes being generated based on the variable ramp signal. As an example, the ramp generation branch includes a current source and a ramp control switch, the power supply terminal of the current source being connected to the power supply voltage, the output terminal being connected to the ramp control switch, and the second terminal of the ramp control switch serving as the branch output terminal of the corresponding ramp generation branch.

[0117] As an example, the data processing circuit includes:

[0118] A reset memory unit is used to store a reset signal in order to obtain a multiplexed reset signal;

[0119] Multiple image storage units are used to store a first image signal and a second image signal respectively, so as to obtain the first stored signal and the second stored signal;

[0120] The data computing circuit is coupled to each storage unit and is used to acquire a first quantized signal based on the stored multiplexed reset signal and the stored first image signal, i.e., the first storage signal, and to acquire a second quantized signal based on the stored multiplexed reset signal and the stored second image signal, i.e., the second storage signal.

[0121] Example 3:

[0122] The present invention also provides an electronic device including an image sensor as described in any of the above embodiments. The electronic device can be a security monitoring device, an in-vehicle electronics device, a mobile phone camera, a machine vision device, etc. The image sensor based on the present invention can acquire high-quality image information, particularly for infrared-utilizing devices.

[0123] In summary, this application, through the design of an image sensor and its control method, effectively solves the problems of difficulty in achieving high dynamic range and artifacts or ghosting in multi-frame HDR based on single-frame HDR technology. The frame rate of this application is not significantly reduced, avoiding the sharp increase in power consumption caused by a significant increase in quantization time. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0124] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. All equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A control method for an image sensor, characterized in that, The control method includes: Integrated charge signals are acquired using an image sensor; The reset signal is obtained based on the integrated charge signal; Based on the integrated charge signal, first image signals and second image signals with different gains are obtained, and based on the reset signal and the corresponding image signal, first quantization signal and second quantization signal are obtained; The actual signal of the image is obtained based on the first quantization signal and the second quantization signal.

2. The control method for the image sensor as described in claim 1, characterized in that, The step of obtaining the first quantized signal and the second quantized signal based on the reset signal and the corresponding image signal includes: The first quantization signal corresponds to a first gain, the second quantization signal corresponds to a second gain, and the first gain is greater than the second gain; the reset signal is acquired at the first gain; and / or, the quantization process of the second image signal and the acquisition process of the first quantization signal overlap, or correspondingly, the quantization process of the first image signal and the acquisition process of the second quantization signal overlap.

3. The control method for the image sensor as described in claim 2, characterized in that, The methods for acquiring the reset signal, the corresponding image signal, and the quantization signal include: The reset signal is acquired before the first image signal and the second image signal are acquired; and / or the second image signal is acquired after the first image signal is acquired; and / or the second quantization signal is acquired after the first quantization signal is acquired.

4. The control method for the image sensor as described in claim 1, characterized in that, The methods for obtaining first and second image signals with different gains based on the integrated charge signal include: Based on the integrated charge signal, sub-integrated charge signals with different quantization capacities are generated, and at least one of the first image signal and the second image signal is generated corresponding to the different integrated charge signals.

5. The control method for an image sensor as described in claim 1, characterized in that, After obtaining the reset signal based on the integrated charge signal, the method further includes the following steps: The reset signal is stored to obtain actual sub-signals based on the first image signal and the second image signal respectively, and the actual signal is obtained based on the actual sub-signals. The actual signal is realized in a single frame relative to the integrated charge signal and has an improved dynamic range.

6. The control method for an image sensor as described in claim 5, characterized in that, The steps for obtaining the actual sub-signals based on the reset signal corresponding to the first image signal and the second image signal respectively include: The corresponding reset signal is obtained based on the electrical integrated charge signal; Store the reset signal to obtain a multiplexed reset signal; The first image signal is obtained based on the integrated charge signal; Store the first image signal to obtain the first stored signal; The second image signal is obtained based on the integrated charge signal; Store the second image signal to obtain the second stored signal; A first actual sub-signal is obtained based on the multiplexed reset signal and the first stored signal, and a second actual sub-signal is obtained based on the multiplexed reset signal and the second image signal.

7. The control method for an image sensor as described in any one of claims 1-6, characterized in that, The steps for obtaining the first quantized signal and the second quantized signal corresponding to different gains include: The first image signal and the second image signal are obtained based on the ramp signals with different slopes, so as to obtain the first quantization signal and the second quantization signal respectively.

8. The control method for an image sensor as described in claim 7, characterized in that, The method involves acquiring ramp signals with different slopes based on current sources, and acquiring the first image signal and the second image signal based on the ramp signals with different slopes and the integrated charge signal using a comparison counting circuit; and / or, acquiring the initial voltage of the ramp signal based on the setting of the initial number of current sources turned on; and / or, acquiring the ramp signal corresponding to the first image signal with a slope less than the ramp signal corresponding to the second image signal, and acquiring the initial voltage of the ramp signal corresponding to the second image signal with a slope greater than or equal to the initial voltage of the ramp signal corresponding to the first image signal.

9. An image sensor, characterized in that, The image sensor includes: A pixel array includes pixel units arranged in an array, wherein the pixel units are used to acquire an integrated charge signal and output a corresponding pixel reset signal and a pixel image signal based on the integrated charge signal; An analog-to-digital conversion circuit includes a comparator-counter circuit that receives a ramp signal and acquires a corresponding reset signal, a first image signal, and a second image signal based on the ramp signal, the pixel reset signal, and the pixel image signal; and... The data processing circuit is used to obtain the actual signal for improving the dynamic range of the single frame corresponding to the integrated charge signal based on the reset signal, the first image signal and the second image signal.

10. The image sensor as claimed in claim 9, characterized in that, The analog-to-digital conversion circuit includes a ramp generation circuit, and the comparator counting circuit has a first input terminal and a second input terminal, wherein: The first input terminal of the comparison counting circuit is coupled to the pixel array and is used to receive the output signal of the pixel array; the second input terminal of the comparison counting circuit is coupled to the ramp generating circuit and is used to receive ramp signals with different slopes provided by the ramp generating circuit.

11. The image sensor as claimed in claim 10, characterized in that, The ramp generating circuit includes multiple ramp generating branches connected in parallel, wherein each ramp generating branch includes: A first output terminal and a second output terminal are provided, wherein the first output terminal of each of the slope generating branches is connected to form a first slope signal, and the second output terminal of each of the slope generating branches is connected to form a second slope signal, so as to form the slope signals with different slopes based on at least one of the first slope signal and the second slope signal; or, a branch output terminal is provided, wherein the branch output terminal is connected to form a variable slope slope signal, and the slope signals with different slopes are formed based on the variable slope slope signal.

12. The image sensor as claimed in claim 11, characterized in that, The ramp generating branch includes a current source and a first switch and a second switch, wherein: The power supply terminal of the current source is connected to the power supply voltage, and the output terminal is connected to the first terminal of the first switch and the second switch. The second terminal of the first switch serves as the first output terminal of the corresponding ramp-generating branch, and the second terminal of the second switch serves as the second output terminal of the corresponding ramp-generating branch; or... The slope generating branch includes a current source and a slope control switch. The power supply terminal of the current source is connected to the power supply voltage, and the output terminal is connected to the slope control switch. The second terminal of the slope control switch serves as the branch output terminal of the corresponding slope generating branch.

13. The image sensor according to any one of claims 9-12, characterized in that, The data processing circuit includes: A reset storage unit, coupled to the comparator counting circuit, is used to store the reset signal to obtain a multiplexed reset signal; Multiple image storage units, coupled to the comparison counting circuit, are used to store the first image signal and the second image signal respectively, to obtain a first stored signal and a second stored signal; and, A data calculation circuit, coupled to each storage cell, is used to obtain the first quantization signal based on the stored multiplexed reset signal and the stored first storage signal, and to obtain the second quantization signal based on the stored multiplexed reset signal and the stored second storage signal.

14. The image sensor as claimed in claim 13, characterized in that, The data calculation circuit includes a subtractor; and / or, the comparison counting circuit includes a connected comparator and a counter; and / or, the pixel unit includes a capacitive switch for controlling the formation of sub-integrated charge signals of different capacities.

15. An electronic device, characterized in that, The electronic device includes an image sensor as described in any one of claims 9-14.

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