Semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a first substrate including a substrate having an active region and extending in a first horizontal direction and a second horizontal direction intersecting each other; a contact plug connected to the active region; a bit line structure disposed adjacent to the contact plug in the first horizontal direction and extending along the second horizontal direction; a landing pad disposed on the bit line structure and connected to the contact plug; a spacer pattern spaced apart from each other on an upper surface of the bit line structure and in contact with at least one sidewall of the landing pad; a separation pattern extending to an inner sidewall of the bit line structure between the spacer patterns; and an oxide film disposed between the spacer pattern and the separation pattern, wherein the oxide film is not disposed between the separation pattern and the bit line structure.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0185945, filed with the Korean Intellectual Property Office on December 13, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor memory device and a method for manufacturing the semiconductor device. Background Technology

[0004] As semiconductor devices become increasingly integrated, individual circuit patterns are being miniaturized to accommodate more semiconductor devices within the same area. In other words, as the integration density of semiconductor devices increases, the design rules for semiconductor device components are decreasing.

[0005] In highly scaled semiconductor devices, the process of forming multiple wiring lines and multiple contacts in between is becoming increasingly complex and challenging. Summary of the Invention

[0006] One object of this disclosure is to provide a semiconductor memory device with improved reliability and performance.

[0007] Another object of this disclosure is to provide a method for manufacturing semiconductor memory devices with improved reliability and performance.

[0008] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not expressly stated will be clearly understood by those skilled in the art based on the following description.

[0009] A semiconductor memory device according to some embodiments of the present disclosure includes: a substrate having an active region and extending in a first horizontal direction and a second horizontal direction intersecting each other; a contact plug connected to the active region; a bit line structure disposed adjacent to the contact plug in the first horizontal direction and extending in the second horizontal direction; a bonding pad disposed on the bit line structure and connected to the contact plug; spacer patterns spaced apart from each other on an upper surface of the bit line structure and contacting at least one sidewall of the bonding pad; a separation pattern extending between the spacer patterns to an inner sidewall of the bit line structure; and an oxide film disposed between the spacer patterns and the separation pattern, wherein the oxide film is not disposed between the separation pattern and the bit line structure.

[0010] A semiconductor memory device according to some other embodiments of the present disclosure includes: a substrate having an active region and extending in a first horizontal direction and a second horizontal direction that intersect each other perpendicularly; a contact plug connected to the active region; a bit line structure arranged alternately with the contact plug in the first horizontal direction and extending in the second horizontal direction; bonding pads connected to the contact plugs on the bit line structure and including a barrier film in contact with the sidewalls and upper surface of the bit line structure, and a first metal film on the barrier film; a second metal film disposed between the contact plugs and the bonding pads; spacer patterns spaced apart from each other on the upper surface of the bit line structure and in contact with the sidewalls of the bonding pads; a separation pattern extending vertically between the spacer patterns to the inner sidewall of one of the bit line structures; and an oxide film between the spacer patterns and the separation pattern, wherein the separation pattern includes a first portion in contact with the inner sidewall of one of the bit line structures and the inner sidewall of one of the bonding pads, and a second portion disposed on the first portion and in contact with the oxide film.

[0011] A method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure includes: forming a bit line structure extending in a first horizontal direction on a substrate; forming a contact plug on the substrate adjacent to the bit line structure and connected to an active region in a second horizontal direction; forming a bonding pad on the contact plug, the bonding pad including a pre-blocking film and a pre-metal film, the pre-blocking film extending along the sidewalls and upper surface of the bit line structure, the pre-metal film being on the pre-blocking film; forming a metal film by removing at least a portion of the pre-metal film and the pre-blocking film, the metal film having a first recess exposing a portion of the bit line structure; forming a pre-spacer film within the first recess along the surface of the metal film; forming a spacer pattern by removing at least a portion of the pre-spacer film, the bit line structure, and the pre-blocking film, the spacer pattern having a second recess exposing the inner sidewalls of the bit line structure; forming a separation pattern located between the spacer patterns within the second recess; and forming an oxide film on the spacer pattern, wherein the oxide film is not formed between the bit line structure and the separation pattern.

[0012] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will become apparent from the following description. Attached Figure Description

[0013] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0014] Figure 1 This is a schematic layout of a semiconductor memory device according to some example embodiments;

[0015] Figure 2 It is along Figure 1 An exemplary cross-sectional view taken by line A-A';

[0016] Figure 3 yes Figure 2 A magnified view of region S in the image; and

[0017] Figures 4 to 18 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor memory device according to some example embodiments. Detailed Implementation

[0018] Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. Throughout the document, the same reference numerals denote the same elements.

[0019] It will be understood that when a component is referred to as being “connected” or “coupled” to another component or “on” another component, the component may be directly connected or coupled to that other component or directly on that other component, or there may be intermediate components. In contrast, when a component is referred to as being “directly connected” or “directly coupled” to another component, or as being “in contact” with another component or “in contact with” another component (or any form of using the word “in contact”), there are no intermediate components at the point of contact.

[0020] Figure 1 This is a schematic layout of a semiconductor memory device according to some example embodiments.

[0021] refer to Figure 1 According to some example embodiments, a semiconductor memory device may include a plurality of active regions ACT. The active regions ACT may be arranged diagonally relative to a first horizontal direction X and a second horizontal direction Y. A plurality of word lines WL may extend longitudinally parallel to each other along the first horizontal direction X across the active regions ACT. Above the word lines WL, a plurality of bit lines BL may extend longitudinally parallel to each other along a second horizontal direction Y intersecting the first horizontal direction X. The bit lines BL may be connected to the active regions ACT via direct contacts DC.

[0022] Multiple buried contacts BC can be formed between each pair of adjacent bit lines BL. In some embodiments, the buried contacts BC can be arranged in rows along a first horizontal direction X and a second horizontal direction Y. Multiple bonding pads LP can be arranged on the buried contacts BC. The bonding pads LP can be connected to multiple capacitor structures CP.

[0023] The buried contact BC and the bonding pad LP can be used to connect the lower electrode of the capacitor structure CP to the active region ACT. At least a portion of the bonding pad LP can vertically overlap with the buried contact BC. At least a portion of the capacitor structure CP can vertically overlap with the bonding pad LP.

[0024] Figure 2 It is along Figure 1An exemplary cross-sectional view taken from line A-A'. Figure 3 yes Figure 2 A magnified view of region S in the image.

[0025] refer to Figure 2 According to some embodiments, a semiconductor memory device may include a substrate 110, a contact plug 150, a bit line structure BLS, a bonding pad LP, a spacer pattern 157, an oxide film 158, a separation pattern 159, and a capacitor structure CP.

[0026] refer to Figure 2 According to some embodiments, a semiconductor memory device may include a substrate 110, in which a plurality of active regions ACT are defined by an isolation film 112. The isolation film 112 may be formed in a device isolation trench T1, which is formed in the substrate 110.

[0027] Substrate 110 may include silicon (Si) (e.g., single-crystal Si, polycrystalline Si, or amorphous Si). For example, substrate 110 may include semiconductor elements such as Si or germanium (Ge), or compound semiconductors such as SiGe, SiC, GaAs, InAs, or InP. In some embodiments, substrate 110 may include conductive regions (e.g., doped wells or doped structures). Isolation film 112 may be formed of an oxide film, a nitride film, or a combination thereof. Figure 1 The word line WL shown can be embedded in the substrate 110.

[0028] A buffer layer 122 may be formed on the substrate 110. The buffer layer 122 may cover the active region ACT and the upper surface of the isolation film 112. The buffer layer 122 may contact the active region ACT and the upper surface of the isolation film 112. The buffer layer 122 may include, but is not limited to, a first silicon oxide film, a silicon nitride film and a second silicon oxide film sequentially formed on the substrate 110.

[0029] Multiple bit lines BL extending parallel to the second horizontal direction Y can be arranged on the buffer layer 122. The bit lines BL can be spaced apart from each other along the first horizontal direction X. A direct contact DC can be disposed on a portion of the active region ACT. The direct contact DC can contact the active region ACT. The bit lines BL can be connected to the active region ACT through the direct contact DC. The direct contact DC can include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or combinations thereof. In some embodiments, the direct contact DC can include doped polysilicon.

[0030] Bit lines BL may each include a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134 sequentially formed on a substrate 110. For example, the intermediate conductive layer 132 may contact the upper surface of the lower conductive layer 130, and the upper conductive layer 134 may contact the upper surface of the intermediate conductive layer 132. The upper surface of the bit line BL may be covered with an insulating capping pattern 136. The insulating capping pattern 136 may be disposed on the upper conductive layer 134. For example, the upper conductive layer 134 may contact the upper surface of the intermediate conductive layer 132. The upper surface of the lower conductive layer 130 and the upper surface of the direct contact portion DC may be disposed on the same plane.

[0031] Figure 2 The diagram illustrates a structure where each of multiple bit lines BL has a three-layer conductive layer structure comprising a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134, but this disclosure is not limited thereto. Alternatively, for example, each bit line BL may be formed as having a single conductive layer, two conductive layers, or a stack of four or more conductive layers.

[0032] In some embodiments, the lower conductive layer 130 may be formed of a doped polycrystalline silicon film. The intermediate conductive layer 132 and the upper conductive layer 134 may each comprise materials including Ti, TiN, TiSiN, tungsten (W), WN, or tungsten silicide (WSi). x ), silicon tungsten nitride (WSi) x N y Layers of ruthenium (Ru) or combinations thereof. For example, the intermediate conductive layer 132 may include a TiN film and / or a TiSiN film, and the upper conductive layer 134 may include Ti, TiN, W, WN, WSi. x N y Ru or combinations thereof. The insulating capping pattern 136 may be formed from silicon nitride films.

[0033] In some regions of substrate 110, multiple recessed spaces R1 may be formed in active regions ACT. Each recessed space R1 may be filled with a plurality of contact plugs 150. Contact plugs 150 may have a cylindrical shape extending from the recessed space R1 in the vertical direction Z. Contact plugs 150 may contact the active regions ACT. The lower end of the contact plug 150 may be positioned at a level lower than the upper surface of substrate 110 to be embedded within substrate 110. Contact plugs 150 may include, but are not limited to, impurity-doped semiconductor patterns.

[0034] In a semiconductor memory device according to some embodiments, a direct contact DC and a pair of contact plugs 150 facing each other across the direct contact DC can be connected to different active regions ACT among a plurality of active regions ACT.

[0035] Multiple contact plugs 150 can be arranged in a row along a second horizontal direction Y between a pair of adjacent bit lines BL selected from multiple bit lines BL. Insulating fence (e.g., Figure 12 The insulating fences 149 can be disposed between the contact plugs 150 arranged in a row along the second horizontal direction Y. The contact plugs 150 can be electrically isolated from each other by the plurality of insulating fences 149. The insulating fences 149 can have a columnar shape extending in the vertical direction Z on the substrate 110. In some embodiments, the insulating fences 149 can be formed of a silicon nitride film.

[0036] Multiple metal silicide films 152 and multiple bonding pads LP can be disposed on the contact plug 150. The bonding pads LP can each extend longitudinally in the vertical direction Z above the contact plug 150. The bonding pads LP can be connected to the contact plug 150 via the metal silicide films 152. For example, the bonding pads LP can contact the upper surfaces of the multiple metal silicide films 152, and the multiple metal silicide films 152 can contact the upper surface of the contact plug 150.

[0037] Each bonding pad LP may include a conductive barrier film 154 and a metal film 156. In some embodiments, the conductive barrier film 154 may include at least one of titanium (Ti) and titanium nitride (TiN), and the metal film 156 may include tungsten (W). When viewed in a plan view, the bonding pad LP may have an island pattern. In some embodiments, the metal silicide film 152 may include, but is not limited to, cobalt silicide, nickel silicide, or manganese silicide.

[0038] The contact plug 150 and the metal silicide film 152 can constitute Figure 1 The buried contact portion BC. The contact plug 150, the metal silicide film 152 and the bonding pad LP arranged sequentially on the substrate 110 can form a contact structure that is connected to the active region ACT of the substrate 110 at a position near the bit line BL along the first horizontal direction X.

[0039] The two sidewalls of the bit line BL and the two sidewalls of the insulating cap pattern 136 covering the upper surface of the bit line BL can be covered by bit line spacer structures SP. A single bit line spacer structure SP can be located between one of the bit lines BL and a plurality of contact plugs 150 arranged in a row along the second horizontal direction Y near that bit line BL. Each bit line spacer structure SP can include an inner insulating spacer 142, an intermediate insulating spacer 146, and an outer insulating spacer 148.

[0040] The inner insulating spacer 142 of the bit line spacer structure SP can contact the sidewall of the bit line BL and the sidewall of the direct contact portion DC. The inner insulating spacer 142 of the bit line spacer structure SP may include a portion that contacts the contact plug 150. The inner insulating spacer 142 of the bit line spacer structure SP may be formed of a silicon nitride film.

[0041] Intermediate insulating spacer 146 may be located between inner insulating spacer 142 and outer insulating spacer 148 in a first horizontal direction X. Intermediate insulating spacer 146 may have a sidewall across inner insulating spacer 142 facing bit line BL, and a sidewall across outer insulating spacer 148 facing contact plug 150, metal silicide film 152, and bonding pad LP. Intermediate insulating spacer 146 may be formed from silicon oxide film, air spacer, or a combination thereof. In this specification, the term "air" may refer to ambient air or other gases present during the manufacture of semiconductor memory devices according to some embodiments.

[0042] The outer insulating spacer 148 may contact the sidewalls of the contact plug 150, the sidewalls of the metal silicide film 152, and the sidewalls of the bonding pad LP. The outer insulating spacer 148 may be spaced apart from the inner insulating spacer 142 across the intermediate insulating spacer 146. In some embodiments, the outer insulating spacer 148 may each be formed from a silicon nitride film.

[0043] The bit line spacer structure SP can extend parallel to the bit line BL along the second horizontal direction Y. The insulating cap pattern 136 and the bit line spacer structure SP can form an insulating structure covering the upper surface and sidewalls of the bit line BL. In this specification, the bit line structure BLS can refer to the configuration including the bit line BL and the bit line spacer structure SP.

[0044] A gap-filling insulating pattern 144 may be located between the direct contact portion DC and the contact plug 150. The gap-filling insulating pattern 144 may be spaced apart from the direct contact portion DC across the inner insulating spacer 142. The gap-filling insulating pattern 144 may cover and surround the sidewalls of the direct contact portion DC. The gap-filling insulating pattern 144 may contact the inner insulating spacer 142 and the contact plug 150. In some embodiments, the gap-filling insulating pattern 144 may be formed from silicon nitride films.

[0045] Spacer pattern 157 may be disposed on the upper surface of the bit line structure BLS. Spacer pattern 157 may contact at least one sidewall of the bonding pad LP. Spacer pattern 157 may contact the metal film 156. Spacer pattern 157 may include silicon nitride. Spacer pattern 157 may not contact the inner sidewall of the bit line structure BLS. Spacer pattern 157 may contact the conductive barrier film 154 on the upper surface of the bit line structure BLS.

[0046] The oxide film 158 may be disposed between the separation pattern 159 and the spacer pattern 157, as will be described later. The oxide film 158 may not be disposed between the separation pattern 159 and the bit line structure BLS, or between the separation pattern 159 and the bonding pad LP. The oxide film 158 may include an oxide material.

[0047] Separation patterns 159 may be disposed between spacer patterns 157. Separation patterns 159 may extend to the inner sidewall of the bitline structure BLS. Separation patterns 159 may contact the inner sidewall of the bitline structure BLS. Separation patterns 159 may contact the conductive barrier film 154 on the sidewall of the bitline structure BLS.

[0048] The separation pattern 159 may include a first portion that contacts the first inner wall of the bit line structure BLS and the first inner wall of the corresponding bonding pad LP, and a second portion disposed on the first portion and in contact with the oxide film 158. The first portion of the separation pattern 159 may be positioned at a level extending up to the upper surface of the insulating cap pattern 136, and the second portion of the separation pattern 159 may be positioned at a level higher than the upper surface of the insulating cap pattern 136.

[0049] The maximum width W1 of the first portion of the separation pattern 159 may be smaller than the maximum width W2 of the second portion of the separation pattern 159. In an example embodiment, the maximum width W1 of the first portion of the separation pattern 159 may be the width of the separation pattern 159 at the horizontal level of the upper surface of the insulating capping pattern 136. The width of the first portion of the separation pattern 159 may decrease as it approaches the substrate 110.

[0050] The first portion of the separation pattern 159 can be formed in a first recess within the bit line structure BLS. The spacer pattern 157 can be formed in a second recess within the bonding pad LP. The width of the first recess can be smaller than the width of the second recess.

[0051] The separation pattern 159 can contact the sidewall of the first region 156A. In the vertical direction Z, the length H1 of the separation pattern 159 can be greater than the length H2 of the spacer pattern 157.

[0052] The oxide film 158 may not be disposed between the first portion of the separation pattern 159 and the first inner sidewall of the bit line structure BLS, but may be disposed between the second portion of the separation pattern 159 and the spacer pattern 157.

[0053] The separation pattern 159 may be formed of or include silicon nitride.

[0054] The metal film 156 may include a first region 156A on the sidewall of the bit line structure BLS and a second region 156B on the upper surface of the bit line structure BLS. The spacer pattern 157 may contact the sidewall of the second region 156B.

[0055] Multiple capacitor structures CP can be disposed on bonding pads LP. Each capacitor structure CP may include multiple lower electrodes 171, dielectric films 173, and upper electrodes 172. The dielectric film 173 may cover the lower electrodes 171. The dielectric film 173 may be disposed along the surface of the lower electrodes 171. For example, the dielectric film 173 may contact the lower electrodes 171. The upper electrodes 172 may cover the dielectric film 173 and may face across the dielectric film 173 towards the lower electrodes 171. For example, the upper electrode 172 may contact the dielectric film 173.

[0056] The lower electrode 171 may protrude upward in a direction away from the substrate 110. The lower electrode 171 may have a cylindrical shape extending upward in the vertical direction Z, but this disclosure is not limited thereto. Alternatively, for example, the lower electrode 171 may have a cup-shaped or bottom-closed cylindrical cross-sectional structure.

[0057] A lower electrode 171 may be disposed on the capping layer 160. The lower electrode 171 may include a portion extending between adjacent capping layers 160 within the capping layer 160. The lower electrode 171 may contact the upper surface and side surfaces of the capping layer 160. The capping layer 160 may cover the separation pattern 159. For example, the capping layer 160 may contact the upper surface of the separation pattern 159. In an example embodiment, the capping layer 160 may cover and contact the entire upper surface of each separation pattern 159 and at least a portion of the second region 156B of the metal film 156. The capping layer 160 may be formed of or comprise an insulating material. The capping layer 160 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon carbonitride, and silicon boron nitride.

[0058] The lower electrode 171 may include a first metal. The upper electrode 172 may include a second metal. In some embodiments, the second metal may be the same as the first metal. In other embodiments, the second metal may be different from the first metal.

[0059] The lower electrode 171 and the upper electrode 172 may each comprise a metal film, a conductive metal oxide film, a conductive metal nitride film, a conductive metal nitride film, or a combination thereof. In some embodiments, the lower electrode 171 and the upper electrode 172 may each comprise niobium (Nb), Nb oxide, Nb nitride, Nb nitride, Ti, Ti oxide, Ti nitride, Ti nitride, cobalt (Co), Co oxide, Co nitride, Co nitride, tin (Sn), Sn oxide, Sn nitride, Sn nitride, or a combination thereof. For example, the lower electrode 171 and the upper electrode 172 may each comprise NbN, TiN, CoN, SnO2, or a combination thereof. In other embodiments, the lower electrode 171 and the upper electrode 172 may each comprise TaN, TiAlN, TaAlN, V, VN, Mo, MoN, W, WN, Ru, RuO2, SrRuO3, Ir, IrO2, Pt, PtO, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCO ((La,Sr)CoO3), or combinations thereof. However, the materials constituting the lower electrode 171 and the upper electrode 172 are not limited to these examples.

[0060] The dielectric film 173 may be formed of a high-k dielectric film. As used herein, the term "high-k dielectric film" refers to a dielectric film with a dielectric constant greater than that of a silicon oxide film. In some embodiments, the dielectric film 173 may be formed of a metal oxide including at least one metal selected from hafnium (Hf), zirconium (Zr), aluminum (Al), Nb, cerium (Ce), lanthanum (La), tantalum (Ta), and Ti. In some embodiments, the dielectric film 173 may have a monolayer structure formed of a single high-k dielectric film. In other embodiments, the dielectric film 173 may have a multilayer structure including multiple high-k dielectric films. One or more high-k dielectric films may be formed from, but are not limited to, HfO2, ZrO2, Al2O3, La2O3, Ta2O5, Nb2O5, CeO2, TiO2, GeO2, or combinations thereof.

[0061] Figures 4 to 18 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor memory device according to some example embodiments. Figures 4 to 12 It is along Figure 1 The cross-sectional view taken from lines A-A' and B-B'. Figures 13 to 18 It is along Figure 1 The cross-sectional view taken by line A-A' shows... Figure 12 The subsequent processes shown are described below. For simplicity, they will not be repeated. Figures 1 to 3 Repeated description.

[0062] refer to Figure 4Device isolation trenches T1 can be formed in the substrate 110, and isolation films 112 can be formed in the device isolation trenches T1. Isolation films 112 can define multiple active regions ACT in the substrate 110.

[0063] Multiple word line trenches T2 can be formed in the substrate 110. The word line trenches T2 can extend parallel to each other along a first horizontal direction X and can have a linear shape extending across the active region ACT. To form word line trenches T2 with steps at their bottoms, the isolation film 112 and the substrate 110 can be etched in separate etching processes, such that the etching depths of the isolation film 112 and the substrate 110 can be different from each other. After cleaning the resulting structure with the formed word line trenches T2, a gate dielectric film 116, word lines 118, and a buried insulating film 120 can be sequentially formed in the word line trenches T2. The word lines 118 can correspond to... Figure 1 The character line WL is shown.

[0064] The gate dielectric film 116 may be formed from at least one selected from silicon oxide film, silicon nitride film, silicon oxynitride film, oxide / nitride / oxide (ONO) film, and high-k dielectric film with a dielectric constant greater than that of silicon oxide film. The high-k dielectric film may be formed from HfO2, Al2O3, HfAlO2, Ta2O3, TiO2, or combinations thereof. The word line 118 may be formed from Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or combinations thereof. The buried insulating film 120 may be formed from silicon oxide film, silicon nitride film, silicon oxynitride film, or combinations thereof. An ion implantation process for forming multiple source / drain regions in the upper part of the active region ACT may be performed before or after the formation of the word line 118.

[0065] A buffer layer 122 and a lower conductive layer 130 can be sequentially formed on the substrate 110. The buffer layer 122 can cover the upper surface of the active region ACT, the upper surface of the isolation film 112, and the buried insulating film 120. To form the buffer layer 122, a first silicon oxide film, a silicon nitride film, and a second silicon oxide film can be sequentially formed on the substrate 110, but this disclosure is not limited thereto. The lower conductive layer 130 can be formed of a doped polycrystalline silicon film.

[0066] refer to Figure 5 A mask pattern MP1 can be formed on the lower conductive layer 130, and a direct contact hole DCH can be formed by etching the portion of the lower conductive layer 130 exposed through the opening MH of the mask pattern MP1, as well as a portion of the underlying buffer layer 122, substrate 110, and isolation film 112 to expose the active region ACT of the substrate 110. The mask pattern MP1 can be formed from an oxide film, a nitride film, or a combination thereof, but is not limited thereto.

[0067] refer to Figure 6It can remove the mask pattern MP1 and form the direct contact DC in the direct contact hole DCH.

[0068] To form the direct contact portion DC, a doped polysilicon film of sufficient thickness to fill the direct contact portion hole DCH can be formed on the inner surface of the direct contact portion hole DCH and the upper surface of the lower conductive layer 130. Then, unwanted portions of the doped polysilicon film can be removed, leaving only the doped polysilicon film within the direct contact portion hole DCH. In some embodiments, the direct contact portion DC can be formed from polysilicon films each doped with an n-type dopant. The n-type dopant can be selected from phosphorus (P), arsenic (As), and antimony (Sb).

[0069] refer to Figure 7 An intermediate conductive layer 132, an upper conductive layer 134, and multiple insulating capping patterns 136 can be sequentially formed on the lower conductive layer 130 and the direct contact portion DC. The insulating capping pattern 136 can be a line pattern extending longitudinally along the second horizontal direction Y.

[0070] refer to Figure 8 Multiple bit lines BL can be formed on the substrate 110 by etching the upper conductive layer 134, the intermediate conductive layer 132, the lower conductive layer 130, and a portion of the direct contact DC using the insulating cap pattern 136 as an etching mask. The bit lines BL may include the remaining portions of the lower conductive layer 130, the intermediate conductive layer 132, and the upper conductive layer 134.

[0071] After the bit line BL is formed, a portion of the direct contact hole DCH can be re-exposed around the direct contact DC, and a line space LS extending longitudinally along the second horizontal direction Y can be formed between the bit lines BL.

[0072] refer to Figure 9 An inner insulating spacer 142 can be formed in the line space LS to conformally cover the surface exposed by the line space, and a gap-filling insulating pattern 144 can be formed on the inner insulating spacer 142 to fill the remaining space in the direct contact hole DCH.

[0073] The inner insulating spacer 142 can be formed to conformally cover the direct contact DC, the lower conductive layer 130, the intermediate conductive layer 132, the upper conductive layer 134, and the insulating capping pattern 136. The inner insulating spacer 142 can be formed from individual silicon nitride films. The inner insulating spacer 142 can be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes.

[0074] To form the gap-filling insulating pattern 144, a gap-filling insulating film (not shown) can be formed using CVD or ALD processes to cover the sidewalls of the bit line BL, the sidewalls of the insulating cap pattern 136, and the sidewalls of the direct contact portion DC, while simultaneously filling the remaining space within the direct contact portion hole DCH. Subsequently, the gap-filling insulating film can be etched to form the gap-filling insulating pattern 144 from the remaining portion of the film.

[0075] refer to Figure 10 An intermediate insulating spacer film (not shown) covering the exposed surface can be conformally formed using CVD or ALD processes, and then the intermediate insulating spacer film can be anisotropically etched to form a plurality of intermediate insulating spacers 146 from the intermediate insulating spacer film.

[0076] During the anisotropic etching of the intermediate insulating spacer film to form the intermediate insulating spacer 146, a portion of the inner insulating spacer 142 and a portion of the buffer layer 122 can be removed. As a result, a portion of the substrate 110, a portion of the inner insulating spacer 142, and a portion of the gap-filling insulating pattern 144 can be exposed through the line space LS. The intermediate insulating spacer 146 can cover the bit line BL and the sidewalls of the insulating capping pattern 136 over the inner insulating spacer 142. In some embodiments, the intermediate insulating spacer 146 can be formed individually from silicon oxide films.

[0077] refer to Figure 11 The outer insulating spacer 148 can be formed. The outer insulating spacer 148 can be formed using CVD or ALD processes.

[0078] refer to Figure 12 Multiple insulating barriers 149 can be formed between bit lines in a line space LS defined by an outer insulating spacer 148 to divide the line space LS into multiple contact spaces CS.

[0079] The insulating fence 149 may be formed to overlap the letter line 118 in the vertical Z direction above the letter line 118. The insulating fence 149 may be formed of silicon nitride. In some embodiments, during the formation of the insulating fence 149, a portion of the insulating cap pattern 136 and a portion of the surrounding insulating film may be consumed, thereby reducing their height.

[0080] Subsequently, a portion of the structure exposed through the contact space CS can be removed to form multiple recessed spaces R1 of the active region ACT between the in-situ lines BL of the exposed substrate 110. The recessed spaces R1 can be formed using anisotropic etching processes or a combination of anisotropic and isotropic etching processes. For example, anisotropic etching can be performed on a portion of the outer insulating spacer 148 and the portion of the underlying substrate 110 exposed at the bottom of the contact space CS, followed by isotropic etching on the exposed portion of the active region ACT of the substrate 110 to form the recessed spaces R1. The recessed spaces R1 can be connected to the contact space CS respectively. During the etching process used to form the recessed spaces R1, portions of the inner insulating spacer 142 near the upper surface of the substrate 110 and portions of the gap-filling insulating pattern 144 near the upper surface of the substrate 110 may be consumed.

[0081] A portion of the active region ACT of the substrate 110, a portion of the inner insulating spacer 142, and a portion of the gap-filling insulating pattern 144 can be exposed through the recessed space R1. After forming the recessed space R1, the inner insulating spacer 142, the intermediate insulating spacer 146, and the outer insulating spacer 148 retained on the two sidewalls of the bit line BL can form the bit line spacer structure SP.

[0082] refer to Figure 13 Multiple contact plugs 150 can be formed to fill the recessed space R1 and a portion of the contact space CS between bit lines BL. Multiple metal silicide films 152 can be formed on the contact plugs 150, and a first pre-blocking film P1_154 and a pre-metallized film P156 can be formed sequentially. The first pre-blocking film P1_154 and the pre-metallized film P156 fill the remaining space of the contact space CS and cover the insulating cap pattern 136 and the bit line spacer structure SP.

[0083] refer to Figure 14 A hard mask structure HM can be formed on the pre-metallized film P156, and a mask pattern MP2 can be formed on the hard mask structure HM.

[0084] The hard mask structure HM can have a stacked structure of multiple hard mask layers formed of different materials. In some embodiments, the hard mask structure HM may include a first hard mask layer M1, a second hard mask layer M2, a third hard mask layer M3, and a fourth hard mask layer M4 sequentially stacked on a metal film 156. For example, the first hard mask layer M1 may be formed of an amorphous carbon layer (ACL), the second hard mask layer M2 may be formed of amorphous polysilicon, the third hard mask layer M3 may be formed of a spin-coated hard mask (SOH) material, and the fourth hard mask layer M4 may be formed of SiON. However, this disclosure is not limited to this example.

[0085] The mask pattern MP2 can be formed from individual photoresist patterns. The mask patterns MP2 can be spaced apart from each other.

[0086] refer to Figure 15 The mask pattern MP2 can be used as an etching mask to etch at least a portion of the fourth hard mask layer M4, the third hard mask layer M3, the second hard mask layer M2, the first hard mask layer M1, the pre-metallized film P156, and the first pre-blocking film P1_154 to form a metal film 156 having a third recess RC1 that exposes a portion of the bit line structure BLS. The third recess RC1 may expose a portion of the inner sidewall of the metal film 156, a portion of the inner sidewall of the second pre-blocking film P2_154, and a portion of the upper surface of the bit line structure BLS.

[0087] refer to Figure 16 A pre-spacer film P157 can be formed along the surface of the metal film 156. The pre-spacer film P157 can be formed on a portion of the inner sidewall of the metal film 156, a portion of the inner sidewall of the second pre-blocking film P2_154, and a portion of the upper surface of the bit line structure BLS. The pre-spacer film P157 may include silicon nitride.

[0088] refer to Figure 17 At least a portion of the pre-spacer film P157, the bit line structure BLS, and the second pre-blocking film P2_154 can be removed to form a fourth recess RC2 that exposes a portion of the inner sidewall of the bit line structure BLS and a portion of the second pre-blocking film P2_154. Spacer patterns 157 spaced apart from each other can be formed through the fourth recess RC2. A portion of the inner sidewall of the upper bit line structure BLS, a portion of the inner sidewall of the conductive blocking film 154, and a portion of the inner sidewall of the metal film 156 can also be exposed through the fourth recess RC2.

[0089] The width of the fourth recess RC2 can be smaller than the width of the third recess RC1.

[0090] refer to Figure 18 A separation pattern 159 may be formed between the spacer patterns 157 within the fourth recess RC2. The separation pattern 159 may include silicon nitride. An oxide film 158 may be inserted on the spacer pattern 157. The oxide film 158 may not be formed between the bit line structure BLS and the separation pattern 159.

[0091] refer to Figure 2 Elements 160 and multiple capacitor structures CP can be formed on the metal film 156 and the separation pattern 159.

[0092] In some embodiments, a fourth recess RC2 with a width smaller than that of the third recess RC1 can be formed, and a separation pattern 159 can be formed within the fourth recess RC2. As a result, the width D1 of the metal film 156 between the separation pattern 159 and the bit line structure BLS can be further ensured to accommodate the spacer pattern 157. Therefore, a semiconductor memory device with improved reliability and performance can be provided.

[0093] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and can be made in various other forms. Those skilled in the art will understand that modifications and implementations of the technical scope or essential characteristics of the present disclosure can be made in other specific forms without departing from the spirit of the invention. Therefore, the above embodiments should be understood as illustrative in all respects and not restrictive.

Claims

1. A semiconductor memory device, comprising: The substrate has an active region and extends in a first horizontal direction and a second horizontal direction that intersect each other; Contact plug, connected to the active area; The bit line structure is disposed adjacent to the contact plug in the first horizontal direction and extends along the second horizontal direction; The bonding pad is disposed on the bit line structure and connected to the contact plug; The spacer pattern is spaced apart from each other on the upper surface of the bit line structure and contacts at least one sidewall of the bonding pad; Separation patterns extend between the spacer patterns to the inner wall of the bit line structure; as well as An oxide film is disposed between the spacer pattern and the separation pattern. The oxide film is not disposed between the separation pattern and the bit line structure.

2. The semiconductor memory device according to claim 1, wherein, The separation pattern contacts the inner sidewall of the bit line structure.

3. The semiconductor memory device according to claim 1, wherein, The bonding pad includes a first region on the sidewall of the bit line structure and a second region on the upper surface of the bit line structure.

4. The semiconductor memory device according to claim 3, wherein, The spacer pattern is in contact with the second region.

5. The semiconductor memory device according to claim 3, wherein, The separation pattern is in contact with the first region.

6. The semiconductor memory device according to claim 1, wherein, The length of the separation pattern in the vertical direction is greater than the length of each of the spacer patterns in the vertical direction.

7. The semiconductor memory device according to claim 1, wherein, The bonding pad includes a barrier film that contacts the sidewall and upper surface of the bit line structure, and a metal film on the barrier film.

8. The semiconductor memory device according to claim 7, in, The separation pattern includes a first portion that contacts the inner wall of the barrier film and the bit line structure, and a second portion that contacts the spacer pattern. The maximum width of the first part is less than the maximum width of the second part.

9. The semiconductor memory device according to claim 7, in, The barrier film comprises titanium nitride, and The metal film includes tungsten.

10. The semiconductor memory device according to claim 1, wherein, The spacer pattern and the separation pattern each comprise silicon nitride.

11. A semiconductor memory device, comprising: The substrate has an active region and extends in a first horizontal direction and a second horizontal direction that intersect each other perpendicularly; Contact plug, connected to the active area; The bit line structure is arranged alternately with the contact plug in the first horizontal direction and extends along the second horizontal direction; The bonding pads are respectively connected to the contact plugs on the bit line structure, and include a barrier film that contacts the sidewall and upper surface of the bit line structure, and a first metal film on the barrier film; A second metal film is disposed between the contact plug and the bonding pad; The spacer pattern is spaced apart from each other on the upper surface of the bit line structure and contacts the sidewall of the bonding pad; Separating patterns extend vertically between the spacer patterns to the inner wall of one of the bit line structures; as well as An oxide film is placed between the spacer pattern and the separation pattern. The separation pattern includes a first portion that contacts the inner sidewall of one of the bit line structures and the inner sidewall of one of the bonding pads, and a second portion disposed on the first portion and in contact with the oxide film.

12. The semiconductor memory device according to claim 11, wherein, The oxide film is not disposed between the first portion and the inner sidewall of one of the bit line structures, but is disposed between the second portion and the spacer pattern.

13. The semiconductor memory device according to claim 11, wherein, The spacer pattern does not contact the inner wall of the bit line structure, but contacts the barrier film on the upper surface of the bit line structure.

14. The semiconductor memory device according to claim 11, in, The first portion is formed in a first recess within the bit line structure. The spacer pattern is formed in the second recess within the bonding pad, and The width of the first recess is smaller than the width of the second recess.

15. The semiconductor memory device according to claim 11, wherein, The width of the first portion decreases as it approaches the substrate.

16. The semiconductor memory device of claim 11, further comprising: A capacitor structure on the bonding pad, the capacitor structure including a lower electrode protruding away from the substrate in the vertical direction, a dielectric film disposed along the surface of the lower electrode, and an upper electrode on the dielectric film.

17. A method for manufacturing a semiconductor memory device, the method comprising: A bit line structure extending along a first horizontal direction is formed on the substrate; A contact plug is formed on the substrate that is adjacent to the bit line structure in a second horizontal direction and connected to the active region; A bonding pad is formed on the contact plug, the bonding pad including a pre-blocking film and a pre-metall film, the pre-blocking film extending along the sidewall and upper surface of the bit line structure, and the pre-metall film on the pre-blocking film; A metal film is formed by removing at least a portion of the pre-metal film and the pre-blocking film, the metal film having a first recess that exposes a portion of the bit line structure; A pre-spacer film is formed along the surface of the metal film within the first recess; A spacer pattern is formed by removing at least a portion of the pre-spacer film, the bit line structure, and the pre-blocking film, the spacer pattern having a second recess that exposes the inner sidewall of the bit line structure; A separation pattern is formed within the second recess, located between the spacer patterns; as well as An oxide film is formed on the spacer pattern. The oxide film is not formed between the bit line structure and the separation pattern.

18. The method according to claim 17, wherein, The width of the second recess is smaller than the width of the first recess.

19. The method of claim 17, wherein, The pre-spacer membrane and the separation pattern each comprise silicon nitride.

20. The method according to claim 17, in, The pre-blocking film comprises titanium nitride, and The pre-metallized film includes tungsten.

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