Floating gate memory chip stack capacitor structure and method of manufacture

Abstract

The present application relates to the technical fields of semiconductor device design and manufacturing, in particular to a floating gate memory chip laminated capacitor structure and a preparation method. The present application forms a first capacitor structure in a substrate under a third capacitor structure without increasing the chip layout area. Meanwhile, a first metal electrode, an interlayer dielectric layer and a second metal electrode are stacked in a top space to form a second capacitor structure in a vertical direction without increasing the chip layout area. The second region is left out to electrically connect the active area, the control gate and the first metal electrode with the same polarity, and to electrically connect the isolation trench, the floating gate and the second metal electrode with the same polarity. The third capacitor structure, the first capacitor structure and the second capacitor structure are connected in parallel to improve the floating gate memory chip capacitance value and the programming voltage, so as to realize a three-layer capacitor parallel laminated structure and achieve a higher capacitance density without increasing the chip layout area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device design and manufacturing technology, and in particular to a floating gate memory chip stacked capacitor structure and its fabrication method. Background Technology

[0002] Floating-gate memory chips widely utilize charge pump capacitors in high-voltage modules (HV Macros) to enable programming and erasing operations. Compared to conventional logic chips, floating-gate memory chips require higher operating voltages, necessitating larger capacitance values ​​to ensure the stability and efficiency of the charge pump capacitors. Traditionally, metal-oxide-semiconductor (MOS) capacitor structures are commonly used as charge pump capacitors in logic regions. However, this structure is susceptible to breakdown or leakage current under high-voltage conditions and struggles to meet the high capacitance density requirements of floating-gate memory chips. Therefore, current technologies typically shift towards using polysilicon-insulator-polysilicon (PIP) stacked capacitor designs as an alternative. This PIP stacked capacitor structure includes: a floating gate (FG) as one end of the capacitor, oxide-nitride-oxide (ONO) and tunnel oxide (Tunnel OX) layers as insulating dielectric layers, and an active region (AA) and control gate (CG) as the other end of the capacitor. The stacked structure is formed by two parallel PIP units, thereby improving the overall capacitance density and withstand voltage.

[0003] However, floating-gate memory chips in industrial and automotive applications must meet capacitance stability and efficiency requirements far exceeding those of the consumer market; and in the consumer electronics sector, even stricter cost constraints exist. On one hand, industrial / automotive grade chips often require increased programming voltages to obtain wider programming / erase voltage windows, thereby enhancing data retention and durability. This directly demands higher capacitance density in floating-gate memory chips to support high-current, high-voltage output. On the other hand, external floating-gate memory chips for low-power consumer applications urgently need to reduce the layout area of ​​charge pump capacitors to lower wafer manufacturing costs, further posing demands on the capacitance density of floating-gate memory chips.

[0004] Existing PIP stacked capacitor designs cannot fully meet the high capacitance density requirements of the aforementioned application areas. Therefore, how to improve the capacitance density of charge pump capacitors in existing floating gate memory chips has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The present invention aims to provide a floating gate memory chip stacked capacitor structure and a method for fabricating it, so as to improve the capacitance density of the floating gate memory chip and solve the problem that the capacitance density of the existing floating gate memory chip is not high enough.

[0006] To achieve the above objectives, a first aspect of the present invention provides a floating-gate memory chip stacked capacitor structure, comprising: A substrate, wherein an active region is disposed therein; The substrate surface is covered with a tunneling oxide layer, and a first region of the tunneling oxide layer surface is sequentially covered with a floating gate, an ONO dielectric layer and a control gate; Both the second region on the surface of the tunneling oxide layer and the surface of the control gate are deposited with an interlayer dielectric layer. A first metal electrode and a second metal electrode are disposed within the interlayer dielectric layer. The active region and the control gate are respectively electrically connected to the first metal electrode; the floating gate is electrically connected to the second metal electrode. The active region, the tunneling oxide layer, the floating gate, the ONO dielectric layer, and the control gate form a first capacitor structure; the first metal electrode, the interlayer dielectric layer, and the second metal electrode form a second capacitor structure.

[0007] The aforementioned floating-gate memory chip stacked capacitor structure, based on the PIP stacked capacitor structure formed by the active region-tunneling oxide layer-floating gate-ONO dielectric layer-floating gate, utilizes the top space of the control gate-ONO dielectric layer-floating gate to stack a first metal electrode, an interlayer dielectric layer, and a second metal electrode, forming a second capacitor structure in the vertical direction without increasing the chip layout area. The reserved second region allows for the electrical connection of the active region, control gate, and first metal electrode with the same polarity, and also allows for the electrical connection of the floating gate and second metal electrode with the same polarity. This parallel connection of the first and second capacitor structures increases the capacitance value and programming voltage of the PIP stacked capacitor structure, thereby realizing a multi-level parallel capacitor stacked structure. This multi-level parallel stacked structure achieves higher capacitance density without increasing the chip layout area, positively promoting the miniaturization of floating-gate memory chips.

[0008] Furthermore, the floating gate memory chip stacked capacitor structure further includes a first contact hole, a second contact hole, and a third contact hole; wherein: The first contact hole passes through the interlayer dielectric layer and the tunneling oxide layer to electrically connect the active region and the first metal electrode. The second contact hole passes through the interlayer dielectric layer to electrically connect the control gate and the first metal electrode; The third contact hole passes through the interlayer dielectric layer, the control gate, and the ONO dielectric layer to electrically connect the floating gate and the second metal electrode.

[0009] It should be noted that a contact hole is a conductive connection structure filled with metal or a metal mixture. The ONO dielectric layer is a three-layer dielectric structure consisting of oxide-nitride-oxide layers stacked sequentially. In this implementation, the contact hole electrically connects the active region, control gate, and first metal electrode with the same polarity, and also electrically connects the floating gate and second metal electrode with the same polarity. Since a second region is left on the surface of the tunneling oxide layer for depositing the interlayer dielectric layer, the first contact hole can pass through the interlayer dielectric layer and the tunneling oxide layer in the second region to connect the active region and the first metal electrode.

[0010] Furthermore, the floating gate memory chip stacked capacitor structure also includes a fourth contact hole; an isolation trench and a pad oxide layer are also provided in the substrate; one side of the pad oxide layer is attached to the isolation trench, and the other side of the pad oxide layer is attached to the active region; wherein: The fourth contact hole passes through the interlayer dielectric layer, the control gate, the ONO dielectric layer, the floating gate, and the tunneling oxide layer to electrically connect the isolation trench and the second metal electrode; The isolation trench, the liner oxide layer, and the active region form a third capacitor structure.

[0011] In this implementation, based on the first capacitor structure formed by the control gate-ONO dielectric layer-floating gate-tunneling oxide layer-active region, a third capacitor structure is formed in the substrate below the first capacitor structure by utilizing the electrical properties of the active region and the isolation trench, as well as the insulation properties of the pad oxide layer, without increasing the chip layout area. The second region provides a second connection for electrically connecting the active region, control gate, and first metal electrode with the same polarity, and also for electrically connecting the isolation trench, floating gate, and second metal electrode with the same polarity. This parallel connection of the first, second, and third capacitor structures, based on the aforementioned multi-level parallel capacitor stacked structure, further increases the number of capacitor layers within the original layout space, achieving a higher capacitor density.

[0012] Furthermore, the substrate is provided with a selection gate and a plurality of parallel isolation sub-trenches, each of the isolation sub-trenches being connected to the selection gate to form the isolation trench; The isolation sub-trenches and the active region form an interdigitated structure.

[0013] In this implementation, several isolation sub-trenches are arranged in parallel, with active regions spaced between each pair of isolation sub-trenches, thus forming an interpolation structure with the active regions. The interpolation structure increases the effective surface area between the isolation trenches and the active regions as capacitor electrodes, ultimately increasing the effective capacitance value of the third capacitor structure without increasing the chip layout area, achieving a higher capacitance density.

[0014] Further, the first metal electrode includes a first electrode strip and a plurality of first electrode fingers, and the second metal electrode includes a second electrode strip and a plurality of second electrode fingers; wherein: Each of the first electrode interdigitates is connected to the first electrode strip; Each of the second electrode interdigitates is connected to the second electrode strip; A plurality of first electrode intercalation fingers and a plurality of second electrode intercalation fingers are arranged alternately and at intervals within the interlayer dielectric layer to form an intercalation structure.

[0015] In this implementation, a plurality of first electrode interpolations and a plurality of second electrode interpolations form an interpolation structure within the interlayer dielectric layer. The interpolation structure increases the effective surface area between the first metal electrode and the second metal electrode, which serves as the capacitor electrode. Ultimately, without increasing the chip layout area, the effective capacitance value of the second capacitor structure is increased, resulting in a higher capacitance density.

[0016] Furthermore, the floating gate memory chip stacked capacitor structure also includes several vertically stacked second capacitor structures, wherein: Each of the second capacitor structures is vertically stacked through the interlayer dielectric layer corresponding to the second capacitor structure; The first metal electrodes of each second capacitor structure are electrically connected; the second metal electrodes of each second capacitor structure are electrically connected.

[0017] In this implementation, by vertically stacking multiple identical second capacitors, the effective capacitance value of the floating gate memory chip is further increased without increasing the chip layout area, thus achieving a higher capacitance density.

[0018] A second aspect of the present invention provides a method for fabricating a floating-gate memory chip multilayer capacitor structure, which is used to fabricate a floating-gate memory chip multilayer capacitor structure as described in any embodiment of the first aspect. The method includes the following steps: A substrate is determined, and an active region is formed in the substrate; A tunneling oxide layer is formed on the surface of the substrate; A floating gate, an ONO dielectric layer, and a control gate are sequentially formed in the first region on the surface of the tunneling oxide layer. An interlayer dielectric layer is deposited in the second region on the surface of the tunneling oxide layer and on the surface of the control gate. A first electrode trench and a second electrode trench are etched in the interlayer dielectric layer, thereby electrically connecting the active region and the control gate to the first electrode trench, and electrically connecting the floating gate to the second electrode trench. A first metal electrode is formed by filling the first electrode trench with a metallic substance, and a second metal electrode is formed by filling the second electrode trench with a metallic substance.

[0019] Further, determining the substrate and forming an active region in the substrate includes: Several parallel isolation sub-trenches are etched into the substrate; A first oxide layer is filled in each of the isolation sub-trenches to deposit a silicon nitride hard mask on the substrate and all the surfaces of the first oxide layer, and then photolithography is performed based on the silicon nitride hard mask to define the selection gate pattern; The substrate is etched based on the selected gate pattern to form a selected gate, and the selected gate is connected to each of the isolation sub-trenches; Photolithography and etching are performed on the substrate and all the isolation sub-trenches to remove the silicon nitride hard mask and the first oxide layer; The pad oxide layer is formed in the select gate and all the isolation sub-trenches, and then amorphous silicon is formed on the surface of the pad oxide layer; The selected gate and all the isolation trenches are defined as the isolation trenches, and the remaining area of ​​the substrate is defined as the active region.

[0020] Further, the interlayer dielectric layer deposited between the second region on the surface of the tunneling oxide layer and the surface of the control gate includes: A first connection hole is etched onto the surface of the control gate, such that the first connection hole is etched to the floating gate; A second connection hole is etched onto the surface of the control gate, such that the second connection hole is etched into the isolation trench; An interlayer dielectric layer is deposited in the second region on the surface of the tunneling oxide layer, the surface of the control gate, the first connection hole, and the second connection hole.

[0021] In this implementation, the first and second connecting holes are etched before depositing the interlayer dielectric layer, laying the foundation for the subsequent etching to form the third and fourth contact holes. Specifically, the interlayer dielectric layer fills the first and second connecting holes, so that when contact holes are subsequently etched through the connecting holes to form them, the interlayer dielectric layer attached to the inner wall of the first connecting hole can serve as the insulating medium between the third contact hole and the control gate, and the interlayer dielectric layer attached to the inner wall of the second connecting hole can serve as the insulating medium between the fourth contact hole and the control gate. This avoids electrical connections between structures of different polarities and improves the electrical stability of the parallel connection of the third capacitor structure, the first capacitor structure, and the second capacitor structure.

[0022] Further, the etching process to form a first electrode trench and a second electrode trench in the interlayer dielectric layer, thereby electrically connecting the active region and the control gate to the first electrode trench respectively, and electrically connecting the floating gate to the second electrode trench, includes: A first contact hole is etched on the surface of the interlayer dielectric layer, so that the first contact hole penetrates the interlayer dielectric layer and the tunneling oxide layer to the active region, and then the first contact hole is filled with a metal mixture. A second contact hole is etched on the surface of the interlayer dielectric layer, so that the second contact hole is etched through the interlayer dielectric layer to the control gate, and then the second contact hole is filled with a metal mixture; A third contact hole is etched on the surface of the interlayer dielectric layer, so that the third contact hole passes through the first connection hole and is etched to the floating gate, and then the third contact hole is filled with a metal mixture. A fourth contact hole is etched on the surface of the interlayer dielectric layer, so that the fourth contact hole passes through the second connection hole and is etched to the isolation trench, and then the fourth contact hole is filled with a metal mixture. The interlayer dielectric layer is etched to form a first electrode trench on the first contact hole and the second contact hole, and a second electrode trench on the third contact hole and the fourth contact hole.

[0023] In this implementation, an active region, a control gate, and a first metal electrode of the same polarity are electrically connected via contact holes, and an isolation trench, a floating gate, and a second metal electrode of the same polarity are also electrically connected. Since a second region is left on the surface of the tunneling oxide layer for depositing an interlayer dielectric layer, the first contact hole can pass through the interlayer dielectric layer and the tunneling oxide layer in the second region to connect the active region and the first metal electrode. Simultaneously, a third contact hole is etched through the first connection hole to the floating gate. The interlayer dielectric layer deposited in the first connection hole prevents the floating gate from being electrically connected to a control gate of different polarity. Similarly, a fourth contact hole is etched through the second connection hole to the isolation trench. The interlayer dielectric layer deposited in the second connection hole also prevents the isolation trench from being electrically connected to a control gate of different polarity, thus improving the electrical stability of the parallel connection of the third capacitor structure, the first capacitor structure, and the second capacitor structure.

[0024] Further, the first region on the surface of the tunneling oxide layer sequentially forms a floating gate, an ONO dielectric layer, and a control gate, including: Amorphous silicon is deposited on the surface of the tunneling oxide layer; The amorphous silicon is etched to form the floating gate in a first region on the surface of the tunneling oxide layer; An ONO dielectric is deposited on the tunneling oxide layer and the surface of the floating gate, and then the ONO dielectric on the surface of the tunneling oxide layer is etched to form an ONO dielectric layer on the surface of the floating gate. A control gate material is deposited on the tunneling oxide layer and the floating gate surface, and then the control gate material on the surface of the tunneling oxide layer is etched to form the control gate on the surface of the ONO dielectric layer.

[0025] In this implementation, an ONO dielectric layer is used as the inter-electrode insulating layer between the floating gate and the control gate, wherein the ONO dielectric layer is an insulating layer formed by stacking silicon oxide, silicon nitride and silicon oxide.

[0026] Further, the first electrode trench includes a first strip-shaped trench and a plurality of first interdigitation trenches, and the second electrode trench includes a second strip-shaped trench and a plurality of second interdigitation trenches; wherein: Each of the first interdigitated finger grooves is connected to the first strip groove; Each of the second interdigitated grooves is connected to the second strip groove; A plurality of first interdigitation grooves and a plurality of second interdigitation grooves are arranged alternately and at intervals within the interlayer dielectric layer to form an interdigitation structure.

[0027] In this implementation, a plurality of first electrode interpolations and a plurality of second electrode interpolations form an interpolation structure within the interlayer dielectric layer. The interpolation structure increases the effective surface area between the first metal electrode and the second metal electrode, which serves as the capacitor electrode. Ultimately, without increasing the chip layout area, the effective capacitance value of the second capacitor structure is increased, resulting in a higher capacitance density. Attached Figure Description

[0028] Figure 1 This is a cross-sectional view of a floating gate memory chip stacked capacitor structure provided in an embodiment of the present invention; Figure 2 This is a cross-sectional view of a floating gate memory chip stacked capacitor structure provided in an embodiment of the present invention; Figure 3 This is a schematic flowchart illustrating a method for fabricating a floating-gate memory chip multilayer capacitor structure according to an embodiment of the present invention. Figure 4 a to Figure 14 a is a top view of the method for fabricating the floating gate memory chip stacked capacitor structure provided in an embodiment of the present invention; Figure 4 b to Figure 14 b is a cross-sectional view of the method for fabricating the floating gate memory chip stacked capacitor structure provided in the embodiment of the present invention; Figure 15 a to Figure 16a is a top view of another floating gate memory chip stacked capacitor structure provided in an embodiment of the present invention; Figure 15 b to Figure 16 b is a cross-sectional view of another floating gate memory chip stacked capacitor structure provided in an embodiment of the present invention; Figure 17 a to Figure 20 a is a top view of another floating gate memory chip stacked capacitor structure provided in an embodiment of the present invention; Figure 17 b to Figure 20 b is a cross-sectional view of another floating gate memory chip stacked capacitor structure provided in an embodiment of the present invention; Wherein: 1. Substrate; 2. Isolation trench; 21. Isolation sub-trench; 22. Select gate; 3. Pad oxide layer; 4. Active region; 51. Tunneling oxide layer; 52. Floating gate; 53. ONO dielectric layer; 54. Control gate; 61. First connection hole; 62. Second connection hole; 7. Interlayer dielectric layer; 81. First contact hole; 82. Second contact hole; 83. Third contact hole; 84. Fourth contact hole; 85. Fifth contact hole; 86. Sixth contact hole; 91. First metal electrode; 92. Second metal electrode; 911. First electrode strip; 912. First electrode finger; 921. Second electrode strip; 922. Second electrode finger. Detailed Implementation

[0029] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "first," "second," etc., in the specification and claims or the foregoing drawings are used to distinguish different objects and not to describe a particular order.

[0030] The first aspect of this invention provides a floating-gate memory chip stacked capacitor structure. Please refer to... Figure 1 The floating gate 52 memory chip multilayer capacitor structure includes: Substrate 1, wherein an active region 4 is disposed therein; The surface of the substrate 1 is covered with a tunneling oxide layer 51, and a first region on the surface of the tunneling oxide layer 51 is sequentially covered with a floating gate 52, an ONO dielectric layer 53 and a control gate 54. An interlayer dielectric layer 7 is deposited on the second region of the surface of the tunneling oxide layer 51 and the surface of the control gate 54. The interlayer dielectric layer 7 is provided with a first metal electrode 91 and a second metal electrode 92. The active region 4 and the control gate 54 are electrically connected to the first metal electrode 91, respectively; the floating gate 52 is electrically connected to the second metal electrode 92. The active region 4, the tunneling oxide layer 51, the floating gate 52, the ONO dielectric layer 53, and the control gate 54 form a first capacitor structure; the first metal electrode 91, the interlayer dielectric layer 7, and the second metal electrode 92 form a second capacitor structure.

[0031] The aforementioned floating-gate 52 memory chip stacked capacitor structure, based on the PIP stacked capacitor structure formed by active region 4-tunneling oxide layer 51-floating gate 52-ONO dielectric layer 53-floating gate 52, utilizes the top space of the control gate-ONO dielectric layer 53-floating gate 52 to stack a first metal electrode 91, an interlayer dielectric layer 7, and a second metal electrode 92, forming a second capacitor structure in the vertical direction without increasing the chip layout area. The reserved second area allows the active region 4, control gate 54, and first metal electrode 91, which have the same polarity, to be electrically connected, and the floating gate 52 and second metal electrode 92, which have the same polarity, to be electrically connected, thus connecting the first and second capacitor structures in parallel. This increases the capacitance value and programming voltage of the PIP stacked capacitor structure, thereby realizing a multi-level parallel capacitor stacked structure. This multi-level parallel stacked structure achieves higher capacitance density without increasing the chip layout area, positively promoting the miniaturization of the floating-gate 52 memory chip.

[0032] Further, please refer to Figure 1 The floating gate 52 memory chip stacked capacitor structure further includes a first contact hole 81, a second contact hole 82, and a third contact hole 83; wherein: The first contact hole 81 passes through the interlayer dielectric layer 7 and the tunneling oxide layer 51 to electrically connect the active region 4 and the first metal electrode 91. The second contact hole 82 passes through the interlayer dielectric layer 7 to electrically connect the control gate 54 and the first metal electrode 91; The third contact hole 83 passes through the interlayer dielectric layer 7, the control gate 54 and the ONO dielectric layer 53 to electrically connect the floating gate 52 and the second metal electrode 92.

[0033] It should be noted that a contact hole is a conductive connection structure filled with metal or a metal mixture. The ONO dielectric layer 53 is a three-layer dielectric structure consisting of oxide-nitride-oxide layers stacked sequentially. In this implementation, the contact hole electrically connects the active region 4, the control gate 54, and the first metal electrode 91, which have the same polarity, and also electrically connects the isolation trench 2, the floating gate 52, and the second metal electrode 92, which have the same polarity. Since a second region is left on the surface of the tunneling oxide layer 51 for depositing the interlayer dielectric layer 7, the first contact hole 81 can pass through the interlayer dielectric layer 7 and the tunneling oxide layer 51 in the second region to connect the active region 4 and the first metal electrode 91.

[0034] Further, please refer to Figure 2 In this embodiment, the floating gate 52 memory chip stacked capacitor structure further includes a fourth contact hole 84; an isolation trench 2 and a pad oxide layer 3 are also provided in the substrate 1; one side of the pad oxide layer 3 is attached to the isolation trench 2, and the other side of the pad oxide layer 3 is attached to the active region 4; wherein: The fourth contact hole 84 passes through the interlayer dielectric layer 7, the control gate 54, the ONO dielectric layer 53, the floating gate 52 and the tunneling oxide layer 51 to electrically connect the isolation trench 2 and the second metal electrode 92; The isolation trench 2, the liner oxide layer 3, and the active region 4 form a third capacitor structure.

[0035] In this implementation, based on the first capacitor structure formed by the control gate 54-ONO dielectric layer 53-floating gate 52-tunneling oxide layer 51-active region 4, a third capacitor structure is formed in the substrate 1 below the first capacitor structure by utilizing the electrical properties of the active region 4 and the isolation trench 2, as well as the insulating properties of the pad oxide layer 3, without increasing the chip layout area. The second region provides a second connection for the active region 4, control gate 54, and first metal electrode 91 with the same polarity, and also connects the isolation trench 2, floating gate 52, and second metal electrode 92 with the same polarity. This parallel connection of the first, second, and third capacitor structures further increases the number of capacitor layers within the original layout space, achieving a higher capacitor density.

[0036] Furthermore, please refer to the following: Figure 7 a, Figure 7 b、 Figure 8 a and Figure 8 b. Among them, Figure 6 b is Figure 6 The dashed line in 'a' represents a cross-sectional view of the cross section. Figure 8 b is Figure 8The dashed line in section a represents a cross-sectional view. The isolation trench 2 and the active region 4 are separated by a pad oxide layer 3. The pad oxide layer 3... Figure 6 a and Figure 7 Not shown in section a. The substrate 1 is provided with a selection gate 22 and a plurality of parallel isolation sub-trenches 21, each of the isolation sub-trenches 21 being connected to the selection gate 22, thereby forming the isolation trench 2; The plurality of the isolation sub-grooves 21 and the active region 4 form an interdigitated structure.

[0037] In this implementation, several isolation sub-trenches 21 are arranged in parallel, with active regions 4 spaced between each pair of isolation sub-trenches 21, thus forming an interpolation structure with the active regions 4. The interpolation structure increases the effective surface area between the isolation trenches 2 and the active regions 4 as capacitor electrodes, ultimately increasing the effective capacitance value of the third capacitor structure without increasing the chip layout area, achieving a higher capacitance density.

[0038] Furthermore, please refer to the following: Figure 13 a, Figure 13 b、 Figure 14 a and Figure 14 b. Among them, Figure 13 b is Figure 13 The dashed line in 'a' represents a cross-sectional view of the cross section. Figure 14 b is Figure 14 The dashed line in figure a represents a cross-sectional view. In a preferred embodiment shown in the figure, both the first metal electrode 91 and the second metal electrode 92 are plate structures. More specifically, the first metal electrode 91 and the second metal electrode 92 are arranged as plates on the left and right sides of the interlayer dielectric layer 7, facing each other.

[0039] This embodiment effectively expands the volume of the first metal electrode 91 and the second metal electrode 92, thereby improving the charge storage capacity of the stacked capacitor of the floating gate 52 memory chip.

[0040] Furthermore, in a preferred embodiment, the floating gate 52 memory chip stacked capacitor structure further includes a plurality of vertically stacked second capacitor structures, wherein: Each of the second capacitor structures is vertically stacked through the interlayer dielectric layer 7 corresponding to the second capacitor structure; The first metal electrodes 91 of each of the second capacitor structures are electrically connected through a fifth contact hole 85; the second metal electrodes 92 of each of the second capacitor structures are electrically connected through a sixth contact hole 86.

[0041] In this implementation, by vertically stacking multiple identical second capacitors, the effective capacitance value of the floating gate 52 memory chip is further increased without increasing the chip layout area, thus achieving a higher capacitance density.

[0042] Furthermore, please refer to the following: Figure 15 a, Figure 15 b、 Figure 16 a and Figure 16 b. Among them, Figure 15 b is Figure 15 The dashed line in 'a' represents a cross-sectional view of the cross section. Figure 16 b is Figure 16 The dashed line in figure a represents a cross-sectional view. In a preferred embodiment shown in the figure, the first metal electrode 91 and the second metal electrode 92 are arranged vertically opposite each other as a plate within the interlayer dielectric layer 7. Compared to being arranged opposite each other on the left and right sides, this embodiment increases the effective surface area between the first metal electrode 91 and the second metal electrode 92 by arranging them vertically opposite each other without increasing the chip layout area, thereby increasing the effective capacitance value of the second capacitor structure and achieving a higher capacitance density.

[0043] Furthermore, in a preferred embodiment, the floating gate 52 memory chip stacked capacitor structure further includes a plurality of vertically stacked second capacitor structures, wherein: Each of the second capacitor structures is vertically stacked through the interlayer dielectric layer 7 corresponding to the second capacitor structure; The first metal electrodes 91 of each of the second capacitor structures are electrically connected through a fifth contact hole 85; the second metal electrodes 92 of each of the second capacitor structures are electrically connected through a sixth contact hole 86.

[0044] In this implementation, by vertically stacking multiple identical second capacitors, the effective capacitance value of the floating gate 52 memory chip is further increased without increasing the chip layout area, thus achieving a higher capacitance density.

[0045] Furthermore, please refer to the following: Figure 17 a, Figure 17 b、 Figure 18 a and Figure 18 b. Among them, Figure 17 b is Figure 17 The dashed line in 'a' represents a cross-sectional view of the cross section. Figure 18 b is Figure 18 The dashed line in figure a represents a cross-sectional view. In a preferred embodiment shown in the figure, the first metal electrode 91 includes a first electrode strip 911 and a plurality of first electrode fingers 912, and the second metal electrode 92 includes a second electrode strip 921 and a plurality of second electrode fingers 922; wherein: Each of the first electrode interdigitates 912 is connected to the first electrode strip 911; Each of the second electrode interdigitates 922 is connected to the second electrode strip 921; A plurality of first electrode intercalation fingers 912 and a plurality of second electrode intercalation fingers 922 are arranged alternately and at intervals within the interlayer dielectric layer 7 to form an intercalation structure.

[0046] In this implementation, a plurality of first electrode intercalation fingers 912 and a plurality of second electrode intercalation fingers 922 form an intercalation structure within the interlayer dielectric layer 7. This intercalation structure increases the effective surface area between the first metal electrode 91 and the second metal electrode 92, which serves as the capacitor electrode. Compared to the plate structure and the vertically opposed arrangement structure in the above embodiments, this significantly increases the effective surface area. Ultimately, without increasing the chip layout area, the effective capacitance value of the second capacitor structure is increased, achieving a higher capacitance density.

[0047] Furthermore, please refer to the following: Figure 19 a, Figure 19 b、 Figure 20 a and Figure 20 b. Among them, Figure 19 b is Figure 19 The dashed line in 'a' represents a cross-sectional view of the cross section. Figure 20 b is Figure 20 The dashed line in 'a' represents a cross-sectional view. In a preferred embodiment shown in the figure, the floating gate 52 memory chip stacked capacitor structure further includes several vertically stacked second capacitor structures, wherein: Each of the second capacitor structures is vertically stacked through the interlayer dielectric layer 7 corresponding to the second capacitor structure; The first metal electrodes 91 of each of the second capacitor structures are electrically connected through a fifth contact hole 85; the second metal electrodes 92 of each of the second capacitor structures are electrically connected through a sixth contact hole 86.

[0048] In this implementation, by vertically stacking multiple identical second capacitors, the effective capacitance value of the floating gate 52 memory chip is further increased without increasing the chip layout area, thus achieving a higher capacitance density.

[0049] It should also be noted that in the above embodiments, multiple first contact holes 81, second contact holes 82, third contact holes 83 and fourth contact holes 84 are provided at intervals, which improves the electrical connection stability and physical connection stability between the first capacitor structure, the second capacitor structure and the third capacitor structure, and also improves the charge conduction efficiency between the first capacitor structure, the second capacitor structure and the third capacitor structure.

[0050] It should be understood that in some possible embodiments, the position and number of the first contact hole 81, the second contact hole 82, the third contact hole 83 and the fourth contact hole 84 can be adaptively adjusted.

[0051] refer to Figure 3 The second aspect of this invention provides a method for fabricating a floating-gate memory chip multilayer capacitor structure, comprising the following steps: S101. Determine substrate 1 and form active region 4 in substrate 1; S102, A tunneling oxide layer 51 is formed on the surface of the substrate 1; S103, a floating gate 52, an ONO dielectric layer 53 and a control gate 54 are sequentially formed in the first region on the surface of the tunneling oxide layer 51; S104. An interlayer dielectric layer 7 is deposited in the second region on the surface of the tunneling oxide layer 51 and on the surface of the control gate 54. S105. A first electrode trench and a second electrode trench are etched in the interlayer dielectric layer 7, thereby electrically connecting the active region 4 and the control gate 54 to the first electrode trench, and electrically connecting the floating gate 52 to the second electrode trench. S106. Fill the first electrode trench with a metallic substance to form a first metal electrode 91, and fill the second electrode trench with a metallic substance to form a second metal electrode 92.

[0052] refer to Figure 4 a to Figure 14 a and Figure 4 b to Figure 14 b. In another embodiment of the present invention, a method for fabricating a floating-gate memory chip multilayer capacitor structure is also provided, which is used to fabricate a floating-gate 52 memory chip multilayer capacitor structure. The method includes the following steps: S1. Determine substrate 1, and form isolation trench 2, pad oxide layer 3, and active region 4 in substrate 1, including: refer to Figure 4 a and Figure 4 b, Figure 4 b is Figure 4 The dashed lines in the top view shown in Figure a represent a cross-sectional view generated by the cross-section. Specifically, a plurality of parallel isolation sub-trenches 21 are etched into the substrate 1; a first oxide layer is filled in each of the isolation sub-trenches 21 to deposit a silicon nitride hard mask on the substrate 1 and all the surfaces of the first oxide layer, and then photolithography is performed based on the silicon nitride hard mask to define the pattern of the selection gate 22.

[0053] refer to Figure 5 a and Figure 5 b, Figure 5 b is Figure 5The dashed lines in the top view shown in Figure a represent a cross-sectional view generated by the cross-section. Specifically, the substrate 1 is etched based on the pattern of the selection gate 22 to form the selection gate 22, and the selection gate 22 is connected to each of the isolation sub-trenches 21.

[0054] refer to Figure 6 a and Figure 6 b, Figure 6 b is Figure 6 The dashed lines in the top view shown in Figure a represent a cross-sectional view generated by cross-section. Specifically, the substrate 1 and all the isolation trenches 21 are photolithographically etched and etched to remove the silicon nitride hard mask and the first oxide layer.

[0055] refer to Figure 7 a and Figure 7 b, Figure 7 b is Figure 7 The dashed lines in the top view shown in Figure a represent a cross-sectional view generated by the cross-section. Specifically, the pad oxide layer 3 is formed in the selection gate 22 and all the isolation sub-trenches 21, and then amorphous silicon is formed on the surface of the pad oxide layer 3; The selection gate 22 and all the isolation trenches 2 are defined as the isolation trenches 2, and the remaining area of ​​the substrate 1 is defined as the active region 4; Chemical mechanical polishing is performed on the surface of substrate 1 to smooth the isolation trench 2 and the active region 4.

[0056] To further illustrate the interdigitation structure formed in the above steps, please refer to the following: Figure 7 a, Figure 7 b、 Figure 8 a and Figure 8 b, of which Figure 7 b is Figure 7 The dashed lines in the top view shown in Figure a represent the cross-section generated from the cross-section. Figure 8 b is Figure 8 The dashed lines in the top view shown in Figure a represent the cross-section generated from the cross-section. It should be noted that... Figure 7 a and Figure 8 The pad oxide layer 3 is not shown in figure a. As shown in the figure, several isolation sub-trenches 21 are arranged side by side, with active regions 4 between each pair of isolation sub-trenches 21, thus forming an interdigitated structure with the active regions 4. The interdigitated structure increases the effective surface area between the isolation trenches 2 and the active regions 4 as capacitor electrodes, ultimately increasing the effective capacitance value of the third capacitor structure without increasing the chip layout area, achieving a higher capacitance density.

[0057] S2, Reference Figure 9 a and Figure 9 b, Figure 9 b is Figure 9The dashed lines in the top view shown in Figure a represent a cross-sectional view generated by the cross-section. Specifically, a tunneling oxide layer 51 is formed on the surface of the substrate 1.

[0058] S3, Reference Figure 9 a and Figure 9 b. A floating gate 52, an ONO dielectric layer 53, and a control gate 54 are sequentially formed in a first region on the surface of the tunneling oxide layer 51, including: Amorphous silicon is deposited on the surface of the tunneling oxide layer 51; The amorphous silicon is etched to form the floating gate 52 in a first region on the surface of the tunneling oxide layer 51; An ONO dielectric is deposited on the surface of the tunneling oxide layer 51 and the floating gate 52, and then the ONO dielectric on the surface of the tunneling oxide layer 51 is etched to form an ONO dielectric layer 53 on the surface of the floating gate 52. A control gate 54 material is deposited on the surface of the tunneling oxide layer 51 and the floating gate 52, and then the control gate 54 material on the surface of the tunneling oxide layer 51 is etched to form the control gate 54 on the surface of the ONO dielectric layer 53.

[0059] S4, Reference Figure 10 a and Figure 10 b, Figure 10 b is Figure 10 The dashed lines in the top view shown in Figure a represent a cross-sectional view generated from a cross section. Specifically, an interlayer dielectric layer 7 is deposited in the second region on the surface of the tunneling oxide layer 51 and the surface of the control gate 54, comprising: A plurality of first connection holes 61 are etched on the surface of the control gate 54, such that each first connection hole 61 is etched to the floating gate 52; A plurality of second connection holes 62 are etched on the surface of the control gate 54, such that each second connection hole 62 is etched to the isolation trench 2; An interlayer dielectric layer 7 is deposited in the second region on the surface of the tunneling oxide layer 51, the surface of the control gate 54, all the first connection holes 61 and all the second connection holes 62.

[0060] It should be noted that the number and position of the plurality of first connecting holes 61 and the plurality of second connecting holes 62 are set accordingly based on the number and position of the plurality of isolation sub-grooves 21.

[0061] In a preferred embodiment, the method for etching the first connecting hole 61 and the second connecting hole 62 is as follows: The control gate 54 is etched using a GP (Gated Poly) grooving process, so that the first connection hole 61 and the second connection hole 62 are respectively etched onto the top silicon oxide layer of the ONO dielectric layer 53.

[0062] The ONO dielectric layer 53 is further etched using the SPA process, which etches the middle silicon nitride layer and the bottom silicon oxide layer of the ONO dielectric layer 53 through the first connection hole 61 and the second connection hole 62. Finally, each of the first connection holes 61 is etched to the floating gate 52 and each of the second connection holes 62 is etched to the isolation trench 2.

[0063] S5, Reference Figure 11 a, Figure 11 b、 Figure 12 a and Figure 12 b. Among them, Figure 10 b is Figure 10 The dashed lines in the top view shown in Figure a represent the cross-section generated from the cross-section. Figure 11 b is Figure 11 The dashed lines in the top view shown in Figure a represent a cross-sectional view generated from the cross-section. A first electrode trench and a second electrode trench are etched in the interlayer dielectric layer 7, thereby electrically connecting the active region 4 and the control gate 54 to the first electrode trench, and electrically connecting the isolation trench 2 and the floating gate 52 to the second electrode trench, respectively. This includes: A plurality of first contact holes 81 are etched on the surface of the interlayer dielectric layer 7, such that each first contact hole 81 is etched through the interlayer dielectric layer 7 and the tunneling oxide layer 51 to the active region 4, and then each first contact hole 81 is filled with a metal mixture or metal substance. A plurality of second contact holes 82 are etched on the surface of the interlayer dielectric layer 7, such that each second contact hole 82 passes through the interlayer dielectric layer 7 and is etched to the control gate 54, and then each second contact hole 82 is filled with a metal mixture or metal material. A plurality of third contact holes 83 are etched on the surface of the interlayer dielectric layer 7, such that each third contact hole 83 passes through the corresponding first connection hole 61 and is etched to the floating gate 52, and then each third contact hole 83 is filled with a metal mixture or metal material; A plurality of fourth contact holes 84 are etched on the surface of the interlayer dielectric layer 7, such that each fourth contact hole 84 passes through the corresponding second connection hole 62 and is etched to the isolation trench 2, and then each fourth contact hole 84 is filled with a metal mixture or metal substance.

[0064] It should be noted that the number and position of the plurality of first contact holes 81, second contact holes 82, third contact holes 83 and fourth contact holes 84 are set accordingly based on the number and position of the plurality of isolation sub-grooves 21.

[0065] By setting multiple first contact holes 81, second contact holes 82, third contact holes 83 and fourth contact holes 84, they can cooperate with the interdigitated structures formed in the third capacitor structure and the second capacitor structure, thereby improving the charge flow rate between the same polarity structures in the third capacitor structure, the first capacitor structure and the second capacitor structure, and making the parallel electrical connection between the stacked capacitor structures more stable.

[0066] The interlayer dielectric layer 7 is etched to form first electrode trenches on all the first contact holes 81 and all the second contact holes 82, and to form second electrode trenches on all the third contact holes 83 and all the fourth contact holes 84.

[0067] It should be noted that, for the purpose of demonstrating the structure, Figure 11 a and Figure 12 Interlayer medium layer 7 is not shown in a.

[0068] S6, please refer to this as well. Figure 13 a, Figure 13 b、 Figure 14 a and Figure 14 b. Among them, Figure 13 b is Figure 13 The dashed lines in the top view shown in Figure a represent the cross-section generated from the cross-section. Figure 14 b is Figure 14 The dashed lines in the top view shown in Figure a represent a cross-sectional view generated by the cross-section. Metal material is filled into the first electrode trench to form a first metal electrode 91, and metal material is filled into the second electrode trench to form a second metal electrode 92.

[0069] It should be noted that, for the purpose of demonstrating the structure, Figure 13 a and Figure 14 Interlayer medium layer 7 is not shown in a.

[0070] S7, please refer to this as well. Figure 13 a, Figure 13 b、 Figure 14 a and Figure 14 b. Based on the second capacitor structure, a second capacitor structure is further stacked in the vertical direction, including: An interlayer dielectric layer 7 is deposited on the surface of the floating gate 52 memory chip capacitor structure.

[0071] A plurality of fifth contact holes 85 are etched on the surface of the interlayer dielectric layer 7, such that each fifth contact hole 85 passes through the interlayer dielectric layer 7 and is etched to the first electrode strip 911, and then each fifth contact hole 85 is filled with a metal mixture or metal substance.

[0072] A plurality of sixth contact holes 86 are etched on the surface of the interlayer dielectric layer 7, such that each sixth contact hole 86 passes through the interlayer dielectric layer 7 and is etched to the second electrode strip 921, and then each sixth contact hole 86 is filled with a metal mixture or metal substance.

[0073] The interlayer dielectric layer 7 is etched to form first electrode trenches on all the fifth contact holes 85 and second electrode trenches on all the sixth contact holes 86.

[0074] A first metal electrode 91 is formed by filling the first electrode trench with a metallic substance, and a second metal electrode 92 is formed by filling the second electrode trench with a metallic substance.

[0075] refer to Figure 13 a, Figure 13 b、 Figure 14 a and Figure 14 As shown in Figure b, the first metal electrode 91 and the second metal electrode 92 are plate structures. Specifically, in each second capacitor structure, the first metal electrode 91 and the second metal electrode 92 are arranged opposite each other.

[0076] In another preferred embodiment, please refer to [the following text is also included]. Figure 15 a, Figure 15 b、 Figure 16 a and Figure 16 b. Among them, Figure 15 b is Figure 15 The dashed lines in the top view shown in Figure a represent the cross-section generated from the cross-section. Figure 16 b is Figure 16 The dashed lines in the top view shown in Figure a represent the cross-section generated from the cross-section.

[0077] In the embodiment shown in the figure, step S5 includes: etching the interlayer dielectric layer 7 to form a first electrode trench on all the first contact holes 81 and all the second contact holes 82, and then filling the first electrode trench with a metal material to form a first metal electrode 91.

[0078] An interlayer dielectric layer 7 is grown on the first metal electrode 91, and then the interlayer dielectric layer 7 is etched to form a second electrode trench on all the third contact holes 83 and all the fourth contact holes 84, and the second electrode trench is filled with a metal material to form a second metal electrode 92.

[0079] Further, step S7 includes: An interlayer dielectric layer 7 is deposited on the surface of the floating gate 52 memory chip capacitor structure.

[0080] A plurality of fifth contact holes 85 are etched on the surface of the interlayer dielectric layer 7, such that each fifth contact hole 85 passes through the interlayer dielectric layer 7 and is etched to the first electrode strip 911, and then each fifth contact hole 85 is filled with a metal mixture or metal substance.

[0081] A plurality of sixth contact holes 86 are etched on the surface of the interlayer dielectric layer 7, such that each sixth contact hole 86 passes through the interlayer dielectric layer 7 and is etched to the second electrode strip 921, and then each sixth contact hole 86 is filled with a metal mixture or metal substance.

[0082] The interlayer dielectric layer 7 is etched to form first electrode trenches on all the fifth contact holes 85, and the first electrode trenches are filled with metal material to form first metal electrodes 91.

[0083] An interlayer dielectric layer 7 is grown on the first metal electrode 91, and then the interlayer dielectric layer 7 is etched to form a second electrode trench on all the sixth contact holes 86, and the second electrode trench is filled with a metal material to form a second metal electrode 92.

[0084] The above embodiment increases the effective surface area between the first metal electrode 91 and the second metal electrode 92 by setting the structure with the upper and lower electrodes opposite each other, thereby increasing the effective capacitance value of the second capacitor structure and achieving a higher capacitance density.

[0085] In yet another preferred embodiment, please refer to [the following text is also included]. Figure 17 a, Figure 17 b、 Figure 18 a and Figure 18 b. Among them, Figure 17 b is Figure 17 The dashed lines in the top view shown in Figure a represent the cross-section generated from the cross-section. Figure 18 b is Figure 18 The dashed lines in the top view shown in Figure a represent a cross-sectional view generated from the cross-section. The first electrode trench includes a first strip-shaped trench and a plurality of first interdigitation trenches, and the second electrode trench includes a second strip-shaped trench and a plurality of second interdigitation trenches. Each first interdigitation trench is connected to a first strip-shaped trench; each second interdigitation trench is connected to a second strip-shaped trench; the plurality of first interdigitation trenches and the plurality of second interdigitation trenches are arranged alternately and at intervals within the interlayer dielectric layer 7, forming an interdigitation structure.

[0086] Further, the first strip groove is filled with metal material to form a first electrode strip 911; each of the first insertion finger grooves is filled with metal material to form a plurality of first electrode insertion fingers 912; the second strip groove is filled with metal material to form a second electrode strip 921; and each of the second insertion finger grooves is filled with metal material to form a plurality of second electrode insertion fingers 922.

[0087] Furthermore, please refer to the following: Figure 19 a, Figure 19 b、 Figure 20 a and Figure 20 b. Among them, Figure 19 b is Figure 19 The dashed lines in the top view shown in Figure a represent the cross-section generated from the cross-section. Figure 20 b is Figure 20 The dashed lines in the top view shown in Figure a represent the cross-sectional view generated from the cross-section. In this embodiment, step S7 includes: An interlayer dielectric layer 7 is deposited on the surface of the floating gate 52 memory chip capacitor structure.

[0088] A plurality of fifth contact holes 85 are etched on the surface of the interlayer dielectric layer 7, such that each fifth contact hole 85 passes through the interlayer dielectric layer 7 and is etched to the first electrode strip 911, and then each fifth contact hole 85 is filled with a metal mixture or metal substance.

[0089] A plurality of sixth contact holes 86 are etched on the surface of the interlayer dielectric layer 7, such that each sixth contact hole 86 passes through the interlayer dielectric layer 7 and is etched to the second electrode strip 921, and then each sixth contact hole 86 is filled with a metal mixture or metal substance.

[0090] The interlayer dielectric layer 7 is etched to form first electrode trenches on all the fifth contact holes 85 and second electrode trenches on all the sixth contact holes 86.

[0091] The first electrode trench includes a first strip trench and a plurality of first interdigitation trenches, and the second electrode trench includes a second strip trench and a plurality of second interdigitation trenches; wherein: each first interdigitation trench is connected to the first strip trench; each second interdigitation trench is connected to the second strip trench; the plurality of first interdigitation trenches and the plurality of second interdigitation trenches are arranged alternately and at intervals within the interlayer dielectric layer 7 to form an interdigitation structure.

[0092] The first strip groove is filled with metal to form a first electrode strip 911; each of the first insertion grooves is filled with metal to form a plurality of first electrode insertion fingers 912; the second strip groove is filled with metal to form a second electrode strip 921; and each of the second insertion grooves is filled with metal to form a plurality of second electrode insertion fingers 922.

[0093] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the concept of this application, and these improvements and substitutions should also be considered within the scope of protection of this invention. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A floating-gate memory chip multilayer capacitor structure, characterized in that, include: A substrate, wherein an active region is disposed therein; The substrate surface is covered with a tunneling oxide layer, and a first region of the tunneling oxide layer surface is sequentially covered with a floating gate, an ONO dielectric layer and a control gate; Both the second region on the surface of the tunneling oxide layer and the surface of the control gate are deposited with an interlayer dielectric layer. A first metal electrode and a second metal electrode are disposed within the interlayer dielectric layer. The active region and the control gate are respectively electrically connected to the first metal electrode; the floating gate is electrically connected to the second metal electrode. The active region, the tunneling oxide layer, the floating gate, the ONO dielectric layer, and the control gate form a first capacitor structure; the first metal electrode, the interlayer dielectric layer, and the second metal electrode form a second capacitor structure.

2. The floating gate memory chip stacked capacitor structure according to claim 1, characterized in that, It also includes a first contact hole, a second contact hole, and a third contact hole; wherein: The first contact hole passes through the interlayer dielectric layer and the tunneling oxide layer to electrically connect the active region and the first metal electrode. The second contact hole passes through the interlayer dielectric layer to electrically connect the control gate and the first metal electrode; The third contact hole passes through the interlayer dielectric layer, the control gate, and the ONO dielectric layer to electrically connect the floating gate and the second metal electrode.

3. The floating gate memory chip stacked capacitor structure according to claim 1, characterized in that, It also includes a fourth contact hole; the substrate further includes an isolation trench and a pad oxide layer; one side of the pad oxide layer is attached to the isolation trench, and the other side of the pad oxide layer is attached to the active region; wherein: The fourth contact hole passes through the interlayer dielectric layer, the control gate, the ONO dielectric layer, the floating gate, and the tunneling oxide layer to electrically connect the isolation trench and the second metal electrode; The isolation trench, the liner oxide layer, and the active region form a third capacitor structure.

4. The floating gate memory chip stacked capacitor structure according to claim 3, characterized in that, The substrate has a selection gate and a plurality of parallel isolation sub-trenches, each of the isolation sub-trenches being connected to the selection gate to form the isolation trench; The isolation sub-trenches and the active region form an interdigitated structure.

5. The floating gate memory chip stacked capacitor structure according to claim 1, characterized in that, The first metal electrode includes a first electrode strip and a plurality of first electrode fingers, and the second metal electrode includes a second electrode strip and a plurality of second electrode fingers; wherein: Each of the first electrode interdigitates is connected to the first electrode strip; Each of the second electrode interdigitates is connected to the second electrode strip; A plurality of first electrode intercalation fingers and a plurality of second electrode intercalation fingers are arranged alternately and at intervals within the interlayer dielectric layer to form an intercalation structure.

6. The floating gate memory chip stacked capacitor structure according to claim 1, characterized in that, It also includes several vertically stacked second capacitor structures, wherein: Each of the second capacitor structures is vertically stacked through the interlayer dielectric layer corresponding to the second capacitor structure; The first metal electrodes of each second capacitor structure are electrically connected; the second metal electrodes of each second capacitor structure are electrically connected.

7. A method for fabricating a floating-gate memory chip multilayer capacitor structure, characterized in that, The method for fabricating the floating-gate memory chip multilayer capacitor structure as described in any one of claims 1 to 6 includes the following steps: A substrate is determined, and an active region is formed in the substrate; A tunneling oxide layer is formed on the surface of the substrate; A floating gate, an ONO dielectric layer, and a control gate are sequentially formed in the first region on the surface of the tunneling oxide layer. An interlayer dielectric layer is deposited in the second region on the surface of the tunneling oxide layer and on the surface of the control gate. A first electrode trench and a second electrode trench are etched in the interlayer dielectric layer, thereby electrically connecting the active region and the control gate to the first electrode trench, and electrically connecting the floating gate to the second electrode trench. A first metal electrode is formed by filling the first electrode trench with a metallic substance, and a second metal electrode is formed by filling the second electrode trench with a metallic substance.

8. The method for fabricating a floating-gate memory chip stacked capacitor structure according to claim 7, characterized in that, The determination of the substrate and the formation of an active region in the substrate include: Several parallel isolation sub-trenches are etched into the substrate; A first oxide layer is filled in each of the isolation sub-trenches to deposit a silicon nitride hard mask on the substrate and all the surfaces of the first oxide layer, and then photolithography is performed based on the silicon nitride hard mask to define the selection gate pattern; The substrate is etched based on the selected gate pattern to form a selected gate, and the selected gate is connected to each of the isolation sub-trenches; Photolithography and etching are performed on the substrate and all the isolation sub-trenches to remove the silicon nitride hard mask and the first oxide layer; The pad oxide layer is formed in the select gate and all the isolation sub-trenches, and then amorphous silicon is formed on the surface of the pad oxide layer; The selected gate and all the isolation trenches are defined as the isolation trenches, and the remaining area of ​​the substrate is defined as the active region.

9. The method for fabricating a floating-gate memory chip multilayer capacitor structure according to claim 8, characterized in that, The interlayer dielectric layer deposited between the second region on the surface of the tunneling oxide layer and the surface of the control gate includes: A first connection hole is etched onto the surface of the control gate, such that the first connection hole is etched to the floating gate; A second connection hole is etched onto the surface of the control gate, such that the second connection hole is etched into the isolation trench; An interlayer dielectric layer is deposited in the second region on the surface of the tunneling oxide layer, the surface of the control gate, the first connection hole, and the second connection hole; The process of etching a first electrode trench and a second electrode trench in the interlayer dielectric layer, thereby electrically connecting the active region and the control gate to the first electrode trench respectively, and electrically connecting the floating gate to the second electrode trench, includes: A first contact hole is etched on the surface of the interlayer dielectric layer, so that the first contact hole penetrates the interlayer dielectric layer and the tunneling oxide layer to the active region, and then the first contact hole is filled with a metal mixture. A second contact hole is etched on the surface of the interlayer dielectric layer, so that the second contact hole is etched through the interlayer dielectric layer to the control gate, and then the second contact hole is filled with a metal mixture; A third contact hole is etched on the surface of the interlayer dielectric layer, so that the third contact hole passes through the first connection hole and is etched to the floating gate, and then the third contact hole is filled with a metal mixture. A fourth contact hole is etched on the surface of the interlayer dielectric layer, so that the fourth contact hole passes through the second connection hole and is etched to the isolation trench, and then the fourth contact hole is filled with a metal mixture. The interlayer dielectric layer is etched to form a first electrode trench on the first contact hole and the second contact hole, and a second electrode trench on the third contact hole and the fourth contact hole.

10. The method for fabricating a floating-gate memory chip multilayer capacitor structure according to claim 7, characterized in that, The first region on the surface of the tunneling oxide layer sequentially forms a floating gate, an ONO dielectric layer, and a control gate, including: Amorphous silicon is deposited on the surface of the tunneling oxide layer; The amorphous silicon is etched to form the floating gate in a first region on the surface of the tunneling oxide layer; An ONO dielectric is deposited on the tunneling oxide layer and the surface of the floating gate, and then the ONO dielectric on the surface of the tunneling oxide layer is etched to form an ONO dielectric layer on the surface of the floating gate. A control gate material is deposited on the tunneling oxide layer and the floating gate surface, and then the control gate material on the surface of the tunneling oxide layer is etched to form the control gate on the surface of the ONO dielectric layer.

11. The method for fabricating a floating-gate memory chip multilayer capacitor structure according to claim 7, characterized in that, The first electrode trench includes a first strip-shaped trench and a plurality of first interdigitation trenches; the second electrode trench includes a second strip-shaped trench and a plurality of second interdigitation trenches; wherein: Each of the first interdigitated finger grooves is connected to the first strip groove; Each of the second interdigitated grooves is connected to the second strip groove; A plurality of first interdigitation grooves and a plurality of second interdigitation grooves are arranged alternately and at intervals within the interlayer dielectric layer to form an interdigitation structure.

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