Memory elements and methods of making the same

Abstract

A memory element and a method of fabricating the same are disclosed. The memory element includes two memory cells, a first gate, and a doped region. The two memory cells are disposed on a substrate. The first gate is disposed between the two memory cells. The first gate includes an embedded portion embedded in the substrate. The doped region is disposed in the substrate and surrounds the embedded portion.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and in particular to a memory device and a method of fabricating the same. BACKGROUND

[0002] With the booming development of cutting-edge technologies such as the Internet of Things, edge computing, and artificial intelligence, huge information processing capabilities are required, and memory devices are an indispensable role. When the information to be processed is huge, the memory cells in the memory device also need to be increased accordingly. Even the most basic electronic products usually contain millions of memory cells. Therefore, how to improve the properties of the memory device has become the goal of continuous efforts of relevant manufacturers. SUMMARY

[0003] According to an embodiment of the present application, a memory device is provided, comprising two memory cells, a first gate, and a doped region. The two memory cells are disposed on a substrate, and the first gate is disposed between the two memory cells, wherein the first gate comprises an embedded portion embedded in the substrate. The doped region is disposed in the substrate and surrounds the embedded portion.

[0004] According to another embodiment of the present application, a method of fabricating a memory device is provided, comprising the following steps. Form two memory cells on a substrate. Form a recess in the substrate, wherein the recess is located between the two memory cells. Form a doped region in the substrate and around the recess. Form a first gate between the two memory cells, wherein the first gate comprises an embedded portion disposed in the recess, and the doped region surrounds the embedded portion.

[0005] Compared with the prior art, the present application has an embedded portion in the first gate, which is beneficial to increase the cross-sectional area of the doped region surrounding the first gate, and is beneficial to reduce the resistance of the doped region, thereby improving the electrical performance of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 is a step cross-sectional view of fabricating a memory device according to an embodiment of the present application;

[0007] Figure 10 is a top view of a memory device according to another embodiment of the present application;

[0008] Figure 11 is a cross-sectional view of a memory device according to still another embodiment of the present application.

[0009] Symbol explanation

[0010] 1, 1A: memory element

[0011] 10: memory region

[0012] 18: tunneling material layer

[0013] 20: floating gate material layer

[0014] 22: barrier material layer

[0015] 22a, 26a: first material layer

[0016] 22b, 26b: second material layer

[0017] 22c: third material layer

[0018] 24: control gate material layer

[0019] 26: mask material layer

[0020] 42: gate dielectric material layer

[0021] 52: gate conductive layer

[0022] 100: substrate

[0023] 101, 201: top surface

[0024] 110: recess

[0025] 120: insulating structure

[0026] 121: top surface

[0027] 130, 130A: recess

[0028] 132: sidewall

[0029] 134: bottom wall

[0030] 140, 140A: doped region

[0031] 141, 141A: horizontal portion

[0032] 142: vertical portion

[0033] 142A: first inclined portion

[0034] 143A: second inclined portion

[0035] 160: doped region

[0036] 170: channel region

[0037] 180: Tunneling layer

[0038] 200: Floating gate

[0039] 202: Inner surface

[0040] 204: Outer surface

[0041] 220: Barrier layer

[0042] 220a, 260a: First layer

[0043] 220b, 260b: Second layer

[0044] 220c: Third layer

[0045] 240: Control gate

[0046] 260: Mask layer

[0047] 310, 320, 330, 340, 350, 360: Spacer wall

[0048] 410, 410A: Tunneling layers

[0049] 420: Gate dielectric layer

[0050] 510, 510A: First gate

[0051] 512, 512A: Embedded part

[0052] 514, 514A: upper part

[0053] 520: Second gate

[0054] D1, D2: Horizontal direction

[0055] D3: vertical direction

[0056] MU: Storage Unit

[0057] P1: Ion implantation fabrication process

[0058] S1, S3: Outer surfaces

[0059] S2, S4: Inner surfaces

[0060] SK: Stacking

[0061] ST: Stepped structure Detailed Implementation

[0062] The foregoing description and other technical contents, features, and effects of this invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. To make the content of this invention clearer and easier to understand, the following drawings are simplified schematic diagrams, and the elements therein may not be drawn to scale. Furthermore, the number and size of the elements in the drawings are merely illustrative and not intended to limit the invention. Directional terms mentioned in the following embodiments, such as up, down, left, right, front, back, bottom, and top, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the invention. In addition, in the following embodiments, the same or similar elements will be referred to by the same or similar reference numerals.

[0063] The following description of "the first feature is formed on or above the second feature" can refer to "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature" so that the first feature and the second feature are not in direct contact.

[0064] This invention uses terms such as "first," "second," etc., to describe elements, regions, layers, and / or sections. However, it should be understood that these terms are only used to distinguish one element, region, layer, and / or section from another, and do not inherently imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this invention, the first element, region, layer, and / or section discussed below may also be referred to as the second element, region, layer, and / or section. The terms used in the claims may not be the same as those in the description, and may be replaced by first, second, third… according to the order of the elements declared in the claims.

[0065] Please refer to Figures 1 to 9 This is a cross-sectional schematic diagram illustrating the steps of fabricating a memory element according to an embodiment of the present invention. Figure 1 As shown, firstly, a substrate 100 is provided. The substrate 100 can be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. The substrate 100 may define a memory region 10 and at least one other region (not shown) adjacent to the memory region 10. The memory region 10 can be used to house memory elements, such as embedded flash memory or embedded super-flash memory. The other region can be a logic region or a peripheral region, but is not limited thereto.

[0066] Next, forming the insulating structure 120 in the substrate 100 may include the following steps. First, a pad layer (not shown) and a mask layer (not shown) are sequentially formed to completely cover the substrate 100. The material of the pad layer may include oxides such as silicon dioxide, and the material of the mask layer may include nitrides such as silicon nitride, but is not limited thereto. Next, using semiconductor fabrication processes such as photolithography and etching, a portion of the mask layer and pad layer is removed to pattern the mask layer and pad layer. Then, using the patterned mask layer and pad layer as a mask, an etching process is performed to remove a portion of the substrate 100 to form a groove 110. Next, a dielectric material may be filled into the groove 110 using a deposition process, and a portion of the dielectric material may be removed using a planarization process such as chemical mechanical polishing, so that the top surface of the dielectric material is flush with the top surface of the mask layer. Finally, the patterned mask layer and pad layer are removed to complete the fabrication of the insulating structure 120. At this stage, the top surface 121 of the insulating structure 120 is higher than the top surface 101 of the substrate 100. The material of the insulating structure 120 may include a dielectric material, which may include an oxide, such as silicon oxide.

[0067] Next, an ion implantation process can be performed to form a well region (not shown) in the substrate 100. The conductivity of the well region can be determined by its dopant. For example, the well region can be doped with N-type impurities, such as arsenic or phosphorus, to have a first conductivity type. Or, for example, the well region can be doped with P-type impurities, such as boron or indium, to have a second conductivity type.

[0068] Next, a tunneling material layer 18 and a floating gate material layer 20 are sequentially formed to fully cover the substrate 100. Then, a planarization process, such as chemical mechanical polishing, is performed to make the top surface 201 of the floating gate material layer 20 flush with the top surface 121 of the insulating structure 120. Figure 1 As shown. The tunneling material layer 18 may comprise a dielectric material, such as silicon oxide, silicon nitride (Si3N4), silicon oxynitride (SiON), a high dielectric constant material, other non-conductive materials, or combinations thereof. The tunneling material layer 18 may be formed, for example, using a thermal oxidation process or other suitable fabrication process. The floating gate material layer 20 may comprise a conductor for storing charge, such as doped polycrystalline silicon or doped amorphous silicon, or may comprise a non-conductor for trapping charge, such as silicon nitride (SiN), to form a charge trapping layer for storing charge. In some embodiments, the material of the floating gate material layer 20 may comprise a metal, a metal alloy, or a combination thereof.

[0069] Next, as Figure 2As shown, a barrier material layer 22, a control gate material layer 24, and a mask material layer 26 are sequentially formed to completely cover the substrate 100. The barrier material layer 22 can be a single-layer structure or a multi-layer structure. The material of the barrier material layer 22 may include dielectric materials, such as silicon dioxide, silicon nitride (Si3N4), silicon oxynitride (SiON), high dielectric constant materials, other non-conductive materials, or combinations thereof. High dielectric constant materials may, for example, include dielectric materials with a dielectric constant greater than 10. In this embodiment, the barrier material layer 22 is illustrated as a three-layer structure, sequentially including a first material layer 22a, a second material layer 22b, and a third material layer 22c from bottom to top. The first material layer 22a, the second material layer 22b, and the third material layer 22c are, in sequence, oxide, nitride, and oxide, but are not limited thereto. In some embodiments, the material of the barrier material layer 22 may be the same as the material of the tunneling material layer 18. The control gate material layer 24 may include a non-metallic conductive material, such as doped polycrystalline silicon or doped amorphous silicon. In some embodiments, the control gate material layer 24 may comprise a metal, a metal alloy, or a combination thereof. The mask material layer 26 may be a single-layer or multi-layer structure, and may comprise an oxide, a nitride, or a combination thereof. The mask material layer 26 is illustrated herein as a two-layer structure, comprising a first material layer 26a and a second material layer 26b sequentially from bottom to top. The first material layer 26a and the second material layer 26b may be, but are not limited to, an oxide and a nitride sequentially. The aforementioned oxide may be, for example, silicon oxide, and the nitride may be, for example, silicon nitride.

[0070] Next, as Figure 3 As shown, a portion of the mask material layer 26, the control gate material layer 24, and the barrier material layer 22 can be removed along the horizontal direction D2 using semiconductor fabrication processes such as photolithography and etching to form a dual-stack SK. The dual-stack SK are arranged adjacent to each other along the horizontal direction D1 and spaced apart from each other. Each stacked SK includes a barrier layer 220, a control gate 240, and a mask layer 260 from bottom to top. The barrier layer 220 includes a first layer 220a, a second layer 220b, and a third layer 220c from bottom to top, and the mask layer 260 includes a first layer 260a and a second layer 260b from bottom to top. The materials of the barrier layer 220, the control gate 240, and the mask layer 260 can be referred to the relevant descriptions of the barrier material layer 22, the control gate material layer 24, and the mask material layer 26 above, and will not be repeated here.

[0071] Next, one or more spacer walls are formed on the side surfaces (including the outer surface S1 and the inner surface S2) of the two stacked SK. For example, one or more spacer wall materials can be formed to completely cover the substrate 100 using a deposition process. Then, the horizontal portions of the spacer wall material can be removed using an etching process, leaving the vertical portions to complete the fabrication of the spacer walls. The spacer wall material can include nitrides, oxides, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof. Here, a three-layer spacer wall is taken as an example, with spacer walls 310, 320, and 330 in sequence from the inside out. The materials of spacer walls 310, 320, and 330 are oxide, nitride, and oxide in sequence, but this is not limited to these, and the number of spacer wall layers can be adjusted according to actual needs.

[0072] Next, as Figure 4 As shown, semiconductor fabrication processes such as photolithography and etching can be used to remove the outer surface S1 of the two stacked SK layers (see...). Figure 3 The spacer wall 330 on the SK is retained, while the inner surface S2 of the two stacked SK is preserved (see Figure 3 The spacer wall 330 on the stacked SK. Next, using the two stacked SK and the spacer walls 310, 320 and 330 as masks, an etching process is performed to remove part of the floating gate material layer 20 to form two memory cells MU on the substrate 100. The definitions of the aforementioned outer surface S1 and inner surface S2 are as follows: a center line can be defined between the two stacked SK, the outer surface S1 is the side surface of the two stacked SK that is farther away from the center line, and the inner surface S2 is the side surface of the two stacked SK that is closer to the center line.

[0073] Figure 4 In this structure, each memory cell MU comprises, from bottom to top, a floating gate 200, a barrier layer 220, a control gate 240, and a mask layer 260. Spacer walls 310, 320, and 330 are disposed on the inner surfaces of the barrier layer 220, the control gate 240, and the mask layer 260, while spacer walls 310 and 320 are disposed on the outer surfaces of these components. In other words, at this stage, the number of spacer wall layers disposed on the inner surface S4 of each memory cell MU is greater than the number of spacer wall layers disposed on the outer surface S3 of each memory cell MU. Furthermore, no spacer walls are disposed on either the inner or outer surface of the floating gate 200. The definitions of the aforementioned outer surface S3 and inner surface S4 are as follows: a center line can be defined between the two memory cells MU; the outer surface S3 is the side surface of the two memory cells MU that is farther from the center line; and the inner surface S4 is the side surface of the two memory cells MU that is closer to the center line.

[0074] Next, as Figure 5As shown, a spacer wall 340 is formed on the side surface (including the outer surface S3 and the inner surface S4) of the two memory cells MU. For example, the spacer wall material can be formed to completely cover the substrate 100 using a deposition process, and then the horizontal portion of the spacer wall material can be removed using an etching process while retaining the vertical portion of the spacer wall material to complete the fabrication of the spacer wall 340. The material of the spacer wall 340 may include nitrides, oxides, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof. In Figure 5, the spacer wall 340 directly contacts the side surface of the floating gate 200.

[0075] Next, as Figure 6 As shown, a groove 130 is formed in the substrate 100, wherein the groove 130 is located between two memory cells MU. For example, a photoresist (not shown) can be formed on the substrate 100 first, exposing the portion of the two memory cells MU near the inside and the area between the two memory cells MU. Then, the spacer walls 340 and 330 on the inner surface S4 of the two memory cells MU are removed first, and a dry etching process is performed using the photoresist, the two memory cells MU, and the spacer walls 310 and 320 as an etching mask. The process involves etching downwards along the spacer wall 320 on the inner surface S4 of the two memory cells MU and the inner surface 202 of the floating gate 200, removing part of the substrate 100 to form the groove 130 in the substrate 100. The sidewall 132 of the groove 130 can be flush with the inner surface 202 of the floating gate 200, but is not limited to this. In other embodiments, the groove 130 can be formed first, and then the gap walls 340 and 330 located on the inner surface S4 of the two memory cells MU can be removed. In this case, the side wall 132 of the groove 130 may not be flush with the inner surface 202 of the floating gate 200.

[0076] Next, as Figure 7 As shown, a doped region 140 is formed in the substrate 100 and surrounds the groove 130. For example, an ion implantation process P1 can be performed to form the doped region 140 on the substrate 100 between two memory cells MU. The doped region 140 can, for example, serve as the memory element 1 subsequently formed (see...). Figure 9The source line of the doped region 140. The ion implantation process P1 can be, for example, an angled ion implantation process. This facilitates the insertion of the dopant into the substrate 100 below the two memory cells MU, and a portion of the doped region 140 is located within the substrate 100 below the two memory cells MU. Specifically, the doped region 140 may have a U-shaped cross-section, and may have two vertical portions 142 and a horizontal portion 141 disposed between the two vertical portions 142. In the vertical direction D3, the two vertical portions 142 may overlap with the two memory cells MU respectively, and in the vertical direction D3, the horizontal portion 141 does not overlap with the two memory cells MU. The conductivity type of the doped region 140 can be determined by its dopant. For example, the doped region 140 may be doped with N-type impurities, such as arsenic or phosphorus, and has a first conductivity type; or, for example, the doped region 140 may be doped with P-type impurities, such as boron or indium, and has a second conductivity type. The conductivity type of the doped region 140 is different from the aforementioned well region conductivity type.

[0077] Next, as Figure 8 As shown, a tunneling layer 410 is formed on the side surface (i.e., the inner surface S4) of the two memory cells MU facing the recess 130 and on the surface of the substrate 100 exposed by the recess 130 (i.e., the sidewall 132 and bottom wall 134 of the recess 130). For example, a tunneling material layer can be formed to completely cover the substrate 100. Then, the portion of the tunneling material layer located on the top surface, outer surface S3, and the portion on the substrate 100 outside the two memory cells MU is removed, and the remaining tunneling material layer is the tunneling layer 410. In addition, while removing the aforementioned tunneling material layer, the portion of the tunneling material layer 18 not covered by the two memory cells MU can be removed, exposing the substrate 100 outside the two memory cells MU. The portion of the tunneling material layer 18 below the two memory cells MU that has not been removed is the tunneling layer 180. The materials of the tunneling layers 180 and 410 can be referred to in the relevant description of the tunneling material layer 18, and will not be repeated here. Figure 8 As shown, the tunneling layer 410 extends from the top of the inner surface S4 of one storage cell MU to the side wall 132, bottom wall 134 of the groove 130, and another side wall 132 to the top of the inner surface S4 of another storage cell MU. The tunneling layer 410 has a U-shaped cross-section, and more specifically, the tunneling layer 410 has a U-shaped cross-section with a stepped structure.

[0078] Next, a gate dielectric material layer 42 is formed on the substrate 100 outside the two memory cells MU. Here, a thermal oxidation process is used to oxidize the exposed portion of the substrate 100 (i.e., the portion of the substrate 100 located outside the two memory cells MU) to obtain an oxide layer as the gate dielectric material layer 42. For example, the thermal oxidation process can be performed in an oxygen-containing environment, which can be achieved by introducing oxygen or an oxygen-containing gas (e.g., water vapor) into the fabrication chamber of the thermal oxidation process. The thermal oxidation process may include, but is not limited to, in-situ steam generation (ISSG) oxidation, wet furnace tube oxidation, or dry furnace tube oxidation. In the thermal oxidation process, oxygen atoms from the oxygen-containing gas enter the substrate 100 and bond with the silicon in the substrate 100, causing the surface layer of the portion of the substrate 100 located outside the two memory cells MU to be oxidized to form the gate dielectric material layer 42. Therefore, after the thermal oxidation process, the top surface of the portion of the substrate 100 located outside the two memory cells MU will be slightly lower than the top surface 101 of the substrate 100 before the thermal oxidation process (see...). Figure 7 The top surface of the gate dielectric layer 42 (unless otherwise labeled) will be slightly higher than the top surface 101 of the substrate 100 before the thermal oxidation process (see [link]). Figure 7 At this point, the gate dielectric layer 42 may contain silicon oxide, but is not limited thereto. For example, in other embodiments, the gate dielectric layer 42 may be formed using a deposition process, in which case the gate dielectric layer 42 may contain silicon oxide, silicon nitride, silicon oxynitride, other non-conductive materials, or combinations thereof.

[0079] Next, a first gate 510 is formed between two memory cells MU and two second gates 520 are formed (see...). Figure 9 The following steps may be included on the side of the two memory cells MU that is away from the first gate 510. Figure 8 In the process, firstly, a gate conductive material is formed to fully cover the substrate 100, and then a portion of the gate conductive material is removed by back etching. The gate conductive material located between the two memory cells MU forms the first gate 510, and the gate conductive material located outside the two memory cells MU forms the gate conductive layer 52. The first gate 510 is disposed on the tunneling layer 410, and the gate conductive layer 52 is disposed on the gate dielectric material layer 42.

[0080] Next, as Figure 9 As shown, semiconductor fabrication processes such as photolithography and etching can be used to remove part of the gate conductive layer 52 and the gate dielectric material layer 42 to form the second gate 520 and the gate dielectric layer 420. The materials of the first gate 510 and the second gate 520 may include conductive materials, such as doped polycrystalline silicon, doped amorphous silicon, metal, or metal compound.

[0081] Next, two spacer walls 350 can be formed on the outer surfaces of the two second gates 520, and two spacer walls 360 can be formed on the side surfaces of the two memory cells MU. The two spacer walls 360 are respectively disposed at the top of the first gate 510 and the top of the second gate 520. For example, one or more layers of spacer wall material can be formed to completely cover the substrate 100. Then, the horizontal portion of the spacer wall material can be removed by an etching process while retaining the vertical portion of the spacer wall material to complete the fabrication of spacer walls 350 and 360. That is, spacer walls 350 and 360 can be formed in the same fabrication process. Here, spacer walls 350 and 360 are illustrated as a single-layer structure, but are not limited thereto. The number of layers of spacer walls 350 and 360 can be adjusted according to actual needs. The material of spacer walls 350 and 360 may include nitrides, oxides or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or combinations thereof.

[0082] Next, another ion implantation process is performed to form a doped region 160 on the substrate 100 between the spacer wall 350 and the insulating structure 120. The conductivity of the doped region 160 can be the same as that of the doped region 140, but different from that of the well region. This completes the fabrication of memory element 1.

[0083] The aforementioned film layers, such as insulating structure 120, tunneling material layer 18, floating gate material layer 20, barrier material layer 22, control gate material layer 24, mask material layer 26, spacers 310, 320, 330, 340, 350 and 360, gate dielectric material layer 42, first gate 510 and second gate 520, etc., can be formed by any suitable means, such as by, but not limited to, molecular-beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), etc.

[0084] Please refer to the following at the same time Figure 9 and Figure 10 , Figure 10 This is a top view schematic diagram of a memory device according to another embodiment of the present invention. Figure 9 yes Figure 10 A cross-sectional view of the memory device along section line A-A'. For simplicity, compared to... Figure 9 , Figure 10 Some components are omitted and not shown. For example, compared toFigure 9 , Figure 10 At least the gap walls 310, 320, 340, 350, 360 and the mask layer 260 are omitted. Figure 10 The memory device may include a plurality of memory elements 1 arranged at intervals along the horizontal direction D2. Here, the number of memory elements 1 is three, but this is only an example and the invention is not limited thereto.

[0085] Memory element 1 may include two memory cells MU, a first gate 510, and a doped region 140. The two memory cells MU are disposed on a substrate 100, and the first gate 510 is disposed between the two memory cells MU. The first gate 510 includes an embedding portion 512 embedded in the substrate 100, and the doped region 140 is disposed in the substrate 100 and surrounds the embedding portion 512. The presence of the embedding portion 512 in the first gate 510 facilitates an increase in the cross-sectional area of ​​the doped region 140. For example, compared to the case without the embedding portion 512, the doped region 140 of the present invention has an additional vertical portion 142 (see...). Figure 7 The area of ​​the doped region 140 is reduced, which helps to reduce the resistance of the doped region 140 and thus improves the electrical performance of the memory element 1.

[0086] The memory element 1 may further include two second gates 520, two doped regions 160, and a channel region 170. The two second gates 520 are respectively disposed on the side of the two memory cells MU away from the first gate 510. The two doped regions 160 and the channel region 170 are located in the substrate 100, and the channel region 170 is located between the doped regions 140 and 160. The memory cells MU and the second gates 520 are disposed above the channel region 170, and the first gate 510 is disposed above the doped region 140. The plurality of memory elements 1 and the insulating structure 120 are arranged adjacent to each other and staggered in the horizontal direction D2. Furthermore, the floating gates 200 of the plurality of memory elements 1 and the insulating structure 120 are arranged adjacent to each other and staggered in the horizontal direction D2. The insulating structure 120 provides the necessary electrical isolation between the plurality of memory elements 1.

[0087] In detail, the first gate 510 may further include an upper portion 514 disposed on the substrate 100. The upper portion 514 includes a two-tiered structure ST corresponding to two memory cells MU respectively. The upper portion 514 may have a T-shaped cross-section. The upper portion 514 may be the part of the first gate 510 that is higher than the top surface 101 of the substrate 100. The embedded portion 512 may be the part of the first gate 510 that is embedded in the substrate 100, that is, the part of the first gate 510 that is lower than the top surface 101 of the substrate 100. The embedded portion 512 may have a rectangular cross-section.

[0088] The doped region 140 may overlap with at least one of the two memory cells MU in the vertical direction D3. Here, the doped region 140 overlaps with the two memory cells MU in the vertical direction D3. The doped region 140 may have a U-shaped cross-section, and the doped region 140 may have two vertical portions 142 (see...). Figure 7 ) and a horizontal section 141 (see Figure 7 It is disposed between the two vertical portions 142. In the vertical direction D3, the two vertical portions 142 can overlap with the two storage cells MU respectively, and in the vertical direction D3, the horizontal portion 141 does not overlap with the two storage cells MU.

[0089] Each memory cell MU includes, from bottom to top, a tunneling layer 180, a floating gate 200, a barrier layer 220, and a control gate 240, and optionally also includes a mask layer 260 disposed above the control gate 240.

[0090] The memory element 1 may further include a tunneling layer 410 disposed between the first gate 510 and the second memory cell MU. The memory element 1 may further include a gate dielectric layer 420 disposed between the substrate 100 and the second gate 520.

[0091] The memory element 1 may further include spacers 310, 320, and 340, wherein spacers 310 and 320 are disposed on the inner surface S4 and outer surface S3 of the two memory cells MU, and are disposed at the top of the floating gate 200, that is, the bottom ends of spacers 310 and 320 contact the top end of the floating gate 200, wherein the outer surface of spacer 320 disposed on the outer surface S3 of the two memory cells MU is adjacent to the outer surface 204 of the floating gate 200 (see...). Figure 6 The outer surface of the spacer wall 320, which is disposed on the inner surface S4 of the two memory cells MU, is not flush with the inner surface 202 of the floating gate 200. Specifically, the inner surface 202 of the floating gate 200 protrudes from the outer surface of the spacer wall 320 along the horizontal direction D1. The spacer wall 340 is disposed on the outer surface S3 of the two memory cells MU and on the outer surface 204 of the floating gate 200.

[0092] The memory element 1 may further include two spacer walls 350 respectively disposed on the outer surface of the second gate 520, that is, the side surface away from the two memory cells MU.

[0093] The memory element 1 may further include two gap walls 360 respectively disposed on the side surfaces of the two memory cells MU, the two gap walls 360 being disposed on the top of the first gate 510, and the two gap walls 360 being disposed on the top of the second gate 520.

[0094] like Figure 10As shown, the first gate 510 and the second gate 520 extend along the horizontal direction D2. Two memory cells MU are symmetrically arranged on both sides of the first gate 510 along the horizontal direction D1. Two second gates 520 are respectively arranged on the side of the two memory cells MU away from the first gate 510 along the horizontal direction D1, and the two second gates 520 are symmetrically arranged on both sides of the first gate 510 along the horizontal direction D1.

[0095] In memory element 1, the first gate 510 can be an erase gate, and the second gate 520 can be a select gate. The doped region 140 can serve as a source region, and the doped region 160 can serve as a drain region, wherein the doped region 140 is shared by two memory cells MU arranged along the horizontal direction D1. In some embodiments, the second gate 520 can serve as a word line, and the doped region 140 can serve as a source line.

[0096] Please refer to Figure 11 This is a cross-sectional schematic diagram of a memory element according to another embodiment of the present invention. The main difference between memory element 1A and memory element 1 is that the shapes of the recess 130A, the doped region 140A, the tunneling layer 410A, and the first gate 510A are different from the shapes of the recess 130, the doped region 140, the tunneling layer 410, and the first gate 510.

[0097] In detail, the recess 130A has a hexagonal cross-section. For example, the type and proportion of etchant in the etching process, the etching parameters, etc., can be adjusted to make the recess 130A have a hexagonal cross-section. The embedding portion 512A of the first gate 510A also has a hexagonal cross-section corresponding to the recess 130A, while the upper portion 514A of the first gate 510A maintains a T-shaped cross-section. The doped region 140A generally follows the contour of the recess 130A and may include a horizontal portion 141A, a first inclined portion 142A, and a second inclined portion 143A connected sequentially from bottom to top. Other details about the memory element 1A can be found in the relevant content of memory element 1 above, and will not be repeated here.

[0098] Compared to the prior art, the present invention has an embedded portion in the first gate, which is beneficial to increase the cross-sectional area of ​​the doped region surrounding the first gate, thereby reducing the resistance of the doped region and improving the electrical performance of the memory element.

[0099] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A memory element comprising: Two storage units are mounted on the substrate; A first gate is disposed between the two memory cells, wherein the first gate includes an embedding portion embedded in the substrate; and A doped region is disposed in the substrate and surrounds the embedded portion.

2. The memory element of claim 1, wherein the doped region overlaps with at least one of the two memory cells in the vertical direction.

3. The memory element of claim 1, wherein the embedded portion has a rectangular cross-section.

4. The memory element of claim 3, wherein the doped region has a U-shaped profile.

5. The memory element of claim 1, wherein the embedded portion has a hexagonal cross-section.

6. The memory element of claim 5, wherein the doped region comprises a horizontal portion, a first inclined portion, and a second inclined portion connected sequentially from bottom to top.

7. The memory element of claim 1, wherein the first gate further includes an upper portion disposed on the substrate, the upper portion including a two-dimensional structure corresponding to the two memory cells respectively.

8. The memory element of claim 1, further comprising: Two first gap walls are respectively disposed on the side surfaces of the two memory cells, and the two first gap walls are disposed on the top of the first gate.

9. The memory element of claim 1, wherein each memory cell comprises, from bottom to top, a first tunneling layer, a floating gate, a blocking layer, and a control gate.

10. The memory element of claim 1, further comprising: A second tunneling layer is disposed between the first gate and the two memory cells.

11. The memory element of claim 1, further comprising: Two second gates are respectively disposed on the side of the two memory cells away from the first gate.

12. The memory element of claim 11, further comprising: Two first gap walls are respectively disposed on the side surfaces of the two memory cells, and the two first gap walls are respectively disposed on the top ends of the two second gates.

13. The memory element of claim 11, wherein the first gate is an erase gate and the second gate is a select gate.

14. A method for manufacturing a memory element, comprising: Two memory cells are formed on the substrate; A groove is formed in the substrate, wherein the groove is located between the two storage cells; A doped region is formed in the substrate and surrounding the groove; and A first gate is formed between the two memory cells, wherein the first gate includes an embedded portion disposed in the groove, and the doped region surrounds the embedded portion.

15. The method of claim 14, further comprising: A second tunneling layer is formed on the side surface of the two storage cells facing the recess and on the surface of the substrate exposed by the recess; and The first gate is formed on the second tunneling layer.

16. The method of claim 14, further comprising: Two first gap walls are formed on the side surfaces of the two memory cells, wherein the two first gap walls are disposed at the top of the first gate.

17. The method of claim 14, further comprising: Two second gates are formed on the side of the two memory cells away from the first gate.

18. The method of claim 17, further comprising: Two first gap walls are formed on the side surfaces of the two memory cells, wherein the two first gap walls are respectively disposed at the top ends of the two second gates.

19. The method of claim 14, wherein the doped region is formed by an oblique angle ion implantation process.

20. The method of claim 14, wherein the doped region overlaps with at least one of the two memory cells in the vertical direction.

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