Rc-igbt device and method of manufacturing the same

Abstract

The application provides an RC-IGBT device and a preparation method thereof. The device comprises: a metal collector, a collector region, an N-type drift region, a P well, an N-type carrier blocking layer, a P-type base region, an N-type emitter region and a metal emitter, which are stacked in sequence; a split gate structure extending from the P-type base region into the N-type drift region; an emitter gate structure extending from the P-type base region into the N-type drift region; a sub-control gate structure extending from the P-type base region into the N-type carrier blocking layer; and an N-type channel region arranged between two adjacent sub-control gate structures, the N-type channel region connecting the N-type carrier blocking layer and the metal emitter. The application introduces a split gate structure into the IGBT to reduce the Miller capacitance, optimize the switching loss and the electric field distribution, improve the reliability of the device, and improve the compromise between the on-state voltage drop and the off-state loss.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to an RC-IGBT device and its fabrication method. Background Technology

[0002] The IGBT device structure was proposed in the early 1880s. After more than 30 years of development, its performance and reliability have been greatly improved, and its application range has been greatly expanded. Currently, it is widely used in switching frequencies below 30kHz and is one of the mainstream fully controllable power semiconductor devices. In the past decade, IGBT devices have mainly developed towards higher cell density, larger wafer size, thinner chip thickness, and higher operating junction temperature. Currently, its performance is approaching its theoretical limit. An important future development trend for IGBT devices is towards multi-functional integration, such as: integrating current and temperature sensors inside the chip to improve the current utilization rate of a single chip and improve the timeliness of protection; and integrating the IGBT and freewheeling diode on-chip to further reduce the cost of power devices and increase power density. The latter is the reverse-conducting IGBT (RC-IGBT).

[0003] To reduce the on-resistance of RC-IGBTs, SBL-RC-IGBT (Super Body Layer-RC-IGBT) and trench gate structures can be employed. The concept of the SBL-RC-IGBT structure is to introduce a hole storage layer (shallow N-layer) to accumulate a large number of hole carriers in the drift region during conduction. Compared to the traditional RC-IGBT structure, this method inserts a hole storage layer inside the P-body region. This structure has the effect of accumulating hole carriers from the collector side and also enhances the injection of electron carriers from the device surface. The trench gate structure allows for a higher channel density and surface utilization efficiency in the IGBT, while avoiding the JFET effect, reducing the on-state voltage drop, and increasing the device's current carrying capacity. However, the increased carrier accumulation leads to higher reverse recovery charge and switching losses in the diode. The larger contact area between the trench gate and the drift region results in increased Miller capacitance, slower switching speed, and increased switching losses, affecting its frequency characteristics and limiting high-frequency applications.

[0004] Therefore, controlling the switching losses of IGBTs and diodes while maintaining the low on-resistance of RC-IGBTs is a challenging task.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an RC-IGBT device and its fabrication method, which solves the problems of large Miller capacitance of RC-IGBT in the prior art, resulting in large gate charge, increased drive loss, and slow switching speed, as well as the difficulty in simultaneously achieving and reducing low on-resistance and switching loss.

[0007] To achieve the above and other related objectives, the present invention provides an RC-IGBT device, the RC-IGBT device comprising:

[0008] Metal current collector;

[0009] The collector region includes a P-type collector region and an N-type collector region arranged side by side on the metal collector electrode;

[0010] An N-type drift region is located on the collector region;

[0011] The P-well is located on the N-type drift region;

[0012] An N-type carrier blocking layer is located on the P-well;

[0013] The P-type base region is located on the N-type carrier blocking layer;

[0014] A split gate structure extends from the P-type base region to the N-type drift region. The split gate structure includes a first gate dielectric layer located on the sidewall and bottom wall of the trench, a main control gate electrode and a shielding gate electrode filled in the first gate dielectric layer within the trench; wherein the shielding gate electrode is located below the main control gate electrode and the two are isolated by a second gate dielectric layer.

[0015] An emitter gate structure extending from the P-type base region to the N-type drift region;

[0016] A secondary control gate structure, wherein the secondary control gate structure extends from the P-type base region into the N-type carrier blocking layer;

[0017] An N-type emitter region is disposed in the P-type base region and on the side of the main control gate electrode;

[0018] A metal emitter is disposed on the P-type base region and connected to the N-type emitter region;

[0019] An N-type channel region is disposed between two adjacent control gate structures, and the N-type channel region connects the N-type carrier blocking layer and the metal emitter;

[0020] The main control gate electrode is connected to the main gate drive of the device, the shield gate electrode and the first gate electrode of the emitter gate structure are both connected to the metal emitter of the device, and the second gate electrode of the sub-control gate structure is connected to the sub-gate drive of the device.

[0021] Optionally, during diode operation of the RC-IGBT device, zero voltage is applied to the second gate electrode of the sub-control gate structure, giving the N-type channel region high conductivity. The N-type carrier blocking layer is short-circuited to the metal emitter through the N-type channel region, thus maintaining the barrier of the N-type carrier blocking layer. This prevents forward bias at the interface between the P-type base region and the N-type carrier blocking layer and suppresses hole injection from the P-type base region to the P-well.

[0022] Optionally, during the operation of the RC-IGBT device, a positive voltage is applied to the main control gate electrode, enabling the IGBT device to operate normally. A negative voltage is applied to the second gate electrode of the sub-control gate structure, generating a large depletion region. This results in the N-type channel region being in a low conductivity state, and the conductive channel between the N-type carrier blocking layer and the metal emitter is pinched off. This ensures that the threshold voltage, conduction characteristics, and turn-off characteristics of the IGBT device remain unchanged. At the same time, the Miller capacitance of the device is reduced by the discrete gate structure, significantly improving the switching performance of the device and reducing the risk of false turn-on.

[0023] Optionally, the main control gate electrode extends from the P-type base region into the N-type carrier blocking layer.

[0024] Optionally, the sub-control gate structure is disposed between the split gate structure and the emitter gate structure, and is disposed above the N-type collector region.

[0025] Optionally, the two sides of the N-type channel region are closely connected to the sub-control gate structure, and the two ends are closely connected to the N-type carrier blocking layer and the metal emitter, respectively.

[0026] Optionally, the RC-IGBT device further includes an N-type buffer layer located between the collector region and the N-type drift region.

[0027] Optionally, the depth of the discrete gate structure is 5 micrometers to 10 micrometers and the width is 1 micrometer to 3 micrometers, and the depth of the emitter gate structure is 5 micrometers to 10 micrometers and the width is 1 micrometer to 3 micrometers.

[0028] Optionally, the depth of the P-well is 3.5 micrometers to 9 micrometers, and the doping concentration is 5 × 10⁻⁶. 15 cm -3 ~2×10 18 cm -3 The depth of the N-type carrier blocking layer is 2 micrometers to 6 micrometers, and the doping concentration is 4 × 10⁻⁶. 15 cm -3 ~6×10 18 cm -3 The depth of the P-type base region is 1.5 micrometers to 4 micrometers, and the doping concentration is 1×10⁻⁶. 16 cm -3 ~4×10 17 cm -3 .

[0029] Optionally, the depth of the sub-control gate structure is 1.5 micrometers to 5.5 micrometers, and the width is 0.5 micrometers to 2 micrometers.

[0030] Optionally, the depth of the N-type channel region is 1.5 micrometers to 4 micrometers, the width is 0.5 micrometers to 2 micrometers, and the doping concentration is 1×10⁻⁶. 15 cm -3 ~2×10 18 cm -3 .

[0031] The present invention also provides a method for fabricating an RC-IGBT device as described in any one of the above claims, the method comprising the steps of:

[0032] A substrate is provided, the substrate comprising an N-type buffer layer, an N-type drift region, a P-well, an N-type carrier blocking layer and a P-type base region stacked sequentially;

[0033] A discrete gate structure, an emitter gate structure, and a sub-control gate structure are formed in the substrate. The discrete gate structure extends from the P-type base region to the N-type drift region. The discrete gate structure includes a first gate dielectric layer located on the sidewall and bottom wall of the trench, a main control gate electrode and a shielding gate electrode filled in the first gate dielectric layer within the trench, the shielding gate electrode being located below the main control gate electrode and isolated from it by a second gate dielectric layer. The emitter gate structure includes a third gate dielectric layer and a first gate electrode, extending from the P-type base region to the N-type drift region. The sub-control gate structure includes a fourth gate dielectric layer and a second gate electrode, wherein the sub-control gate structure extends from the P-type base region to the N-type carrier blocking layer.

[0034] An N-type emitter region is formed in the P-type base region, and the N-type emitter region is disposed on the side of the main control gate electrode;

[0035] An N-type channel region is formed in the substrate, and the N-type channel region is disposed between two adjacent control gate structures;

[0036] A metal emitter is formed on the substrate, the metal emitter is connected to the N-type emitter region, and the N-type channel region connects the N-type carrier blocking layer and the metal emitter;

[0037] A current-collecting region is formed on the back side of the substrate, the current-collecting region including P-type current-collecting regions and N-type current-collecting regions arranged in parallel;

[0038] A metal current collector electrode is formed on the surface of the current collector region;

[0039] The main control gate electrode is connected to the main gate drive of the device, the shield gate electrode and the first gate electrode of the emitter gate structure are both connected to the metal emitter of the device, and the second gate electrode of the sub-control gate structure is connected to the sub-gate drive of the device.

[0040] As described above, the RC-IGBT device and its fabrication method of the present invention have the following beneficial effects:

[0041] This invention, by setting a separate gate structure, connects the shielded gate electrode in the separate gate structure to the metal emitter, thereby blocking the electric field coupling between the main control gate electrode and the collector. As a result, the Miller capacitance between the main control gate electrode and the collector is greatly reduced, which makes the switching speed of the device faster and the turn-on and turn-off losses significantly reduced.

[0042] Reducing switching losses helps to optimize relevant parameters to further reduce on-state voltage drop, or simultaneously increase the switching frequency, thereby improving the trade-off relationship between on-state voltage drop and turn-off losses.

[0043] The shielded gate electrode connected to the emitter absorbs electric field lines, alleviating the electric field stress in the gate dielectric layer under blocked conditions. This helps optimize the electric field distribution near the bottom of the trench, thereby improving device reliability and allowing for the use of higher doping concentrations to reduce on-resistance. Attached Figure Description

[0044] Figures 1-7 The diagram shows the structural schematics of each step in the fabrication method of the RC-IGBT device according to an embodiment of the present invention. Figure 7 The diagram shown is a structural schematic of an RC-IGBT device according to an embodiment of the present invention.

[0045] Component designation explanation

[0046] 11 N-type buffer layer 12 N-type drift zone 13 P-well 14 N-type charge carrier blocking layer 15 P-type base region 16 N-type launch area 17 Discrete gate structure 171 First gate dielectric layer 172 Second gate dielectric layer 173 Main control gate electrode 174 Shielded gate electrode 18 Emitter gate structure 181 Third gate dielectric layer 182 First gate electrode 19 Sub-control gate structure 191 Fourth gate dielectric layer 192 Second gate electrode 20 N-type trench area 21 Metal emitter 22 P-type collector area 23 N-type collector area 24 Metal current collector Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0049] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0050] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0051] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0052] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0053] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] like Figure 7 As shown, this embodiment provides an RC-IGBT device, which includes:

[0055] Metal collector 24;

[0056] The current collection region includes a P-type current collection region 22 and an N-type current collection region 23 arranged side by side on the metal current collector 24;

[0057] The N-type drift region 12 is located on the current collecting region;

[0058] P-trap 13 is located on the N-type drift region 12;

[0059] An N-type carrier blocking layer 14 is located on the P-well 13;

[0060] The P-type base region 15 is located on the N-type carrier blocking layer 14;

[0061] A split gate structure 17 extends from the P-type base region 15 to the N-type drift region 12. The split gate structure 17 includes a first gate dielectric layer 171 located on the sidewall and bottom wall of the trench, a main control gate electrode 173 and a shield gate electrode 174 filled in the first gate dielectric layer 171 within the trench; wherein the shield gate electrode 174 is located below the main control gate electrode 173 and the two are isolated by a second gate dielectric layer 172.

[0062] Emitter gate structure 18, which extends from the P-type base region 15 to the N-type drift region 12;

[0063] A sub-control gate structure 19 extends from the P-type base region 15 into the N-type carrier blocking layer 14;

[0064] The N-type emitter region 16 is disposed in the P-type base region 15 and on the side of the main control gate electrode 173;

[0065] An N-type channel region 20 is disposed between two adjacent control gate structures 19, and the N-type channel region 20 connects the N-type carrier blocking layer 14 and the metal emitter 21;

[0066] A metal emitter 21 is disposed on the P-type base region 15 and connected to the N-type emitter region 16;

[0067] The main control gate electrode 173 is connected to the main gate drive of the device, the shield gate electrode 174 and the first gate electrode 182 of the emitter gate structure 18 are both connected to the metal emitter 21 of the device, and the second gate electrode 192 of the sub-control gate structure 19 is connected to the sub-gate drive of the device.

[0068] In one embodiment, the main control gate electrode 173 extends from the P-type base region 15 into the N-type carrier blocking layer 14, thereby ensuring that the shielding gate electrode 174 effectively reduces Miller capacitance without affecting the normal function of the main control gate electrode 173 in controlling the IGBT to turn on or off.

[0069] In one embodiment, the RC-IGBT device further includes an N-type buffer layer 11, which is located between the collector region and the N-type drift region 12.

[0070] In one embodiment, the substrate used in the RC-IGBT device can be silicon, germanium-silicon, germanium, silicon carbide, group III-V compounds, etc. In one embodiment, the substrate is selected as silicon, that is, the main material of the collector region, N-type buffer layer 11, N-type drift region 12, P-well 13, N-type carrier blocking layer 14 and P-type base region 15 is selected as silicon. The corresponding functions can be achieved by doping silicon with different ions (such as phosphorus, boron, etc.) and setting appropriate concentrations.

[0071] In one embodiment, during diode operation, zero voltage is applied to the second gate electrode 192 of the sub-control gate structure 19, giving the N-type channel region 20 high conductivity. The N-type carrier blocking layer 14 is short-circuited to the metal emitter 21 through the N-type channel region 20, maintaining the barrier of the N-type carrier blocking layer 14. This prevents forward bias at the interface between the P-type base region 15 and the N-type carrier blocking layer 14 and suppresses hole injection from the P-type base region 15 to the P-well 13. In this embodiment, the low resistivity of the N-type carrier blocking layer 14 and the N-type channel region 20, along with the low concentration of the P-well 13, results in low hole injection efficiency, reducing the accumulated hole density on the diode anode side. This allows for a balance between diode forward voltage and switching losses without the need for lifetime control techniques.

[0072] In one embodiment, during IGBT operation, a positive voltage is applied to the main control gate electrode 173, enabling the IGBT to operate normally. A negative voltage is applied to the second gate electrode 192 of the sub-control gate structure 19, generating a large depletion region. This results in the N-type channel region 20 being in a low conductivity state, and the conductive channel between the N-type carrier blocking layer 14 and the metal emitter 21 is pinched off. This ensures that the threshold voltage, conduction characteristics, and turn-off characteristics of the IGBT remain unchanged. At the same time, the Miller capacitance of the device is reduced through the split gate structure 17, significantly improving the switching performance of the device and reducing the risk of false turn-on.

[0073] In one embodiment, the sub-control gate structure 19 is disposed between the split gate structure 17 and the emitter gate structure 18, and is disposed above the N-type collector region 23.

[0074] In one embodiment, the two sides of the N-type channel region 20 are tightly connected to the sub-control gate structure 19, and both ends are tightly connected to the N-type carrier blocking layer 14 and the metal emitter 21, respectively. This allows the N-type channel region 20 to have high conductivity during diode operation. During IGBT device operation, the N-type channel region 20 is pinched off by the sub-control gate structure 19 to keep the threshold voltage, conduction characteristics, and turn-off characteristics of the IGBT device unchanged. At the same time, the Miller capacitance of the device is reduced by the separated gate structure, which significantly improves the switching performance of the device and reduces the risk of false turn-on.

[0075] In one embodiment, the depth of the N-type channel region 20 is 1.5 micrometers to 4 micrometers, for example, 2 micrometers or 3 micrometers, and the width is 0.5 micrometers to 2 micrometers, for example, 1 micrometer or 1.5 micrometers, with a doping concentration of 1×10⁻⁶. 15 cm -3 ~2×10 18 cm -3 For example, 1×10 17 cm -3 1×10 18 cm -3 This allows the performance of the N-type channel region 20 to be controlled within a better range.

[0076] In one embodiment, the first gate dielectric layer 171, the second gate dielectric layer 172, the third gate dielectric layer 181, and the fourth gate dielectric layer 191 may be silicon dioxide, silicon oxynitride, high-K dielectric, etc., and the main control gate electrode 173, the shielding gate electrode 174, the first gate electrode 182, and the second gate electrode 192 may be doped polysilicon, metal, etc.

[0077] In one embodiment, the split gate structure 17 and the emitter gate structure 18 extend into the N-type drift region 12 to a depth, such as 5 to 10 micrometers. In a specific example, the depth of the split gate structure 17 is 5 to 10 micrometers and the width is 1 to 3 micrometers, and the depth of the emitter gate structure 18 is 5 to 10 micrometers and the width is 1 to 3 micrometers.

[0078] In one embodiment, the sub-control gate structure 19 extends into the N-type carrier blocking layer 14 to a depth, for example, 1.5 micrometers to 5.5 micrometers, to improve the pinch-off effect of the sub-control gate structure 19 on the N-type channel region 20 under negative pressure. In a specific example, the depth of the sub-control gate structure 19 is 1.5 micrometers to 5.5 micrometers, for example, 3 micrometers, 4 micrometers, 5 micrometers, etc., and the width is 0.5 micrometers to 2 micrometers, for example, 1 micrometer, 1.5 micrometers, etc.

[0079] In one embodiment, the depth of the P-well 13 is 3.5 micrometers to 9 micrometers, for example, 5 micrometers, 7 micrometers, 8 micrometers, etc., and the doping concentration is 5 × 10⁻⁶. 15 cm -3 ~2×10 18 cm -3 For example, 1×10 17 cm -3 1×10 18 cm -3 The depth of the N-type carrier blocking layer 14 is 2 micrometers to 6 micrometers, for example, 4 micrometers, 5 micrometers, etc., and the doping concentration is 4 × 10⁻⁶. 15 cm -3 ~6×10 18 cm -3 For example, 6×10 17 cm -3 5×10 18 cm -3 The depth of the P-type base region 15 is 1.5 micrometers to 4 micrometers, for example, 2 micrometers, 3 micrometers, 4 micrometers, etc., and the doping concentration is 1×10⁻⁶. 16 cm -3 ~4×10 17 cm -3 For example, 5×10 16 cm -3 1×10 17 cm -3 wait.

[0080] In one embodiment, the cell width of the RC-IGBT device is 8 micrometers to 20 micrometers, such as 10 micrometers, 12 micrometers, 14 micrometers, 16 micrometers, 18 micrometers, etc.

[0081] like Figures 1-7 As shown, this embodiment also provides a method for fabricating an RC-IGBT device. This method can be used to fabricate the RC-IGBT device described in this embodiment. The fabrication method includes the following steps:

[0082] like Figure 1As shown, step 1) is performed first to provide a substrate, which includes an N-type buffer layer 11, an N-type drift region 12, a P-well 13, an N-type carrier blocking layer 14, and a P-type base region 15 stacked sequentially.

[0083] In one embodiment, the substrate material can be silicon, germanium-silicon, germanium, silicon carbide, group III-V compounds, etc., and the depth of the P-well 13 is 3.5 micrometers to 9 micrometers, for example, 5 micrometers, 7 micrometers, 8 micrometers, etc., with a doping concentration of 5 × 10⁻⁶. 15 cm -3 ~2×10 18 cm -3 For example, 1×10 17 cm -3 1×10 18 cm -3 The depth of the N-type carrier blocking layer 14 is 2 micrometers to 6 micrometers, for example, 4 micrometers, 5 micrometers, etc., and the doping concentration is 4 × 10⁻⁶. 15 cm -3 ~6×10 18 cm -3 For example, 6×10 17 cm -3 5×10 18 cm -3 The depth of the P-type base region 15 is 1.5 micrometers to 4 micrometers, for example, 2 micrometers, 3 micrometers, 4 micrometers, etc., and the doping concentration is 1×10⁻⁶. 16 cm -3 ~4×10 17 cm -3 For example, 5×10 16 cm -3 1×10 17 cm -3 wait.

[0084] like Figure 2As shown, step 2) is then performed to form a discrete gate structure 17, an emitter gate structure 18, and a sub-control gate structure 19 in the substrate. The discrete gate structure 17 extends from the P-type base region 15 to the N-type drift region 12. The discrete gate structure 19 includes a first gate dielectric layer 171 located on the trench sidewall and bottom wall, a main control gate electrode 173 and a shielding gate electrode 174 filled in the trench on the first gate dielectric layer 171. The shielding gate electrode 174 is located below the main control gate electrode 173 and the two are isolated by a second gate dielectric layer 172. The emitter gate structure 18 includes a third gate dielectric layer 181 and a first gate electrode 182. The emitter gate structure 18 extends from the P-type base region 15 to the N-type drift region 12. The sub-control gate structure 19 includes a fourth gate dielectric layer 191 and a second gate electrode 192. The sub-control gate structure 19 extends from the P-type base region 15 to the N-type carrier blocking layer 14.

[0085] In one embodiment, the first gate dielectric layer 171, the second gate dielectric layer 172, the third gate dielectric layer 181, and the fourth gate dielectric layer 191 may be silicon dioxide, silicon oxynitride, high-K dielectric, etc., and the main control gate electrode 173, the shielding gate electrode 174, the first gate electrode 182, and the second gate electrode 192 may be doped polysilicon, metal, etc.

[0086] In one embodiment, the sub-control gate structure 19 extends into the N-type carrier blocking layer 14 to a depth, for example, 1.5 micrometers to 5.5 micrometers, to improve the pinch-off effect of the sub-control gate structure 19 on the N-type channel region 20 under negative pressure. In a specific example, the depth of the sub-control gate structure 19 is 1.5 micrometers to 5.5 micrometers, for example, 3 micrometers, 4 micrometers, 5 micrometers, etc., and the width is 0.5 micrometers to 2 micrometers, for example, 1 micrometer, 1.5 micrometers, etc.

[0087] In one embodiment, the discrete gate structure 17 and the emitter gate structure 18 extend into the N-type drift region 12 to a depth, such as 5 to 10 micrometers, to reduce the on-resistance of the IGBT device. In a specific example, the depth of the discrete gate structure 17 is 5 to 10 micrometers and the width is 1 to 3 micrometers, and the depth of the emitter gate structure 18 is 5 to 10 micrometers and the width is 1 to 3 micrometers.

[0088] like Figure 3 As shown, then step 3) is performed to form an N-type emitter region 16 in the P-type base region 15, and the N-type emitter region 16 is disposed on the side of the main control gate electrode 173.

[0089] like Figure 4As shown, then step 4) is performed to form an N-type channel region 20 in the substrate, wherein the N-type channel region 20 is disposed between two adjacent control gate structures 19.

[0090] In one embodiment, the two sides of the N-type channel region 20 are closely connected to the sub-control gate structure 19, and both ends are closely connected to the N-type carrier blocking layer 14 and the metal emitter 21, respectively. This allows the N-type channel region 20 to have high conductivity during diode operation, while during IGBT device operation, the N-type channel region 20 is pinched off by the sub-control gate structure 19 to keep the threshold voltage, conduction characteristics and turn-off characteristics of the IGBT device unchanged.

[0091] In one embodiment, the depth of the N-type channel region 20 is 1.5 micrometers to 4 micrometers, for example, 2 micrometers or 3 micrometers, and the width is 0.5 micrometers to 2 micrometers, for example, 1 micrometer or 1.5 micrometers, with a doping concentration of 1×10⁻⁶. 15 cm -3 ~2×10 18 cm -3 For example, 1×10 17 cm -3 1×10 18 cm -3 This allows the performance of the N-type channel region 20 to be controlled within a better range.

[0092] like Figure 5 As shown, step 5) is then performed to form a metal emitter 21 on the substrate. The metal emitter 21 is connected to the N-type emitter region 16, and the N-type channel region 20 connects the N-type carrier blocking layer 14 and the metal emitter 21.

[0093] like Figure 6 As shown, step 6) is then performed to form a collector region on the back side of the substrate, the collector region including a P-type collector region 22 and an N-type collector region 23 arranged in parallel.

[0094] like Figure 7 As shown, step 7) is performed last to form a metal collector electrode 24 on the surface of the collector region; wherein the main control gate electrode 173 is connected to the main gate drive of the device, the shield gate electrode 174 and the first gate electrode 182 of the emitter gate structure 18 are both connected to the metal emitter 21 of the device, and the second gate electrode 192 of the sub-control gate structure 19 is connected to the sub-gate drive of the device.

[0095] As described above, the RC-IGBT device and its fabrication method of the present invention have the following beneficial effects:

[0096] This invention, by setting a separate gate structure, connects the shielded gate electrode in the separate gate structure to the metal emitter, thereby blocking the electric field coupling between the main control gate electrode and the collector. As a result, the Miller capacitance between the main control gate electrode and the collector is greatly reduced, which makes the switching speed of the device faster and the turn-on and turn-off losses significantly reduced.

[0097] Reducing switching losses helps to optimize relevant parameters to further reduce on-state voltage drop, or simultaneously increase the switching frequency, thereby improving the trade-off relationship between on-state voltage drop and turn-off losses.

[0098] The shielded gate electrode connected to the emitter absorbs electric field lines, relieving the electric field stress of the gate dielectric layer in the blocking state. This helps optimize the electric field distribution near the bottom of the trench, thereby improving the reliability of the device and allowing the use of higher doping concentrations to reduce on-resistance.

[0099] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An RC-IGBT device, characterized in that, The RC-IGBT device includes: Metal current collector; The collector region includes a P-type collector region and an N-type collector region arranged side by side on the metal collector electrode; An N-type drift region is located on the collector region; The P-well is located on the N-type drift region; An N-type carrier blocking layer is located on the P-well; The P-type base region is located on the N-type carrier blocking layer; A split gate structure extends from the P-type base region to the N-type drift region. The split gate structure includes a first gate dielectric layer located on the sidewall and bottom wall of the trench, a main control gate electrode and a shielding gate electrode filled in the first gate dielectric layer within the trench; wherein the shielding gate electrode is located below the main control gate electrode and the two are isolated by a second gate dielectric layer. An emitter gate structure extending from the P-type base region to the N-type drift region; A secondary control gate structure, wherein the secondary control gate structure extends from the P-type base region into the N-type carrier blocking layer; An N-type emitter region is disposed in the P-type base region and on the side of the main control gate electrode; A metal emitter is disposed on the P-type base region and connected to the N-type emitter region; An N-type channel region is disposed between two adjacent control gate structures, and the N-type channel region connects the N-type carrier blocking layer and the metal emitter; The main control gate electrode is connected to the main gate drive of the device, the shield gate electrode and the first gate electrode of the emitter gate structure are both connected to the metal emitter of the device, and the second gate electrode of the sub-control gate structure is connected to the sub-gate drive of the device.

2. The RC-IGBT device according to claim 1, characterized in that: During diode operation of the RC-IGBT device, zero voltage is applied to the second gate electrode of the sub-control gate structure, giving the N-type channel region high conductivity. The N-type carrier blocking layer is short-circuited to the metal emitter through the N-type channel region, thus maintaining the barrier of the N-type carrier blocking layer. This prevents forward bias at the interface between the P-type base region and the N-type carrier blocking layer and suppresses hole injection from the P-type base region to the P-well.

3. The RC-IGBT device according to claim 1, characterized in that: During operation, a positive voltage is applied to the main control gate electrode of the RC-IGBT device, enabling normal operation. A negative voltage is applied to the second gate electrode of the sub-control gate structure, creating a large depletion region. This results in a low conductivity N-type channel region, pinching off the conductive channel between the N-type carrier blocking layer and the metal emitter. Consequently, the threshold voltage, turn-on characteristics, and turn-off characteristics of the IGBT device remain unchanged. Simultaneously, the separated gate structure reduces the Miller capacitance of the device, significantly improving its switching performance and reducing the risk of false turn-on.

4. The RC-IGBT device according to claim 1, characterized in that: The main control gate electrode extends from the P-type base region into the N-type carrier blocking layer.

5. The RC-IGBT device according to claim 1, characterized in that: The secondary control gate structure is disposed between the discrete gate structure and the emitter gate structure, and is disposed above the N-type collector region.

6. The RC-IGBT device according to claim 1, characterized in that: The two sides of the N-type channel region are closely connected to the sub-control gate structure, and the two ends are closely connected to the N-type carrier blocking layer and the metal emitter, respectively.

7. The RC-IGBT device according to claim 1, characterized in that: The RC-IGBT device further includes an N-type buffer layer, which is located between the collector region and the N-type drift region.

8. The RC-IGBT device according to claim 1, characterized in that: The depth of the discrete gate structure is 5 micrometers to 10 micrometers and the width is 1 micrometer to 3 micrometers. The depth of the emitter gate structure is 5 micrometers to 10 micrometers and the width is 1 micrometer to 3 micrometers.

9. The RC-IGBT device according to claim 1, characterized in that: The P-well has a depth of 3.5 μm to 9 μm and a doping concentration of 5 × 10⁻⁶. 15 cm -3 ~2×10 18 cm -3 The depth of the N-type carrier blocking layer is 2 micrometers to 6 micrometers, and the doping concentration is 4 × 10⁻⁶. 15 cm -3 ~6×10 18 cm -3 The depth of the P-type base region is 1.5 micrometers to 4 micrometers, and the doping concentration is 1×10⁻⁶. 16 cm -3 ~4×10 17 cm -3 .

10. The RC-IGBT device according to claim 1, characterized in that: The depth of the sub-control gate structure is 1.5 micrometers to 5.5 micrometers, and the width is 0.5 micrometers to 2 micrometers.

11. The RC-IGBT device according to claim 1, characterized in that: The N-type channel region has a depth of 1.5 μm to 4 μm, a width of 0.5 μm to 2 μm, and a doping concentration of 1 × 10⁻⁶. 15 cm -3 ~2×10 18 cm -3 .

12. A method for fabricating an RC-IGBT device as described in any one of claims 1 to 11, characterized in that, The preparation method includes the following steps: A substrate is provided, the substrate comprising an N-type buffer layer, an N-type drift region, a P-well, an N-type carrier blocking layer and a P-type base region stacked sequentially; A discrete gate structure, an emitter gate structure, and a sub-control gate structure are formed in the substrate. The discrete gate structure extends from the P-type base region to the N-type drift region. The discrete gate structure includes a first gate dielectric layer located on the sidewall and bottom wall of the trench, a main control gate electrode and a shielding gate electrode filled in the first gate dielectric layer within the trench, the shielding gate electrode being located below the main control gate electrode and isolated from it by a second gate dielectric layer. The emitter gate structure includes a third gate dielectric layer and a first gate electrode, extending from the P-type base region to the N-type drift region. The sub-control gate structure includes a fourth gate dielectric layer and a second gate electrode, wherein the sub-control gate structure extends from the P-type base region to the N-type carrier blocking layer. An N-type emitter region is formed in the P-type base region, and the N-type emitter region is disposed on the side of the main control gate electrode; An N-type channel region is formed in the substrate, and the N-type channel region is disposed between two adjacent control gate structures; A metal emitter is formed on the substrate, the metal emitter is connected to the N-type emitter region, and the N-type channel region connects the N-type carrier blocking layer and the metal emitter; A current-collecting region is formed on the back side of the substrate, the current-collecting region including P-type current-collecting regions and N-type current-collecting regions arranged in parallel; A metal current collector electrode is formed on the surface of the current collector region; The main control gate electrode is connected to the main gate drive of the device, the shield gate electrode and the first gate electrode of the emitter gate structure are both connected to the metal emitter of the device, and the second gate electrode of the sub-control gate structure is connected to the sub-gate drive of the device.

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