A multi-point avalanche triggered siC mos controlled thyristor

Abstract

The present application belongs to SiC semiconductor devices, and particularly relates to a SiC MOS-controlled thyristor with multi-point avalanche triggering. In the process of manufacturing the device, the number of ion implantation and the energy of the p-well are increased, and one or two or more times of ion implantation is carried out during the implantation of the p-well, and the depth of the implantation is greater than the depth of the first implantation, so as to generate a large-curvature junction surface and form multiple avalanche points. Under the condition of high-voltage pulse discharge, the avalanche points can generate a large amount of carriers to assist in triggering the conduction and expansion of the thyristor. The thyristor of the present application has a more rapid regional conduction and expansion, a faster device opening, and a smaller conduction resistance. In the pulse discharge experiment, the peak current I peak is increased by about 65%, and the current rise rate di / dt is increased by about 2.5 times.

Description

Technical Field

[0001] This invention pertains to SiC semiconductor devices, specifically a SiC MOS controlled thyristor with multi-point avalanche triggering. Background Technology

[0002] Pulsed power systems achieve significant power amplification in a very short time by rapidly releasing long-term stored high-density energy to the load. Key characteristics include high voltage, high current, and a strong pulse effect. As the core component of a pulsed power system, the performance of the pulsed power switch directly affects the system's power output level, waveform quality, and overall reliability. Therefore, pulsed power switches are expected to have high turn-on speed and low on-resistance. Compared to traditional silicon-based power devices, SiC power devices offer several significant advantages: Thanks to their larger bandgap, SiC exhibits a higher breakdown electric field strength, enabling them to withstand higher voltages and currents, making them suitable for high-voltage and high-power applications; at the same voltage rating, SiC devices have lower on-resistance and switching losses, allowing for higher power density; at the same power, the size and weight of SiC devices can be significantly reduced, achieving system miniaturization and weight reduction; SiC power devices have higher saturated electron drift velocity, enhancing their current capability and switching performance; and SiC power devices also have higher melting points and thermal conductivity, allowing them to operate at temperatures above 300°C, maintaining excellent electrical performance in high-temperature environments, reducing the likelihood of performance degradation or failure, and improving system reliability and stability.

[0003] The inherent thyristor structure within a MOS-controlled thyristor is key to achieving strong conductivity modulation and low on-resistance. During pulsed operation, the generation of internal non-equilibrium carriers is not controlled by the MOS channel, resulting in a stronger conductivity modulation effect and enabling high pulse current. Combining the advantages of SiC material and thyristor-type devices, SiC MOS-controlled thyristors show great promise in pulsed power applications. However, due to the large bandgap of SiC, the high built-in potential and high turn-on voltage of the SiC PN junction lead to slow turn-on of the p-well / n drift region junction in SiC MOS-controlled thyristors, hindering their rapid conduction. Summary of the Invention

[0004] This invention addresses the slow turn-on phenomenon of p-well / n-well junctions in SiC MOS controlled thyristors by proposing a multi-point avalanche triggering SiC MOS controlled thyristor.

[0005] The technical solution of this invention is:

[0006] A multi-point avalanche-triggered SiC MOS controlled thyristor is disclosed. The p-well of the thyristor is formed by at least two ion implantations. After the first ion implantation, the contact surface between the p-well and the n-drift region is planar. Each subsequent ion implantation is performed within the window of the previous ion implantation. Depending on the requirements, one or more windows smaller than the previous ion implantation window are selected for ion implantation. Furthermore, the implantation junction depth of each subsequent ion implantation is greater than that of the previous ion implantation. This results in one or more protrusion structures forming at the bottom of the p-well along the vertical direction of the device into the n-drift region, thereby obtaining multiple avalanche points. During pulse discharge, the avalanche points under high voltage generate a large number of charge carriers, which assist in triggering the thyristor, enabling the device to conduct quickly and achieve a lower on-resistance.

[0007] Furthermore, the p-well of the thyristor is formed by two ion implantations. The second ion implantation is based on the first ion implantation. A mask with multiple windows is made in the window of the first ion implantation to perform the second ion implantation as required, thereby obtaining multiple protrusion structures that protrude into the n-drift region along the vertical direction of the device. The protrusion structure is defined as an avalanche junction, and each avalanche junction introduces multiple avalanche points.

[0008] Furthermore, the p-well of the thyristor is formed by three ion implantations. The second ion implantation is performed based on the first ion implantation. A mask with multiple windows is fabricated within the window of the first ion implantation to perform the second ion implantation, thereby obtaining multiple protrusion structures protruding into the n-drift region along the vertical direction of the device. The third ion implantation is performed based on the second ion implantation. A mask with one or more windows is fabricated within the window of the second ion implantation to perform the third ion implantation, thereby continuing to protrude into the n-drift region along the vertical direction of the device at the bottom of the protrusion structure obtained by the second ion implantation, obtaining the corresponding protrusion structure of the third ion implantation window. The protrusion structure is defined as an avalanche junction, and each avalanche junction introduces multiple avalanche points.

[0009] The beneficial effects of this invention are that the thyristor region of this invention conducts and expands more rapidly, the device turns on faster, and the on-resistance is lower. In pulse discharge experiments, the peak current I of this invention is lower than that of conventional SiC MOS controlled thyristors. peak It improved by about 65%, and the current rise rate di / dt improved by about 2.5 times. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of an additional ion implantation in a SiC MOS-controlled thyristor triggered by multi-point avalanche.

[0011] Figure 2This is a schematic diagram of a SiC MOS-controlled thyristor with multiple avalanche triggering, involving two additional ion implantations.

[0012] Figure 3 This is a schematic diagram of the structure of a SiC MOS-controlled thyristor with multiple ion implantations triggered by multi-point avalanche.

[0013] Figure 4 This is a schematic diagram of a pulse discharge circuit;

[0014] Figure 5 This is a schematic diagram of the two-dimensional motion mechanism of internal charge carriers in a SiC MOS controlled thyristor triggered by multi-point avalanche.

[0015] Figure 6 This is a schematic diagram comparing the collision ionization rates of a SiC MOS-controlled thyristor triggered by multi-point avalanche and a conventional SiC MOS-controlled thyristor.

[0016] Figure 7 This is a comparison chart of the diffusion velocity of the thyristor operating region between a SiC MOS controlled thyristor triggered by multi-point avalanche and a conventional SiC MOS controlled thyristor.

[0017] Figure 8 This is a comparison chart of the pulse current of a SiC MOS controlled thyristor with multi-point avalanche triggering and a conventional SiC MOS controlled thyristor.

[0018] Figure 9 This is a graph showing the resistance changes of a multi-point avalanche-triggered SiC MOS-controlled thyristor and a conventional SiC MOS-controlled thyristor during the pulse process. Detailed Implementation

[0019] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0020] This invention primarily addresses the issue by increasing the number of ion implantations in the p-well. During the initial p-well implantation, additional one, two, or even more ion implantations are performed, resulting in a junction depth greater than the first implantation. This increases the curvature of the p-well / n drift region junction, creating numerous avalanche points. Under high-voltage pulsed discharge conditions, these numerous avalanche points generate a large number of charge carriers, triggering the thyristor and achieving faster device turn-on and lower on-resistance.

[0021] Example 1:

[0022] like Figure 1As shown, in this example, an additional implantation is performed based on a conventional thyristor, that is, a total of two ion implantations are carried out in this example. The second ion implantation is based on the first ion implantation. By fabricating the required multi-window mask plate, a plurality of protruding structures that protrude into the n-drift region are obtained. In the cross-sectional view of the thyristor, the protruding P-wells obtained by the second ion implantation and the p-wells implanted for the first time form an inverted "convex" shaped avalanche junction, and 1-3 avalanche points can be introduced for each avalanche junction.

[0023] Example 2:

[0024] As Figure 2 shown, in this example, a third ion implantation is performed based on Example 1. The third ion implantation selects one implantation window through the mask plate in each window of the second ion implantation, so that the bottom of each protruding structure obtained by the second ion implantation further protrudes into the n-drift region to obtain a new protruding structure. In the cross-sectional view of the thyristor, the formed multiple protruding P-wells are in a pagoda shape, thereby obtaining more avalanche junctions.

[0025] Example 3:

[0026] As Figure 3 shown, in this example, a third ion implantation is performed based on Example 1. The third ion implantation selects two implantation windows through the mask plate in each window of the second ion implantation, so that the bottom of each protruding structure obtained by the second ion implantation further protrudes into the n-drift region to obtain 2 protruding structures arranged along the lateral direction of the device, thereby obtaining more avalanche junctions.

[0027] Based on the above examples, more additional implantations can be selected. By increasing the number of implantations or adjusting the positions of multiple implantations, more avalanche points can be introduced.

[0028] The core technology of the present invention is based on the parallel junction surface of the conventional structure p-well / n-drift region. Through a special mask plate, the number of ion implantations is increased, the curvature of the p-well / n-drift region junction surface is increased, the number of avalanche points is increased, and a large number of carriers are generated under high voltage conditions to assist in triggering the thyristor. Compared with the conventional structure, the present invention only needs to increase the number of p-well ion implantations during device fabrication and does not require the introduction of additional processes.

[0029] The SiC MOS controlled thyristor with multi-point avalanche triggering has a typical application scenario of a capacitive pulse discharge circuit, such as Figure 4 shown. Among them, the DC power supply uses a constant voltage source, R g is the gate resistance, R CL1 and L2 are the charging resistors of the charging circuit, L1 and L2 are the parasitic inductances of the discharging circuit, MCT is the SiC MOS control thyristor with multi-point avalanche triggering in this invention, and C is the energy storage capacitor. During the charging phase, MCT is in a blocking state, the discharging circuit is open, and the DC power supply charges capacitor C through the charging circuit until the capacitor voltage equals the power supply voltage. When the capacitor voltage reaches the power supply voltage, the charging circuit is disconnected, and MCT is turned on via a gate signal. The capacitor will then discharge through the discharging circuit until its stored energy is completely depleted. If MCT is considered equivalent to a resistor, the discharging circuit can be considered equivalent to an RLC series circuit. When the equivalent resistance of MCT is sufficiently small, the pulse current is underdamped, and the peak pulse current I... peak It is extremely high and has a high rate of change of current di / dt.

[0030] During the initial conduction phase, a positive voltage is applied to the gate of the MOSFET, forming a MOSFET channel that allows electron current to flow into the N-drift region. When this electron current is injected into the N-drift region, electrons are rapidly swept into the P-drift region by the high electric field. + On the anode side, the injection of electrons, acting as excess charge carriers, lowers the potential of the N-drift region. This lower potential becomes the base current of the PNP thyristor, driving the injection of holes into the P+ anode to form a hole current. This hole current then travels through the N-drift region to the p-well. Figure 5 As shown, due to the presence of a cathode short-circuit point, holes will expand laterally towards the cathode short-circuit point. This current flows through the P-well resistor, generating a voltage drop. If this voltage drop is greater than the PN junction turn-on voltage (approximately 2.8~3V), the P-well / N+ junction will turn on, triggering the thyristor. The thyristor always turns on first near the turn-on channel, forming the initial conduction region. Then, with the lateral movement of charge carriers, the thyristor conduction region expands laterally to the entire thyristor region. During the conduction process, the thyristor conduction region always expands laterally from the initial conduction region to the entire cell.

[0031] Let's take performing an additional injection as an example. Figure 6 As shown, the collisional ionization generation rate of the multi-point avalanche-triggered SiC MOS-controlled thyristor at the p-well / n drift region interface is much higher than that of the conventional SiC MOS-controlled thyristor. It can generate a large number of charge carriers under high voltage, which is the key to realizing fast-triggered thyristors.

[0032] In a conventional SiC MOS-controlled thyristor structure, the holes triggering the P-well / N+ junction are entirely supplied by the P+ anode, and this current is affected by factors such as anode injection efficiency. However, in a multi-point avalanche-triggered SiC MOS-controlled thyristor, these holes are supplied not only by the P+ anode but also by numerous avalanche points. The holes generated by avalanche ionization serve as part of the hole current, assisting in thyristor triggering. For example... Figure 7As shown, the presence of electron injection in the P-well is observed, and the activation of the P-well / N+ junction is used as the criterion for determining whether the thyristor's operating region is activated. The thyristor operating region of the multi-point avalanche-triggered SiC MOS-controlled thyristor diffuses much more rapidly, having propagated approximately 50 μm at 100 ns and approximately 75 μm at 200 ns; while in conventional structures, expansion only begins at 100 ns and reaches only 40 μm at 200 ns.

[0033] like Figure 8 As shown, at a discharge voltage of 800V, the parasitic inductance of the circuit is approximately 75nH, and the discharge capacitance is approximately 0.1uF. The multi-point avalanche triggered SiC MOS controlled thyristor exhibits superior pulse performance, with a pulse peak current I... peak It reaches 746A, higher than the conventional structure's 452A, representing an improvement of approximately 65%; the current rise rate di / dt reaches 6.78kA / μs, higher than the conventional structure's 1.92kA / μs, representing an improvement of 2.5 times.

[0034] like Figure 9 As shown, the minimum on-resistance of a multi-point avalanche triggered SiC MOS controlled thyristor is less than 1mΩ, while the minimum on-resistance of a conventional structure under this condition is only about 10mΩ.

[0035] In summary, the proposed multi-point avalanche-triggered SiC MOS controlled thyristor utilizes the large number of charge carriers generated to assist in triggering the p-well / n-well junction, enabling the device to quickly enter the thyristor conduction mode. This is of great significance for the research and application of pulsed power systems.

Claims

1. A multi-point avalanche triggered SiC MOS controlled thyristor, characterized in that, The p-well of a thyristor is formed by at least two ion implantations. After the first ion implantation, the contact surface between the p-well and the n-drift region is planar. Each subsequent ion implantation is performed within the window of the previous ion implantation. Depending on the requirements, one or more windows smaller than the previous ion implantation window are selected for ion implantation. Furthermore, the implantation junction depth of each subsequent ion implantation is greater than that of the previous ion implantation. This results in one or more bulge structures forming at the bottom of the p-well along the vertical direction of the device into the n-drift region, thus creating multiple avalanche points. During pulse discharge, the avalanche points under high voltage generate a large number of charge carriers, which assist in triggering the thyristor, enabling the device to conduct quickly and achieve a lower on-resistance.

2. The multi-point avalanche triggered SiC MOS controlled thyristor according to claim 1, characterized in that, The p-well of the thyristor is formed by two ion implantations. The second ion implantation is based on the first ion implantation. A mask with multiple windows is made in the window of the first ion implantation and then the second ion implantation is performed to obtain multiple protrusion structures that protrude into the n-drift region along the vertical direction of the device. The protrusion structure is defined as an avalanche junction, and each avalanche junction introduces multiple avalanche points.

3. A multi-point avalanche triggered SiC MOS controlled thyristor according to claim 1, characterized in that, The p-well of the thyristor is formed by three ion implantations. The second ion implantation is performed based on the first ion implantation. A mask with multiple windows is fabricated within the window of the first ion implantation to perform the second ion implantation, thereby obtaining multiple protrusion structures protruding into the n-drift region along the vertical direction of the device. The third ion implantation is performed based on the second ion implantation. A mask with one or more windows is fabricated within the window of the second ion implantation to perform the third ion implantation, thereby continuing to protrude into the n-drift region along the vertical direction of the device at the bottom of the protrusion structure obtained by the second ion implantation, resulting in the corresponding protrusion structure of the third ion implantation window. The protrusion structure is defined as an avalanche junction, and each avalanche junction introduces multiple avalanche points.

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