A semiconductor device, a manufacturing method thereof, and an electronic apparatus

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the manufacturing method comprising: providing a semiconductor substrate, the semiconductor substrate being formed with a fin structure; sequentially forming a dummy gate dielectric layer and a dummy gate electrode layer on the fin structure; etching the dummy gate electrode layer and the dummy gate dielectric layer to form a dummy gate structure across the fin structure; performing a first modification process on the dummy gate structure to form a first modification layer on the sidewall of the dummy gate structure; forming a sidewall layer outside the first modification layer; etching the fin structure on both sides of the sidewall layer to form a source-drain recess; and forming an epitaxial source-drain structure in the source-drain recess. The modification of the sidewall of the dummy gate structure can avoid lateral consumption of the dummy gate dielectric layer when forming the source-drain recess, better preserve the dummy gate dielectric layer between the epitaxial source-drain structure and the dummy gate electrode layer, and protect the epitaxial source-drain structure from being damaged when removing the dummy gate electrode layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] As semiconductor device dimensions continue to shrink, challenges in manufacturing and design have spurred the development of 3D transistors. Compared to existing planar transistors, 3D transistors can effectively increase the density of transistor arrays formed on a substrate. Furthermore, the use of fin-like 3D structures increases the contact area, thereby improving semiconductor performance and reducing current leakage.

[0003] Currently, in the fabrication of 3D transistors, a dummy gate structure is first formed on the fin structure. Then, grooves are etched into the fin structures on both sides of the dummy gate structure, and an epitaxial layer is formed in the grooves using an epitaxial process. Finally, the source / drain structure is formed through a doping process. However, the etching and cleaning of the grooves can easily cause lateral loss of the dummy gate dielectric layer, which can damage the epitaxial layer and cause short circuits between the source / drain and the gate during subsequent dummy gate removal. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] A semiconductor substrate is provided, on which a fin structure is formed;

[0007] A pseudo-gate dielectric layer and a pseudo-gate electrode layer are sequentially formed on the fin structure;

[0008] The dummy gate electrode layer and the dummy gate dielectric layer are etched to form a dummy gate structure spanning the fin structure;

[0009] A first modification process is performed on the pseudo-gate structure to form a first modification layer on the sidewalls of the pseudo-gate dielectric layer and the pseudo-gate electrode layer;

[0010] A sidewall layer is formed on the outside of the first modified layer;

[0011] The fin structures on both sides of the sidewall layer are etched to form source / drain grooves;

[0012] An epitaxial source-drain structure is formed in the source-drain groove.

[0013] In some embodiments, the first modification process includes a nitriding process, and the first modified layer includes a first nitriding layer.

[0014] In some embodiments, the nitriding process includes a decoupled plasma nitriding process, and the first modification process further includes a post-nitriding annealing process performed after the decoupled plasma nitriding process.

[0015] In some embodiments, after forming the dummy gate dielectric layer and before forming the dummy gate electrode layer, the method further includes:

[0016] A second modification process is performed on the dummy gate dielectric layer to form a second modified layer on the surface of the dummy gate dielectric layer.

[0017] In some embodiments, the second modification process includes a nitriding process, and the second modified layer includes a second nitrided layer.

[0018] In some embodiments, the nitriding process includes a decoupled plasma nitriding process, and the second modification process further includes a post-nitriding annealing process performed after the decoupled plasma nitriding process.

[0019] In some embodiments, after forming the epitaxial source-drain structure, the method further includes:

[0020] A filler layer is formed between the sidewall layers, the filler layer exposing the upper surface of the dummy gate electrode layer;

[0021] Remove the dummy gate electrode layer to form a gate recess in the fill layer;

[0022] A gate structure is formed in the gate recess.

[0023] In some embodiments, the pseudo-gate structure further includes a pseudo-gate hard mask layer formed above the pseudo-gate electrode layer, and the first modified layer is also formed on the sidewalls and upper surface of the pseudo-gate hard mask layer.

[0024] The process of forming a fill layer between the sidewall layers, the fill layer exposing the upper surface of the dummy gate electrode layer, includes:

[0025] A filling layer is formed to cover the pseudo-gate structure;

[0026] A planarization process is used to remove the dummy gate hard mask layer and the filler layer formed above the dummy gate hard mask layer to expose the upper surface of the dummy gate electrode layer.

[0027] A second aspect of the present invention provides a semiconductor device, which is manufactured using the method described above.

[0028] A third aspect of the present invention provides an electronic device, the electronic device comprising the semiconductor device described above.

[0029] According to the semiconductor device and its manufacturing method and electronic device provided by the present invention, modifying the sidewall of the dummy gate structure can avoid lateral consumption of the dummy gate dielectric layer when forming the source-drain groove, better preserve the dummy gate dielectric layer between the source-drain epitaxial structure and the dummy gate electrode layer, and protect the epitaxial source-drain structure from damage when removing the dummy gate electrode layer. Attached Figure Description

[0030] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0031] In the attached image:

[0032] Figures 1A to 1E A cross-sectional schematic diagram is shown of a semiconductor device obtained by sequentially performing the steps of a semiconductor device manufacturing method according to the related art;

[0033] Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0034] Figures 3A to 3I A schematic cross-sectional view of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0036] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] The current manufacturing process for 3D transistors is as follows: Figure 1A As shown, a semiconductor substrate 100 including a fin structure 101 is provided, and a dummy gate dielectric layer 102, a dummy gate layer 103, and a dummy gate hard mask layer 104 are formed on the fin structure 101; as Figure 1BAs shown, a patterning process is performed on the dummy gate dielectric layer 102, the dummy gate layer 103, and the dummy gate hard mask layer 104 to form a dummy gate structure. Sidewalls 105 are formed on both sides of the dummy gate structure, and source / drain grooves are etched in the fin structures 101 on both sides of the dummy gate structure. Figure 1C As shown, an epitaxial source / drain structure 106 is formed in the source / drain groove using an epitaxial process; as Figure 1D As shown, a filling layer 107 is formed on both sides of the dummy gate structure, and the gate hard mask layer 104 is removed to expose the dummy gate electrode layer 103; finally, as... Figure 1E As shown, the dummy gate electrode layer 103 is removed to form a gate groove, and a metal gate can be formed in the gate groove subsequently.

[0041] In the above manufacturing process, during the etching of source / drain grooves on both sides of the dummy gate structure and the pre-cleaning of the source / drain grooves, lateral consumption of the dummy gate dielectric layer 102 is easily caused, such as... Figure 1C As shown. Then as... Figure 1E As shown, when the dummy gate electrode layer 103 is removed, the etchant will contact the epitaxial source-drain structure 106 from the damaged part of the dummy gate dielectric layer 102, thereby damaging the epitaxial source-drain structure 106 and causing a short circuit effect between the source-drain electrode and the gate.

[0042] In view of the aforementioned technical problems, embodiments of the present invention propose a method for fabricating a semiconductor device. The following refers to... Figure 2 and Figures 3A to 3I The method for fabricating the semiconductor device according to embodiments of the present invention will be described in detail, wherein, Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. Figures 3A to 3I A schematic cross-sectional view of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0043] First, execute step S201, such as Figure 3A As shown, a semiconductor substrate 300 is provided, on which a fin structure 301 is formed.

[0044] The semiconductor substrate 300 is made of at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI).

[0045] A fin structure 301 is formed on a semiconductor substrate 300. The method for forming the fin structure is not limited to one specific method; an exemplary method is given below: a hard mask layer is formed on the semiconductor substrate 300; the hard mask layer is patterned to form multiple separate hard mask patterns for etching the semiconductor substrate 300 to form fins thereon. In one embodiment, a self-aligned double-patterning process can be used to perform the patterning process; finally, the semiconductor substrate 300 is etched under the mask of the hard mask layer to form the fin structure 301 thereon. Depending on the type of device to be formed, different types of dopant ions can be doped into the fin structure 301 to adjust electrical parameters such as the threshold voltage of the transistor.

[0046] Next, step S202 is performed, in which a dummy gate dielectric layer 302 and a dummy gate electrode layer 303 are sequentially formed on the fin structure. Specifically, firstly as follows... Figure 3A As shown, a dummy gate dielectric layer 302 is formed on the fin structure 301. The material of the dummy gate dielectric layer 302 is, for example, silicon oxide, and the dummy gate dielectric layer 302 can be formed by a suitable deposition process such as chemical vapor deposition or atomic layer deposition.

[0047] For example, after forming the dummy gate dielectric layer 302, a second modification process can be performed on the dummy gate dielectric layer 302 to form a second modified layer 302' on the surface of the dummy gate dielectric layer 302. In the subsequent etching process of the source / drain trenches and the pre-cleaning process, the second modified layer 302' can protect the dummy gate dielectric layer 302 from longitudinal loss, thereby avoiding damage to the subsequently formed epitaxial source / drain structure.

[0048] For example, the second modification process includes a nitriding process, and the second modified layer 302' is a nitriding layer. The nitriding layer has a lower etching rate in etchants such as HF (hydrogen fluoride) and SiCoNi (remote plasma-assisted dry etching process) than the etching rate of silicon oxide, thus protecting the dummy gate dielectric layer 302.

[0049] Furthermore, the second modification process includes, for example: Figure 3B The decoupled plasma nitridation (DPN) process shown, and as... Figure 3CThe post-nitriding annealing (PNA) process is shown. The decoupled plasma nitriding process utilizes plasma activation to form a nitrided layer on the surface of the pseudo-gate dielectric layer 302 through chemical reactions. Decoupling refers to adjusting various parameters of the nitriding process, separating and regulating influencing factors such as chemical reactions, electronic excitation, and gas flow to achieve optimal deposition results. Decoupling can include temporal decoupling and spatial decoupling. Temporal decoupling involves adjusting parameters such as reaction time, nitrogen source concentration, and reaction temperature to change the degree of plasma activation and the chemical reaction rate, thus better controlling the thickness and quality of the nitrided layer. Spatial decoupling involves changing the gas flow and electronic excitation state in the plasma to achieve fine control of the nitriding process. Therefore, by adjusting the nitriding parameters, efficient control of the nitriding process can be achieved. The post-nitriding annealing process can eliminate stress in the nitrided layer, repair lattice damage, and stabilize the doped nitrogen ions. Furthermore, the second modification process can also include other suitable nitriding treatments such as remote plasma nitriding.

[0050] Next, as Figure 3D As shown, a dummy gate electrode layer 303 is deposited on the second modified layer 302'. The constituent material of the dummy gate electrode layer 303 may include polysilicon, and the polysilicon layer may be formed using a chemical vapor deposition process. Subsequently, a dummy gate hard mask layer 304 may be formed on the dummy gate electrode layer 303, the dummy gate hard mask layer 304 comprising a silicon nitride layer, a silicon oxide layer, or a stack of both.

[0051] Next, proceed to step S203, as follows: Figure 3E As shown, the dummy gate electrode layer 303 and the dummy gate dielectric layer 302 are etched to form a dummy gate structure spanning the fin structure 301. Exemplarily, a patterned photoresist layer can be formed above the dummy gate hard mask layer 304, and the dummy gate hard mask layer 304, the dummy gate electrode layer 303, and the dummy gate dielectric layer 302 are sequentially etched using the photoresist layer as a mask to form the dummy gate structure.

[0052] Next, step S204 is performed to conduct a first modification process on the dummy gate structure to form a first modification layer 305 on the sidewalls of the dummy gate dielectric layer 302 and the dummy gate electrode layer 303. Exemplarily, the first modification layer 305 is also formed on the sidewalls and upper surface of the dummy gate hard mask layer; in the subsequent etching process of the source / drain trenches, the first modification layer 305 can protect the dummy gate dielectric layer 302 from damage by the etchant, thereby preventing damage to the subsequently formed epitaxial source / drain structure.

[0053] For example, the first modification process includes a nitriding process, and the first modified layer 305 is a nitriding layer. The etching rate of the nitriding layer in etchants such as HF (hydrogen fluoride) and SiCoNi (far-end plasma-assisted dry etching process) is lower than that of silicon oxide. Therefore, the first modified layer 305 formed on both sides of the dummy gate dielectric layer 302 can protect the dummy gate dielectric layer 302 and prevent the dummy gate dielectric layer 302 from being laterally consumed.

[0054] Furthermore, the first modification process includes decoupled plasma nitriding (DPN) and post-nitriding anneal treatment (PNA). DPN utilizes plasma activation to form a nitrided layer on the sidewall surface of the pseudo-gate structure through a chemical reaction. Efficient control of the nitriding process can be achieved by adjusting the nitriding parameters. Post-nitriding annealing can eliminate stress in the nitrided layer, repair lattice damage, and stabilize the doped nitrogen ions. In addition, the first modification process may also include other suitable nitriding treatments such as remote plasma nitriding.

[0055] Next, proceed to step S205, as follows: Figure 3F As shown, a sidewall layer 306 is formed on the outer side of the first modified layer 305. Exemplarily, a sidewall material layer covering the dummy gate structure is first deposited; the sidewall material layer is then etched back until the first modified layer 305 on top of the dummy gate hard mask layer 304 is exposed, thereby forming the dummy gate sidewall 306. Exemplarily, the sidewall material layer can be deposited using atomic layer deposition, and the sidewall material layer includes, but is not limited to, a silicon nitride layer.

[0056] Next, step S206 is performed to etch the fin structures 301 on both sides of the sidewall layer 306 to form source / drain grooves 307. Specifically, etching is performed using the sidewall layer 306 as a mask to form source / drain grooves 307 in the fin structures 301 on both sides of the sidewall layer 306. Exemplarily, a dry etching process and a wet etching process are performed sequentially to form the source / drain grooves 307. First, using the sidewall layer 306 as a mask, an anisotropic dry etching process is used to form a bowl-shaped groove in the fin structure 301. Next, a wet etching process is used to etch the bowl-shaped groove, taking advantage of the different etching rates of the etchant in the wet etching process on different crystal orientations of the constituent materials of the fin structure to extend the etching of the bowl-shaped groove. As an example, the etchant for wet etching includes a tetramethylammonium hydroxide (TMAH) solution.

[0057] Next, the process includes a cleaning process for subsequent epitaxial growth of the source / drain groove 307. The cleaning process is used to remove the oxide layer, surface contaminants, and surface passivation layer from the surface of the source / drain groove 307. The cleaning process generally includes DHF (dilute hydrofluoric acid) pre-cleaning and SiCoNi in-situ cleaning.

[0058] In the etching and cleaning process of the source-drain groove 307, since a modified layer is formed on both the surface and sidewall of the dummy gate dielectric layer 302, the modified layer has a low reaction rate in both the etchant and the cleaning solution, thus protecting the dummy gate dielectric layer 302 from longitudinal or lateral loss.

[0059] Next, proceed to step S207, as follows: Figure 3G As shown, an epitaxial source / drain structure 308 is formed in the source / drain trench 307. Specifically, a stress layer can be grown in the source / drain trench 307 using selective epitaxial growth, and the stress layer can be doped to form the epitaxial source / drain structure 308. Selective epitaxial growth can employ one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). In P-type 3D transistor devices, the stress layer has compressive stress, and its material includes, but is not limited to, SiGe. In N-type 3D transistor devices, the stress layer has tensile stress, and its material includes SiP, SiC, or other suitable materials that can provide tensile stress.

[0060] For example, after forming the epitaxial source-drain structure 308, as Figure 3H As shown, a fill layer 309 is formed between the sidewall layers 306, exposing the upper surface of the dummy gate electrode layer 303. The material of the fill layer 309 is different from the material of the dummy gate electrode layer 303; for example, the material of the fill layer 309 can be silicon oxide. For example, the fill layer 309 covering the dummy gate structure is formed using a deposition process or a spin coating process; then, a planarization process is used to remove the dummy gate hard mask layer 304 and the fill layer 309 formed above the dummy gate hard mask layer 304 to expose the upper surface of the dummy gate electrode layer 303.

[0061] Next, as Figure 3IAs shown, the dummy gate electrode layer 303 is removed to form a gate trench in the fill layer 309. The dummy gate electrode layer 303 can be removed using either dry etching or wet etching processes. In one embodiment, a TMAH solution with high selectivity for the material of the dummy gate electrode layer 303 can be used to remove it. Because the modified process used in this embodiment better preserves the dummy gate dielectric layer 302 between the dummy gate electrode layer 303 and the epitaxial source / drain structure 308, avoiding lateral and longitudinal losses in the dummy gate dielectric layer 302, the etchant will not contact the epitaxial source / drain structure 308 at the point of loss in the dummy gate electrode layer 302 during the removal of the dummy gate electrode layer 303. This avoids damage to the epitaxial source / drain structure 308, thus preventing a short circuit between the source / drain and the gate.

[0062] Finally, a gate structure (not shown) is formed in the gate trench. Specifically, a metal material can be filled in the gate trench to form a metal gate. As an example, the metal material includes tungsten or aluminum. The metal gate may also include multiple stacked layers such as a work function layer and a barrier layer. The method for forming the metal gate includes depositing a metal material layer using a process such as atomic layer deposition, physical vapor deposition, or chemical vapor deposition, and then performing a planarization process, such as chemical mechanical polishing, to planarize the device surface until the filling layer 309 is exposed.

[0063] Thus, the process steps of the semiconductor device manufacturing method according to the first aspect embodiment of the present invention are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0064] The semiconductor device manufacturing method provided by the present invention modifies the sidewalls of the dummy gate structure, which can avoid lateral consumption of the dummy gate dielectric layer when forming source-drain grooves, better preserve the dummy gate dielectric layer between the source-drain epitaxial structure and the dummy gate electrode layer, and protect the epitaxial source-drain structure from damage when removing the dummy gate electrode layer.

[0065] This invention also provides a semiconductor device that can be prepared by the methods described in the foregoing embodiments.

[0066] Below, for reference Figure 3I The semiconductor device of the present invention will be described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing embodiments. For a detailed explanation and description, please refer to the description in Embodiment 1.

[0067] Specifically, such as Figure 3IAs shown, the semiconductor device of this embodiment includes: a semiconductor substrate 300, on which a fin structure 301 is formed; a filling layer 309 covering the fin structure, in which a gate recess spanning the fin structure 301 is formed, a dummy gate dielectric layer 302 and a second modification layer 302' above the dummy gate dielectric layer 302 are formed at the bottom of the gate recess, and a first modification layer 305 is formed on the sidewall of the gate recess; and epitaxial source / drain structures 308 in the fin structure 301 located on both sides of the gate recess.

[0068] The semiconductor device of this invention is prepared by the above method and thus has a complete epitaxial source-drain structure 308, and can avoid the short-circuit effect between the source / drain and the gate.

[0069] A third aspect of the present invention also provides an electronic device including the aforementioned semiconductor device, which is prepared according to the aforementioned method.

[0070] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned semiconductor devices, has better performance.

[0071] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A semiconductor substrate is provided, on which a fin structure is formed; A pseudo-gate dielectric layer and a pseudo-gate electrode layer are sequentially formed on the fin structure; The dummy gate electrode layer and the dummy gate dielectric layer are etched to form a dummy gate structure spanning the fin structure; A first modification process is performed on the pseudo-gate structure to form a first modification layer on the sidewalls of the pseudo-gate dielectric layer and the pseudo-gate electrode layer; A sidewall layer is formed on the outside of the first modified layer; The fin structures on both sides of the sidewall layer are etched to form source / drain grooves; An epitaxial source-drain structure is formed in the source-drain groove.

2. The manufacturing method as described in claim 1, characterized in that, The first modification process includes a nitriding process, and the first modified layer includes a first nitriding layer.

3. The manufacturing method as described in claim 1, characterized in that, The nitriding process includes a decoupled plasma nitriding process, and the first modification process further includes a post-nitriding annealing process performed after the decoupled plasma nitriding process.

4. The manufacturing method as described in claim 1, characterized in that, After forming the dummy gate dielectric layer and before forming the dummy gate electrode layer, the method further includes: A second modification process is performed on the dummy gate dielectric layer to form a second modified layer on the surface of the dummy gate dielectric layer.

5. The manufacturing method as described in claim 4, characterized in that, The second modification process includes a nitriding process, and the second modified layer includes a second nitrided layer.

6. The manufacturing method as described in claim 5, characterized in that, The nitriding process includes a decoupled plasma nitriding process, and the second modification process further includes a post-nitriding annealing process performed after the decoupled plasma nitriding process.

7. The manufacturing method as described in claim 1, characterized in that, After forming the epitaxial source-drain structure, the method further includes: A filler layer is formed between the sidewall layers, the filler layer exposing the upper surface of the dummy gate electrode layer; Remove the dummy gate electrode layer to form a gate recess in the fill layer; A gate structure is formed in the gate recess.

8. The manufacturing method as described in claim 7, characterized in that, The pseudo-gate structure further includes a pseudo-gate hard mask layer formed above the pseudo-gate electrode layer, and the first modified layer is also formed on the sidewall and upper surface of the pseudo-gate hard mask layer. The process of forming a fill layer between the sidewall layers, the fill layer exposing the upper surface of the dummy gate electrode layer, includes: A filling layer is formed to cover the pseudo-gate structure; A planarization process is used to remove the dummy gate hard mask layer and the filler layer formed above the dummy gate hard mask layer to expose the upper surface of the dummy gate electrode layer.

9. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device as described in claim 9.

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