A semiconductor device and a manufacturing method thereof
By forming an additional silicon layer during the semiconductor device manufacturing process for a second metal silicide treatment, the problem of high silicon substrate consumption is solved, achieving performance improvement and economical use of silicon substrates.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RUNPENG SEMICONDUCTOR (SHENZHEN) CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-06-16
AI Technical Summary
During the semiconductor device manufacturing process, the formation of metal silicides consumes a large amount of silicon substrate, resulting in waste of silicon substrate and limited performance improvement.
The consumption of silicon substrate is reduced by forming an additional silicon layer after the first metal silicide treatment and then performing a second metal silicide treatment. The specific steps include forming a first metal silicide layer, a silicon layer covering the sidewalls and the first metal silicide layer, performing a second metal silicide reaction, and removing the silicon layer on the sidewalls.
It effectively reduces the consumption of silicon substrates, improves the performance of semiconductor devices, and reduces the risk of leakage.
Smart Images
Figure CN122227607A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor devices, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] In the manufacturing process of semiconductor devices, metal silicides are typically formed in the gate, source, and drain regions to reduce contact resistance and improve the performance of semiconductor devices.
[0003] However, forming metal silicides in the gate, source, and drain regions requires the consumption of silicon substrate in these regions, resulting in a large amount of silicon substrate consumption.
[0004] Therefore, there is a current need to reduce the amount of silicon substrate consumed when forming metal silicides. Summary of the Invention
[0005] In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which can reduce the consumption of silicon substrate and improve the performance of the semiconductor device.
[0006] To achieve the above objectives, this application provides the following technical solution:
[0007] This application provides a method for manufacturing a semiconductor device, the method comprising:
[0008] A semiconductor structure is provided, the semiconductor structure including a silicon substrate and a gate structure located on one side of the silicon substrate, the gate structure including a gate and a sidewall located on the gate sidewall, the silicon substrate including a source region and a drain region, and the gate structure being disposed between the source region and the drain region;
[0009] The gate, the source region, and the drain region are subjected to metal silicide treatment to form a first metal silicide layer;
[0010] A silicon layer is formed, which covers the sidewall and the first metal silicide layer;
[0011] The silicon layer located on the first metal silicide layer is subjected to metal silicide treatment to form a second metal silicide layer;
[0012] Remove the silicon layer located on the sidewall.
[0013] Optionally, the second metal silicide layer disposed on the gate protrudes away from the substrate relative to the sidewall;
[0014] The second metal silicide layer disposed on the source region or the drain region protrudes relative to the surface of the substrate.
[0015] Optionally, the thickness of the second metal silicide layer is a preset thickness, and the thickness of the silicon layer is determined according to the preset thickness.
[0016] Optionally, the step of metallizing the silicon layer located on the first metal silicide layer to form the second metal silicide layer includes:
[0017] The silicon layer and the first metal silicide layer located on the first metal silicide layer are subjected to rapid thermal annealing to form a second metal silicide layer.
[0018] Optionally, the step of metallizing the gate, the source region, and the drain region to form a first metal silicide layer includes:
[0019] A metal layer is formed, the metal layer covering the gate structure, the source region and the drain region;
[0020] The metal layer, the gate, the source region, and the drain region are subjected to rapid thermal annealing to form a first metal silicide layer;
[0021] Remove the metal layer.
[0022] Optionally, the surface of the first metal silicide layer located in the region where the gate is located on the side away from the substrate and the surface of the sidewall on the side away from the substrate are flush.
[0023] The surface of the first metal silicide layer located in the source region or the drain region is flush with the surface of the substrate.
[0024] Optionally, the gate is made of polycrystalline silicon, and the sidewalls are made of at least silicon oxide.
[0025] This application provides a semiconductor device, the semiconductor device comprising:
[0026] A semiconductor structure, the semiconductor structure including a silicon substrate and a gate structure located on one side of the silicon substrate, the gate structure including a gate and a sidewall located on the gate sidewall, the silicon substrate including a source region and a drain region, and the gate structure disposed between the source region and the drain region;
[0027] A first metal silicide layer and a second metal silicide layer, wherein the second metal silicide layer is disposed on the side surface of the gate, the source region and the drain region away from the substrate; the first metal silicide layer is disposed between the second metal silicide layer and the gate, the source region and the drain region.
[0028] Optionally, the second metal silicide layer disposed on the gate protrudes away from the substrate relative to the sidewall;
[0029] The second metal silicide layer disposed on the source region or the drain region protrudes relative to the surface of the substrate.
[0030] Optionally, the surface of the first metal silicide layer located in the region where the gate is located on the side away from the substrate and the surface of the sidewall on the side away from the substrate are flush.
[0031] The surface of the first metal silicide layer located in the source region or the drain region is flush with the surface of the substrate.
[0032] This application provides a method for manufacturing a semiconductor device. The method includes: providing a semiconductor structure, the semiconductor structure including a silicon substrate and a gate structure located on one side of the silicon substrate, the gate structure including a gate and a sidewall located on the gate sidewall, the silicon substrate including a source region and a drain region, and the gate structure disposed between the source region and the drain region; performing metal silicide treatment on the gate, source region and drain region to form a first metal silicide layer, that is, performing a first metal silicide treatment to form a first metal silicide layer on the gate, source region and drain region; forming a silicon layer covering the sidewall and the first metal silicide layer, that is, forming an additional silicon layer, which can be used for subsequent metal silicide reactions, thereby reducing the consumption of silicon substrate; performing metal silicide treatment on the silicon layer located on the first metal silicide layer to form a second metal silicide layer, that is, using the silicon layer located on the first metal silicide layer for a second metal silicide reaction to achieve upward reaction and avoid downward reaction consuming silicon substrate; removing the silicon layer located on the sidewall to prevent the silicon layer from causing leakage current in the semiconductor device. In other words, this application forms an additional silicon layer after the first metal silicide treatment and performs a second metal silicide treatment. The second metal silicide treatment can reduce the consumption of silicon substrate. That is, the additional silicon layer can reduce the amount of silicon substrate consumed and improve the performance of semiconductor devices. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown;
[0035] Figures 2-8 A schematic diagram of the structure of a semiconductor device manufactured according to the manufacturing method of the semiconductor device provided in the embodiments of this application is shown.
[0036] The structure includes a silicon substrate 110, a gate 121, a sidewall 122, a gate dielectric layer 123, a source region 111, a drain region 112, a first metal silicide layer 210, a metal layer 310, a silicon layer 410, and a second metal silicide layer 220. Detailed Implementation
[0037] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0038] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0039] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.
[0040] In the manufacturing process of semiconductor devices, metal silicides are typically formed in the gate, source, and drain regions to reduce contact resistance and improve the performance of semiconductor devices.
[0041] However, forming metal silicides in the gate, source, and drain regions requires first forming a metal layer, followed by two rapid thermal annealing processes, which consumes silicon substrate in these regions, resulting in a large amount of silicon substrate consumed.
[0042] As the size of semiconductor devices gradually shrinks, the requirements for silicon substrate consumption in ultra-shallow junctions (USJs) are becoming increasingly stringent, thus necessitating efforts to minimize silicon substrate consumption.
[0043] Therefore, there is a current need to reduce the amount of silicon substrate consumed when forming metal silicides.
[0044] Based on the above technical problems, embodiments of this application provide a method for manufacturing a semiconductor device. The method includes: providing a semiconductor structure, the semiconductor structure including a silicon substrate and a gate structure located on one side of the silicon substrate, the gate structure including a gate and a sidewall located on the sidewall of the gate, the silicon substrate including a source region and a drain region, and a gate structure disposed between the source region and the drain region; performing metal silicide treatment on the gate, source region and drain region to form a first metal silicide layer, that is, performing a first metal silicide treatment to form a first metal silicide layer on the gate, source region and drain region; forming a silicon layer covering the sidewall and the first metal silicide layer, that is, forming an additional silicon layer, which can be used for subsequent metal silicide reactions, thereby reducing the consumption of silicon substrate; performing metal silicide treatment on the silicon layer located on the first metal silicide layer to form a second metal silicide layer, that is, using the silicon layer located on the first metal silicide layer for a second metal silicide reaction to achieve upward reaction and avoid downward reaction consuming silicon substrate; removing the silicon layer located on the sidewall to prevent the silicon layer from causing leakage current in the semiconductor device. In other words, this application forms an additional silicon layer after the first metal silicide treatment and performs a second metal silicide treatment. The second metal silicide treatment can reduce the consumption of silicon substrate. That is, the additional silicon layer can reduce the amount of silicon substrate consumed and improve the performance of semiconductor devices.
[0045] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.
[0046] refer to Figure 1 The diagram shown is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application. The method includes the following steps:
[0047] S101 provides a semiconductor structure, the semiconductor structure including a silicon substrate and a gate structure located on one side of the silicon substrate, the gate structure including a gate and a sidewall located on the gate sidewall, the substrate including a source region and a drain region, and the gate structure disposed between the source region and the drain region.
[0048] In embodiments of this application, a semiconductor structure can be provided, and a semiconductor device can be fabricated based on the semiconductor structure. The semiconductor structure includes a silicon substrate 110 and a gate structure located on one side of the silicon substrate 110, as shown in the reference. Figure 2 As shown.
[0049] The silicon substrate 110 is made of at least silicon. The gate structure includes a gate 121, a sidewall 122, and a gate dielectric layer 123. The sidewall 122 is disposed on the sidewall of the gate 121, and the gate dielectric layer 123 is disposed between the gate 121 and the silicon substrate 110. The gate 121 is made of polycrystalline silicon, and the gate dielectric layer 123 is made of an insulating material, such as silicon oxide. The sidewall 122 can be composed of an independent film layer or multiple film layers. When the sidewall 122 is an independent film layer, the sidewall 122 can be made of an insulating material, such as silicon oxide. When the sidewall 122 is composed of multiple film layers, the sidewall 122 can be a stacked structure, such as silicon oxide, silicon nitride, and silicon oxide stacked sequentially, with the stacking direction of the stacked structure perpendicular to the sidewall direction of the gate 121.
[0050] The silicon substrate 110 includes a source region 111 and a drain region 112. A gate structure is disposed between the source region 111 and the drain region 112 in a direction parallel to the surface of the silicon substrate 110; that is, the source region 111 and the drain region 112 are disposed on both sides of the gate structure. The source region 111 and the drain region 112 can be formed by ion implantation of the silicon substrate 110.
[0051] S102, metal silicide treatment is performed on the gate, source and drain regions to form a first metal silicide layer.
[0052] In embodiments of this application, the gate 121, source region 111, and drain region 112 can be metallized to form a first metal silicide layer 210, as shown in the reference. Figure 5 As shown. Metal silicide treatment involves reacting metal and silicon to form a metal silicide. In other words, the first metal silicide layer 210 is formed after metal silicide treatment of the gate 121, source region 111, and drain region 112.
[0053] As one possible implementation, a metal layer 310 is first formed on the semiconductor structure, which covers the gate structure, source region 111, and drain region 112, as shown in the reference. Figure 3 As shown. This metal layer 310 can provide the metal material for the subsequent formation of the first metal silicide layer 210.
[0054] Rapid thermal annealing is performed on metal layer 310, gate 121, source region 111, and drain region 112 to form a first metal silicide layer 210, as shown in the reference. Figure 4As shown, the rapid thermal annealing of the metal layer 310, gate 121, source region 111, and drain region 112 enables metal atoms in the metal layer 310 to enter the gate 121, source region 111, and drain region 112, and combine with silicon atoms in the gate 121, source region 111, and drain region 112 to form the first metal silicide layer 210. The rapid thermal annealing of the metal layer 310, gate 121, source region 111, and drain region 112 enables the simple, rapid, and efficient formation of the first metal silicide layer 210 and reduces lattice defects.
[0055] After the first metal silicide layer 210 is formed on the gate 121, source region 111, and drain region 112, the metal layer 310 can be removed to prevent leakage. (Refer to...) Figure 5 As shown.
[0056] In the embodiments of this application, since the first metal silicide layer 210 is obtained by reacting silicon atoms of the gate 121, source region 111 and drain region 112 with metal atoms in the metal layer 310, the first metal silicide layer 210 is located in the region where the gate 121 is located, the region where the source region 111 is located and the region where the drain region 112 is located.
[0057] Specifically, the surface of the first metal silicide layer 210 in the region where the gate 121 is located is flush with the surface of the sidewall 122 in the region where the sidewall 122 is located. The surface of the first metal silicide layer 210 in the region where the source region 111 or the drain region 112 is located is flush with the surface of the substrate 110. That is, the first metal silicide layer 210 in the region where the gate 121 is located has no protrusion relative to the surface of the sidewall 122, and the first metal silicide layer 210 in the region where the source region 111 or the drain region 112 is located has no protrusion relative to the surface of the silicon substrate 110. In other words, the first metal silicide layer 210 is formed in the gate 121 and the silicon substrate 110, which consumes the silicon material in the gate 121 and the silicon substrate 110 to form a first metal silicide layer 210 with better conductivity in the gate 121 and the silicon substrate 110, which facilitates subsequent electrical connection.
[0058] S103, a silicon layer is formed, which covers the sidewalls and the first metal silicide layer.
[0059] In embodiments of this application, considering the need to reduce the consumption of silicon substrate 110, a silicon layer 410 can be formed, as referenced. Figure 6 As shown, the silicon layer 410 covers the semiconductor structure, that is, the silicon layer 410 covers the sidewall 122 and the first metal silicide layer 210. The silicon layer 410 can be used for metal silicide reaction, thereby reducing the consumption of silicon substrate 110.
[0060] Specifically, a silicon layer 410 can be formed using a deposition process.
[0061] S104, the silicon layer located on the first metal silicide layer is subjected to metal silicide treatment to form a second metal silicide layer.
[0062] In the embodiments of this application, after forming the silicon layer 410 covering the semiconductor structure, the silicon layer 410 is additionally provided with silicon material. At this time, there is additional silicon material on the surface of the first metal silicide layer 210. The silicon layer 410 located on the first metal silicide layer 210 can be metallized to form the second metal silicide layer 220. (Refer to...) Figure 7 As shown. That is, the second metal silicide reaction is performed using the silicon layer 410 located on the first metal silicide layer 210, achieving an upward reaction and avoiding the downward reaction from consuming the silicon substrate 110. The second metal silicide treatment can reduce the consumption of the silicon substrate 110, that is, the additional silicon layer 410 can reduce the consumption of the silicon substrate 110 and improve the performance of the semiconductor device.
[0063] As one possible implementation, after forming the silicon layer 410, the silicon layer 410 and the first metal silicide layer 210 located on the first metal silicide layer 210 are subjected to rapid thermal annealing to form the second metal silicide layer 220. That is, the silicon layer 410 and the first metal silicide layer 210 are rapidly thermally annealed, which allows metal atoms in the first metal silicide layer 210 to enter the silicon layer 410 and combine with the silicon atoms in the silicon layer 410 to form the second metal silicide layer 220. Rapid thermal annealing of the silicon layer 410 and the first metal silicide layer 210 can achieve simple, rapid and efficient formation of the second metal silicide layer 220 and reduce lattice defects.
[0064] In the embodiments of this application, the second metal silicide layer 220 disposed on the gate 121 protrudes away from the substrate 110 relative to the sidewall 122, and the second metal silicide layer 220 disposed on the source region 111 or drain region 112 protrudes relative to the surface of the substrate 110. That is, since the silicon layer 410 is disposed on the surface of the gate 121 and the surface of the source region 111 or drain region 112, the second metal silicide layer 220 formed is also disposed on the surface of the gate 121 and the surface of the source region 111 or drain region 112. At this time, the second metal silicide layer 220 protrudes relative to the surface of the sidewall 122 and the surface of the substrate 110, thereby achieving the formation of the second metal silicide layer 220 by consuming the silicon layer 410, minimizing the silicon consumption of the silicon substrate 110 or the gate 121.
[0065] In the embodiments of this application, the thickness of the second metal silicide layer 220 is a preset thickness, and the thickness of the silicon layer 410 is determined according to the preset thickness. That is, when forming the second metal silicide layer 220, the silicon layer 410 located in the region where the gate 121 is located, the region where the source region 111 is located, or the region where the drain region 112 is located needs to be completely consumed. Therefore, the thickness of the silicon layer 410 can be determined according to the preset thickness of the second metal silicide layer 220, which can both avoid the silicon layer 410 not being completely consumed and provide enough silicon layer 410 to form the second metal silicide layer 220, further reducing the silicon consumption of the silicon substrate 110.
[0066] S105, Remove the silicon layer located on the sidewall.
[0067] In embodiments of this application, after the second metal silicide layer 220 is formed, the silicon layer 410 located on the sidewall 122 can be removed, see reference. Figure 8 As shown, this is to prevent leakage of silicon layer 410.
[0068] Specifically, the silicon layer 410 can be removed using an etching process.
[0069] Therefore, this application forms an additional silicon layer after the first metal silicide treatment and performs a second metal silicide treatment. The second metal silicide treatment can reduce the consumption of the silicon substrate. That is, the additional silicon layer can reduce the consumption of the silicon substrate and avoid the consumption of the silicon substrate in both metal silicide treatments, thereby improving the performance of the semiconductor device.
[0070] Based on the semiconductor device manufacturing method provided in the above embodiments, this application also provides a semiconductor device, see reference. Figure 8 The diagram shown is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. The semiconductor device includes: a semiconductor structure, a first metal silicide layer 210, and a second metal silicide layer 220.
[0071] The semiconductor structure includes a silicon substrate 110 and a gate structure located on one side of the silicon substrate 110.
[0072] The silicon substrate 110 is made of at least silicon. The gate structure includes a gate 121, a sidewall 122, and a gate dielectric layer 123. The sidewall 122 is disposed on the sidewall of the gate 121, and the gate dielectric layer 123 is disposed between the gate 121 and the silicon substrate 110. The gate 121 is made of polycrystalline silicon, and the gate dielectric layer 123 is made of an insulating material, such as silicon oxide. The sidewall 122 can be composed of an independent film layer or multiple film layers. When the sidewall 122 is an independent film layer, the sidewall 122 can be made of an insulating material, such as silicon oxide. When the sidewall 122 is composed of multiple film layers, the sidewall 122 can be a stacked structure, such as silicon oxide, silicon nitride, and silicon oxide stacked sequentially, with the stacking direction of the stacked structure perpendicular to the sidewall direction of the gate 121.
[0073] The silicon substrate 110 includes a source region 111 and a drain region 112. A gate structure is disposed between the source region 111 and the drain region 112 in a direction parallel to the surface of the silicon substrate 110; that is, the source region 111 and the drain region 112 are disposed on both sides of the gate structure. The source region 111 and the drain region 112 can be formed by ion implantation of the silicon substrate 110.
[0074] The second metal silicide layer 220 is disposed on the side surface of the gate 121, source region 111, and drain region 112 away from the substrate 110; the first metal silicide layer 210 is disposed between the second metal silicide layer 220 and the gate 121, source region 111, and drain region 112. That is, the second metal silicide layer 220 is disposed on the surface of the first metal silicide layer 210.
[0075] In the embodiments of this application, the second metal silicide layer 220 disposed on the gate 121 protrudes away from the substrate 110 relative to the sidewall 122, and the second metal silicide layer 220 disposed on the source region 111 or drain region 112 protrudes relative to the surface of the substrate 110. That is, since the silicon layer 410 is disposed on the surface of the gate 121 and the surface of the source region 111 or drain region 112, the second metal silicide layer 220 formed is also disposed on the surface of the gate 121 and the surface of the source region 111 or drain region 112. At this time, the second metal silicide layer 220 protrudes relative to the surface of the sidewall 122 and the surface of the substrate 110, thereby achieving the formation of the second metal silicide layer 220 by consuming the silicon layer 410, minimizing the silicon consumption of the silicon substrate 110 or the gate 121.
[0076] In the embodiments of this application, the thickness of the second metal silicide layer 220 is a preset thickness, and the thickness of the silicon layer 410 is determined according to the preset thickness. That is, when forming the second metal silicide layer 220, the silicon layer 410 located in the region where the gate 121 is located, the region where the source region 111 is located, or the region where the drain region 112 is located needs to be completely consumed. Therefore, the thickness of the silicon layer 410 can be determined according to the preset thickness of the second metal silicide layer 220, which can both avoid the silicon layer 410 not being completely consumed and provide enough silicon layer 410 to form the second metal silicide layer 220, further reducing the silicon consumption of the silicon substrate 110.
[0077] In the embodiments of this application, the surface of the first metal silicide layer 210 located in the region of the gate 121 that is away from the substrate 110 is flush with the surface of the sidewall 122 that is away from the substrate 110. The surface of the first metal silicide layer 210 located in the region of the source region 111 or the drain region 112 is flush with the surface of the substrate 110. That is, the first metal silicide layer 210 located in the region of the gate 121 has no protrusion relative to the surface of the sidewall 122, and the first metal silicide layer 210 located in the region of the source region 111 or the drain region 112 has no protrusion relative to the surface of the silicon substrate 110. In other words, the first metal silicide layer 210 is formed in the gate 121 and the silicon substrate 110, and consumes the silicon material in the gate 121 and the silicon substrate 110.
[0078] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, structural embodiments are generally similar to method embodiments and are therefore described simply; relevant details can be found in the descriptions of the method embodiments.
[0079] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor structure is provided, the semiconductor structure including a silicon substrate and a gate structure located on one side of the silicon substrate, the gate structure including a gate and a sidewall located on the gate sidewall, the silicon substrate including a source region and a drain region, and the gate structure being disposed between the source region and the drain region; The gate, the source region, and the drain region are subjected to metal silicide treatment to form a first metal silicide layer; A silicon layer is formed, which covers the sidewall and the first metal silicide layer; The silicon layer located on the first metal silicide layer is subjected to metal silicide treatment to form a second metal silicide layer; Remove the silicon layer located on the sidewall.
2. The manufacturing method according to claim 1, characterized in that, The second metal silicide layer disposed on the gate protrudes away from the substrate relative to the sidewall; The second metal silicide layer disposed on the source region or the drain region protrudes relative to the surface of the substrate.
3. The manufacturing method according to claim 1, characterized in that, The thickness of the second metal silicide layer is a preset thickness, and the thickness of the silicon layer is determined according to the preset thickness.
4. The manufacturing method according to claim 1, characterized in that, The step of metal silicide treatment on the silicon layer located on the first metal silicide layer to form the second metal silicide layer includes: The silicon layer and the first metal silicide layer located on the first metal silicide layer are subjected to rapid thermal annealing to form a second metal silicide layer.
5. The manufacturing method according to claim 1, characterized in that, The step of performing metal silicide treatment on the gate, the source region, and the drain region to form a first metal silicide layer includes: A metal layer is formed, the metal layer covering the gate structure, the source region and the drain region; The metal layer, the gate, the source region, and the drain region are subjected to rapid thermal annealing to form a first metal silicide layer; Remove the metal layer.
6. The manufacturing method according to claim 5, characterized in that, The surface of the first metal silicide layer located in the region where the gate is located is flush with the surface of the sidewall located in the region away from the substrate. The surface of the first metal silicide layer located in the source region or the drain region is flush with the surface of the substrate.
7. The manufacturing method according to claim 1, characterized in that, The gate is made of polycrystalline silicon, and the sidewalls are made of at least silicon oxide.
8. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor structure, the semiconductor structure including a silicon substrate and a gate structure located on one side of the silicon substrate, the gate structure including a gate and a sidewall located on the gate sidewall, the silicon substrate including a source region and a drain region, and the gate structure disposed between the source region and the drain region; A first metal silicide layer and a second metal silicide layer, wherein the second metal silicide layer is disposed on the side surface of the gate, the source region and the drain region away from the substrate; the first metal silicide layer is disposed between the second metal silicide layer and the gate, the source region and the drain region.
9. The semiconductor device according to claim 8, characterized in that, The second metal silicide layer disposed on the gate protrudes away from the substrate relative to the sidewall; The second metal silicide layer disposed on the source region or the drain region protrudes relative to the surface of the substrate.
10. The semiconductor device according to claim 8, characterized in that, The surface of the first metal silicide layer located in the region where the gate is located is flush with the surface of the sidewall located in the region away from the substrate. The surface of the first metal silicide layer located in the source region or the drain region is flush with the surface of the substrate.