A ring gate nanosheet transistor and a method of fabricating the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2026-05-19
- Publication Date
- 2026-06-16
Smart Images
Figure CN122227615A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a gate ring nanosheet transistor and its fabrication method. Background Technology
[0002] As semiconductor feature sizes have entered the 3nm and below node, gate-all-around (GAA) nanosheet transistors have become the mainstream architecture.
[0003] In the fabrication of gate-all-around nanosheet transistors (GAAFETs), the formation of the source and drain regions relies on high-quality epitaxial growth. In conventional process flows, during the etching of the fin stacks, all sacrificial layers (SiGe layers) are typically completely removed, and source and drain epitaxy is performed on the nanosheet end faces of the silicon substrate and sidewalls. This creates parasitic channels between the fin stack and the silicon substrate. Consequently, current bypasses the gate-controlled nanosheet channels and flows directly through the substrate, leading to increased turn-off current, deteriorated subthreshold swing, and negatively impacting device performance.
[0004] To address these issues, the current mainstream approach is to use an insulating layer to isolate the silicon substrate in the source and drain regions. However, the lack of an effective lattice-matching seed layer after isolation easily leads to dislocations and growth defects in the epitaxial layer, resulting in unstable epitaxial quality and affecting device quality. Summary of the Invention
[0005] The purpose of this invention is to provide a gate-around nanosheet transistor and its fabrication method, in order to solve the problem of how to improve the device performance and quality of gate-around nanosheet transistors.
[0006] To solve the above-mentioned technical problems, the present invention provides a method for fabricating a gate-ring nanosheet transistor, comprising: Provide substrate; A first silicon-germanium layer is formed on the substrate; Multiple layers of second silicon-germanium layers and silicon layers are alternately formed from bottom to top on the first silicon-germanium layer to obtain a fin stacked structure; A gate structure is formed, which covers the top and sidewalls of a portion of the fin stack structure; Selective etching removes at least a portion of the first silicon-germanium layer; A first insulating layer is formed, which fills the voids created by selective etching. The silicon layer and the second silicon-germanium layer of the fin stack structure are etched sequentially, while the bottommost second silicon-germanium layer is retained as the epitaxial crystal seed layer. Laterally etch the second silicon-germanium layer to expose the gaps between the silicon layers as an inner isolation layer; A second insulating layer is formed, which fills the gaps created by the lateral etching. Epitaxial growth of source and drain electrodes.
[0007] Optionally, in the method for fabricating the ring-gate nanosheet transistor, the atomic ratio of silicon to germanium in the first silicon-germanium layer is different from that in the second silicon-germanium layer.
[0008] Optionally, in the method for fabricating the ring-gate nanosheet transistor, the atomic ratio of silicon to germanium in the first silicon-germanium layer is 0.6:0.4~0.5:0.5; and the atomic ratio of silicon to germanium in the second silicon-germanium layer is 0.7:0.3~0.8:0.2.
[0009] Optionally, in the method for fabricating the gate-around nanosheet transistor, the method for forming a first silicon-germanium layer on the substrate includes: A third silicon-germanium layer is formed on the substrate, wherein the atomic ratio of silicon to germanium in the third silicon-germanium layer is the same as or similar to the atomic ratio of silicon to germanium in the second silicon-germanium layer; The first silicon-germanium layer is formed on the third silicon-germanium layer.
[0010] Optionally, in the fabrication method of the ring-gate nanosheet transistor, the thickness of the first silicon-germanium layer is 5nm~8nm.
[0011] Optionally, in the fabrication method of the ring-gate nanosheet transistor, the material of the first insulating layer is Si3N4, SiOC, SiON, SiCN or SiBCN.
[0012] Optionally, in the method for fabricating the ring-gate nanosheet transistor, the method for forming the first insulating layer includes: A first insulating capping layer is formed on the surface of the fin stack structure, the gate structure surface, and the substrate surface using an atomic layer deposition process; By using reactive ion etching and adjusting the ratio of transverse to longitudinal etching rates, the first insulating capping layer is etched back to form the top and sidewall window morphology, thus obtaining the first insulating layer.
[0013] Optionally, in the fabrication method of the ring-gate nanosheet transistor, the material of the second insulating layer is Si3N4, SiOC, SiON, SiCN or SiBCN.
[0014] Optionally, in the method for fabricating the ring-gate nanosheet transistor, the method for forming the second insulating layer includes: A second insulating capping layer is formed on the surface of the fin stack structure, the gate structure surface, and the substrate surface using an atomic layer deposition process; By using reactive ion etching and adjusting the cross-sectional and longitudinal etching rate ratio, the second insulating capping layer is etched back, leaving only the second insulating capping layer between the inner isolation layers to obtain the second insulating layer.
[0015] To address the aforementioned technical problems, the present invention also provides a gate-around nanosheet transistor, manufactured using the method for fabricating a gate-around nanosheet transistor as described in any of the preceding claims. The gate-around nanosheet transistor includes a substrate and a fin stack structure; a gate structure covers a portion of the top and sidewalls of the fin stack structure; the fin stack structure covered by the gate structure includes alternating layers of second silicon-germanium layers and silicon layers arranged from bottom to top; a first silicon-germanium layer is disposed between the bottom of the fin stack structure covered by the gate structure and the substrate, or a first silicon-germanium layer and a first insulating layer located on the same layer are disposed between the bottom of the fin stack structure covered by the gate structure and the substrate, or a first insulating layer is disposed between the bottom of the fin stack structure covered by the gate structure and the substrate; the exposed fin stack structure includes a second silicon-germanium layer and alternating layers of second insulating layers and silicon layers arranged from bottom to top; a first insulating layer is disposed between the bottom of the exposed fin stack structure and the substrate; an source electrode and a drain electrode are epitaxially grown at the exposed fin stack structure.
[0016] The present invention provides a gate-ring nanosheet transistor and a method for fabricating the same, comprising: providing a substrate; forming a first silicon-germanium layer on the substrate; forming multiple alternating layers of a second silicon-germanium layer and a silicon layer on the first silicon-germanium layer from bottom to top to obtain a fin stack structure; forming a gate structure, the gate structure covering the top and sidewalls of a portion of the fin stack structure; selectively etching away at least a portion of the first silicon-germanium layer; forming a first insulating layer, the first insulating layer filling the gaps generated by the selective etching; sequentially etching the silicon layer and the second silicon-germanium layer of the fin stack structure, retaining the bottommost second silicon-germanium layer as an epitaxial seed layer; laterally etching the second silicon-germanium layer to expose the gaps between a portion of the silicon layers as an inner isolation layer; forming a second insulating layer, the second insulating layer filling the gaps generated by the lateral etching; and epitaxially growing a source and a drain. By first forming a first silicon-germanium layer between the substrate and the fin stack structure, and then selectively etching away the first silicon-germanium layer before filling with a first insulating layer, the fin stack structure is isolated from the substrate. At the same time, since the bottom second silicon-germanium layer is retained as the epitaxial crystal seed layer, the growth quality of the source and drain electrodes of the epitaxial growth is improved. Moreover, the second insulating layer can be used to construct a multilayer composite isolation structure, which improves the device structure stability, ensures the device electrical performance, and solves the problem of how to improve the device performance and quality of the gate-around nanosheet transistor. Attached Figure Description
[0017] Figure 1 A flowchart illustrating the fabrication method of the gate-around nanosheet transistor provided in this embodiment. Figures 2(A) to 2(L) are schematic diagrams of the device structure corresponding to each step in the fabrication method of the gate ring nanosheet transistor provided in this embodiment; Figure 3This is a schematic diagram of the device structure of the first type of gate ring nanosheet transistor provided in this embodiment; Figure 4 This is a schematic diagram of the device structure of the second type of ring-gate nanosheet transistor provided in this embodiment; Figure 5 This is a schematic diagram of the device structure of the third type of ring-gate nanosheet transistor provided in this embodiment; The labels in the attached figures are explained as follows: 100 - Substrate; 110 - First silicon-germanium layer; 111 - Third silicon-germanium layer; 120 - Fin stacked structure; 121 - Second silicon-germanium layer; 122 - Silicon layer; 130 - Gate structure; 140 - First insulating layer; 150 - Second insulating layer; 161 - Source; 162 - Drain. Detailed Implementation
[0018] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the proposed gate-ring nanosheet transistor and its fabrication method. It should be noted that the drawings are all in a very simplified form and use non-precise scales, intended only to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.
[0019] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0020] This embodiment provides a method for fabricating a gate-around nanosheet transistor, such as... Figure 1 As shown, it includes: S1 provides the substrate; S2, a first silicon-germanium layer is formed on the substrate; S3, a second silicon-germanium layer and a silicon layer are alternately formed on the first silicon-germanium layer from bottom to top to obtain a fin stacked structure; S4, forming a gate structure that covers the top and sidewalls of a portion of the fin stack structure; S5, selectively etch away at least a portion of the first silicon-germanium layer; S6, forming a first insulating layer, the first insulating layer filling the voids created by selective etching; S7, sequentially etch the silicon layer and the second silicon-germanium layer of the fin stack structure, and retain the bottommost second silicon-germanium layer as the epitaxial crystal seed layer; S8, laterally etch the second silicon-germanium layer to expose the gap between the silicon layers as an inner isolation layer; S9, forming a second insulating layer, the second insulating layer filling the gaps created by the lateral etching; S10, epitaxial growth of the source and drain.
[0021] The method for fabricating a gate-around nanosheet transistor provided in this embodiment first forms a first silicon-germanium layer between the substrate and the fin stack structure, then selectively etches away the first silicon-germanium layer and fills it with a first insulating layer, thereby isolating the fin stack structure from the substrate. At the same time, since the bottom second silicon-germanium layer is retained as an epitaxial crystal seed layer, the growth quality of the epitaxial source and drain is improved. Moreover, the second insulating layer can be used to construct a multilayer composite isolation structure, which improves the device structure stability, ensures the device electrical performance, and solves the problem of how to improve the device performance and quality of the gate-around nanosheet transistor.
[0022] Specifically, in this embodiment, step S1, as shown in FIG2(A), involves providing a substrate 100.
[0023] In practical applications, the substrate 100 can be a silicon substrate, and the substrate 100 may also have other device structures, such as metal interconnect layers, which will not be elaborated in this application.
[0024] Furthermore, in this embodiment, step S2, as shown in FIG2(B), involves forming a first silicon-germanium layer 110 on the substrate 100.
[0025] Specifically, in this embodiment, the first silicon-germanium layer 110 is a high-concentration germanium silicon-germanium layer. In practical applications, the atomic ratio of silicon to germanium in the first silicon-germanium layer 110 can be 0.6:0.4 to 0.5:0.5. Furthermore, in practical applications, the thickness of the first silicon-germanium layer 110 is 5 nm to 8 nm.
[0026] In other embodiments, as shown in FIG2(C), before forming the first silicon-germanium layer 110, the fabrication method further includes: firstly, forming a third silicon-germanium layer 111 on the substrate 100; and then forming the first silicon-germanium layer 110 on the third silicon-germanium layer 111. In practical applications, the third silicon-germanium layer 111 can be a silicon-germanium layer with a low concentration of germanium, for example, the atomic ratio of silicon to germanium in the third silicon-germanium layer 111 is 0.7:0.3 to 0.8:0.2. Of course, in other embodiments, the third silicon-germanium layer 111 can also be a stack of multiple silicon-germanium layers with different silicon-germanium atomic ratios, and this application does not limit this.
[0027] Furthermore, in this embodiment, step S3, as shown in FIG2(D), involves forming multiple alternating layers of a second silicon-germanium layer 121 and a silicon layer 122 on the first silicon-germanium layer 110 from bottom to top to obtain a fin stack structure 120. FIG2(D) shows a schematic diagram of the device structure along the length direction on the left and a cross-sectional view of the device structure along the width direction on the right.
[0028] The specific formation method of the fin stack structure 120 is something that those skilled in the art can obtain in the existing manufacturing methods of ring gate nanosheet transistors, and this application will not elaborate on it further.
[0029] It should be noted that, in this embodiment, the atomic ratio of silicon to germanium in the second silicon-germanium layer 121 is different from that in the first silicon-germanium layer 110. This facilitates the subsequent selective etching process in completely removing the first silicon-germanium layer 110 while preserving the complete second silicon-germanium layer 121. In practical applications, when the first silicon-germanium layer 110 is a high-concentration germanium layer, for example, with a silicon to germanium atomic ratio of 0.6:0.4 to 0.5:0.5, the second silicon-germanium layer 121 is a low-concentration germanium layer, for example, with a silicon to germanium atomic ratio of 0.7:0.3 to 0.8:0.2.
[0030] Furthermore, in this embodiment, the thickness of the multilayer second silicon-germanium layer 121 is consistent, for example, 8nm~10nm, specifically 10nm; the thickness of the multilayer silicon layer 122 is consistent, for example, 4nm~6nm, specifically 5nm.
[0031] In practical applications, when a third silicon-germanium layer 111 is formed, the atomic ratio of silicon to germanium in the second silicon-germanium layer 121 can be the same as or similar to that in the third silicon-germanium layer 111. When the atomic ratio of silicon to germanium in the second silicon-germanium layer 121 is the same as that in the third silicon-germanium layer 111, the second silicon-germanium layer 121 can be formed using the process of the third silicon-germanium layer 111, thereby reducing the process complexity.
[0032] Furthermore, in this embodiment, step S4, as shown in FIG2(E), forms a gate structure 130, which covers the top and sidewalls of a portion of the fin stack structure 120. FIG2(E) shows a schematic diagram of the device structure along the length direction on the left and a cross-sectional view of the device structure along the width direction on the right.
[0033] In practical applications, the surface of the gate structure 130 is covered by a dielectric layer, which can be silicon nitride. Furthermore, the specific formation method of the gate structure 130 is something that those skilled in the art can obtain using existing methods for manufacturing gate-to-ring nanosheet transistors, and will not be elaborated upon here.
[0034] Furthermore, in this embodiment, step S5 involves selectively etching away at least a portion of the first silicon-germanium layer 110.
[0035] Specifically, in this embodiment, as shown in FIG2(F), the first silicon-germanium layer 110 at the bottom of the fin stack structure 120 not covered by the gate structure 130 can be removed, while the first silicon-germanium layer 110 at the bottom of the fin stack structure 120 covered by the gate structure 130 is retained. FIG2(F) shows a schematic diagram of the device structure along the length direction on the left, with the first silicon-germanium layer 110 indicated by the dashed line being the first silicon-germanium layer 110 located at the bottom of the fin stack structure 120 covered by the gate structure 130. The right side shows a cross-sectional view of the device structure along the width direction.
[0036] In another embodiment, as shown in FIG2(G), the first silicon-germanium layer 110 at the bottom of the fin stack structure 120 can be completely removed. FIG2(G) shows a schematic diagram of the device structure along its length on the left and a cross-sectional view of the device structure along its width on the right.
[0037] Of course, in other embodiments, while removing the first silicon-germanium layer 110 at the bottom of the fin stack structure 120 not covered by the gate structure 130, etching can be performed inwards to remove a portion of the first silicon-germanium layer 110 at the bottom of the fin stack structure 120 covered by the gate structure 130. In other words, in practical applications, it is only necessary to ensure that at least the first silicon-germanium layer 110 at the bottom of the fin stack structure 120 not covered by the gate structure 130 is completely removed. Whether the first silicon-germanium layer 110 is completely removed can be reasonably set according to the process precision, thereby reducing the difficulty of process implementation.
[0038] Specifically, in practical applications, wet etching or dry etching can be used to selectively etch the first silicon-germanium layer 110 with the lowest concentration of germanium, thereby preserving the second silicon-germanium layer 121 with a low concentration of germanium.
[0039] In the following steps, only the device structure shown in FIG2(F), which retains the first silicon-germanium layer 110 at the bottom of the fin stack structure 120 covered by the gate structure 130, is used as an example to illustrate the specific implementation process of the fabrication method of the gate-ring nanosheet transistor provided in this application. Those skilled in the art can understand the specific implementation process of the fabrication method after completely removing the first silicon-germanium layer 110 based on this embodiment, and this application will not elaborate on it further.
[0040] Furthermore, in this embodiment, step S6, as shown in FIG2(H), forms a first insulating layer 140, which fills the gaps generated by selective etching. FIG2(H) shows a schematic diagram of the device structure along the length direction on the left and a cross-sectional view of the device structure along the width direction on the right.
[0041] Specifically, in this embodiment, the material of the first insulating layer 140 can be insulating materials such as Si3N4, SiOC, SiON, SiCN or SiBCN.
[0042] In this embodiment, the method for forming the first insulating layer 140 includes: First, forming a first insulating capping layer on the surface of the fin stack structure 120, the surface of the gate structure 130, and the surface of the substrate 100 using atomic layer deposition (ALD). The first insulating capping layer can simultaneously fill the voids formed by selective etching. In practical applications, the thickness of the first insulating capping layer can be 4-5 nm. Then, using reactive ion etching (RIE), the horizontal and vertical etching rate ratio is adjusted to etch back the first insulating capping layer, forming a top and sidewall window morphology to obtain the first insulating layer 140. At this time, the first insulating layer 140 is located at the voids exposed by selective etching and at the corner interfaces of the various structural materials. That is, the first insulating layer 140 is located in the area where the original first silicon-germanium layer 110 was located, as well as at the junctions of the fin stack structure 120 and the substrate 100, the junctions of the fin stack structure 120 and the gate structure 130, and the junctions of the gate structure 130 and the substrate 100 (the first insulating layer 140 at the junctions is not shown in Figure 2(H)).
[0043] Furthermore, in this embodiment, in step S7, as shown in FIG2(I), the silicon layer 122 and the second silicon-germanium layer 121 of the fin stack structure 120 are etched sequentially, and the bottommost second silicon-germanium layer 121 is retained as the epitaxial crystal seed layer. FIG2(I) shows a schematic diagram of the device structure along the length direction on the left, where the dashed line represents the fin stack structure 120 covered by the gate structure 130 and the first insulating layer 140. The right side shows a cross-sectional view of the device structure along the width direction.
[0044] The specific method of sequentially etching the fin stack structure 120 is something that those skilled in the art can obtain in the existing manufacturing methods of ring gate nanosheet transistors, and will not be described in detail here.
[0045] It should be noted that, since the first insulating layer 140 is still located at the junction of the fin stack structure 120 and the gate structure 130 in step S6, the fin stack structure 120 under the first insulating layer 140 will be retained when the fin stack structure 120 is etched sequentially.
[0046] Furthermore, in this embodiment, step S8, as shown in FIG2(J), involves laterally etching the second silicon-germanium layer 121 to expose the gaps between the silicon layers 122 as an inner isolation layer.
[0047] Specifically, in this embodiment, lateral etching is achieved by adjusting the lateral-to-longitudinal etching rate ratio. At this time, approximately 3-5 nm of the second silicon-germanium layer 121 between the silicon layers 122 is removed by lateral etching, allowing the exposed 3-5 nm spacing between the silicon layers 122 to serve as an inner spacer. Simultaneously, the bottommost retained second silicon-germanium layer 121 is still preserved in this step for auxiliary growth in subsequent epitaxial growth. Figure 2(J) shows a schematic diagram of the device structure along its length, where the dashed line with a gray background represents the second silicon-germanium layer 121 retained within the gate structure 130 after lateral etching. The diagram on the right is a cross-sectional view of the device structure along its width.
[0048] Furthermore, in this embodiment, step S9, as shown in FIG2(K), forms a second insulating layer 150, which fills the gaps generated by the transverse etching. FIG2(K) shows a schematic diagram of the device structure along the length direction on the left and a cross-sectional view of the device structure along the width direction on the right.
[0049] Specifically, in this embodiment, the material of the second insulating layer 150 can be insulating materials such as Si3N4, SiOC, SiON, SiCN or SiBCN.
[0050] Similar to the formation of the first insulating layer 140, in this embodiment, the method for forming the second insulating layer 150 includes: First, forming a second insulating capping layer on the surface of the fin stack structure 120, the surface of the gate structure 130, and the surface of the substrate 100 using an atomic layer deposition process. The second insulating capping layer can simultaneously fill the gaps formed by lateral etching. Since the thickness of the second silicon-germanium layer 121 in this embodiment is 8-10 nm, the thickness of the second insulating capping layer is also 8-10 nm, ensuring that the gaps formed by lateral etching are completely filled by the second insulating capping layer. Then, using reactive ion etching, the lateral and longitudinal etching rate ratio is adjusted to etch back the second insulating capping layer, retaining only the second insulating capping layer at the inner isolation layer to obtain the second insulating layer 150. At this time, the second insulating layer 150 is only located in the gaps left by lateral etching, that is, the second insulating layer 150 replaces the second silicon-germanium layer 121 between the silicon layers 122 and is located between the silicon layers 122.
[0051] Furthermore, in this embodiment, step S10, as shown in FIG2 (L), involves epitaxially growing a source electrode 161 and a drain electrode 162. FIG2 (L) shows a schematic diagram of the device structure along the length direction on the left and a cross-sectional view of the device structure along the width direction on the right.
[0052] The specific implementation of epitaxial growth of source 161 and drain 162 is something that those skilled in the art can obtain in the existing manufacturing methods of gate ring nanosheet transistors, and will not be described in detail here.
[0053] The fabrication method of the gate-around nanosheet transistor provided in this embodiment utilizes a first insulating layer 140 as a barrier layer between the substrate 100 and the fin stack structure 120. Simultaneously, a bottom second silicon-germanium layer 121 is retained on the first insulating layer 140, and a second insulating layer 150 is filled between the silicon layers 122 to form a composite gap isolation structure. Therefore, during epitaxial growth, the first insulating layer 140 can be used to avoid the formation of parasitic channels, while the retained second silicon-germanium layer 121 serves as a seed layer for epitaxial crystals to prevent dislocations and growth defects. Furthermore, the composite gap isolation structure provided by the second insulating layer improves the electrical performance of the device while ensuring structural stability. Thus, high-quality source-drain epitaxial growth is achieved, solving the problem of how to improve the device performance and quality of the gate-around nanosheet transistor.
[0054] This embodiment also provides a gate-around nanosheet transistor, which is manufactured using the gate-around nanosheet transistor fabrication method described above. Figure 3 As shown, the left diagram is a schematic diagram of the device structure along the length direction, and the right diagram is a cross-sectional view of the device structure along the width direction. The structure within the source and drain is shown in perspective. The gate-ring nanosheet transistor includes a substrate 100 and a fin stack structure 120; a gate structure 130 covers a portion of the top and sidewalls of the fin stack structure 120; the fin stack structure 120 covered by the gate structure 130 includes alternating layers of second silicon-germanium layers 121 and silicon layers 122 arranged from bottom to top. A first silicon-germanium layer 110 is disposed between the bottom of the fin stack structure 120 covered by the gate structure 130 and the substrate 100; the exposed fin stack structure 120 includes a second silicon-germanium layer 121 and alternating layers of a second insulating layer 150 and a silicon layer 122 disposed sequentially from bottom to top, and a first insulating layer 140 is disposed between the bottom of the exposed fin stack structure 120 and the substrate 100; an source electrode 161 and a drain electrode 162 are epitaxially grown at the exposed fin stack structure 120.
[0055] Furthermore, this embodiment also provides a gate-ring nanosheet transistor, which is manufactured using the gate-ring nanosheet transistor fabrication method described above, such as... Figure 4As shown, the left diagram is a schematic diagram of the device structure along the length direction, and the right diagram is a cross-sectional view of the device structure along the width direction. The structure located within the source and drain is shown in perspective. The ring-gate nanosheet transistor includes a substrate 100 and a fin stack structure 120; a gate structure 130 covers a portion of the top and sidewalls of the fin stack structure 120; the fin stack structure 120 covered by the gate structure 130 includes alternating layers of second silicon-germanium layers 121 and silicon layers 122 arranged from bottom to top, and is covered by the gate structure. A first silicon-germanium layer 110 and a first insulating layer 140 located on the same layer are disposed between the bottom of the fin stack structure 120 covered by 130 and the substrate 100; the exposed fin stack structure 120 includes a second silicon-germanium layer 121 and alternating layers of a second insulating layer 150 and a silicon layer 122 disposed sequentially from bottom to top, and a first insulating layer 140 is disposed between the bottom of the exposed fin stack structure 120 and the substrate 100; an source electrode 161 and a drain electrode 162 are epitaxially grown at the exposed fin stack structure 120.
[0056] This embodiment also provides a gate-around nanosheet transistor, which is manufactured using the gate-around nanosheet transistor fabrication method described above. Figure 5 As shown, the left diagram is a schematic diagram of the device structure along the length direction, and the right diagram is a cross-sectional view of the device structure along the width direction. The structure within the source and drain is shown in perspective. The gate-ring nanosheet transistor includes a substrate 100 and a fin stack structure 120; a gate structure 130 covers a portion of the top and sidewalls of the fin stack structure 120; the fin stack structure 120 covered by the gate structure 130 includes alternating layers of second silicon-germanium layers 121 and silicon layers 122 arranged from bottom to top. A first insulating layer 140 is disposed between the bottom of the fin stack structure 120 covered by the gate structure 130 and the substrate 100; the exposed fin stack structure 120 includes a second silicon-germanium layer 121 and alternating layers of a second insulating layer 150 and a silicon layer 122 disposed sequentially from bottom to top, and the first insulating layer 140 is disposed between the bottom of the exposed fin stack structure 120 and the substrate 100; an source electrode 161 and a drain electrode 162 are epitaxially grown at the exposed fin stack structure 120.
[0057] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0058] The ring-gate nanosheet transistor and its fabrication method provided in this embodiment include: providing a substrate; forming a first silicon-germanium layer on the substrate; forming multiple alternating layers of second silicon-germanium layer and silicon layer on the first silicon-germanium layer from bottom to top to obtain a fin stack structure; forming a gate structure, the gate structure covering the top and sidewalls of a portion of the fin stack structure; selectively etching away at least a portion of the first silicon-germanium layer; forming a first insulating layer, the first insulating layer filling the gaps generated by the selective etching; sequentially etching the silicon layer and the second silicon-germanium layer of the fin stack structure, retaining the bottommost second silicon-germanium layer as an epitaxial seed layer; laterally etching the second silicon-germanium layer to expose the gaps between a portion of the silicon layers as an inner isolation layer; forming a second insulating layer, the second insulating layer filling the gaps generated by the lateral etching; and epitaxially growing a source and a drain. By first forming a first silicon-germanium layer between the substrate and the fin stack structure, and then selectively etching away the first silicon-germanium layer before filling with a first insulating layer, the fin stack structure is isolated from the substrate. At the same time, since the bottom second silicon-germanium layer is retained as the epitaxial crystal seed layer, the growth quality of the source and drain electrodes of the epitaxial growth is improved. Moreover, the second insulating layer can be used to construct a multilayer composite isolation structure, which improves the device structure stability, ensures the device electrical performance, and solves the problem of how to improve the device performance and quality of the gate-around nanosheet transistor.
[0059] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for fabricating a ring-gate nanosheet transistor, characterized in that, include: Provide substrate; A first silicon-germanium layer is formed on the substrate; Multiple layers of second silicon-germanium layers and silicon layers are alternately formed from bottom to top on the first silicon-germanium layer to obtain a fin stacked structure; A gate structure is formed, which covers the top and sidewalls of a portion of the fin stack structure; Selective etching removes at least a portion of the first silicon-germanium layer; A first insulating layer is formed, which fills the voids created by selective etching. The silicon layer and the second silicon-germanium layer of the fin stack structure are etched sequentially, while the bottommost second silicon-germanium layer is retained as the epitaxial crystal seed layer. Laterally etch the second silicon-germanium layer to expose the gaps between the silicon layers as an inner isolation layer; A second insulating layer is formed, which fills the gaps created by the lateral etching. Epitaxial growth of source and drain electrodes.
2. The method for fabricating a gate-ring nanosheet transistor according to claim 1, characterized in that, The atomic ratio of silicon to germanium in the first silicon-germanium layer is different from that in the second silicon-germanium layer.
3. The method for fabricating a ring-gate nanosheet transistor according to claim 2, characterized in that, The atomic ratio of silicon to germanium in the first silicon-germanium layer is 0.6:0.4~0.5:0.5; the atomic ratio of silicon to germanium in the second silicon-germanium layer is 0.7:0.3~0.8:0.
2.
4. The method for fabricating a ring-gate nanosheet transistor according to claim 1, characterized in that, The method for forming a first silicon-germanium layer on a substrate includes: A third silicon-germanium layer is formed on the substrate, wherein the atomic ratio of silicon to germanium in the third silicon-germanium layer is the same as or similar to the atomic ratio of silicon to germanium in the second silicon-germanium layer; The first silicon-germanium layer is formed on the third silicon-germanium layer.
5. The method for fabricating a ring-gate nanosheet transistor according to claim 1, characterized in that, The thickness of the first silicon-germanium layer is 5nm~8nm.
6. The method for fabricating a ring-gate nanosheet transistor according to claim 1, characterized in that, The material of the first insulating layer is Si3N4, SiOC, SiON, SiCN or SiBCN.
7. The method for fabricating a ring-gate nanosheet transistor according to claim 1, characterized in that, The method for forming the first insulating layer includes: A first insulating capping layer is formed on the surface of the fin stack structure, the gate structure surface, and the substrate surface using an atomic layer deposition process; By using reactive ion etching and adjusting the ratio of transverse to longitudinal etching rates, the first insulating capping layer is etched back to form the top and sidewall window morphology, thus obtaining the first insulating layer.
8. The method for fabricating a gate-ring nanosheet transistor according to claim 1, characterized in that, The material of the second insulating layer is Si3N4, SiOC, SiON, SiCN or SiBCN.
9. The method for fabricating a ring-gate nanosheet transistor according to claim 1, characterized in that, The method for forming the second insulating layer includes: A second insulating capping layer is formed on the surface of the fin stack structure, the gate structure surface, and the substrate surface using an atomic layer deposition process; By using reactive ion etching and adjusting the cross-sectional and longitudinal etching rate ratio, the second insulating capping layer is etched back, leaving only the second insulating capping layer between the inner isolation layers to obtain the second insulating layer.
10. A gate-ring nanosheet transistor, manufactured using the method for fabricating a gate-ring nanosheet transistor as described in any one of claims 1 to 9, characterized in that, The gate-ring nanosheet transistor includes a substrate and a fin stack structure; a gate structure is covered on a portion of the top and a portion of the sidewalls of the fin stack structure; the fin stack structure covered by the gate structure includes alternating layers of second silicon-germanium layers and silicon layers from bottom to top. A first silicon-germanium layer is disposed between the bottom of the fin stack structure covered by the gate structure and the substrate; or, a first silicon-germanium layer and a first insulating layer located on the same layer are disposed between the bottom of the fin stack structure covered by the gate structure and the substrate; or, a first insulating layer is disposed between the bottom of the fin stack structure covered by the gate structure and the substrate. The exposed fin stack structure includes a second silicon-germanium layer and alternating layers of a second insulating layer and a silicon layer arranged sequentially from bottom to top; a first insulating layer is disposed between the bottom of the exposed fin stack structure and the substrate; Active and drain electrodes are epitaxially grown at the exposed fin stack structure.