A ring gate nanosheet field effect transistor and a manufacturing method thereof

Abstract

The application provides a ring gate nanosheet field effect transistor and a manufacturing method thereof, and comprises the following steps: providing a basic device structure, wherein the basic device structure comprises a fin stack structure and a gate structure on a substrate, the fin stack structure comprises silicon germanium layers and silicon layers alternately formed from bottom to top, and the gate structure covers the top and sidewall of part of the fin stack structure; at least removing part of the silicon germanium layers which are not covered by the gate structure; forming an insulating layer to fill the gap generated after the silicon germanium layers are removed; taking the gate structure as a mask, etching the silicon layers and the insulating layer in sequence, and reserving the bottommost insulating layer; and epitaxially growing source and drain electrodes. By replacing the silicon germanium layers in the fin stack structure used for growing the source and drain electrodes with the insulating layer and reserving the bottommost insulating layer, the silicon layers are isolated from the substrate silicon due to the insulating layer, so that the formation of a parasitic channel is effectively avoided when the source and drain electrodes are epitaxially grown, and the problem of how to eliminate the parasitic path of the ring gate nanosheet field effect transistor to improve the device performance is solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a gate-ring nanosheet field-effect transistor and its fabrication method. Background Technology

[0002] As semiconductor technology nodes continue to shrink to 3nm and below, gate-around nanosheet field-effect transistors (GAAFETs) have become the mainstream architecture.

[0003] In the fabrication of gate-all-around nanosheet field-effect transistors (GAAFETs), the source and drain regions are typically epitaxially grown on both sides of the fins. In conventional process flows, when etching the fin stack structure (Fin Recess process), selective etching often stops at the surface of the insulating dielectric, exposing the silicon substrate.

[0004] However, due to the consistency of the epitaxial process, the source and drain regions are simultaneously epitaxially grown on the exposed silicon substrate surface. This creates parasitic pathways, allowing current to bypass the gate-controlled nanosheet channel and leak directly from the substrate. This not only increases the turn-off current and prevents the device from being completely turned off, but also deteriorates the subthreshold swing, severely impacting the device's low-power performance. Summary of the Invention

[0005] The purpose of this invention is to provide a gate-ring nanosheet field-effect transistor and its fabrication method, so as to solve the problem of how to eliminate parasitic paths in gate-ring nanosheet field-effect transistors to improve device performance.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for fabricating a gate-ring nanosheet field-effect transistor, comprising: A basic device structure is provided, the basic device structure including a substrate and a fin stack structure and a gate structure located on the substrate, the fin stack structure including silicon-germanium layers and silicon layers formed alternately from bottom to top, and the gate structure covering part of the top and sidewalls of the fin stack structure; At least the portion of the silicon-germanium layer in the fin stack structure that is not covered by the gate structure should be removed; An insulating layer is formed, which fills the gaps created after the removal of the silicon-germanium layer; Using the gate structure as a mask, the silicon layer and the insulating layer are etched sequentially, while the bottom insulating layer is retained; Epitaxial growth of source and drain electrodes.

[0007] Optionally, in the method for fabricating the ring-gate nanosheet field-effect transistor, the method for at least removing the portion of the silicon-germanium layer not covered by the gate structure in the fin stack structure includes: Reactive ion etching or wet etching processes are used to remove all silicon-germanium layers in the fin stack structure that are not covered by the gate structure.

[0008] Optionally, in the fabrication method of the ring-gate nanosheet field-effect transistor, the insulating layer is made of Si3N4, SiOC, SiON, SiCN, or SiBCN.

[0009] Optionally, in the method for fabricating the ring-gate nanosheet field-effect transistor, the method for forming the insulating layer includes: An insulating capping layer is formed on the surface of the silicon layer, the surface of the gate structure, and the surface of the substrate using atomic layer deposition technology; By employing reactive ion etching technology and adjusting the longitudinal and transverse etching rate ratio, the insulating capping layer is etched back to form the top and sidewall window morphology, thus obtaining the insulating layer.

[0010] Optionally, in the fabrication method of the ring-gate nanosheet field-effect transistor, the thickness of the insulating capping layer is consistent with the thickness of the silicon-germanium layer, so as to fill the gap generated after the silicon-germanium layer is removed.

[0011] To address the aforementioned technical problems, the present invention also provides a gate-around nanosheet field-effect transistor, manufactured using the method described in any of the preceding claims. The gate-around nanosheet field-effect transistor includes a substrate and a fin stack structure. A gate structure covers a portion of the top and sidewalls of the fin stack structure. The fin stack structure covered by the gate structure includes alternating layers of silicon-germanium and silicon layers arranged from bottom to top, and / or includes alternating layers of insulating and silicon layers arranged from bottom to top. The exposed fin stack structure includes alternating layers of insulating and silicon layers arranged from bottom to top. An active electrode and a drain electrode are epitaxially grown at the exposed fin stack structure.

[0012] Optionally, in the aforementioned gate-ring nanosheet field-effect transistor, the insulating layer is made of Si3N4, SiOC, SiON, SiCN, or SiBCN.

[0013] Optionally, in the aforementioned gate-ring nanosheet field-effect transistor, the thickness of the insulating layer is consistent with the thickness of the silicon-germanium layer.

[0014] Optionally, in the aforementioned gate-around nanosheet field-effect transistor, the substrate includes a dielectric layer and a bottom silicon layer located within the dielectric layer, with the bottom silicon layer exposed on the substrate surface; the fin stack structure is located on top of the bottom silicon layer.

[0015] Optionally, in the aforementioned gate-ring nanosheet field-effect transistor, the bottommost insulating layer covers the bottom silicon layer.

[0016] The present invention provides a gate-around nanosheet field-effect transistor and its fabrication method, comprising: providing a basic device structure, the basic device structure including a substrate and a fin stack structure and a gate structure located on the substrate, the fin stack structure including alternating layers of silicon-germanium layers and silicon layers formed from bottom to top, the gate structure covering part of the top and sidewalls of the fin stack structure; removing at least a portion of the silicon-germanium layers in the fin stack structure not covered by the gate structure; forming an insulating layer, the insulating layer filling the gaps generated after removing the silicon-germanium layers; using the gate structure as a mask, sequentially etching the silicon layer and the insulating layer, retaining the bottom insulating layer; and epitaxially growing the source and drain. By replacing the silicon-germanium layers in the fin stack structure used for growing the source and drain with an insulating layer, and retaining the bottom insulating layer, the silicon layer is isolated from the substrate silicon by the insulating layer, thereby effectively avoiding the formation of parasitic channels during the epitaxial growth of the source and drain, solving the problem of how to eliminate parasitic paths in gate-around nanosheet field-effect transistors to improve device performance. Attached Figure Description

[0017] Figure 1 A flowchart illustrating the fabrication method of the gate-ring nanosheet field-effect transistor provided in this embodiment; Figures 2(A) to 2(G) are schematic diagrams of the device structure corresponding to each step in the fabrication method of the ring gate nanosheet field-effect transistor provided in this embodiment; Figure 3 This is a schematic diagram of the structure of the first type of ring-gate nanosheet field-effect transistor provided in this embodiment; Figure 4 This is a schematic diagram of the structure of the second type of ring-gate nanosheet field-effect transistor provided in this embodiment; Figure 5 This is a schematic diagram of the structure of the third type of ring-gate nanosheet field-effect transistor provided in this embodiment; The labels in the attached figures are explained as follows: 100 - Substrate; 101 - Dielectric layer; 102 - Bottom silicon layer; 110 - Fin stacked structure; 111 - Silicon-germanium layer; 112 - Silicon layer; 120 - Gate structure; 130 - Insulating capping layer; 131 - Insulating layer; 141 - Source; 142 - Drain. Detailed Implementation

[0018] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the proposed ring-gate nanosheet field-effect transistor and its fabrication method. It should be noted that the drawings are all in a very simplified form and use non-precise scales, intended only to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0019] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] This embodiment provides a method for fabricating a gate-ring nanosheet field-effect transistor, such as... Figure 1 As shown, it includes: S1, providing a basic device structure, the basic device structure including a substrate and a fin stack structure and a gate structure located on the substrate, the fin stack structure including silicon-germanium layers and silicon layers formed alternately from bottom to top, the gate structure covering part of the top and sidewalls of the fin stack structure; S2, at least remove the portion of the silicon-germanium layer in the fin stack structure that is not covered by the gate structure; S3, forming an insulating layer that fills the gaps created after removing the silicon-germanium layer; S4, using the gate structure as a mask, the silicon layer and the insulating layer are etched sequentially, while the bottom insulating layer is retained; S5, epitaxial growth of the source and drain.

[0021] The fabrication method of the gate-around nanosheet field-effect transistor provided in this embodiment replaces the silicon-germanium layer in the fin stack structure used to grow the source and drain electrodes with an insulating layer, while retaining the bottom insulating layer. This isolates the silicon layer from the substrate silicon due to the insulating layer, thereby effectively avoiding the formation of parasitic channels during the epitaxial growth of the source and drain electrodes. This solves the problem of how to eliminate parasitic pathways in the gate-around nanosheet field-effect transistor to improve device performance.

[0022] Specifically, in this embodiment, step S1 involves providing a basic device structure.

[0023] As shown in Figure 2(A), the basic device structure includes a substrate 100 and a fin stack structure 110 and a gate structure 120 located on the substrate 100. The fin stack structure 110 includes alternating layers of silicon-germanium 111 and silicon 112 formed from bottom to top. The gate structure 120 covers part of the top and sidewalls of the fin stack structure 110. The left side of Figure 2(A) shows a schematic diagram of the device structure along the length direction, and the right side shows a cross-sectional view of the device structure along the width direction.

[0024] Specifically, in this embodiment, as shown in FIG2(A), the substrate 100 includes a dielectric layer 101 and a bottom silicon layer 102 located in the dielectric layer 101, with the top of the bottom silicon layer 102 exposed on the surface of the substrate 100. Specifically, the dielectric layer 101 may be made of silicon oxide.

[0025] Of course, in practical applications, the substrate 100 may also contain other device structures, such as metal interconnect layers, which will not be elaborated in this application.

[0026] In this embodiment, as shown in FIG2(A), a fin stack structure 110 is formed on the bottom silicon layer 102. The fin stack structure 110 includes alternating layers of silicon-germanium layers 111 and silicon layers 112 formed from bottom to top. In a specific embodiment, the atomic ratio of silicon to germanium in the silicon-germanium layer 111 is 0.7:0.3 to 0.8:0.2. Furthermore, the thickness of the multiple silicon-germanium layers 111 is uniform, for example, 8nm to 10nm, specifically 10nm; the thickness of the multiple silicon layers 112 is uniform, for example, 4nm to 6nm, specifically 5nm.

[0027] The specific formation method of the fin stack structure 110 is something that those skilled in the art can obtain in the existing manufacturing methods of ring gate nanosheet field-effect transistors, and this application will not elaborate on it further.

[0028] In this embodiment, as shown in FIG2(A), a gate structure 120 is formed on the substrate 100, the gate structure 120 covering the top and sidewalls of the partial fin stack structure 110.

[0029] The specific formation method of the gate structure 120 is something that those skilled in the art can obtain in the existing manufacturing methods of gate ring nanosheet field-effect transistors, and this application will not elaborate on it further.

[0030] Furthermore, in this embodiment, step S2 involves removing at least the portion of the silicon-germanium layer in the fin stack structure that is not covered by the gate structure.

[0031] Specifically, in this embodiment, as shown in FIG2(B), reactive ion etching (RIE) or wet etching can be used to remove all silicon-germanium layers 111 in the fin stack structure 110 not covered by the gate structure 120, thereby making all silicon layers 112 not covered by the gate structure 120 suspended. FIG2(B) shows a schematic diagram of the device structure along the length direction on the left, with the gray-background silicon-germanium layers 111 representing the silicon-germanium layers 111 located in the fin stack structure 110 covered by the gate structure 120. The right side shows a cross-sectional view of the device structure along the width direction.

[0032] In another specific embodiment, as shown in FIG2(C), a reactive ion etching (RIE) process or a wet etching process is used to adjust the longitudinal and transverse etching rate ratio, so that the silicon-germanium layer 111 in the fin stack structure 110 covered by the gate structure 120 is partially removed. FIG2(C) shows a schematic diagram of the device structure along the length direction on the left, with the gray-background silicon-germanium layer 111 representing the silicon-germanium layer 111 located in the fin stack structure 110 covered by the gate structure 120. The right side shows a cross-sectional view of the device structure along the width direction.

[0033] In the third specific embodiment, as shown in Figure 2(D), a reactive ion etching (RIE) process or a wet etching process is used to adjust the longitudinal and transverse etching rate ratio, so that the silicon-germanium layer 111 in the fin stack structure 110 is completely removed. The left side of Figure 2(D) shows a schematic diagram of the device structure along the length direction, and the right side shows a cross-sectional view of the device structure along the width direction.

[0034] The following describes the implementation process of subsequent steps in the fabrication method of the ring-gate nanosheet field-effect transistor provided in this embodiment, using the device structure shown in Figure 2(B) as an example.

[0035] Furthermore, in this embodiment, in step S3, an insulating layer 131 is formed, which fills the gaps generated after the removal of the silicon-germanium layer 111.

[0036] Specifically, in this embodiment, firstly, as shown in FIG2(E), an insulating capping layer 130 is formed on the surface of the silicon layer 112, the surface of the gate structure 120, and the surface of the substrate 100 using atomic layer deposition (ALD). The thickness of the insulating capping layer 130 is consistent with the thickness of the silicon-germanium layer 111 to ensure that the gaps formed by etching away the silicon-germanium layer 111 are completely filled by the insulating capping layer 130. For example, in this embodiment, the thickness of the silicon-germanium layer 111 is 8~10nm, therefore, the thickness of the insulating capping layer 130 is also 8~10nm. FIG2(E) shows a schematic diagram of the device structure along the length direction, displaying the device structure inside the insulating capping layer 130 in perspective, and a cross-sectional view of the device structure along the width direction on the left side.

[0037] In practical applications, the insulating cover layer 130 can be made of insulating materials such as Si3N4, SiOC, SiON, SiCN, or SiBCN.

[0038] Then, in this embodiment, as shown in FIG2(F), a reactive ion etching (RIE) process is used to adjust the longitudinal and transverse etching rate ratio to etch back the insulating capping layer 130 to form the top and sidewall window morphology, thereby obtaining the insulating layer 131.

[0039] In practical applications, by adjusting the longitudinal and transverse etching rate ratio, the portions of the insulating capping layer 130 deposited on the surface of the substrate 100, the top of the gate structure 120, and the sidewalls of the gate structure 120 can be removed at a faster rate, while the portions filled between the silicon layers 112 can be retained, forming a top and sidewall windowed morphology. At this point, the resulting insulating layer 131 only fills the gaps formed by the etched silicon-germanium layers 111, meaning the spaces between the exposed silicon layers 112 in the fin stack structure 110 are filled by the insulating layer 131. This transforms the silicon layers 112 after the removal of the silicon-germanium layers 111 from a suspended state to one supported by the insulating layer 131, ensuring the integrity and effectiveness of the device structure. Figure 2(F) shows a schematic diagram of the device structure along its length on the left and a cross-sectional view of the device structure along its width on the right.

[0040] Of course, those skilled in the art can learn from the above-described method of forming insulating layer 131 that forms insulating layer 131 on the device structure shown in FIG2(C) or FIG2(D), as well as the device structure after forming insulating layer 131, and this application will not elaborate further on this.

[0041] Furthermore, in this embodiment, in step S4, as shown in FIG2 (G), the silicon layer 112 and the insulating layer 131 are etched sequentially using the gate structure 120 as a mask, while the bottom insulating layer 131 is retained.

[0042] Specifically, the silicon layer 112 and the insulating layer 131 are etched sequentially in steps, using methods that can be obtained by those skilled in the art in the existing manufacturing methods of gate-around nanosheet field-effect transistors, and will not be described in detail here. Figure 2(G) shows a schematic diagram of the device structure along its length on the left, with the gray-background silicon layer 112 and insulating layer 131 representing the silicon layer 112 and insulating layer 131 retained after the step-by-step etching. The figure on the right is a cross-sectional view of the device structure along its width.

[0043] This embodiment retains the bottom insulating layer 131, so that the exposed fin stack structure 110 for growing source and drain electrodes is isolated from the substrate 100 (bottom silicon layer 102) by the insulating layer 131. Thus, the retained insulating layer 131 is used as a barrier layer to prevent the bottom silicon layer 102 from growing during the epitaxial growth process, thereby effectively avoiding the formation of parasitic channels and solving the problem of how to eliminate parasitic paths of gate ring nanosheet field-effect transistors to improve device performance.

[0044] Furthermore, in this embodiment, step S5, as follows: Figure 3 , Figure 4 or Figure 5 As shown, source electrode 141 and drain electrode 142 are epitaxially grown.

[0045] The specific implementation methods of epitaxially growing the source 141 and drain 142 are those that can be obtained by those skilled in the art in the existing manufacturing methods of gate-around nanosheet field-effect transistors, and will not be elaborated further in this application. Figure 3 , Figure 4 and Figure 5 The left diagram shows a schematic diagram of the device structure along the length direction, displaying the internal device structure of the source 141 and drain 142 in perspective. The right diagram shows a cross-sectional view of the device structure along the width direction.

[0046] The fabrication method of the gate-around nanosheet field-effect transistor provided in this embodiment achieves a self-aligned isolation process by replacing the silicon-germanium layer 111 in the fin stack structure 110 used for growing the source and drain electrodes with an insulating layer 131. This reduces the difficulty of the process while improving the process accuracy. At the same time, by retaining the bottom insulating layer 131, the silicon layer 112 and the bottom silicon layer 102 in the substrate 100 are isolated by the insulating layer 131. This effectively avoids the formation of parasitic channels during the epitaxial growth of the source and drain electrodes, suppresses leakage current from the source and drain regions to the substrate, improves device performance, and solves the problem of how to eliminate parasitic paths in the gate-around nanosheet field-effect transistor to improve device performance.

[0047] This embodiment also provides a gate-around nanosheet field-effect transistor, which is manufactured using the gate-around nanosheet field-effect transistor fabrication method described above. The gate-around nanosheet field-effect transistor includes a substrate 100 and a fin stack structure 110 located on the substrate 100. A gate structure 120 covers a portion of the top and a portion of the sidewalls of the fin stack structure 110. The fin stack structure 110 covered by the gate structure 120 includes alternating layers of silicon-germanium layers 111 and silicon layers 112 arranged from bottom to top, and / or includes alternating layers of insulating layers 131 and silicon layers 112 arranged from bottom to top. The exposed fin stack structure 110 includes alternating layers of insulating layers 131 and silicon layers 112 arranged from bottom to top. An active electrode 141 and a drain electrode 142 are epitaxially grown at the exposed fin stack structure 110.

[0048] In one specific embodiment, such as Figure 3 As shown (wherein the structure within the source and drain is shown in perspective), the gate-ring nanosheet field-effect transistor includes a substrate 100 and a fin stack structure 110 on the substrate 100; a gate structure 120 covers a portion of the top and a portion of the sidewalls of the fin stack structure 110; the fin stack structure 110 covered by the gate structure 120 includes alternating layers of silicon-germanium 111 and silicon 112 arranged from bottom to top; the exposed fin stack structure 110 includes alternating layers of insulating 131 and silicon 112 arranged from bottom to top; a source 141 and a drain 142 are epitaxially grown at the exposed fin stack structure 110.

[0049] In another specific embodiment, such as Figure 4 As shown (wherein the structure within the source and drain is shown in perspective), the gate-ring nanosheet field-effect transistor includes a substrate 100 and a fin stack structure 110 on the substrate 100; a gate structure 120 covers a portion of the top and a portion of the sidewalls of the fin stack structure 110; the inner portion of the fin stack structure 110 covered by the gate structure 120 includes alternating layers of silicon-germanium 111 and silicon 112 from bottom to top, while the outer portion of the fin stack structure 110 covered by the gate structure 120 includes alternating layers of insulating 131 and silicon 112 from bottom to top; the exposed fin stack structure 110 includes alternating layers of insulating 131 and silicon 112 from bottom to top; a source 141 and a drain 142 are epitaxially grown at the exposed fin stack structure 110.

[0050] In the third specific embodiment, such as Figure 5 As shown (wherein the structure located within the source and drain electrodes is shown in perspective), the gate-ring nanosheet field-effect transistor includes a substrate 100 and a fin stack structure 110 located on the substrate 100; a gate structure 120 is covered on a portion of the top and a portion of the sidewalls of the fin stack structure 110; both the fin stack structure 110 covered by the gate structure 120 and the exposed fin stack structure 110 include an insulating layer 131 and a silicon layer 112 alternately arranged from bottom to top; a source electrode 141 and a drain electrode 142 are epitaxially grown at the exposed fin stack structure 110.

[0051] Furthermore, in this embodiment, the insulating layer 131 is made of insulating materials such as Si3N4, SiOC, SiON, SiCN, or SiBCN.

[0052] Furthermore, in this embodiment, the thickness of the insulating layer 131 is consistent with the thickness of the silicon-germanium layer 111, thereby ensuring that the silicon layer 112 (nanosheet) structure has stable support and ensuring the stability and reliability of the device structure.

[0053] Furthermore, in this embodiment, as Figures 3 to 5As shown, the substrate 100 includes a dielectric layer 101 and a bottom silicon layer 102 located in the dielectric layer 101, with the bottom silicon layer 102 exposed on the surface of the substrate 100; the fin stack structure 110 is located on top of the bottom silicon layer 102. To avoid the formation of parasitic channels between the bottom silicon layer 102 and the silicon layer 112 in the fin stack structure 110 during epitaxial growth, in this embodiment, the bottommost insulating layer 131 of the exposed fin stack structure 110 (the portion not covered by the gate structure 120) is completely preserved, thereby covering the bottom silicon layer 102, so that the insulating layer 131 can be used as a barrier layer to isolate the bottom silicon layer 102 from the silicon layer 112.

[0054] The ring-gate nanosheet field-effect transistor provided in this embodiment has a simple manufacturing process. By using a self-aligned isolation process, an insulating layer 131 is used to replace the silicon-germanium layer 111, thereby retaining the bottom insulating layer 131. This isolates the silicon layer 112 from the bottom silicon layer 102 in the substrate 100 due to the insulating layer 131. This effectively avoids the formation of parasitic channels during the epitaxial growth of the source and drain, suppresses leakage from the source and drain regions to the substrate, improves device performance, and solves the problem of how to eliminate parasitic paths in the ring-gate nanosheet field-effect transistor to improve device performance.

[0055] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0056] This embodiment provides a gate-around nanosheet field-effect transistor and its fabrication method, comprising: providing a basic device structure, the basic device structure including a substrate and a fin stack structure and a gate structure located on the substrate, the fin stack structure including alternating layers of silicon-germanium layers and silicon layers formed from bottom to top, the gate structure covering part of the top and sidewalls of the fin stack structure; removing at least a portion of the silicon-germanium layers in the fin stack structure not covered by the gate structure; forming an insulating layer, the insulating layer filling the gaps generated after removing the silicon-germanium layers; using the gate structure as a mask, sequentially etching the silicon layer and the insulating layer, retaining the bottom insulating layer; and epitaxially growing the source and drain. By replacing the silicon-germanium layers in the fin stack structure used for growing the source and drain with an insulating layer, and retaining the bottom insulating layer, the silicon layer and the substrate silicon are isolated by the insulating layer, thereby effectively avoiding the formation of parasitic channels during the epitaxial growth of the source and drain, solving the problem of how to eliminate parasitic paths in gate-around nanosheet field-effect transistors to improve device performance.

[0057] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a ring-gate nanosheet field-effect transistor, characterized in that, include: A basic device structure is provided, the basic device structure including a substrate and a fin stack structure and a gate structure located on the substrate, the fin stack structure including silicon-germanium layers and silicon layers formed alternately from bottom to top, and the gate structure covering part of the top and sidewalls of the fin stack structure; At least the portion of the silicon-germanium layer in the fin stack structure that is not covered by the gate structure should be removed; An insulating layer is formed, which fills the gaps created after the removal of the silicon-germanium layer; Using the gate structure as a mask, the silicon layer and the insulating layer are etched sequentially, while the bottom insulating layer is retained; Epitaxial growth of source and drain electrodes.

2. The method for fabricating a ring-gate nanosheet field-effect transistor according to claim 1, characterized in that, The method for at least removing the portion of the silicon-germanium layer in the fin stack structure not covered by the gate structure includes: Reactive ion etching or wet etching processes are used to remove all silicon-germanium layers in the fin stack structure that are not covered by the gate structure.

3. The method for fabricating a ring-gate nanosheet field-effect transistor according to claim 1, characterized in that, The insulating layer is made of Si3N4, SiOC, SiON, SiCN, or SiBCN.

4. The method for fabricating a ring-gate nanosheet field-effect transistor according to claim 1, characterized in that, The method for forming the insulating layer includes: An insulating capping layer is formed on the surface of the silicon layer, the surface of the gate structure, and the surface of the substrate using atomic layer deposition technology; By employing reactive ion etching technology and adjusting the longitudinal and transverse etching rate ratio, the insulating capping layer is etched back to form the top and sidewall window morphology, thus obtaining the insulating layer.

5. The method for fabricating a ring-gate nanosheet field-effect transistor according to claim 4, characterized in that, The thickness of the insulating cover layer is the same as the thickness of the silicon-germanium layer, so as to fill the gaps created after the silicon-germanium layer is removed.

6. A gate-around nanosheet field-effect transistor, manufactured using the method for fabricating a gate-around nanosheet field-effect transistor as described in any one of claims 1 to 5, characterized in that, The gate-ring nanosheet field-effect transistor includes a substrate and a fin stack structure located on the substrate; a gate structure is covered on a portion of the top and a portion of the sidewalls of the fin stack structure; the fin stack structure covered by the gate structure includes alternating layers of silicon-germanium layers and silicon layers arranged from bottom to top, and / or includes alternating layers of insulating layers and silicon layers arranged from bottom to top; the exposed fin stack structure includes alternating layers of insulating layers and silicon layers arranged from bottom to top; an active electrode and a drain electrode are epitaxially grown at the exposed fin stack structure.

7. The ring-gate nanosheet field-effect transistor according to claim 6, characterized in that, The insulating layer is made of Si3N4, SiOC, SiON, SiCN, or SiBCN.

8. The ring-gate nanosheet field-effect transistor according to claim 6, characterized in that, The thickness of the insulating layer is the same as the thickness of the silicon-germanium layer.

9. The ring-gate nanosheet field-effect transistor according to claim 6, characterized in that, The substrate includes a dielectric layer and a bottom silicon layer located in the dielectric layer, with the bottom silicon layer exposed on the surface of the substrate; the fin stack structure is located on top of the bottom silicon layer.

10. The ring-gate nanosheet field-effect transistor according to claim 9, characterized in that, The bottommost insulating layer covers the bottom silicon layer.

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