A ring gate field effect transistor and a manufacturing method thereof

Abstract

The application provides a ring gate field effect transistor and a manufacturing method thereof, and comprises the following steps: providing a substrate comprising a first silicon layer; forming a fin stack structure on the first silicon layer; etching the fin stack structure until the surface of the first silicon layer is exposed; etching a silicon germanium layer laterally to expose part of the second silicon layer; forming an insulating cover layer; etching the insulating cover layer at a first aspect ratio etching rate to expose the surface of the substrate to obtain a first insulating layer; oxidizing the first silicon layer to obtain a silicon oxide layer; etching the first insulating layer at a second aspect ratio etching rate to obtain a second insulating layer; and epitaxially growing a source electrode and a drain electrode. By controlling the aspect ratio etching rate ratio when etching the insulating cover layer, the morphology is fine-tuned, so that the first silicon layer can be completely exposed and oxidized to form a silicon oxide layer as a barrier layer, which effectively prevents the formation of a parasitic channel, and the influence of oxidation on the gate structure is avoided, thereby solving the problem of how to eliminate the parasitic path of the ring gate field effect transistor to improve the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a gate-ring field-effect transistor and its fabrication method. Background Technology

[0002] As semiconductor technology nodes continue to shrink to 5nm and below, gate-around field-effect transistors (GAAFETs) are placed on more stringent requirements for gate control capabilities, especially in their integration with existing process flows, where contradictions are exposed.

[0003] In the fabrication of gate-all-around field-effect transistors (GAAFETs), the formation of the source and drain regions relies on high-quality epitaxial growth. In traditional process flows, during the etching of the fin stack structure (Fin Recess process), the etching is typically stopped at the material interface, specifically at the interface between the silicon (Si) and silicon-germanium (SiGe) layers. Furthermore, during the inner spacer fill process, the etching of the inner spacer material is stopped at the silicon oxide (SiO2) interface. The defining characteristic of these two key process steps is the selective stopping point at the interface between the two materials.

[0004] However, existing processes, due to etching stopping at the Si / SiGe or SiO2 interface, result in incomplete isolation between the bottom channel and the substrate, easily forming a weak barrier region. This region is less controlled by the gate electric field and may be inverted or accumulated under bias, creating parasitic pathways. This leads to incomplete turn-off of the bottom channel, exacerbated short-channel effects, and threshold voltage drift. Moreover, the parasitic channels formed at the bottom provide additional leakage paths for current, resulting in a significant increase in off-state leakage current, deterioration of subthreshold swing, and reduced low-power performance. Furthermore, the formation of parasitic channels depends on process variations, increasing device parameter variability and thus affecting device noise and reliability. Summary of the Invention

[0005] The purpose of this invention is to provide a gate-around field-effect transistor and its fabrication method, so as to solve the problem of how to eliminate parasitic paths in gate-around field-effect transistors to improve device performance.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for fabricating a gate-to-ring field-effect transistor, comprising: A substrate is provided, the substrate including a dielectric layer and a first silicon layer located in the dielectric layer, the surface of the substrate exposing the top of the first silicon layer; A fin stack structure is formed on a first silicon layer, the fin stack structure comprising alternating layers of silicon-germanium layers and a second silicon layer formed from bottom to top; A gate structure is formed on a substrate, the gate structure covering the top and sidewalls of a portion of the fin stack structure; Using the gate structure as a mask, the fin stack structure is etched until the surface of the first silicon layer is exposed; Laterally etch the silicon-germanium layer to expose the gap between the second silicon layers as an inner isolation layer; An insulating capping layer is formed, which covers the surface of the fin stack structure, the surface of the gate structure, and the surface of the substrate; The longitudinal and transverse etching rate ratio is adjusted to the first longitudinal and transverse etching rate ratio, and the insulating capping layer is etched back to form a longitudinally open morphology, exposing the substrate surface and obtaining the first insulating layer; The first exposed silicon layer is oxidized to obtain a silicon oxide layer; The longitudinal and transverse etching rate ratio is adjusted to the second longitudinal and transverse etching rate ratio. The first insulating layer is etched back to form the morphology of the channel sidewall opening, exposing the gate structure and obtaining the second insulating layer. The second insulating layer fills the gaps generated by the transverse etching. Epitaxial growth of source and drain electrodes.

[0007] Optionally, in the fabrication method of the gate-ring field-effect transistor, the silicon-germanium layer is laterally etched to a depth of 3-5 nm.

[0008] Optionally, in the fabrication method of the gate-ring field-effect transistor, the insulating capping layer is made of Si3N4, SiOC, SiON, SiCN, or SiBCN.

[0009] Optionally, in the method for fabricating the gate-to-ring field-effect transistor, the method for forming the insulating capping layer includes: An insulating capping layer is formed on the surface of the fin stack structure, the gate structure surface, and the substrate surface using an atomic layer deposition process. The thickness of the insulating capping layer is consistent with the thickness of the silicon-germanium layer.

[0010] Optionally, in the method for fabricating the ring-gate field-effect transistor, the first longitudinal-to-transverse etching rate ratio is 2:1.

[0011] Optionally, in the method for fabricating the ring-gate field-effect transistor, the second longitudinal-to-transverse etching rate ratio is 1:1.

[0012] Optionally, in the fabrication method of the gate-ring field-effect transistor, a reactive ion etching process is used to etch back the insulating capping layer to obtain the first insulating layer.

[0013] Optionally, in the fabrication method of the gate-ring field-effect transistor, a reactive ion etching process is used to etch back the first insulating layer to obtain the second insulating layer.

[0014] To address the aforementioned technical problems, the present invention also provides a gate-around field-effect transistor (GOTFET), manufactured using the GOTFET fabrication method described in any of the preceding claims. The GOTFET includes a substrate and a fin stack structure. The substrate includes a dielectric layer and a first silicon layer located within the dielectric layer. A silicon oxide layer is formed on top of the first silicon layer, and the silicon oxide layer constitutes a portion of the substrate surface. The fin stack structure is located on top of the silicon oxide layer. A gate structure covers a portion of the top and sidewalls of the fin stack structure. The fin stack structure covered by the gate structure includes alternating layers of silicon-germanium and second silicon layers arranged from bottom to top. The exposed fin stack structure includes alternating layers of a second insulating layer and a second silicon layer arranged from bottom to top. An source and a drain are epitaxially grown at the exposed fin stack structure.

[0015] Optionally, in the aforementioned gate-ring field-effect transistor, the material of the second insulating layer is Si3N4, SiOC, SiON, SiCN, or SiBCN.

[0016] The present invention provides a gate-around field-effect transistor and a method for fabricating the same, comprising: providing a substrate, the substrate including a dielectric layer and a first silicon layer located in the dielectric layer, the surface of the substrate exposing the top of the first silicon layer; forming a fin stack structure on the first silicon layer, the fin stack structure including alternating layers of silicon-germanium layers and second silicon layers formed from bottom to top; forming a gate structure on the substrate, the gate structure covering the top and sidewalls of a portion of the fin stack structure; using the gate structure as a mask, etching the fin stack structure until the surface of the first silicon layer is exposed; laterally etching the silicon-germanium layers, with the spacing between the exposed portions of the second silicon layers serving as... An inner isolation layer is formed; an insulating capping layer is formed, which covers the surface of the fin stack structure, the surface of the gate structure, and the surface of the substrate; the longitudinal and transverse etch rate ratio is adjusted to a first longitudinal and transverse etch rate ratio, and the insulating capping layer is etched back to form a longitudinal window morphology, exposing the substrate surface to obtain the first insulating layer; the exposed first silicon layer is oxidized to obtain a silicon oxide layer; the longitudinal and transverse etch rate ratio is adjusted to a second longitudinal and transverse etch rate ratio, and the first insulating layer is etched back to form a channel sidewall window morphology, exposing the gate structure to obtain the second insulating layer, which fills the gaps generated by the transverse etch; the source and drain are epitaxially grown. By controlling the longitudinal and transverse etch rate ratio during the etching of the insulating capping layer, the morphology can be finely adjusted, thereby not only allowing the first silicon layer to be fully exposed and oxidized to form a silicon oxide layer as a barrier layer, effectively preventing the formation of parasitic channels, but also avoiding the influence of oxidation on the gate structure, thus solving the problem of how to eliminate parasitic paths in gate-around field-effect transistors to improve device performance. Attached Figure Description

[0017] Figure 1 A flowchart illustrating the fabrication method of the gate-to-ring field-effect transistor provided in this embodiment; Figures 2(A) to 2(J) are schematic diagrams of the device structure corresponding to each step in the fabrication method of the gate-ring field-effect transistor provided in this embodiment; Figure 3 This is a schematic cross-sectional view of the gate-ring field-effect transistor along its length provided in this embodiment. Figure 4 This is a schematic cross-sectional view of the gate-to-ring field-effect transistor along the width direction provided in this embodiment. The labels in the attached figures are explained as follows: 100 - Substrate; 101 - Dielectric layer; 102 - First silicon layer; 110 - Fin stacked structure; 111 - Silicon-germanium layer; 112 - Second silicon layer; 120 - Gate structure; 130 - Insulating capping layer; 131 - First insulating layer; 132 - Second insulating layer; 140 - Silicon oxide layer; 151 - Source; 152 - Drain. Detailed Implementation

[0018] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the gate-to-ring field-effect transistor and its fabrication method proposed in this invention. It should be noted that the drawings are all in a very simplified form and use non-precise scales, intended only to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0019] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] This embodiment provides a method for fabricating a gate-around field-effect transistor, such as... Figure 1 As shown, it includes: S1, providing a substrate, the substrate including a dielectric layer and a first silicon layer located in the dielectric layer, the surface of the substrate exposing the top of the first silicon layer; S2, a fin stack structure is formed on the first silicon layer, the fin stack structure comprising alternating layers of silicon-germanium layer and second silicon layer from bottom to top; S3, A gate structure is formed on the substrate, the gate structure covering the top and sidewalls of a partial fin stack structure; S4, using the gate structure as a mask, etch the fin stack structure until the surface of the first silicon layer is exposed; S5, laterally etch the silicon-germanium layer to expose the gap between the second silicon layers as an inner isolation layer; S6, forming an insulating cover layer that covers the surface of the fin stack structure, the surface of the gate structure, and the surface of the substrate; S7, adjust the longitudinal and transverse etching rate ratio to the first longitudinal and transverse etching rate ratio, and etch back the insulating capping layer to form a longitudinally open morphology, exposing the substrate surface to obtain the first insulating layer; S8, oxidize the exposed first silicon layer to obtain a silicon oxide layer; S9, adjust the longitudinal and transverse etching rate ratio to the second longitudinal and transverse etching rate ratio, and etch back the first insulating layer to form the morphology of the channel sidewall opening, expose the gate structure, and obtain the second insulating layer. The second insulating layer fills the gaps generated by the transverse etching. S10, epitaxial growth of the source and drain.

[0021] The fabrication method of the gate-ring field-effect transistor provided in this embodiment achieves fine-tuning of the morphology by controlling the longitudinal and transverse etching rate ratio during the etching of the insulating capping layer. This not only allows the first silicon layer to be fully exposed and oxidized to form a silicon oxide layer as a barrier layer, effectively preventing the formation of parasitic channels, but also avoids the influence of oxidation on the gate structure. This solves the problem of how to eliminate parasitic paths in the gate-ring field-effect transistor to improve device performance.

[0022] Specifically, in this embodiment, step S1, as shown in FIG2(A), involves providing a substrate 100.

[0023] In this embodiment, the substrate 100 includes a dielectric layer 101 and a first silicon layer 102 located in the dielectric layer 101, with the top of the first silicon layer 102 exposed on the surface of the substrate 100. In practical applications, the dielectric layer 101 can be made of silicon oxide.

[0024] Of course, in practical applications, the substrate 100 may also contain other device structures, such as metal interconnect layers, which will not be elaborated in this application.

[0025] Furthermore, in this embodiment, step S2, as shown in FIG2(B), forms a fin stack structure 110 on the first silicon layer 102. The fin stack structure 110 includes a silicon-germanium layer 111 and a second silicon layer 112 formed alternately from bottom to top.

[0026] The specific formation method of the fin stack structure 110 is something that those skilled in the art can obtain in the existing manufacturing methods of gate-around field-effect transistors, and will not be described in detail here.

[0027] In practical applications, the atomic ratio of silicon to germanium in the silicon-germanium layer 111 is 0.7:0.3 to 0.8:0.2. Furthermore, in practical applications, the thickness of the multiple silicon-germanium layers 111 is consistent, for example, 8nm to 10nm, specifically 10nm; the thickness of the multiple second silicon layers 112 is consistent, for example, 4nm to 6nm, specifically 5nm.

[0028] Furthermore, in this embodiment, step S3, as shown in FIG2(C), involves forming a gate structure 120 on the substrate 100. The gate structure 120 covers the top and sidewalls of the partial fin stack structure 110. FIG2(C) shows a schematic diagram of the device structure along the length direction on the left and a cross-sectional view of the device structure along the width direction on the right.

[0029] In practical applications, the surface of the gate structure 120 is covered by a dielectric layer, which can be silicon nitride. Furthermore, the specific formation method of the gate structure 120 is obtainable by those skilled in the art in the manufacture of existing gate-to-ring field-effect transistors, and will not be elaborated further in this application.

[0030] Furthermore, in this embodiment, step S4, as shown in FIG2(D), uses the gate structure 120 as a mask to etch the fin stack structure 110 until the surface of the first silicon layer 102 is exposed.

[0031] Specifically, in this embodiment, the second silicon layer 112 and the silicon-germanium layer 111 of the fin stack structure 110 are etched sequentially. In Figure 2(D), the left side shows a schematic diagram of the device structure along the length direction, and the dashed line represents the fin stack structure 110 covered by the gate structure 120. The right side shows a cross-sectional view of the device structure along the width direction.

[0032] The specific method of sequentially etching the fin stack structure 110 is something that those skilled in the art can obtain in the existing manufacturing methods of gate-around field-effect transistors, and will not be described in detail here.

[0033] Furthermore, in this embodiment, step S5, as shown in FIG2(E), involves laterally etching the silicon-germanium layer 111 to expose the gap between portions of the second silicon layer 112 as an inner isolation layer.

[0034] Specifically, in this embodiment, lateral etching is achieved by adjusting the lateral-to-longitudinal etching rate ratio. At this time, approximately 3-5 nm of the silicon-germanium layer 111 between the second silicon layers 112 is removed by lateral etching, allowing the exposed 3-5 nm spacing between the second silicon layers 112 to serve as an inner spacer. Figure 2(E) shows a schematic diagram of the device structure along its length on the left and a cross-sectional view of the device structure along its width on the right. The dashed lines and gray background in the figures represent the silicon-germanium layer 111 retained within the gate structure 120 after lateral etching.

[0035] Furthermore, in this embodiment, step S6, as shown in FIG2(F), forms an insulating cover layer 130, which covers the surface of the fin stack structure 110, the surface of the gate structure 120 and the surface of the substrate 100.

[0036] Specifically, in this embodiment, an insulating capping layer 130 can be formed on the surface of the fin stack structure 110, the gate structure 120, and the substrate 100 using atomic layer deposition (ALD). The insulating capping layer 130 can simultaneously fill the gaps formed by lateral etching. The thickness of the insulating capping layer 130 is consistent with the thickness of the silicon-germanium layer 111 to ensure that the gaps formed by lateral etching are completely filled by the insulating capping layer 130. For example, in this embodiment, the thickness of the silicon-germanium layer 111 is 8~10 nm, therefore, the thickness of the insulating capping layer 130 is also 8~10 nm. Figure 2(F) shows a schematic diagram of the device structure along the length direction on the left, displaying the device structure inside the insulating capping layer 130 in perspective, and a cross-sectional view of the device structure along the width direction on the right.

[0037] In practical applications, the insulating cover layer 130 can be made of insulating materials such as Si3N4, SiOC, SiON, SiCN, or SiBCN.

[0038] Furthermore, in this embodiment, in step S7, as shown in FIG2(G), the longitudinal and transverse etching rate ratio is adjusted to the first longitudinal and transverse etching rate ratio, and the insulating cover layer 130 is etched back to form a longitudinally open morphology, exposing the surface of the substrate 100, and the first insulating layer 131 is obtained.

[0039] Specifically, in this embodiment, the first longitudinal-to-transverse etching rate ratio is 2:1. This allows the portion of the insulating capping layer 130 deposited on the horizontal plane to be removed at a faster rate, while the portion deposited on the vertical plane (sidewall of the gate structure 120) can be retained, forming a longitudinally open morphology. At this point, the resulting first insulating layer 131 is exposed on the surface of the substrate 100, filling the gaps formed by the transverse etching and covering the sidewall of the gate structure 120. Thus, during subsequent oxidation, while oxidizing the first silicon layer 102, oxidation of the second silicon layer 112 and the surface of the gate structure 120 can be avoided, ensuring the integrity and effectiveness of the device structure. Figure 2(G) shows a schematic diagram of the device structure along its length, displaying the device structure inside the first insulating layer 131 in perspective, on the left, and a cross-sectional view of the device structure along its width.

[0040] In practical applications, reactive ion etching (RIE) can be used to etch back the insulating capping layer 130 to obtain the first insulating layer 131.

[0041] Furthermore, in this embodiment, step S8, as shown in FIG2(H), oxidizes the exposed first silicon layer 102 to obtain silicon oxide layer 140.

[0042] Specifically, in this embodiment, oxidation can be performed using a self-aligned oxidation process to oxidize the first silicon layer 102, thereby oxidizing the surface of the first silicon layer 102 into a silicon oxide layer 140. This silicon oxide layer 140 serves as an isolation barrier layer, preventing the formation of parasitic channels between the fin stack structure 110 and the first silicon layer 102 after epitaxial growth of the source and drain electrodes, thus improving the device's turn-off performance. Figure 2(H) shows a schematic diagram of the device structure along its length, displaying the device structure inside the first insulating layer 131 in perspective, on the left. The figure on the right is a cross-sectional view of the device structure along its width.

[0043] Furthermore, in this embodiment, in step S9, as shown in FIG2(I), the longitudinal and transverse etching rate ratio is adjusted to the second longitudinal and transverse etching rate ratio, and the first insulating layer 131 is etched back to form the morphology of the channel sidewall opening, exposing the gate structure 120, and obtaining the second insulating layer 132, which fills the gap generated by the transverse etching.

[0044] Specifically, in this embodiment, the second longitudinal-to-transverse etching rate ratio is 1:1. This effectively removes the first insulating layer 131 on the sidewall of the gate structure 120 while retaining the first insulating layer 131 in the gap formed by the transverse etching, resulting in the second insulating layer 132. Figure 2(I) shows a schematic diagram of the device structure along its length, revealing the internal structure of the second insulating layer 132 in perspective, on the left, and a cross-sectional view of the device structure along its width. In practical applications, due to limitations in the etching process, a small amount of the first insulating layer 131 may remain at the interface between the gate structure 120 and the substrate 100 (the first insulating layer 131 at the interface is not shown in Figure 2(I)).

[0045] In practical applications, reactive ion etching (RIE) can be used to etch back the first insulating layer 131 to obtain the second insulating layer 132.

[0046] Furthermore, in this embodiment, step S10, as shown in FIG2(J), involves epitaxially growing a source electrode 151 and a drain electrode 152.

[0047] The specific implementation of epitaxial growth of the source 151 and drain 152 is something that those skilled in the art can obtain in the existing manufacturing methods of gate-around field-effect transistors, and will not be described in detail here. Among them, the left side of Figure 2(J) is a schematic diagram of the device structure along the length direction, showing the internal device structure of the source 151 and drain 152 in a perspective manner, and the right side is a cross-sectional view of the device structure along the width direction.

[0048] The fabrication method of the gate-around field-effect transistor provided in this embodiment forms an insulating capping layer 130 after lateral etching of the silicon-germanium layer 111. By utilizing a first longitudinal-to-lateral etching rate ratio to etch back the insulating capping layer 130, the resulting first insulating layer 131 not only covers the gap exposed by the lateral etching but also covers the sidewalls of the gate structure 120, while simultaneously exposing the first silicon layer 102 on the substrate 100. Thus, when oxidizing the first silicon layer 102, damage to the second silicon layer 112 and the gate structure 120 caused by the oxidation process can be avoided, ensuring the integrity of the device structure. By oxidizing the first silicon layer 102 on the substrate 100... The first silicon layer 102 is oxidized to form a silicon oxide layer 140 on its surface. This silicon oxide layer 140 acts as a barrier layer, effectively preventing parasitic channels between the fin stack structure 110 and the substrate 100, thus improving the device's turn-off performance. By etching back the first insulating layer 131 using a second longitudinal-to-transverse etch rate ratio, the residual insulating capping layer 130 on the surface of the gate structure 120 is completely removed, while retaining the insulating capping layer 130 in the transverse etch gaps. This ensures that the source 151 and drain 152 have good morphology during epitaxial growth, guaranteeing device quality. Thus, high-quality source-drain epitaxial growth is achieved, solving the problem of eliminating parasitic paths in gate-around field-effect transistors to improve device performance.

[0049] This embodiment also provides a gate-around field-effect transistor, which is manufactured using the gate-around field-effect transistor fabrication method described above, such as... Figure 3 and Figure 4 As shown (where the structure within the source and drain is shown in perspective), the gate-ring field-effect transistor includes a substrate 100 and a fin stack structure 110; the substrate 100 includes a dielectric layer 101 and a first silicon layer 102 located in the dielectric layer 101, a silicon oxide layer 140 is formed on top of the first silicon layer 102, and the silicon oxide layer 140 constitutes a part of the surface of the substrate 100; the fin stack structure 110 is located on top of the silicon oxide layer 140; a gate structure 120 is covered on a portion of the top and a portion of the sidewalls of the fin stack structure 110; the fin stack structure 110 covered by the gate structure 120 includes alternating layers of silicon-germanium layers 111 and second silicon layers 112 from bottom to top; the exposed fin stack structure 110 includes alternating layers of a second insulating layer 132 and a second silicon layer 112 from bottom to top; a source 151 and a drain 152 are epitaxially grown at the exposed fin stack structure 110.

[0050] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0051] The ring-gate field-effect transistor and its fabrication method provided in this embodiment include: providing a substrate, the substrate including a dielectric layer and a first silicon layer located in the dielectric layer, the top of the first silicon layer being exposed on the surface of the substrate; forming a fin stack structure on the first silicon layer, the fin stack structure including alternating layers of silicon-germanium layers and second silicon layers formed from bottom to top; forming a gate structure on the substrate, the gate structure covering the top and sidewalls of a portion of the fin stack structure; using the gate structure as a mask, etching the fin stack structure until the surface of the first silicon layer is exposed; laterally etching the silicon-germanium layers, with the spacing between the exposed portions of the second silicon layers serving as... An inner isolation layer is formed; an insulating capping layer is formed, which covers the surface of the fin stack structure, the surface of the gate structure, and the surface of the substrate; the longitudinal and transverse etch rate ratio is adjusted to a first longitudinal and transverse etch rate ratio, and the insulating capping layer is etched back to form a longitudinal window morphology, exposing the substrate surface to obtain the first insulating layer; the exposed first silicon layer is oxidized to obtain a silicon oxide layer; the longitudinal and transverse etch rate ratio is adjusted to a second longitudinal and transverse etch rate ratio, and the first insulating layer is etched back to form a channel sidewall window morphology, exposing the gate structure to obtain the second insulating layer, which fills the gaps generated by the transverse etch; the source and drain are epitaxially grown. By controlling the longitudinal and transverse etch rate ratio during the etching of the insulating capping layer, the morphology can be finely adjusted, thereby not only allowing the first silicon layer to be fully exposed and oxidized to form a silicon oxide layer as a barrier layer, effectively preventing the formation of parasitic channels, but also avoiding the influence of oxidation on the gate structure, thus solving the problem of how to eliminate parasitic paths in gate-around field-effect transistors to improve device performance.

[0052] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a gate-to-ring field-effect transistor, characterized in that, include: A substrate is provided, the substrate including a dielectric layer and a first silicon layer located in the dielectric layer, the surface of the substrate exposing the top of the first silicon layer; A fin stack structure is formed on a first silicon layer, the fin stack structure comprising alternating layers of silicon-germanium layers and a second silicon layer formed from bottom to top; A gate structure is formed on a substrate, the gate structure covering the top and sidewalls of a partial fin stack structure; Using the gate structure as a mask, the fin stack structure is etched until the surface of the first silicon layer is exposed; Laterally etch the silicon-germanium layer to expose the gap between the second silicon layers as an inner isolation layer; An insulating capping layer is formed, which covers the surface of the fin stack structure, the surface of the gate structure, and the surface of the substrate; The longitudinal and transverse etching rate ratio is adjusted to the first longitudinal and transverse etching rate ratio, and the insulating capping layer is etched back to form a longitudinally open morphology, exposing the substrate surface and obtaining the first insulating layer; The first exposed silicon layer is oxidized to obtain a silicon oxide layer; The longitudinal and transverse etching rate ratio is adjusted to the second longitudinal and transverse etching rate ratio. The first insulating layer is etched back to form the morphology of the channel sidewall opening, exposing the gate structure and obtaining the second insulating layer. The second insulating layer fills the gaps generated by the transverse etching. Epitaxial growth of source and drain electrodes.

2. The method for fabricating a gate-to-ring field-effect transistor according to claim 1, characterized in that, The silicon-germanium layer is etched laterally to a depth of 3-5 nm.

3. The method for fabricating a gate-to-ring field-effect transistor according to claim 1, characterized in that, The insulating covering layer is made of Si3N4, SiOC, SiON, SiCN, or SiBCN.

4. The method for fabricating a gate-to-ring field-effect transistor according to claim 1, characterized in that, The method for forming the insulating covering layer includes: An insulating capping layer is formed on the surface of the fin stack structure, the gate structure surface, and the substrate surface using an atomic layer deposition process. The thickness of the insulating capping layer is consistent with the thickness of the silicon-germanium layer.

5. The method for fabricating a gate-to-ring field-effect transistor according to claim 1, characterized in that, The first longitudinal and transverse etching rate ratio is 2:

1.

6. The method for fabricating a gate-to-ring field-effect transistor according to claim 1, characterized in that, The second longitudinal and transverse etching rate ratio is 1:

1.

7. The method for fabricating a gate-to-ring field-effect transistor according to claim 1, characterized in that, The insulating capping layer is etched back using a reactive ion etching process to obtain the first insulating layer.

8. The method for fabricating a gate-to-ring field-effect transistor according to claim 1, characterized in that, The first insulating layer is etched back using reactive ion etching to obtain the second insulating layer.

9. A gate-to-ring field-effect transistor, manufactured using the method for fabricating a gate-to-ring field-effect transistor as described in any one of claims 1 to 8, characterized in that, The gate-around field-effect transistor includes a substrate and a fin stacked structure; the substrate includes a dielectric layer and a first silicon layer located in the dielectric layer, and a silicon oxide layer is formed on top of the first silicon layer, the silicon oxide layer constituting a part of the surface of the substrate; The fin stack structure is located on top of the silicon oxide layer; The top and sidewalls of the fin stack structure are partially covered by a gate structure; the fin stack structure covered by the gate structure includes alternating layers of silicon-germanium and a second silicon layer arranged from bottom to top; the exposed fin stack structure includes alternating layers of a second insulating layer and a second silicon layer arranged from bottom to top; an active electrode and a drain electrode are epitaxially grown at the exposed fin stack structure.

10. The gate-to-ring field-effect transistor according to claim 9, characterized in that, The material of the second insulating layer is Si3N4, SiOC, SiON, SiCN or SiBCN.

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