SiC mosfet power device and method of manufacturing the same

Abstract

The application provides a SiC MOSFET power device and a preparation method thereof. The SiC MOSFET power device comprises a substrate, an N-type SiC epitaxial layer, a gate, a P-well region, a first N+ region, a P+ region, a second N+ region, a P-type graphene layer, a source and a drain. The N-type SiC epitaxial layer is arranged on the front surface of the substrate. The gate is arranged on the N-type SiC epitaxial layer. The P-well region is arranged in the N-type SiC epitaxial layer and located on both sides of the gate. The first N+ region is arranged in the P-well region and located on both sides of the gate. The P+ region is arranged in the P-well region and located on both sides of the first N+ region. The second N+ region is arranged in the N-type SiC epitaxial layer and located below the gate. The P-type graphene layer is arranged between the gate and the N-type SiC epitaxial layer and connected with the first N+ region and the second N+ region. The source is arranged on the N-type SiC epitaxial layer and located above the P+ region and the first N+ region. The drain is arranged on the back surface of the substrate. The application can improve the carrier channel mobility and reduce the on-resistance while maintaining high voltage resistance, thereby reducing the energy consumption of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a SiC MOSFET power device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) has a wider bandgap, three times that of silicon (Si), resulting in higher breakdown electric field strength, higher thermal conductivity, and better radiation resistance, making it more suitable for fabricating high-power devices. Currently, the bottleneck for SiC vertical-structure metal-oxide-semiconductor field-effect transistors (MOSFETs) lies in reducing their on-resistance, with channel resistance accounting for the majority of this resistance. During the manufacturing process of SiC MOSFETs, significant surface damage and traps are introduced on the channel layer surface, reducing the effective mobility of inversion layer electrons to typically only 10–40 cm⁻¹. 2 / (V·s). Therefore, improving its carrier channel mobility is of great significance. Summary of the Invention

[0003] In view of this, the present invention provides a SiC MOSFET power device and its fabrication method, which can improve carrier channel mobility and reduce on-resistance while maintaining high voltage resistance, thereby reducing the energy consumption of the device.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a SiC MOSFET power device, comprising: Substrate; An N-type SiC epitaxial layer is disposed on the front side of the substrate; The gate is disposed on the N-type SiC epitaxial layer; The P-well region is disposed within the N-type SiC epitaxial layer and located on both sides of the gate. The first N+ region is disposed within the P-well region and located on both sides of the gate, wherein the first N+ region is located on the side of the P-well region away from the substrate; The P+ region is disposed within the P-well region and is located on both sides of the first N+ region; The second N+ region is disposed within the N-type SiC epitaxial layer and located below the gate. A P-type graphene layer is disposed between the gate and the N-type SiC epitaxial layer, and connects the first N+ region and the second N+ region; The source electrode is disposed on the N-type SiC epitaxial layer and located above the P+ region and the first N+ region; and, The drain electrode is disposed on the back side of the substrate.

[0005] Preferably, the gate is a trench structure, the N-type SiC epitaxial layer has a trench, the P-type graphene layer covers the inner surface of the trench, and the gate is disposed in the trench.

[0006] Preferably, the side of the P+ region closest to the substrate is lower than the bottom surface of the trench; and / or, The bottom surface of the trench is lower than the side of the P-well region closest to the substrate; and / or, The width of the groove is 0.3 μm to 1.5 μm.

[0007] Preferably, the substrate comprises a 4H-SiC substrate; and / or, The thickness of the N-type SiC epitaxial layer is 5 μm to 20 μm; and / or, The room-temperature carrier concentration of the N-type SiC epitaxial layer is 5E14 cm⁻¹. -3 ~5E16 cm -3 .

[0008] Preferably, the thickness of the p-type graphene layer is 0.5 nm to 10 nm; and / or, The P-type graphene layer comprises multiple layers of P-type graphene, wherein the number of P-type graphene layers is less than or equal to 5.

[0009] Preferably, the thickness of the P-well region is 0.5 μm to 1 μm; and / or, The doping concentration of the P-well region is 5E16 cm⁻¹. -3 ~5E17 cm -3 ; and / or, The thickness of the first N+ region is 0.1 μm to 0.5 μm; and / or, The doping concentration of the first N+ region is 1E18 cm⁻¹ -3 ~1E21 cm -3 ; and / or, The thickness of the second N+ region is 0.1 μm to 0.3 μm; and / or, The doping concentration of the second N+ region is 1E18 cm⁻¹ -3 ~1E21 cm -3 ; and / or, The thickness of the P+ region is 2 μm to 5 μm; and / or, The doping concentration of the P+ region is 1E18 cm⁻¹ -3 ~1E20 cm -3 .

[0010] Preferably, the SiC MOSFET power device further includes: A gate oxide layer is disposed between the gate electrode and the p-type graphene layer; and / or, A dielectric layer is disposed on the gate; and / or, A source ohmic contact layer is disposed between the source electrode and the N-type SiC epitaxial layer; and / or, A drain ohmic contact layer is disposed between the drain and the substrate.

[0011] Secondly, the present invention also provides a method for fabricating the SiC MOSFET power device, comprising the following steps: S1. An N-type SiC epitaxial layer is formed on the front side of the substrate; S2. Ion implantation is performed on the N-type SiC epitaxial layer to form a P-well region; S3. Ion implantation is performed on the P-well region to form the first N+ region; S4. Ion implantation is performed on the P-well region to form a P+ region; S5. Ion implantation is performed on the N-type SiC epitaxial layer to form a second N+ region, and at least a P-type graphene layer, a gate, and a source are formed on the N-type SiC epitaxial layer. S6. A drain electrode is formed on the back side of the substrate to obtain a SiC MOSFET power device.

[0012] Preferably, the gate is a trench structure, and the SiC MOSFET power device further includes a gate oxide layer, a dielectric layer, and a source ohmic contact layer; step S5 includes: S51. Etch the N-type SiC epitaxial layer to form trenches; S52. Ion implantation is performed on the bottom of the trench to form a second N+ region; S53. A P-type graphene layer is formed in the trench; S54. A gate oxide layer is formed on the P-type graphene layer; S55, A gate is formed in the trench; S56. A dielectric layer is formed on the gate; S57. A source ohmic contact layer is formed on the P+ region and the first N+ region; S58. A source electrode is formed on the source electrode ohmic contact layer.

[0013] Preferably, the SiC MOSFET power device further includes a drain ohmic contact layer; step S6 includes: S61. Thin the back side of the substrate; S62. A drain ohmic contact layer is formed on the back side of the thinned substrate; S63. A drain electrode is formed on the drain ohmic contact layer to obtain a SiC MOSFET power device.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) In this invention, the P-type graphene layer serves as the channel conduction layer, which can improve the carrier channel mobility and reduce the conduction resistance while maintaining high voltage resistance, thereby reducing the energy consumption of the device.

[0015] (2) In this invention, a deep P structure is used, which can optimize the electric field of the trench grid and improve the shielding effect. Attached Figure Description

[0016] Figure 1 For V GS =0 V, schematic diagram of the contact energy band between the source N+ SiC and P-type graphene; Figure 2 For V GS >V th A schematic diagram of the contact energy band between the source N+ SiC and P-type graphene; Figure 3 This is a schematic diagram of the structure of an embodiment of the SiC MOSFET power device provided by the present invention; Figure 4 A schematic diagram of another embodiment of the SiC MOSFET power device provided by the present invention; Figure 5 This is a schematic diagram of another embodiment of the SiC MOSFET power device provided by the present invention; Figure 6 This is a schematic diagram of another embodiment of the SiC MOSFET power device provided by the present invention; Figure 7 Schematic diagram of electric field line distribution with and without deep P structure during reverse withstand voltage; Figure 8 This is a schematic flowchart of an embodiment of the method for fabricating the SiC MOSFET power device provided by the present invention.

[0017] Explanation of reference numerals in the attached figures: 1. Substrate; 2. N-type SiC epitaxial layer; 3. P-well region; 4. First N+ region; 5. P+ region; 6. Second N+ region; 7. P-type graphene layer; 8. Gate oxide layer; 9. Gate electrode; 10. Dielectric layer; 11. Source ohmic contact layer; 12. Source electrode; 13. Drain electrode. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to specific embodiments, so that those skilled in the art can more clearly understand the present invention.

[0019] In a first aspect, the present invention provides a SiC MOSFET power device, see [link to relevant documentation]. Figures 3-6 The SiC MOSFET power device includes a substrate 1, an N-type SiC epitaxial layer 2, a gate 9, a P-well region 3, a first N+ region 4, a P+ region 5, a second N+ region 6, a P-type graphene layer 7, a source 12, and a drain 13. The N-type SiC epitaxial layer 2 is disposed on the front side of the substrate 1. The gate 9 is disposed on the N-type SiC epitaxial layer 2. The P-well region 3 is disposed within the N-type SiC epitaxial layer 2 and located on both sides of the gate 9. The first N+ region 4 is disposed within the P-well region 3 and located on both sides of the gate 9. The P-well region 3 is located on the side away from the substrate 1; the P+ region 5 is disposed within the P-well region 3 and is located on both sides of the first N+ region 4; the second N+ region 6 is disposed within the N-type SiC epitaxial layer 2 and is located below the gate 9; the P-type graphene layer 7 is disposed between the gate 9 and the N-type SiC epitaxial layer 2 and connects the first N+ region 4 and the second N+ region 6; the source 12 is disposed on the N-type SiC epitaxial layer 2 and is located above the P+ region 5 and the first N+ region 4; the drain 13 is disposed on the back side of the substrate 1.

[0020] In this invention, the P-type graphene layer 7 serves as the channel conduction layer, which can improve carrier channel mobility and reduce conduction resistance while maintaining high voltage resistance, thereby reducing the energy consumption of the device.

[0021] It should be noted that during forward conduction, the high carrier mobility of graphene can effectively reduce the channel resistance. The following analysis examines the working principle, and based on band theory, the following band structure diagrams are drawn for different steady states. The band gap of SiC is 3.23 eV, while the band gap of graphene is 0 eV. When V... GS =0 V, when off or reverse biased, the contact between the source N+SiC and the p-type graphene is as follows: Figure 1 As shown, the work function of p-type graphene is between 4.8 eV and 5.2 eV, while that of N+SiC is between 3.7 eV and 4.3 eV. When the two come into contact, the energy band of N+SiC bends upward, and the huge built-in electric field forms a high electron blocking layer, which can suppress the movement of electrons from the drain 13 to the source 12. When V GS >V thWhen p-type graphene is inverted to n-type graphene, the work function of the inverted graphene is between 4.0 eV and 4.4 eV. Suitable parameters can make the work function of the inverted graphene less than or equal to that of N+ SiC. In this case, the contact between graphene and N+ SiC approximates an ohmic contact. The energy band diagram is shown below. Figure 2 As shown, electrons flow from N+ SiC to inverted graphene without or with a small barrier. The contact principle between graphene and N+ SiC in the epitaxial layer is similar to that at source 12.

[0022] Besides improving on-resistance, p-type graphene can also enhance the dynamic performance of devices. Graphene's ultra-high electron mobility means extremely short channel carrier transit times, and its excellent gate control capability can accelerate the charging and discharging of the gate capacitor, increasing switching speed. Faster switching speeds can directly shorten the voltage / current overlap time, thereby significantly reducing energy loss per switch (E0). on E off Due to the extremely low channel resistance of graphene, the gate over-drive voltage required to achieve the same conduction current may be lower, potentially reducing the total gate charge; graphene itself has extremely high thermal conductivity, which facilitates lateral heat diffusion in the channel, enhancing heat dissipation and resulting in lower Ro. on This can also fundamentally reduce the source of heat.

[0023] It is understood that the P-well region 3 is located close to the upper surface of the N-type SiC epitaxial layer 2, and the first N+ region 4 and P+ region 5 are formed within the P-well region 3. The upper surfaces of the first N+ region 4 and P+ region 5 coincide with the upper surface of the N-type SiC epitaxial layer 2. The downward projection of the source 12 at least partially covers the P+ region 3 and at least partially covers the first N+ region 4. The gate 9 is disposed on the N-type SiC epitaxial layer 2, and the gate 9 can be a planar structure (e.g., Figure 5 As shown), it can also be a trench structure (such as...). Figures 3-4 and Figure 6 (As shown); when the gate is a planar structure, please refer to... Figure 5 The SiC MOSFET power device is a planar SiC MOSFET power device. The P-type graphene layer 7 is located on the upper surface of the N-type SiC epitaxial layer 2 and below the gate 9. When forward conducting, a positive voltage V is applied to the gate 9. GS >V th P-type graphene undergoes inversion with the surface layer of P-well SiC, forming rapid electron channels in the graphene layer; applying V DS When the voltage is greater than 0 V, electrons in the source electrode 12 flow rapidly to the graphene, from the graphene to the N+ SiC bulk, then to the N-type SiC epitaxial layer 2, and finally to the drain electrode 13.

[0024] In some embodiments, please refer to Figure 3The gate 9 has a trench structure. A trench is formed on the N-type SiC epitaxial layer 2, and the P-type graphene layer 7 covers the inner surface of the trench. The gate 9 is disposed within the trench. This SiC MOSFET power device is a trench-type SiC MOSFET power device. It should be noted that... (Please refer to...) Figure 4 The N-type SiC epitaxial layer 2 can adopt a superjunction structure. The trench-type SiC MOSFET power device is a trench-type SiC MOSFET device with a superjunction structure, which has better on-resistance and reverse breakdown voltage performance. It can be understood that the inner surface of the trench includes the bottom surface and the side surface, the gate 9 is located on the P-type graphene layer 7, and the second N+ region 6 is disposed in the N-type SiC epitaxial layer 2, located at the bottom of the trench.

[0025] In some embodiments, please refer to Figure 3 The side of the P+ region 5 closest to the substrate 1 is lower than the bottom surface of the trench. The P+ region 5 is configured as a deep P structure. It should be noted that the work function of p-type graphene is higher than that of intrinsic graphene, and its Fermi level will shift its intrinsic Dirac point, modulating it above the valence band. At this time, the graphene layer generates movable holes, attracting electrons from the underlying N-SiC, forming a depletion region. In this state, the p-type graphene has a certain electric field shielding effect. However, its shielding effect is limited; the shielding capability of graphene (determined by its quantum capacitance and density of states) strongly depends on the Fermi level. In the reverse breakdown state (high V... ds When Vgs=0, the entire device is in a depletion state, and the graphene is in a P-type state. Furthermore, the deep P-structure can optimize the electric field of the trench gate, improving the shielding effect. For example... Figure 7 As shown, devices without deep P-structures (such as...) Figure 7 As shown in (a), the side of P+ region 5 closest to substrate 1 is not lower than the bottom surface of the trench. Electric field lines will accumulate at the bottom and corners of the trench, which will cause the gate oxide to break down. Devices with deep P-structures (such as...) Figure 7 (b) As shown, the P+ regions 5 on both sides will terminate most of the electric field, reducing the electric field pressure at the bottom of the trench.

[0026] In some embodiments, the bottom surface of the trench is lower than the side of the P-well region 3 closest to the substrate 1.

[0027] In some embodiments, please refer to Figure 6 The bottom surface of the trench is higher than the side of the P-well region 3 near the substrate 1, and the side of the second N+ region 6 near the substrate 1 is lower than the side of the P-well region 3 near the substrate 1. The second N+ region 6 extends to the N-type SiC epitaxial layer 2, and the trench corners are protected by the P-well region 3, achieving a better shielding effect during reverse breakdown voltage.

[0028] In some embodiments, the width of the trench is 0.3 μm to 1.5 μm.

[0029] In some embodiments, the substrate 1 comprises a 4H-SiC substrate.

[0030] In some embodiments, the thickness of the N-type SiC epitaxial layer 2 is 5 μm to 20 μm.

[0031] In some embodiments, the room-temperature carrier concentration of the N-type SiC epitaxial layer 2 is 5E14 cm⁻¹. -3 ~5E16 cm -3 .

[0032] In some embodiments, the thickness of the P-type graphene layer 7 is 0.5 nm to 10 nm.

[0033] In some embodiments, the p-type graphene layer 7 comprises multiple p-type graphene layers 7, wherein the number of p-type graphene layers 7 is less than or equal to 5. It should be noted that inserting graphene between SiC and the metal, with an increase in the number of layers, helps to lower the potential barrier and form an ohmic contact; therefore, fewer graphene layers can further reduce the work function of the graphene layer, making it easier to control the work function of the inversion graphene to match the work function of N+ SiC; thus achieving inversion faster, reaching the expected work function, and being more beneficial to switching performance.

[0034] In some embodiments, the thickness of the P-well region 3 is 0.5 μm to 1 μm.

[0035] In some embodiments, the doping concentration of the P-well region 3 is 5E16 cm⁻¹. -3 ~5E17 cm -3 .

[0036] In some embodiments, the thickness of the first N+ region 4 is 0.1 μm to 0.5 μm.

[0037] In some embodiments, the doping concentration of the first N+ region 4 is 1E18 cm⁻¹. -3 ~1E21 cm -3 .

[0038] In some embodiments, the thickness of the second N+ region 6 is 0.1 μm to 0.3 μm.

[0039] In some embodiments, the doping concentration of the second N+ region 6 is 1E18 cm⁻¹. -3 ~1E21 cm -3 .

[0040] In some embodiments, the thickness of the P+ region 5 is 2 μm to 5 μm.

[0041] In some embodiments, the doping concentration of the P+ region 5 is 1E18 cm⁻¹. -3 ~1E20 cm -3 .

[0042] In some embodiments, the SiC MOSFET power device further includes a gate oxide layer 8 disposed between the gate 9 and the p-type graphene layer 7. It is understood that the gate oxide layer 8 covers the inner surface of the trench.

[0043] The gate oxide layer 8 is made of a material with a high dielectric constant. In some embodiments, the material of the gate oxide layer 8 includes at least one of halide, aluminum oxide, and titanium oxide.

[0044] In some embodiments, the thickness of the gate oxide layer 8 is 10 nm to 100 nm.

[0045] In some embodiments, the SiC MOSFET power device further includes a dielectric layer 10 disposed on the gate 9. The dielectric layer 10 is used to protect the gate 9.

[0046] In some embodiments, the material of the dielectric layer 10 includes at least one of silicon oxide and silicon nitride.

[0047] In some embodiments, the thickness of the dielectric layer 10 is 200 nm to 1000 nm.

[0048] In some embodiments, the SiC MOSFET power device further includes a source ohmic contact layer 11, which is disposed between the source 12 and the N-type SiC epitaxial layer 2. It is understood that the source ohmic contact layer 11 is located on the P+ region 3 and the first N+4 region.

[0049] In some embodiments, the material of the source ohmic contact layer 11 includes Ni.

[0050] In some embodiments, the SiC MOSFET power device further includes a drain ohmic contact layer disposed between the drain 13 and the substrate 1.

[0051] In some embodiments, the material of the drain ohmic contact layer includes Ni.

[0052] The gate 9 is a metal gate, and in some embodiments, the material of the gate 9 includes Au.

[0053] In some embodiments, the material of the source electrode 12 includes Al.

[0054] In some embodiments, the material of the drain electrode 13 includes a TiNiAg alloy.

[0055] Secondly, the present invention also provides a method for fabricating the SiC MOSFET power device, comprising the following steps: S1. An N-type SiC epitaxial layer 2 is formed on the front side of substrate 1; S2. Ion implantation is performed on the N-type SiC epitaxial layer 2 to form a P-well region 3; S3. Ion implantation is performed on the P-well region 3 to form the first N+ region 4; S4. Ion implantation is performed on the P-well region 3 to form the P+ region 5; S5. Ion implantation is performed on the N-type SiC epitaxial layer 2 to form a second N+ region 6, and at least a P-type graphene layer 7, a gate 9, and a source 12 are formed on the N-type SiC epitaxial layer 2. S6. A drain 13 is formed on the back side of the substrate 1 to obtain a SiC MOSFET power device.

[0056] It should be noted that the ion implantation in steps S2 to S5 can be carried out by channel implantation or a combination of channel implantation and non-channel implantation. Specifically, Al atoms can be implanted into P-well region 3 and P+ region 5, and N atoms or P atoms can be implanted into the first N+ region 4 and the second N+ region 6.

[0057] In some embodiments, in step S5, the P-type graphene layer 7 is formed by in-situ growth. It should be noted that the P-type graphene layer 7 can be formed using one of the following two in-situ growth methods: The first in-situ growth method involves first etching the N-type SiC epitaxial layer 2 in a hydrogen atmosphere at 1600 °C; the graphene synthesis process relies on the dynamic process of argon laminar flow, which can suppress silicon sublimation. Then, in-situ hydrogen intercalation is achieved at 1000 °C in an argon atmosphere of 900 mbar to form the P-type graphene layer 7. The second in-situ growth method involves first depositing a layer of Ni and Cu on the surface of the N-type SiC epitaxial layer 2, annealing it at 1100 °C under ultra-high vacuum, and then completely etching away the surface metal using wet etching to form the P-type graphene layer 7. When the p-type graphene layer 7 is a multilayer structure, controlled irradiation can be used to treat the graphene, induce defects, and enhance the covalent bond points between layers, thereby improving adhesion without excessively damaging the electrical properties of the graphene. Low-energy irradiation (such as ion beams <1 keV and <1×10⁻⁶) is typically used. 13 atoms / cm 2Electron beams of <10 keV and <10 kGy are used to limit damage to the surface or near-surface region, avoiding excessive penetrating damage.

[0058] In some embodiments, the gate 9 is a trench structure, and the SiC MOSFET power device further includes a gate oxide layer 8, a dielectric layer 10, and a source ohmic contact layer 11; step S5 includes: S51. Etch the N-type SiC epitaxial layer 2 to form trenches; S52. Ion implantation is performed on the bottom of the trench to form a second N+ region 6; S53. A P-type graphene layer 7 is formed in the trench; S54. A gate oxide layer 8 is formed on the P-type graphene layer 7; S55, A gate 9 is formed in the trench; S56. A dielectric layer 10 is formed on the gate 9; S57. A source ohmic contact layer 11 is formed on the P+ region 5 and the first N+ region 4. S58. A source electrode 12 is formed on the source electrode ohmic contact layer 11.

[0059] In some embodiments, step S57 includes: depositing an ohmic contact metal on the N-type SiC epitaxial layer 2, and annealing it via RTA to form a source ohmic contact layer 11; wherein the annealing temperature is 750 ℃~1000 ℃, and the annealing time is 0.5 min~5 min.

[0060] In some embodiments, the SiC MOSFET power device further includes a drain ohmic contact layer; step S6 includes: S61. Thin the back side of the substrate 1; S62. A drain ohmic contact layer is formed on the back side of the thinned substrate 1; S63. A drain electrode 13 is formed on the drain ohmic contact layer to obtain a SiC MOSFET power device.

[0061] In some embodiments, in step S61, after the back side is thinned, the overall thickness of the wafer is less than or equal to 50 μm.

[0062] In some embodiments, step S62 includes: depositing an ohmic contact metal on the back side of the thinned substrate 1, followed by laser annealing to form a drain ohmic contact layer; wherein the laser pulse energy is 2 J / cm². 2 ~5 J / cm 2 .

[0063] In one embodiment, please refer to Figure 8The method for fabricating the SiC MOSFET power device includes the following steps: Step 1: Epitaxially grow an N-type SiC epitaxial layer 2 on the front side of a 4H-SiC substrate 1; Step 2: Form a P-well region 3 in the N-type SiC epitaxial layer 2 by ion implantation; Step 3: Form the first N+ region 4 in P-well region 3 by ion implantation; Step 4: Form P+ region 5 in P-well region 3 by ion implantation; Step 5: Form trenches in the N-type SiC epitaxial layer 2 by dry etching; Step 6: Form a second N+ region 6 at the bottom of the trench by ion implantation, then activate it at high temperature and protect the surface with a carbon film; Step 7: Form a P-type graphene layer 7 in situ within the trench and on the surface of the N-type SiC epitaxial layer 2; Step 8: Deposit a high dielectric constant gate oxide layer 8 on the surface of the P-type graphene layer 7; Step 9: Deposit gate metal in the trench and etch it back into the trench to form gate 9; Step 10: Deposit dielectric layer 10 on the gate 9 and the surface of N-type SiC epitaxial layer 2, and form dielectric layer 10 on gate 9 by mask etching, and etch the remaining area to the surface of N-type SiC epitaxial layer 2. Step 11: Deposit a 12-ohm contact metal for the source electrode on the surface of the N-type SiC epitaxial layer 2, anneal it to form the source ohm contact layer 11, and clean the ohm contact metal in the remaining area. Step 12: Deposit electrode metal on the surface of the source ohmic contact layer 11 to form the source 12; Step 13, thinning the back substrate 1; Step 14: Deposit electrode metal on the back side of substrate 1 to form drain 13, thus obtaining SiC MOSFET power device.

[0064] Unless otherwise specified, all raw materials used in this invention are existing substances that can be purchased directly from the market.

[0065] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A SiC MOSFET power device, characterized in that, include: Substrate; An N-type SiC epitaxial layer is disposed on the front side of the substrate; The gate is disposed on the N-type SiC epitaxial layer; The P-well region is disposed within the N-type SiC epitaxial layer and located on both sides of the gate. The first N+ region is disposed within the P-well region and located on both sides of the gate, wherein the first N+ region is located on the side of the P-well region away from the substrate; The P+ region is disposed within the P-well region and is located on both sides of the first N+ region; The second N+ region is disposed within the N-type SiC epitaxial layer and located below the gate. A P-type graphene layer is disposed between the gate and the N-type SiC epitaxial layer, and connects the first N+ region and the second N+ region; The source electrode is disposed on the N-type SiC epitaxial layer and located above the P+ region and the first N+ region; and, The drain electrode is disposed on the back side of the substrate.

2. The SiC MOSFET power device according to claim 1, characterized in that, The gate is a trench structure, with trenches formed on the N-type SiC epitaxial layer, the P-type graphene layer covering the inner surface of the trenches, and the gate disposed within the trenches.

3. The SiC MOSFET power device according to claim 2, characterized in that, The side of the P+ region closest to the substrate is lower than the bottom surface of the trench; and / or, The bottom surface of the trench is lower than the side of the P-well region closest to the substrate; and / or, The width of the groove is 0.3 μm to 1.5 μm.

4. The SiC MOSFET power device according to claim 2, characterized in that, The substrate includes a 4H-SiC substrate; and / or, The thickness of the N-type SiC epitaxial layer is 5 μm to 20 μm; and / or, The room-temperature carrier concentration of the N-type SiC epitaxial layer is 5E14 cm⁻¹. -3 ~5E16 cm -3 .

5. The SiC MOSFET power device according to claim 2, characterized in that, The thickness of the p-type graphene layer is 0.5 nm to 10 nm; and / or, The P-type graphene layer comprises multiple layers of P-type graphene, wherein the number of P-type graphene layers is less than or equal to 5.

6. The SiC MOSFET power device according to claim 2, characterized in that, The thickness of the P-well region is 0.5 μm to 1 μm; and / or, The doping concentration of the P-well region is 5E16 cm⁻¹. -3 ~5E17 cm -3 ; and / or, The thickness of the first N+ region is 0.1 μm to 0.5 μm; and / or, The doping concentration of the first N+ region is 1E18 cm⁻¹ -3 ~1E21 cm -3 ; and / or, The thickness of the second N+ region is 0.1 μm to 0.3 μm; and / or, The doping concentration of the second N+ region is 1E18 cm⁻¹ -3 ~1E21 cm -3 ; and / or, The thickness of the P+ region is 2 μm to 5 μm; and / or, The doping concentration of the P+ region is 1E18 cm⁻¹ -3 ~1E20 cm -3 .

7. The SiC MOSFET power device according to claim 2, characterized in that, The SiC MOSFET power device also includes: A gate oxide layer is disposed between the gate electrode and the p-type graphene layer; and / or, A dielectric layer is disposed on the gate; and / or, A source ohmic contact layer is disposed between the source electrode and the N-type SiC epitaxial layer; and / or, A drain ohmic contact layer is disposed between the drain and the substrate.

8. The method for fabricating a SiC MOSFET power device according to any one of claims 1 to 7, characterized in that, Includes the following steps: S1. An N-type SiC epitaxial layer is formed on the front side of the substrate; S2. Ion implantation is performed on the N-type SiC epitaxial layer to form a P-well region; S3. Ion implantation is performed on the P-well region to form the first N+ region; S4. Ion implantation is performed on the P-well region to form a P+ region; S5. Ion implantation is performed on the N-type SiC epitaxial layer to form a second N+ region, and at least a P-type graphene layer, a gate, and a source are formed on the N-type SiC epitaxial layer. S6. A drain electrode is formed on the back side of the substrate to obtain a SiC MOSFET power device.

9. The method for fabricating a SiC MOSFET power device according to claim 8, characterized in that, The gate is a trench structure, and the SiC MOSFET power device further includes a gate oxide layer, a dielectric layer, and a source ohmic contact layer; step S5 includes: S51. Etch the N-type SiC epitaxial layer to form trenches; S52. Ion implantation is performed on the bottom of the trench to form a second N+ region; S53. A P-type graphene layer is formed in the trench; S54. A gate oxide layer is formed on the P-type graphene layer; S55, A gate is formed in the trench; S56. A dielectric layer is formed on the gate; S57. A source ohmic contact layer is formed on the P+ region and the first N+ region; S58. A source electrode is formed on the source electrode ohmic contact layer.

10. The method for fabricating a SiC MOSFET power device according to claim 8, characterized in that, The SiCMOSFET power device further includes a drain ohmic contact layer; step S6 includes: S61. Thin the back side of the substrate; S62. A drain ohmic contact layer is formed on the back side of the thinned substrate; S63. A drain electrode is formed on the drain ohmic contact layer to obtain a SiC MOSFET power device.

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