A novel trench vdmos structure with high dynamic avalanche resistance

Abstract

The application discloses a novel Trench VDMOS structure with high dynamic avalanche resistance, and belongs to the semiconductor field. The application increases a P+ type high-doped region and a P type buried layer under a source contact hole and at the bottom of a gate respectively on the basis of a conventional Trench VDMOS structure, and the P+ type high-doped region and the P type buried layer play an auxiliary depletion role on an N type epitaxial layer, on the basis of improving the carrier concentration of the N type epitaxial layer, the breakdown voltage is maintained unchanged, and the on-resistance and the on-state loss are reduced; meanwhile, the current path during dynamic avalanche is changed, the opening of a parasitic BJT is effectively inhibited, and therefore the dynamic avalanche resistance of the device is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a novel TrenchVDMOS structure with high dynamic avalanche resistance. Background Technology

[0002] Power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are widely used in high-power applications such as switching power supplies, automotive electronics, and industrial control due to their high input impedance, low drive power, high switching speed, and excellent thermal stability. When conducting large currents, Trench VDMOS (Vertical Double-Diffused MOSFET) exhibits significant advantages due to its trench gate technology, which results in a very low on-state voltage drop. However, in high-voltage and high-temperature environments, Trench VDMOS may experience dynamic avalanche effects, i.e., conduction caused by transient high voltage during off-state operation. This can damage the device, severely impacting its off-state reliability, limiting its use in high-current applications, and seriously jeopardizing system safety and stability.

[0003] Research has found that the activation of parasitic BJTs (bipolar junction transistors) in trench MOS devices is one of the main causes of dynamic avalanche failure. During dynamic avalanche, as the current increases until a certain critical value is reached, the parasitic BJT will activate, further amplifying the avalanche breakdown current inside the device, forming positive feedback, which in turn leads to a rapid increase in the device junction temperature, ultimately causing thermal runaway and burnout. Therefore, suppressing the activation of parasitic BJTs is an important measure to improve the device's resistance to dynamic avalanche.

[0004] Currently, the mainstream approach to suppressing parasitic transistor turn-on is to increase the doping concentration of P-base and reduce the P-base resistance. However, this method not only has limited effectiveness, but also increases the threshold voltage of the device, leading to a significant increase in the on-state loss of the device.

[0005] Therefore, there is an urgent need for a new type of trench MOSFET design with high dynamic avalanche resistance to meet the application requirements of low on-state loss and high off-state reliability of balanced devices. Summary of the Invention

[0006] The purpose of this invention is to provide a novel Trench VDMOS structure with high dynamic avalanche resistance to solve the problem that existing power MOSFET devices are prone to dynamic avalanche failure in high-voltage, high-current application environments.

[0007] To address the aforementioned technical problems, this invention provides a novel TrenchVDMOS structure with high dynamic avalanche resistance, the cell structure of which includes: Drain metal, A silicon substrate and an N-type epitaxial layer are located above the drain metal; the N-type epitaxial layer has a Trench polysilicon gate and a gate oxide layer, a P-base region and an N+ region; above the N+ region are source contact holes, gate contact holes, a SiO2 layer, an interlayer dielectric ILD layer, source metal and gate metal. Below the source contact hole, there is a P+ type highly doped region with deep body contact, and a P-type buried layer is added at the bottom of the Trench gate.

[0008] In one embodiment, the source contact hole and the source metal are located on the upper surface of the interlayer dielectric (ILD) layer in the active region of the VDMOS, and the gate contact hole and the gate metal are located on the upper surface of the interlayer dielectric (ILD) layer in the transition region of the VDMOS. There is a gap between the source contact hole and the gate contact hole, and between the source metal and the gate metal.

[0009] In one embodiment, the P+ type highly doped region and the P type buried layer are not connected.

[0010] In one embodiment, the P-type buried layer is connected to the N-type epitaxial layer, and the doping concentration of the P-type buried layer is 2-3 orders of magnitude higher than that of the N-type epitaxial layer.

[0011] In one embodiment, the doping concentration of the P+ type highly doped region is 1×10⁻⁶. 18 -5×10 18 cm -3 The doping concentration of the P-type buried layer is 3 × 10⁻⁶. 17 -8×10 17 cm -3 .

[0012] This invention provides a novel Trench VDMOS structure with high dynamic avalanche resistance. Based on the conventional Trench VDMOS structure, a P+ type heavily doped region and a P type buried layer are added below the source contact hole and at the bottom of the gate, respectively. These regions play an auxiliary depletion role for the N-type epitaxial layer, increasing the carrier concentration of the N-type epitaxial layer while maintaining a constant breakdown voltage and reducing on-resistance and on-state losses. At the same time, the current path during dynamic avalanche is changed, effectively suppressing the turn-on of parasitic BJTs, thereby greatly improving the dynamic avalanche resistance of the device. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a novel Trench VDMOS with high dynamic avalanche resistance provided by the present invention; Figure 2 This is a schematic diagram of a conventional Trench VDMOS structure; Figure 3 This is a diagram showing the off-state electric field distribution of a conventional Trench VDMOS. Figure 4 This is a diagram showing the off-state electric field distribution of a novel Trench VDMOS with high dynamic avalanche resistance provided by the present invention; Figure 5 This is a schematic diagram of the current path during a conventional Trench VDMOS avalanche. Figure 6 This is a schematic diagram of the current path during an avalanche of a novel Trench VDMOS with high dynamic avalanche resistance provided by the present invention. Detailed Implementation

[0014] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a novel Trench VDMOS structure with high dynamic avalanche resistance proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0015] This invention proposes a novel Trench VDMOS structure with high dynamic avalanche resistance, whose cell structure is as follows: Figure 1As shown, it includes drain metal 1, silicon substrate 2 and N-type epitaxial layer 3 located above drain metal 1; the N-type epitaxial layer 3 has a Trench polysilicon gate 6 and gate oxide layer 5, P-base region 8 and N+ region 9; above N+ region 9 are source contact hole 10, gate contact hole 12, SiO2 layer 15, interlayer dielectric ILD layer 14, source metal 11 and gate metal 13, below source contact hole 10 is a deep body contact P+ type highly doped region 7, and a P-type buried layer 4 is added at the bottom of Trench gate 5.

[0016] The source contact hole 10 and the source metal 11 are located on the upper surface of the interlayer dielectric ILD layer 14 of the active region of the VDMOS, and the gate contact hole 12 and the gate metal 13 are located on the upper surface of the interlayer dielectric ILD layer 14 of the transition region of the VDMOS. There is a gap between the source contact hole 10 and the gate contact hole 12, and between the source metal 11 and the gate metal 13, thereby realizing independent control of the source and gate of the VDMOS.

[0017] The P+ type highly doped region 7 located below the source contact hole and the P-type buried layer 4 located at the bottom of the trench gate are not connected, thus preserving a path for on-state electron current. The P-type buried layer 4 located at the bottom of the trench gate is connected to the N-type epitaxial layer 3, and the doping concentration of the P-type buried layer 4 is much higher than that of the N-type epitaxial layer 3, typically by 2-3 orders of magnitude.

[0018] The P+ type highly doped region 7 located below the source contact hole has a doping concentration of 1×10⁷. 18 -5×10 18 cm -3 The doping concentration of the P-type buried layer 4 located at the bottom of the Trench gate is 3×10⁴. 17 -8×10 17 cm -3 .

[0019] Compared with the solution of the present invention Figure 2 The conventional Trench VDMOS structure shown incorporates a deep-body P+ type highly doped region 7 below the source contact hole 10, and a P-type buried layer 4 at the bottom of the Trench gate 5. Both the P+ type highly doped region 7 and the P-type buried layer 4 work together to assist in the depletion of the N-type epitaxial layer 3, and the electric field distribution is also changed from... Figure 3 The off-state triangular electric field distribution of the conventional TrenchVDMOS shown has been transformed into... Figure 4 The near-trapezoidal electric field distribution of the Trench VDMOS of the present invention shown increases the doping concentration of the N-type epitaxial layer 3 while keeping the breakdown voltage constant, thereby reducing the on-resistance and on-state loss.

[0020] The novel Trench VDMOS structure with high dynamic avalanche resistance proposed in this invention has a different current path during avalanche than the conventional Trench VDMOS structure. A schematic diagram of the current path during avalanche in a conventional Trench VDMOS is shown below. Figure 5 As shown, avalanche breakdown occurs at the bottom of the P-base region. During an avalanche, the avalanche current flows through the P-base region below the N+ region to reach the source contact region. Figure 5 It can be seen from this that the avalanche current flows through the base resistance R of the parasitic BJT transistor. b It will inevitably be in R b When a forward voltage drop is generated on the PN+ junction, and this voltage drop is greater than the forward conduction voltage drop of the PN+ junction, the emitter of the parasitic BJT is forward biased; it enters the amplification region, the breakdown current increases further, and eventually the device burns out.

[0021] The novel Trench VDMOS structure with high dynamic avalanche resistance proposed in this invention, under the common electric field modulation of the P+ type highly doped region and the P type buried layer, avalanche breakdown occurs at the bottom of the P+ type highly doped region. The avalanche current bypasses the P-base region and flows directly through the P+ type highly doped region to reach the source contact region. Its current path is far away from the N+ region, effectively avoiding the base region of the parasitic BJT, thereby greatly improving the dynamic avalanche resistance of the device.

[0022] In summary, this invention provides a novel Trench VDMOS structure with high dynamic avalanche resistance. Based on the conventional Trench VDMOS structure, this structure adds a P+ type heavily doped region below the source contact hole and a P-type buried layer at the bottom of the gate, respectively. These layers act as auxiliary depletion agents for the N-type epitaxial layer, increasing the carrier concentration of the N-type epitaxial layer while maintaining a constant breakdown voltage and reducing on-resistance and on-state losses. Simultaneously, it alters the current path during dynamic avalanche, effectively suppressing the turn-on of parasitic BJTs, thereby significantly improving the device's dynamic avalanche resistance.

[0023] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A novel Trench VDMOS structure with high dynamic avalanche resistance, the cell structure of which includes: Drain end metal (1), A silicon substrate (2) and an N-type epitaxial layer (3) are located above the drain metal (1); the N-type epitaxial layer (3) is provided with a Trench polysilicon gate (6), a gate oxide layer (5), a P-base region (8), and an N+ region (9); above the N+ region (9) are provided a source contact hole (10), a gate contact hole (12), a SiO2 layer (15), an interlayer dielectric ILD layer (14), a source metal (11), and a gate metal (13); Its features are, Below the source contact hole (10) is a P+ type highly doped region (7) with deep body contact, and a P-type buried layer (4) is added to the bottom of the Trench gate (5).

2. The novel Trench VDMOS structure with high dynamic avalanche resistance as described in claim 1, characterized in that, The source contact hole (10) and the source metal (11) are located on the upper surface of the VDMOS active region interlayer dielectric ILD layer (14), and the gate contact hole (12) and the gate metal (13) are located on the upper surface of the VDMOS transition region interlayer dielectric ILD layer (14). There is a gap between the source contact hole (10) and the gate contact hole (12), and between the source metal (11) and the gate metal (13).

3. The novel Trench VDMOS structure with high dynamic avalanche resistance as described in claim 1, characterized in that, The P+ type highly doped region (7) and the P type buried layer (4) are not connected.

4. The novel Trench VDMOS structure with high dynamic avalanche resistance as described in claim 1, characterized in that, The P-type buried layer (4) is connected to the N-type epitaxial layer (3), and the doping concentration of the P-type buried layer (4) is 2-3 orders of magnitude higher than that of the N-type epitaxial layer (3).

5. The novel Trench VDMOS structure with high dynamic avalanche resistance as described in claim 1, characterized in that, The doping concentration of the P+ type highly doped region (7) is 1×10⁻⁶. 18 -5×10 18 cm -3 The doping concentration of the P-type buried layer (4) is 3 × 10⁻⁶. 17 -8×10 17 cm -3 .

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