A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises an epitaxial structure, a source electrode, a drain electrode and a back electrode. The epitaxial structure comprises a substrate, a first heterojunction structure and a second heterojunction structure. The first heterojunction structure is located between the second heterojunction structure and the substrate. The source electrode and the drain electrode are both located on a side of the second heterojunction structure away from the substrate, and both form ohmic contact with the second heterojunction structure. The drain electrode does not form ohmic contact with the first heterojunction structure. The back electrode is located on a side of the substrate away from the first heterojunction structure, and is electrically connected with the first heterojunction structure. In a working circuit of the semiconductor device, the source electrode and the back electrode are grounded. The technical scheme of the embodiment of the application can inhibit the influence of defects in epitaxy on the performance of the device, and further improve the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of microelectronics, and more particularly to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of the power electronics industry, low-cost and high-performance semiconductor devices are increasingly favored by downstream manufacturers and consumers. GaN HEMT (High Electron Mobility Transistor) devices, due to their high breakdown voltage and current density, have become a research hotspot in power electronic semiconductor devices. However, various defects (including but not limited to point defects) are inevitably introduced during the epitaxial growth process of GaN HEMT devices. These defects affect device performance, specifically manifested as slowed switching response speed and overshoot phenomena.

[0003] Traditional power electronic semiconductor devices reduce defect density in epitaxy by optimizing growth conditions. However, this method has high requirements for material growth technology and environment, and it is powerless to deal with defects that have already formed during the growth process, thus failing to reduce the impact of these defects on device performance. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method to suppress the impact of defects in epitaxy on device performance and further improve device performance.

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising:

[0006] Epitaxial structure; the epitaxial structure includes a substrate, a first heterojunction structure and a second heterojunction structure, wherein the first heterojunction structure is located between the second heterojunction structure and the substrate;

[0007] Both the source electrode and the drain electrode are located on the side of the second heterojunction structure away from the substrate, and both form ohmic contacts with the second heterojunction structure; the drain electrode does not form an ohmic contact with the first heterojunction structure.

[0008] The back electrode is located on the side of the substrate away from the first heterojunction structure and is electrically connected to the first heterojunction structure.

[0009] In the working circuit of a semiconductor device, the source electrode and the back electrode are grounded.

[0010] Optionally, along the direction from the substrate to the source electrode, the semiconductor device includes a first conductive via, which penetrates the substrate and forms an ohmic contact with the first heterojunction structure, and the back electrode makes an ohmic contact with the first heterojunction structure through the first conductive via.

[0011] Optionally, the first heterojunction structure includes a first channel layer and a first barrier layer stacked together, wherein the first barrier layer is located on the side of the first channel layer away from the substrate;

[0012] The first conductive via penetrates at least the first channel layer.

[0013] Optionally, the orthographic projection of the first conductive via onto the plane of the substrate overlaps with the orthographic projection of the source electrode onto the plane of the substrate.

[0014] Optionally, the source electrode and the back electrode are electrically connected through a first conductive via.

[0015] Optionally, the semiconductor device may also include a source field plate;

[0016] The source field plate is located on the side of the source electrode away from the substrate and is electrically connected to the source electrode.

[0017] Optionally, the semiconductor device further includes: a gate electrode and a first dielectric layer;

[0018] The gate electrode is located on the side of the second heterojunction structure away from the substrate, and is located between the source electrode and the drain electrode;

[0019] The orthographic projection of the source field plate on the substrate overlaps with the orthographic projection of the gate electrode on the substrate; the first dielectric layer is located between the film layer containing the source field plate and the film layer containing the gate electrode, and covers the gate electrode.

[0020] According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, for fabricating the semiconductor device provided in any embodiment of the present invention, the method comprising:

[0021] An epitaxial structure is formed; the epitaxial structure includes a substrate, a first heterojunction structure, and a second heterojunction structure, wherein the first heterojunction structure is located between the second heterojunction structure and the substrate;

[0022] A source electrode and a drain electrode are formed; both the source electrode and the drain electrode are located on the side of the second heterojunction structure away from the substrate, and both form ohmic contacts with the second heterojunction structure; the drain electrode does not form an ohmic contact with the second heterojunction structure.

[0023] A back electrode is formed; the back electrode is located on the side of the substrate away from the first heterojunction structure and is electrically connected to the first heterojunction structure.

[0024] In the working circuit of a semiconductor device, the source electrode and the back electrode are grounded.

[0025] Optionally, the fabrication method further includes: forming a first conductive via in the epitaxial structure along the direction of the substrate pointing to the source electrode, wherein the first conductive via penetrates the substrate and forms an ohmic contact with the first heterojunction structure;

[0026] The back electrode is electrically connected to the first heterojunction structure through the first conductive via.

[0027] Optionally, the preparation method further includes:

[0028] A source field plate is formed; the source field plate is located on the side of the source electrode away from the substrate and is electrically connected to the source electrode.

[0029] The technical solution of this invention provides an epitaxial structure comprising a first heterojunction structure and a second heterojunction structure. Both the source and drain electrodes form ohmic contacts with the second heterojunction structure, while the drain electrode does not form an ohmic contact with the first heterojunction structure. A back electrode is provided on the back side of the epitaxial structure, electrically connected to the first heterojunction structure. In the working circuit of the semiconductor device, the source electrode and the back electrode are grounded. Thus, when the semiconductor device is operating, the second heterojunction structure is under a positive voltage due to the gate voltage, while the first heterojunction structure is grounded through the back electrode. This creates an electric field in the channel layer of the second heterojunction structure. This electric field can suppress the trapping of electrons by point defects in the channel layer, thereby allowing for the remediation of defects that occurred during the early epitaxial growth process through subsequent processes and device design, suppressing the impact of point defects on the performance of the semiconductor device.

[0030] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0036] Figure 5This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0039] Figure 8 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0040] Figure 9 This is a schematic flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0043] First, it should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms "comprising" and similar terms mean that the element or object preceding the word encompasses the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes. Furthermore, the shapes and sizes of the components in the accompanying drawings do not reflect actual proportions and are only intended to illustrate the content of this invention.

[0044] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 1 As shown, the semiconductor device provided in this embodiment of the invention includes an epitaxial structure 10, a source electrode 20, a gate electrode 30, a drain electrode 40, and a back electrode 50. The epitaxial structure 10 includes a substrate 11, a first heterojunction structure 12, and a second heterojunction structure 13. The first heterojunction structure 12 is located between the second heterojunction structure 13 and the substrate 11. The source electrode 20 and the drain electrode 40 are both located on the side of the second heterojunction structure 13 away from the substrate 11, and both form ohmic contacts with the second heterojunction structure 13. The drain electrode 40 does not form an ohmic contact with the first heterojunction structure 12. The back electrode 50 is located on the side of the substrate 11 away from the first heterojunction structure 12, and is electrically connected to the first heterojunction structure 12. In the working circuit of the semiconductor device, the source electrode 20 and the back electrode 50 are grounded.

[0045] like Figure 1 As shown, the first heterojunction structure 12 includes a first channel layer 121 and a first barrier layer 122 stacked together, with the first barrier layer 122 located on the side of the first channel layer 121 away from the substrate 11. Since the first heterojunction structure 12 is positioned relatively low, it can also be referred to as the lower channel. In this embodiment, the first heterojunction structure 12 serves as a buried field plate. Specifically, the first heterojunction structure 12 is electrically connected to the back electrode 50, which is grounded when the semiconductor device is operating. Therefore, the first heterojunction structure 12 is not controlled by the voltage of the gate electrode 30 and is always in a conductive state. The electron density in the first heterojunction structure 12 can vary, and this embodiment of the invention does not limit this.

[0046] like Figure 1As shown, the second heterojunction structure 13 includes a second channel layer 131 and a second barrier layer 132 stacked together, with the second barrier layer 132 located on the side of the second channel layer 131 away from the substrate 11. Since the second heterojunction structure 13 is positioned relatively high, it can also be referred to as the upper channel. In this embodiment, the second heterojunction structure 13 serves as a conductive channel. Specifically, the gate electrode 30 forms a Schottky contact with the second heterojunction structure 13, and the source electrode 20 and drain electrode 40 both form ohmic contacts with the second heterojunction structure 13. By controlling the voltage on the gate electrode 30, the on / off state of the two-dimensional electron gas (2DEG) and the electron density in the second heterojunction structure 13 can be controlled. The electron density in the second heterojunction structure 13 can be designed according to the performance requirements of the semiconductor device; this embodiment of the invention does not limit this.

[0047] The working principle of this invention is as follows: When the semiconductor device is working, the second heterojunction structure 13 is under a positive voltage under the action of the gate voltage, while the first heterojunction structure 12 is grounded through the back electrode 50, so that an electric field is formed in the second channel layer 131. This electric field can suppress the capture of electrons by point defects in the channel layer, so that defects that occur in the early epitaxial growth process can be remedied through later processes and device design, and the impact of point defects on the performance of semiconductor devices can be suppressed.

[0048] The semiconductor device provided in this embodiment of the invention can be a HEMT device. When this device is applied to a working circuit, the source electrode 20 is grounded. The source electrode 20 can be grounded in any way, and this embodiment of the invention does not limit this.

[0049] Optionally, the substrate 11 may be a substrate material such as silicon, silicon carbide, or sapphire.

[0050] Optionally, the first channel layer 121 and the second channel layer 131 are undoped GaN layers and are non-conductive. The thicknesses of the first channel layer 121 and the second channel layer 131 may be equal or unequal, and this embodiment of the present invention does not limit this.

[0051] Optionally, the first barrier layer 122 and the second barrier layer 132 may be AlGaN layers. The thicknesses of the first barrier layer 122 and the second barrier layer 132 may be equal or unequal, and this embodiment of the present invention does not limit this.

[0052] Optionally, the gate electrode 30 can be made of metals such as nickel, titanium, platinum, and gold, as well as multilayer metals, and the source electrode 20 and drain electrode 40 can be made of metals such as titanium, aluminum, and gold, as well as multilayer metals. For example, the ohmic contact between the source electrode 20 and drain electrode 40 and the second heterojunction structure 13 can be formed by high-temperature alloying, ion implantation, and regrowth of highly doped materials.

[0053] In addition, such as Figure 1 As shown, optionally, the epitaxial structure 10 further includes a buffer layer 14, which is located between the substrate 11 and the first heterojunction structure 12. The buffer layer 14 may be an AlGaN layer of different compositions, used to suppress stress and defects caused by lattice mismatch.

[0054] In addition, such as Figure 1 As shown, optionally, the semiconductor device further includes a passivation layer 70, which is located between the film layer containing the gate electrode 30 and the second heterojunction structure 13. The material of the passivation layer 70 can be a dielectric material such as silicon nitride, silicon oxide, or aluminum oxide.

[0055] In summary, the semiconductor device provided by the embodiments of the present invention, by setting an epitaxial structure including a first heterojunction structure and a second heterojunction structure, ensures that both the source electrode and the drain electrode form ohmic contacts with the second heterojunction structure, while the drain electrode does not form an ohmic contact with the first heterojunction structure. A back electrode is provided on the back side of the epitaxial structure, which is electrically connected to the first heterojunction structure. In the working circuit of the semiconductor device, the source electrode and the back electrode are grounded. Thus, when the semiconductor device is working, the second heterojunction structure is under a positive voltage under the action of the gate voltage, while the first heterojunction structure is grounded through the back electrode. This creates an electric field in the channel layer of the second heterojunction structure (i.e., the aforementioned second channel layer). This electric field can suppress the trapping of electrons by point defects in the channel layer, thereby allowing defects that occur in the early epitaxial growth process to be remedied through subsequent processes and device design, suppressing the impact of point defects on the performance of the semiconductor device.

[0056] Based on the above embodiments, optionally, the gate electrode 30 cannot turn off the first heterojunction structure 12. In this way, the first heterojunction structure 12 can be guaranteed to be unaffected by the gate voltage and always be in the conducting state, thereby forming a stable buried layer field plate.

[0057] like Figure 1 As shown, optionally, along the direction from the substrate 11 to the source electrode 20, the semiconductor device includes a first conductive via 90, which penetrates the substrate 11 and forms an ohmic contact with the first heterojunction structure 12. The back electrode 50 is connected to the first heterojunction structure 12 through the first conductive via 90 in an ohmic contact.

[0058] The first conductive via 90 can be made of metals such as nickel or gold, or multilayer metals. By setting the first conductive via 90, the back electrode 50 and the first heterojunction structure 12 are electrically connected. The process is relatively simple and mature, which helps to ensure yield.

[0059] Optionally, the first conductive via 90 penetrates at least through the first channel layer 121. Specifically, in this embodiment, the first channel layer 121 may be undoped and non-conductive. In this case, the first conductive via 90 needs to penetrate through the first channel layer 121 and contact the first barrier layer 122 to achieve an ohmic contact connection.

[0060] It should be noted that, Figure 1 The illustration only takes the contact between the upper surface of the first conductive via 90 and the lower surface of the first barrier layer 122 as an example. In other embodiments, such as Figure 2 The schematic diagram shown is of another semiconductor device structure provided by the present invention. Optionally, the first conductive via 90 penetrates a portion of the first barrier layer 122, or, as shown... Figure 3 The diagram shown is a schematic of another semiconductor device provided by the present invention, in which the first conductive via 90 can completely penetrate the first barrier layer 122.

[0061] like Figure 1 As shown, optionally, the orthographic projection of the first conductive via 90 onto the plane of the substrate 11 overlaps with the orthographic projection of the source electrode 20 onto the plane of the substrate 11. This arrangement places the first conductive via 90 close to the edge of the device, which helps to reduce its impact on device performance.

[0062] Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 4 As shown, optionally, the source electrode 20 and the back electrode 50 are electrically connected through a first conductive via 90. With this configuration, the source electrode 20 can be connected to the back electrode 50 through the first conductive via 90 and grounded through the back electrode 50, simplifying the device structure and improving fabrication efficiency.

[0063] Reference Figure 4 As a possible implementation, the first conductive via 90 can optionally penetrate the epitaxial structure 10 to achieve electrical connection between the source electrode 20 and the back electrode 50 through the first conductive via 90. It should be noted that when the first conductive via 90 penetrates the epitaxial structure 10, the first conductive via 90 can directly form an ohmic contact with the second heterojunction structure 13, or it can not directly form an ohmic contact; this embodiment of the present invention does not limit this.

[0064] also, Figure 5 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 5 and Figure 6As shown, alternatively, in another feasible implementation, the first conductive via 90 forms an ohmic contact with the second heterojunction structure 13. Since the source electrode 20 forms an ohmic contact with the second heterojunction structure 13, this configuration also allows the source electrode 20 and the back electrode 50 to be electrically connected through the first conductive via 90. In a specific implementation, the first conductive via 90 can optionally penetrate the second channel layer 131 and contact the second barrier layer 132 (e.g., ...). Figure 5 Alternatively, the first conductive via 90 may penetrate a portion of the second channel layer 131 and the second barrier layer 132 (see reference). Figure 6 ).

[0065] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 7 As shown, optionally, the semiconductor device further includes a source field plate 60; the source field plate 60 is located on the side of the source electrode 20 away from the substrate 11 and is electrically connected to the source electrode 20. By providing the source field plate 60, defects in the semiconductor surface and passivation layer 70 can be suppressed, further improving the performance of the semiconductor device.

[0066] like Figure 7 As shown, optionally, the orthographic projection of the source field plate 60 on the substrate 11 overlaps with the orthographic projection of the gate electrode 30 on the substrate 11; the semiconductor device further includes a first dielectric layer 80; the first dielectric layer 80 is located between the film layer where the source field plate 60 is located and the film layer where the gate electrode 30 is located, and covers the gate electrode 30, so as to achieve insulation between the source field plate 60 and the gate electrode 30 through the first dielectric layer 80.

[0067] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in any embodiment of the present invention. For example, Figure 8 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the preparation method includes the following steps:

[0068] S101, Form an epitaxial structure; the epitaxial structure includes a substrate, a first heterojunction structure and a second heterojunction structure, wherein the first heterojunction structure is located between the second heterojunction structure and the substrate.

[0069] Reference Figure 1The first heterojunction structure 12 includes a first channel layer 121 and a first barrier layer 122 stacked together, with the first barrier layer 122 located on the side of the first channel layer 121 away from the substrate 11. The second heterojunction structure 13 includes a second channel layer 131 and a second barrier layer 132 stacked together, with the second barrier layer 132 located on the side of the second channel layer 131 away from the substrate 11. The epitaxial structure 10 also includes a buffer layer 14 located between the substrate 11 and the first heterojunction structure 12. Specifically, the epitaxial structure 10 can be formed by sequentially epitaxially growing the buffer layer 14, the first channel layer 121, the first barrier layer 122, the second channel layer 131, and the second barrier layer 132 on the substrate 11. In other embodiments, the epitaxial structure 10 may also include other semiconductor layers besides the aforementioned semiconductor layers, which is not limited in this embodiment of the present invention.

[0070] The substrate 11 can be a substrate material such as silicon, silicon carbide, or sapphire; the buffer layer 14 can be an AlGaN layer with different compositions; the first channel layer 121 and the second channel layer 131 can be undoped GaN layers; and the first barrier layer 122 and the second barrier layer 132 can be AlGaN layers.

[0071] S102, Forming a source electrode and a drain electrode; Both the source electrode and the drain electrode are located on the side of the second heterojunction structure away from the substrate, and both form ohmic contacts with the second heterojunction structure; The drain electrode does not form an ohmic contact with the first heterojunction structure.

[0072] Specifically, refer to Figure 1 After forming the epitaxial structure 10, the electrode structure on the front side of the epitaxial structure 10 is prepared, namely, the gate electrode 30, the source electrode 20 and the drain electrode 40 are prepared. The preparation process for this part is relatively mature and will not be explained in detail here.

[0073] The gate electrode 30 can be made of metals such as nickel, titanium, platinum, and gold, as well as multilayer metals, while the source electrode 20 and drain electrode 40 can be made of metals such as titanium, aluminum, and gold, as well as multilayer metals. For example, the ohmic contact between the source electrode 20 and drain electrode 40 and the second heterojunction structure 13 can be formed using high-temperature alloys, ion implantation, and the regeneration of highly doped materials.

[0074] S103, Form a back electrode; The back electrode is located on the side of the substrate away from the first heterojunction structure and is electrically connected to the first heterojunction structure 12.

[0075] Specifically, refer to Figure 1 After the source electrode 20, gate electrode 30, and drain electrode 40 on the front side are fabricated, the back electrode 50 is fabricated. The fabrication process can be sputtering or vapor deposition, and this embodiment of the invention is not limited to this. The back electrode 50 can be electrically connected to the first heterojunction structure 12 in any way, and this embodiment of the invention is not limited to this.

[0076] In this embodiment, the source electrode and back electrode are grounded in the working circuit of the semiconductor device. Thus, when the semiconductor device is operating, the second heterojunction structure is under a positive voltage due to the gate voltage, while the first heterojunction structure is grounded through the back electrode. This creates an electric field in the channel layer of the second heterojunction structure (i.e., the aforementioned second channel layer). This electric field can suppress the trapping of electrons by point defects in the channel layer, thereby allowing defects that occurred during the early epitaxial growth process to be remedied through subsequent processes and device design, suppressing the impact of point defects on the performance of the semiconductor device.

[0077] Based on the above embodiments, the back electrode can be electrically connected to the first heterojunction structure by forming conductive vias. Correspondingly, Figure 9 This is a schematic flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention, as shown below. Figure 9 As shown, the preparation method may include the following steps:

[0078] S201, Form an epitaxial structure; the epitaxial structure includes a substrate, a first heterojunction structure and a second heterojunction structure, wherein the first heterojunction structure is located between the second heterojunction structure and the substrate.

[0079] S202, Forming a source electrode and a drain electrode; Both the source electrode and the drain electrode are located on the side of the second heterojunction structure away from the substrate, and both form ohmic contacts with the second heterojunction structure; The drain electrode does not form an ohmic contact with the first heterojunction structure.

[0080] S203. A first conductive via is formed in the epitaxial structure along the direction of the substrate toward the source electrode. The first conductive via penetrates the substrate and forms an ohmic contact with the first heterojunction structure.

[0081] Specifically, refer to Figures 1-7 Any of the following methods can be used to drill a hole in the epitaxial structure 10 along the direction from the substrate 11 to the source electrode 20, and then fill it with metal material to form a first conductive via 90. The first conductive via 90 can be made of metals such as nickel or gold, or multilayer metals.

[0082] Reference Figure 1 As described above, optionally, the first conductive via 90 penetrates at least the first channel layer 121.

[0083] In addition, refer to Figure 1 Optionally, the orthographic projection of the first conductive via 90 onto the plane of the substrate 11 overlaps with the orthographic projection of the source electrode 20 onto the plane of the substrate 11.

[0084] Reference Figure 4Optionally, the first conductive via 90 penetrates the epitaxial structure 10, so that the source electrode 20 and the back electrode 50 are electrically connected through the first conductive via 90, thereby improving fabrication efficiency. Alternatively, refer to... Figure 5 and Figure 6 Optionally, the first conductive via 90 can form an ohmic contact with the second heterojunction structure 13 so that the source electrode 20 and the back electrode 50 are electrically connected through the first conductive via 90.

[0085] S204. Form a back electrode; the back electrode is located on the side of the substrate away from the first heterojunction structure, and is electrically connected to the first heterojunction structure through a first conductive via.

[0086] It should be noted that the metal used for the back electrode 50 can be the same as or different from that used for the first conductive via 90; this embodiment of the invention does not limit this. When the two use the same metal, they can be prepared in the same process or sequentially in different processes; this embodiment of the invention also does not limit this.

[0087] Reference Figure 7 Optionally, the fabrication method further includes forming a source field plate; the source field plate is located on the side of the source electrode away from the substrate and is electrically connected to the source electrode. (Refer to...) Figure 7 The fabrication process of the source field plate 60 can be performed before or after the fabrication of the back electrode 50; this embodiment of the invention does not limit this. By fabricating the source field plate 60 on the side of the source electrode 20 away from the substrate 11, and electrically connecting the source field plate 60 to the source electrode 20, defects in the semiconductor surface and passivation layer 70 can be suppressed using the source field plate 60, further improving device performance.

[0088] Reference Figure 7 As described above, optionally, the orthographic projection of the source field plate 60 on the substrate 11 overlaps with the orthographic projection of the gate electrode 30 on the substrate 11. Accordingly, refer to Figure 7 Optionally, before forming the source field plate, the fabrication method further includes: forming a first dielectric layer 80; the first dielectric layer 80 is located between the film layer containing the source field plate and the film layer containing the gate electrode 30, and covers the gate electrode 30. In this way, insulation between the source field plate and the gate electrode 30 can be achieved through the first dielectric layer 80.

[0089] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized in that, include: Epitaxial structure; The epitaxial structure includes a substrate, a first heterojunction structure, and a second heterojunction structure, wherein the first heterojunction structure is located between the second heterojunction structure and the substrate; The source electrode and the drain electrode are both located on the side of the second heterojunction structure away from the substrate, and both form an ohmic contact with the second heterojunction structure. The drain electrode does not form an ohmic contact with the first heterojunction structure; The back electrode is located on the side of the substrate away from the first heterojunction structure and is electrically connected to the first heterojunction structure. In the operating circuit of the semiconductor device, the source electrode and the back electrode are grounded.

2. The semiconductor device according to claim 1, characterized in that, Along the direction from the substrate to the source electrode, the semiconductor device includes a first conductive via, which penetrates the substrate and forms an ohmic contact with the first heterojunction structure. The back electrode is in ohmic contact with the first heterojunction structure through the first conductive via.

3. The semiconductor device according to claim 2, characterized in that, The first heterojunction structure includes a first channel layer and a first barrier layer stacked together, wherein the first barrier layer is located on the side of the first channel layer away from the substrate; The first conductive via penetrates at least the first channel layer.

4. The semiconductor device according to claim 2, characterized in that, The orthographic projection of the first conductive via onto the plane of the substrate overlaps with the orthographic projection of the source electrode onto the plane of the substrate.

5. The semiconductor device according to claim 4, characterized in that, The source electrode and the back electrode are electrically connected through the first conductive via.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device also includes a source field plate; The source field plate is located on the side of the source electrode away from the substrate and is electrically connected to the source electrode.

7. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes: a gate electrode and a first dielectric layer; The gate electrode is located on the side of the second heterojunction structure away from the substrate, and is located between the source electrode and the drain electrode; The orthographic projection of the source field plate on the substrate overlaps with the orthographic projection of the gate electrode on the substrate; the first dielectric layer is located between the film layer containing the source field plate and the film layer containing the gate electrode, and covers the gate electrode.

8. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 1-7, characterized in that, The preparation method includes: An epitaxial structure is formed; the epitaxial structure includes a substrate, a first heterojunction structure, and a second heterojunction structure, wherein the first heterojunction structure is located between the second heterojunction structure and the substrate; A source electrode and a drain electrode are formed; both the source electrode and the drain electrode are located on the side of the second heterojunction structure away from the substrate, and both form ohmic contacts with the second heterojunction structure; the drain electrode does not form an ohmic contact with the second heterojunction structure. A back electrode is formed; the back electrode is located on the side of the substrate away from the first heterojunction structure and is electrically connected to the first heterojunction structure; In the working circuit of the semiconductor device, the source electrode and the back electrode are grounded.

9. The preparation method according to claim 8, characterized in that, The fabrication method further includes: forming a first conductive via in the epitaxial structure along the direction of the substrate pointing to the source electrode, wherein the first conductive via penetrates the substrate and forms an ohmic contact with the first heterojunction structure; The back electrode is electrically connected to the first heterojunction structure through the first conductive via.

10. The preparation method according to claim 8, characterized in that, The preparation method further includes: A source field plate is formed; the source field plate is located on the side of the source electrode away from the substrate and is electrically connected to the source electrode.

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