Semiconductor structure and method of forming the same

Abstract

The present application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, an epitaxial layer disposed on the substrate, a plurality of first vertical field plate structures disposed in the epitaxial layer and separated from each other in a horizontal direction, a gate structure disposed on the epitaxial layer and comprising a first gate portion and a second gate portion separated from each other in the horizontal direction, and a gap field plate structure disposed in a gap between the first gate portion and the second gate portion.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to semiconductor structures including gap field plate structures. Background Technology

[0002] To achieve the performance requirements of high voltage withstand, high current, and high power density, traditional power transistors have evolved from a planar to a vertical structure. Currently, vertical double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistors with vertical trenches as their field plate structure have been developed. VDMOS field-effect transistors are widely used in various fields, including motor speed control, inverters, uninterruptible power supplies (UPS), electronic switches, high-fidelity speakers, automotive electrical systems, and electronic ballasts.

[0003] However, for VDMOS field-effect transistors with planar gates, it is difficult to achieve a uniform electric field distribution in the epitaxial layer by setting a vertical field plate structure. As a result, the non-uniform electric field distribution of VDMOS field-effect transistors may lead to a large on-resistance and poor breakdown performance.

[0004] In summary, while existing VDMOS field-effect transistors (FETs) largely meet their original intended applications, they do not completely fulfill all requirements. For example, improving the uniformity of the electric field distribution while using a vertical field plate structure to achieve high voltage and high power performance remains a key research topic in the industry. Therefore, the development of VDMOS FETs requires continuous updates and adjustments to address the various operational challenges they present. Summary of the Invention

[0005] A semiconductor structure includes: a substrate; an epitaxial layer disposed on the substrate; a plurality of first vertical field plate structures disposed in the epitaxial layer and spaced apart from each other in a horizontal direction; a gate structure disposed on the epitaxial layer and including a first gate portion and a second gate portion spaced apart from each other in a horizontal direction; and a gap field plate structure disposed in the gap between the first gate portion and the second gate portion.

[0006] A method for forming a semiconductor structure includes: forming an epitaxial layer on a substrate; forming a plurality of first vertical field plate structures in the epitaxial layer, the first vertical field plate structures being separated from each other in a horizontal direction; forming a gate structure on the epitaxial layer, the gate structure including a first gate portion and a second gate portion being separated from each other in a horizontal direction; and forming a gap field plate structure in the gap between the first gate portion and the second gate portion. Attached Figure Description

[0007] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0008] Figure 1A The present invention provides some embodiments thereof, which illustrate cross-sectional views of a semiconductor structure.

[0009] Figure 1B The present invention provides some other embodiments of the present invention, illustrating cross-sectional views of a semiconductor structure.

[0010] Figures 2A to 2F The present invention includes cross-sectional views illustrating various stages of the semiconductor structure manufacturing process according to some embodiments thereof.

[0011] Symbol explanation:

[0012] 10,20 semiconductor structure;

[0013] 100 substrates;

[0014] 110 epitaxial layer;

[0015] 120 First vertical field plate structure;

[0016] 120T trench structure;

[0017] 122 First conductive filling layer;

[0018] 124 First dielectric spacer layer;

[0019] 125 Second vertical field plate structure;

[0020] 126 Second conductive filling layer;

[0021] 128 Second dielectric spacer layer;

[0022] 130 gate structure;

[0023] 131 First gate section;

[0024] 132 Second gate section;

[0025] 133 gap;

[0026] 134 gate dielectric layer;

[0027] 134-1 First gate dielectric layer;

[0028] 140mm gap plate structure;

[0029] 142 dielectric spacer layer;

[0030] 142' dielectric layer;

[0031] 144 electric field adjustment layer;

[0032] 144' conductive layer;

[0033] 150-doped structure;

[0034] 152 doped wells;

[0035] 154 First doped region;

[0036] 156 Second doped region;

[0037] 160 interlayer dielectric layers;

[0038] 168 contact layer;

[0039] 170 source electrode;

[0040] 171 First source pole;

[0041] 172 Second source pole;

[0042] 180 drain electrode;

[0043] Distance between D1 and D2. Detailed Implementation

[0044] The following disclosure provides many different embodiments or examples to illustrate different components of embodiments of the present invention. Specific examples of the components and their arrangements will be disclosed below to simplify the description of the invention. Of course, these specific examples are not intended to limit the invention. For example, if the following description states that a first component is formed on or above a second component, it includes embodiments where the first and second components are in direct contact, as well as embodiments where additional components may be formed between the first and second components, in which case the first and second components are not in direct contact. Furthermore, the various examples in this description may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity and are not intended to limit the various embodiments and / or the relationships between the described configurations.

[0045] Furthermore, to facilitate the description of the relationship between one element or component and another element or component(s) in a diagram, spatial relative terms such as "below," "under," "lower part," "above," "upper part," and similar terms can be used. In addition to the orientations shown in the diagrams, spatial relative terms also cover different orientations of the device during use or operation. When the device is turned to a different orientation (e.g., rotated 90 degrees or otherwise), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0046] Here, the terms "about," "approximately," and "roughly" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without specific mention of "about," "approximately," or "roughly," their meaning is implied.

[0047] The following describes some embodiments of the invention in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Some of the stages may be replaced or omitted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or omitted in different embodiments. Although some of the embodiments discussed perform the steps in a particular order, these steps may still be performed in another logical order.

[0048] As used herein, the term "substantially" means that the value of a given quantity can vary based on a specific technology node associated with the target semiconductor device. In some embodiments, based on a specific technology node, the term "substantially" may mean that the value of a given quantity is within, for example, ±5% of a target (or desired) value.

[0049] This invention provides a semiconductor structure and a method for forming the same, wherein the semiconductor structure includes a gap field plate structure disposed between mutually spaced gate portions. For a VDMOS field-effect transistor with a planar gate, the configuration of the gap field plate structure enables a more uniform electric field distribution among multiple vertical field plate structures. This results in a VDMOS field-effect transistor structure with lower on-resistance and higher breakdown voltage.

[0050] Figure 1AThis is a cross-sectional view of a semiconductor structure 10 according to some embodiments of the present invention. The semiconductor structure 10 may include a substrate 100 and an epitaxial layer 110 disposed on the substrate 100. A plurality of first vertical field plate structures 120 may be disposed in the epitaxial layer 110, and the first vertical field plate structures 120 are spaced apart from each other in the horizontal direction. The semiconductor structure 10 further includes a gate structure 130 disposed above the epitaxial layer 110. The gate structure 130 may include a first gate portion 131 and a second gate portion 132 spaced apart from each other in the aforementioned horizontal direction. Furthermore, a gap field plate structure 140 may be disposed in the gap 133 between the first gate portion 131 and the second gate portion 132.

[0051] In some embodiments, substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. In some embodiments, substrate 100 is formed of silicon, germanium, other suitable semiconductor materials, or combinations thereof. For example, in a particular embodiment, substrate 100 comprises silicon. In some embodiments, substrate 100 may comprise a compound semiconductor, such as silicon carbide, gallium nitride, gallium oxide, gallium arsenide, other suitable semiconductor materials, or combinations thereof. In some embodiments, substrate 100 may comprise an alloy semiconductor, such as silicon-germanium, silicon-germanium carbide, other suitable materials, or combinations thereof. In some embodiments, substrate 100 may be composed of a multilayer material, such as a silicon / silicon-germanium or silicon / silicon carbide multilayer material.

[0052] In some embodiments of the present invention, for example, the substrate 100 is a wafer doped with a dopant of a first conductivity type, and the first conductivity type is n-type. In some other embodiments, the first conductivity type may also be p-type. When the first conductivity type is n-type, the dopant having the first conductivity type may be, for example, nitrogen, phosphorus, arsenic, antimony, bismuth, or silicon. In some embodiments, the doping concentration of the substrate 100 may be approximately 1e19 atoms / cm³. 3 Up to approximately 1E21 atoms / cm 3 between.

[0053] The epitaxial layer 110 may comprise the same or similar material as the substrate 100, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium, silicon carbide germanium, other suitable materials, or combinations thereof. In some embodiments, the substrate 100 and the epitaxial layer 110 have the same conductivity type (e.g., n-type), and the substrate 100 and the epitaxial layer 110 may comprise the same dopant. In some embodiments, the doping concentration of the dopant in the epitaxial layer 110 is less than the doping concentration in the substrate 100. In some embodiments, the doping concentration of the epitaxial layer 110 may be approximately 1e13 atoms / cm². 3 Up to approximately 1e18 atoms / cm 3In some embodiments of the invention, for example, the epitaxial layer 110 comprises silicon carbide. By forming the epitaxial layer 110 with silicon carbide, the epitaxial layer 110 can be doped with a dopant that is suitable for the band range of silicon carbide and has a low activation energy. Furthermore, the epitaxial layer 110 formed of silicon carbide can provide a higher breakdown voltage, a lower leakage current, and a lower on-resistance.

[0054] In some embodiments, the first vertical field plate structure 120 includes polysilicon. Specifically, each first vertical field plate structure 120 may include a first conductive fill layer 122 and a first dielectric spacer layer 124. At least a portion of the first conductive fill layer 122 may be embedded in the epitaxial layer 110, and the first dielectric spacer layer 124 may extend between the first conductive fill layer 122 and the epitaxial layer 110. Figure 1A As shown, the distance D1 between adjacent first vertical field plate structures 120 can be between about 1 micrometer and about 3.5 micrometers. In some embodiments, the top surface of the first vertical field plate structure 120 is substantially coplanar with the top surface of the epitaxial layer 110. The depth of the first vertical field plate structure 120 can be between about 1 micrometer and about 7 micrometers.

[0055] The material of the first conductive filling layer 122 may include polysilicon, metal, metal nitride, other suitable conductive materials, or combinations thereof. The material of the first dielectric spacer layer 124 may include oxide, nitride, oxynitride, carbide, other suitable high-k dielectric materials, other suitable materials, or combinations thereof. In some embodiments, the first dielectric spacer layer 124 comprises an oxide having elements common to the epitaxial layer 110. For example, in a particular embodiment, the epitaxial layer 110 comprises silicon or silicon carbide, and the first dielectric spacer layer 124 comprises silicon oxide.

[0056] The materials of the first gate portion 131 and the second gate portion 132 may be or include polysilicon, metal, alloy, metal nitride, other suitable conductive materials, or combinations thereof.

[0057] In some embodiments, the gate structure 130 further includes a gate dielectric layer 134 extending between the first gate portion 131 and the second gate portion 132 and the epitaxial layer 110. In some embodiments, the gate dielectric layer 134 includes a dielectric material, such as an oxide. The oxide may include silicon oxide, zirconium oxide, aluminum oxide, other suitable high dielectric constant dielectric materials, or combinations thereof. Furthermore, in some embodiments, the gate dielectric layer 134 may also cover the top surfaces of the first gate portion 131 and the second gate portion 132, and may also cover the sidewalls of the first gate portion 131 and the second gate portion 132.

[0058] The gap field plate structure 140 can conformally extend in the gap 133 between the first gate portion 131 and the second gate portion 132 onto the top surface of the epitaxial layer 110 and a plurality of sidewalls of the gate structure 130. In some embodiments, such as Figure 1A As shown, the gap field plate structure 140 partially fills the gap 133 and forms a groove. In addition, the gap field plate structure 140 may include a horizontal portion extending laterally in the gap 133 (e.g., a horizontal portion that directly contacts the top surface of the epitaxial layer 110).

[0059] In some embodiments, such as Figure 1A As shown, the gap field plate structure 140 extends above the top surface of the gate structure 130. However, the top surface of the gap field plate structure 140 may also be coplanar with the top surface of the gate structure 130. In some embodiments, the first vertical field plate structure 120 is located on both sides of the gap field plate structure 140 in the horizontal direction. Specifically, the two endpoints of the gap field plate structure 140 in the horizontal direction may be located between the vertical extension lines of the first vertical field plate structure 120. In other words, in some embodiments, the gap field plate structure 140 extends in the horizontal direction and does not cover or extend directly above the first vertical field plate structures 120 on both sides.

[0060] The gap field plate structure 140 may include a single metal layer or multiple metal layers. Specifically, in some embodiments, the gap field plate structure 140 includes a dielectric spacer layer 142 and an electric field adjustment layer 144. The dielectric spacer layer 142 may be disposed on the epitaxial layer 110, and the electric field adjustment layer 144 may be disposed on the dielectric spacer layer 142. Figure 1A As shown, the dielectric spacer layer 142 separates the electric field adjustment layer 144 from the epitaxial layer 110. In some embodiments, the thickness of the electric field adjustment layer 144 may be greater than the thickness of the dielectric spacer layer 142. For example, the thickness of the dielectric spacer layer 142 may be approximately... and Approximately Between, and the thickness of the electric field adjustment layer 144 can be approximately and Approximately Between. The gap field plate structure 140 may include a single electric field adjustment layer 144 or multiple electric field adjustment layers 144.

[0061] The dielectric spacer layer 142 may be made of oxides, nitrides, oxynitrides, carbides, other suitable high dielectric constant dielectric materials, or combinations thereof. The electric field adjustment layer 144 may be made of polysilicon, metals, alloys, metal nitrides, other suitable conductive materials, or combinations thereof.

[0062] The semiconductor structure 10 may further include a second vertical field plate structure 125 that is horizontally separated from the first vertical field plate structure 120. By providing the second vertical field plate structure 125 between the first vertical field plate structures 120, the electric field uniformity between the first vertical field plate structures 120 can be further improved, making the semiconductor structure 10 suitable for applications requiring higher voltages.

[0063] In some embodiments, the second vertical field plate structure 125 is equidistant from two of the first vertical field plate structures 120 on both sides. For example... Figure 1A As shown, the distance D2 between the second vertical field plate structure 125 and the adjacent first vertical field plate structure 120 can be between approximately 0.5 micrometers and approximately 1.8 micrometers. In some embodiments, such as Figure 1A As shown, the second vertical field plate structure 125 is located directly below the gap field plate structure 140. Furthermore, in another embodiment, the second vertical field plate structure 125 can be in direct contact with the gap field plate structure 140; in other words, the dielectric spacer layer 142 may have a hole (not shown) allowing the second vertical field plate structure 125 to contact the electric field adjustment layer 144. In the horizontal direction, the width of the gap field plate structure 140 may be greater than the thickness of the second vertical field plate structure 125. The second vertical field plate structure 125 may have the same or similar dimensions as the respective first vertical field plate structures 120, such as the same or similar thickness and depth. Furthermore, the second vertical field plate structure 125 may include the same or similar material as the respective first vertical field plate structures 120. The second vertical field plate structure 125 may include a second conductive filler layer 126 and a second dielectric spacer layer 128. The second conductive filling layer 126 and the second dielectric spacer layer 128 may include the same or similar materials as the first conductive filling layer 122 and the first dielectric spacer layer 124, and their detailed description is omitted here for simplicity.

[0064] Figure 1B This is a cross-sectional view of a semiconductor structure 20 according to some other embodiments of the present invention. The difference from semiconductor structure 10 is that semiconductor structure 20 does not have a second vertical field plate structure. In this case, the distance D1 between adjacent first vertical field plate structures 120 can be between about 1 micrometer and about 3.5 micrometers. By omitting the second vertical field plate structure between the first vertical field plate structures 120, process steps and costs can be reduced, and the size of semiconductor structure 20 can be further reduced. It should be understood that the films and components disposed in semiconductor structure 10 discussed later are also applicable to semiconductor structure 20 without a second vertical field plate structure.

[0065] Refer again Figure 1AThe semiconductor structure 10 may further include a doped structure 150 disposed in the epitaxial layer 110, and the doped structure 150 has a doped well 152. In some embodiments, the substrate 100 and the epitaxial layer 110 have a first conductivity type (e.g., n-type), and the doped well 152 has a second conductivity type (e.g., p-type). A portion of the doped well 152 adjacent to the gate structure 130 can be used as a channel region during operation of the semiconductor structure 10.

[0066] The doped structure 150 may further include a first heavily doped region 154 and a second heavily doped region 156 disposed adjacent to each other in the doping well 152. In some embodiments, the first heavily doped region 154 has a first conductivity type, and the second heavily doped region 156 has a second conductivity type. Specifically, the first heavily doped region 154 may have the same first conductivity type as the epitaxial layer 110 (e.g., n-type), and the second heavily doped region 156 may have the same second conductivity type as the doping well 152 (e.g., p-type). In some embodiments, the doping well 152 covers the bottom surfaces of the first heavily doped region 154 and the second heavily doped region 156. In some embodiments, the top surface of the doped structure 150 is substantially coplanar with the top surfaces of the epitaxial layer 110 and the first vertical field plate structure 120.

[0067] The doped structure 150 may include the same or similar material as the portion below the doped structure 150 of the epitaxial layer 110, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium, silicon carbide germanium, other suitable materials, or combinations thereof. The doping concentration of the doped well 152 may be approximately 1e15 atoms / cm². 3 Up to approximately 1e18 atoms / cm 3 Between. The doping concentration of the first doped region 154 can be approximately 1e18 atoms / cm. 3 Up to approximately 1e21 atoms / cm 3 Between. The doping concentration of the second doped region 156 can be approximately 1e18 atoms / cm. 3 Up to approximately 1e21 atoms / cm 3 between.

[0068] This invention does not limit the type of dopant in the doped structure 150; those skilled in the art can determine which dopant to use based on design requirements. The conductivity type of the dopant can be either n-type or p-type. If the conductivity type of the dopant is n-type, the dopant can be, for example, nitrogen, phosphorus, arsenic, antimony, or bismuth. If the conductivity type of the dopant is p-type, the dopant can be, for example, boron, aluminum, gallium, indium, or thallium.

[0069] In some embodiments, the semiconductor structure 10 includes an interlayer dielectric layer 160 covering the epitaxial layer 110, the gate structure 130, and the spacer field structure 140. The interlayer dielectric layer 160 can be used to electrically isolate the gate structure 130 and the spacer field structure 140 from the subsequently formed source electrode 170. The interlayer dielectric layer 160 may include a dielectric material, such as an oxide. The oxide may include silicon oxide, zirconium oxide, aluminum oxide, other suitable high-dielectric-constant dielectric materials, or combinations thereof.

[0070] The semiconductor structure 10 may further include a source electrode 170 disposed on the epitaxial layer 110. The source electrode 170 may have a first source portion 171 and a second source portion 172 respectively disposed in the horizontal direction outside the first gate portion 131 and the second gate portion 132. The source electrode 170 may be electrically connected to the doped structure 150. In some embodiments, such as Figure 1A As shown, the top surface of the source electrode 170 is higher than the top surface of the gate structure 130. Specifically, the first source portion 171 and the second source portion 172 of the source electrode 170 can be electrically connected to the doped structure 150 through a contact layer 168 in the opening of the interlayer dielectric layer 160. In some embodiments, the contact layer 168 covers only a portion of the top surface of the first heavily doped region 154 and completely covers the top surface of the second heavily doped region 156. Furthermore, the semiconductor structure 10 may further include a drain electrode 180 covering the bottom surface of the epitaxial layer 110.

[0071] Contact layer 168 may include polysilicon, metal, alloy, metal nitride, other suitable conductive materials, or a combination thereof.

[0072] During operation of the semiconductor structure 10, the gate structure 130 and the source electrode 170 may have different potentials. The gap field plate structure 140 may have the same potential as the gate structure 130 or the source electrode 170. In some embodiments, by making the gap field plate structure 140 have the same potential as the gate structure 130, the on-resistance of the semiconductor structure 10 can be reduced. In other embodiments, by making the gap field plate structure 140 have the same potential as the source electrode 170, the semiconductor structure 10 can have a higher breakdown voltage.

[0073] Furthermore, the first vertical field plate structure 120 and the second vertical field plate structure 125 may also have the same potential as the gate structure 130 or the source electrode 170. In some embodiments, by having the first vertical field plate structure 120 and the second vertical field plate structure 125 have the same potential as the gate structure 130, the on-resistance of the semiconductor structure 10 can be reduced. In other embodiments, by having the first vertical field plate structure 120 and the second vertical field plate structure 125 have the same potential as the source electrode 170, the semiconductor structure 10 can have a higher breakdown voltage.

[0074] In summary, by placing the gap field plate structure 140 between the separated first gate portion 131 and second gate portion 132 in the semiconductor structures 10 and 20, the electric field distribution among the multiple first vertical field plate structures 120 can be made more uniform. This results in the semiconductor structures 10 and 20 having lower on-resistance and higher breakdown voltage.

[0075] According to some embodiments of the present invention, reference will be made below. Figures 2A to 2F The diagram illustrates the various stages of the manufacturing process of semiconductor structure 10. It should be understood that, except for the formation of the second vertical field plate structure 125, the other parts of the following manufacturing process can also be applied to the formation of semiconductor structure 20.

[0076] First, a substrate 100 may be provided. In some embodiments, a drain electrode 180 is first deposited on the lower surface of the substrate 100. The method for forming the drain electrode 180 may include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, sputtering, electrochemical plating, electroless plating, some other deposition processes, or combinations thereof. In some other embodiments, a deposition process is performed on the drain electrode 180 to form the substrate 100. The deposition process of the substrate 100 may include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), some other deposition processes, or combinations thereof. However, it should be understood that the drain electrode 180 may also be formed on the lower surface of the substrate 100 after other components (e.g., gate structure 130, gap field plate structure 140, etc.) above the upper surface of the semiconductor structure 10 are formed. In this case, a method similar to the deposition process described above can be used to form the drain electrode 180.

[0077] Reference Figure 2AAn epitaxial layer 110 can be formed on the substrate 100. The epitaxial layer 110 can be deposited by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), other suitable deposition processes, or combinations thereof.

[0078] In some embodiments, the epitaxial layer 110 is in-situ doped to have a first conductivity type (e.g., n-type). In some other embodiments, after depositing material for the epitaxial layer 110, a doping process is performed with a dopant having the first conductivity type to form the epitaxial layer 110 having the first conductivity type. For example, the epitaxial layer 110 can be doped by ion implantation, thermal diffusion, other suitable processes, or a combination thereof. The doped epitaxial layer 110 can have the same first conductivity type as the substrate 100, and the dopant concentration in the epitaxial layer 110 can be less than the dopant concentration in the substrate 100.

[0079] Next, a plurality of first vertical field plate structures 120 spaced apart from each other in the horizontal direction can be formed in the epitaxial layer 110. The formation of the first vertical field plate structure 120 may include forming a plurality of trench structures 120T in the epitaxial layer 110, and then filling the trench structures 120T with conductive material. Specifically, in some embodiments, the formation of the first vertical field plate structure 120 includes sequentially depositing a first dielectric spacer layer 124 and a first conductive filler layer 122 in the trench structures 120T.

[0080] The process for forming the trench structure 120T includes forming a patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) over the epitaxial layer 110. The patterned masking layer can be formed by (e.g., by spin coating) forming the masking layer on the epitaxial layer 110, exposing the masking layer to the pattern (e.g., by lithography processes such as photolithography, extreme ultraviolet lithography, etc.), and developing the masking layer. Next, after the patterned masking layer is in place, an etching process is performed on the epitaxial layer 110 based on the patterned masking layer. The etching process removes the unmasked portions of the epitaxial layer 110, thereby forming the trench structure 120T. The distance D1 between adjacent trench structures 120T can be between approximately 1 micrometer and approximately 3.5 micrometers. The depth of the trench structure 120T can be between approximately 1 micrometer and approximately 7 micrometers. In some embodiments, the etching process may be or include, for example, wet etching, dry etching, reactive ion etching (RIE), other suitable etching processes, or a combination thereof.

[0081] In some embodiments, a second vertical field plate structure 125, horizontally separated from the first vertical field plate structure 120, is formed in the epitaxial layer 110. The distance D2 between the second vertical field plate structure 125 and the adjacent first vertical field plate structure 120 can be between about 0.5 micrometers and about 1.8 micrometers. The material and formation method of the second vertical field plate structure 125 can be the same as or similar to those of the first vertical field plate structure 120, for example, including the sequential deposition of a second dielectric spacer layer 128 and a second conductive filler layer 126 in a trench using the same or similar processes, the details of which are omitted here for simplicity.

[0082] The methods for forming the first dielectric spacer layer 124 and the second dielectric spacer layer 128 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sol-gel method, spin coating, other suitable methods, or combinations thereof. The methods for forming the first conductive filling layer 122 and the second conductive filling layer 126 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or combinations thereof.

[0083] Next, a doping process can be performed to form a doped structure 150 in the epitaxial layer 110. In some embodiments, the doped structure 150 is in direct contact with the first vertical field plate structure 120. By performing multiple doping steps on the epitaxial layer 110, a doped structure 150 having a doped well 152, a first heavily doped region 154, and a second heavily doped region 156 can be formed.

[0084] Specifically, prior to the doping step described above, a masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) can be formed on the top surface of the epitaxial layer 110. This can be achieved by forming the masking layer (not shown) on the epitaxial layer 110, exposing the masking layer to a pattern (e.g., by lithography processes such as photolithography, extreme ultraviolet lithography, etc.), and developing the masking layer to form a patterned masking layer that partially covers the top surface of the epitaxial layer 110.

[0085] Subsequently, after the patterned masking layer is in place, the unmasked portion of the epitaxial layer 110 can be doped using ion implantation, thermal diffusion, other suitable processes, or a combination thereof, thereby forming the doped well 152, the first heavily doped region 154, and the second heavily doped region 156 in the doped structure 150. Then, the patterned masking layer can be peeled off. In some embodiments, after the above doping steps, the doped well 152 and the second heavily doped region 156 may have a second conductivity type opposite to the first conductivity type of the epitaxial layer 110, and the first heavily doped region 154 may have the same first conductivity type as the epitaxial layer 110.

[0086] Next, refer to Figure 2B , Figure 2C A gate structure 130 can be formed on the epitaxial layer 110, wherein the gate structure 130 includes a first gate portion 131 and a second gate portion 132 that are horizontally separated from each other. The process steps for forming the gate structure 130 will be described in detail below. It should be understood that the following process steps are merely illustrative and the present invention does not limit the process steps of the gate structure 130.

[0087] First, the formation of the gate structure 130 may include forming a first gate dielectric layer 134-1 on the epitaxial layer 110. Next, a first gate portion 131 and a second gate portion 132 may be formed on the first gate dielectric layer 134-1. In some embodiments, in order to electrically isolate the first gate portion 131 and the second gate portion 132 from other surrounding conductive components, a second gate dielectric layer (not shown) may then be formed on the first gate portion 131 and the second gate portion 132.

[0088] The methods for forming the first gate dielectric layer 134-1 and the second gate dielectric layer may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sol-gel method, spin coating, other suitable methods, or combinations thereof.

[0089] The method for forming the first gate portion 131 and the second gate portion 132 may include depositing a conductive material and a patterning process for the conductive material. The process for depositing the conductive material may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or combinations thereof. The patterning process may include lithography and etching processes. Lithography may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations thereof. The etching process may include dry etching, wet etching, or other suitable etching processes. Dry etching may include plasma etching, plasma-free gas etching, sputter etching, ion milling, reactive ion etching (RIE), neutral beam etching (NBE), and inductively coupled plasma etching. Wet etching may involve using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. Furthermore, the etching process can be purely chemical etching, purely physical etching, or any combination thereof.

[0090] After the first gate dielectric layer 134-1, the first gate portion 131, and the second gate portion 132 are sequentially formed, in some embodiments, the first gate dielectric layer 134-1 is patterned to form a gate dielectric layer 134 exposing the top surface of the underlying epitaxial layer 110, such as... Figure 2C As shown. The patterning process described above may include lithography and etching processes. The details of the patterning process for the first gate dielectric layer 134-1 are similar to those for the patterning processes of the first gate portion 131 and the second gate portion 132, and their detailed description is omitted here for simplicity. After the patterning process, a gap 133 can be formed between the first gate portion 131 and the second gate portion 132.

[0091] Next, refer to Figure 2C , Figure 2D A gap field plate structure 140 can be formed in the gap 133 between the first gate portion 131 and the second gate portion 132. The process steps for forming the gap field plate structure 140 will be described in detail below. It should be understood that the following process steps are merely illustrative, and the present invention does not limit the process steps for the gap field plate structure 140.

[0092] Specifically, the formation of the gap field plate structure 140 may include sequentially forming a dielectric layer 142' and a conductive layer 144' on the epitaxial layer 110 and the gate structure 130. The material of the dielectric layer 142' may include oxides, nitrides, oxynitrides, carbides, other suitable high-dielectric-constant dielectric materials, or combinations thereof. The material of the conductive layer 144' may include polysilicon, metals, alloys, metal nitrides, other suitable conductive materials, or combinations thereof.

[0093] Next, a patterning process can be performed to form a dielectric spacer layer 142 and an electric field adjustment layer 144 in the gap 133. In some embodiments, the patterning process removes portions of the dielectric layer 142' and the conductive layer 144', such that the dielectric layer 142' and the conductive layer 144' are respectively patterned as a dielectric spacer layer 142 and an electric field adjustment layer 144. The patterning process removes portions of the conductive layer 144' above the plurality of top surfaces of the first gate portion 131 and the second gate portion 132. In some embodiments, such as Figure 2D As shown, the above patterning process also removes the dielectric layer 142' and conductive layer 144' located on the outer side of the gate structure 130 in the horizontal direction.

[0094] Next, refer to Figure 2EAn interlayer dielectric layer 160 can be formed on the epitaxial layer 110, the gate structure 130, and the spacer field structure 140. The method for forming the interlayer dielectric layer 160 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sol-gel method, spin coating, other suitable methods, or combinations thereof.

[0095] Next, a source electrode 170 can be formed on the epitaxial layer 110. In some embodiments, the source electrode 170 is electrically connected to the doped structure 150. For example, the first source portion 171 and the second source portion 172 of the source electrode 170 can be electrically connected to the doped structure 150 through a contact layer 168. Before forming the contact layer 168, an opening exposing the top surface of the doped structure 150 can be formed in the interlayer dielectric layer 160 by a patterning process. The contact layer 168 can be deposited in the opening by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or combinations thereof. Then, the source electrode 170 can be deposited in the opening and above the top surface of the interlayer dielectric layer 160 by a deposition process. The deposition process for the source electrode 170 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or combinations thereof. In some other embodiments, the drain electrode 180 is formed by a deposition process performed on the lower surface of the substrate 100 after the source electrode 170 has been formed by flipping the entire semiconductor structure.

[0096] In summary, this invention provides a semiconductor structure and a method for forming the same, wherein the semiconductor structure includes a gap field plate structure disposed between mutually spaced gate portions. For a VDMOS field-effect transistor with a planar gate, the configuration of the gap field plate structure enables a more uniform electric field distribution among multiple vertical field plate structures. This results in a VDMOS field-effect transistor structure with lower on-resistance and higher breakdown voltage.

[0097] The foregoing outlines features of several embodiments to enable those skilled in the art to more readily understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: One substrate; An epitaxial layer is disposed on the substrate; Multiple first vertical field plate structures are disposed in the epitaxial layer and are separated from each other in a horizontal direction; A gate structure is disposed on the epitaxial layer and includes a first gate portion and a second gate portion spaced apart from each other in the horizontal direction; and A gap field plate structure is disposed in a gap between the first gate portion and the second gate portion.

2. The semiconductor structure according to claim 1, characterized in that, The gap field plate structure includes a horizontal portion that extends laterally within the gap.

3. The semiconductor structure according to claim 1, characterized in that, The gap is partially filled by the plate structure, forming a groove.

4. The semiconductor structure according to claim 1, characterized in that, The gap field plate structure extends compliantly within the gap to the top surface of the epitaxial layer and to multiple sidewalls of the gate structure.

5. The semiconductor structure according to claim 1, characterized in that, The gap field plate structure has the same potential as the gate structure or a source electrode.

6. The semiconductor structure according to claim 1, characterized in that, The gap field plate structure extends above the top surface of the gate structure.

7. The semiconductor structure according to claim 1, characterized in that, The first vertical field plate structure is located on both sides of the gap field plate structure in the horizontal direction.

8. The semiconductor structure according to claim 1, characterized in that, The gap plate structure includes: A dielectric spacer layer is disposed on the epitaxial layer; and An electric field adjustment layer is disposed on the dielectric spacer layer. The dielectric spacer layer separates the electric field adjustment layer from the epitaxial layer.

9. The semiconductor structure according to claim 1, characterized in that, Also includes: A second vertical field plate structure is located directly below the gap field plate structure.

10. The semiconductor structure according to claim 9, characterized in that, The second vertical field plate structure is in direct contact with the gap field plate structure.

11. The semiconductor structure according to claim 9, characterized in that, In the horizontal direction, the width of the gap field plate structure is greater than the thickness of the second vertical field plate structure.

12. The semiconductor structure according to claim 1, characterized in that, Also includes: A source electrode is disposed on the epitaxial layer. The source electrode has a first source portion and a second source portion respectively disposed on the outside of the first gate portion and the second gate portion in the horizontal direction.

13. The semiconductor structure according to claim 12, characterized in that, The top surface of the source electrode is higher than the top surface of the gate structure.

14. The semiconductor structure according to claim 1, characterized in that, It also includes a doped structure disposed in the epitaxial layer, and the doped structure has a doped well, wherein the substrate and the epitaxial layer have a first conductivity type, and the doped well has a second conductivity type.

15. The semiconductor structure according to claim 14, characterized in that, Also includes: A source electrode is disposed on the epitaxial layer and electrically connected to the doped structure.

16. The semiconductor structure according to claim 14, characterized in that, The doped structure also includes: A first heavily doped region and a second heavily doped region are disposed in the doped well and are adjacent to each other; wherein the first heavily doped region has the first conductivity type and the second heavily doped region has the second conductivity type.

17. The semiconductor structure according to claim 1, characterized in that, It also includes a drain electrode covering the bottom surface of the epitaxial layer.

18. The semiconductor structure according to claim 1, characterized in that, The gate structure also includes a gate dielectric layer extending between the first gate portion, the second gate portion, and the epitaxial layer.

19. A method for forming a semiconductor structure, characterized in that, include: An epitaxial layer is formed on a substrate; Multiple first vertical field plate structures are formed in the epitaxial layer, and the first vertical field plate structures are separated from each other in a horizontal direction; A gate structure is formed on the epitaxial layer, and the gate structure includes a first gate portion and a second gate portion that are spaced apart from each other in the horizontal direction; and A gap field plate structure is formed in a gap between the first gate portion and the second gate portion.

20. The method for forming a semiconductor structure according to claim 19, characterized in that, The formation of this first vertical field plate structure includes: Multiple trenches are formed in the epitaxial layer; and The trench is filled with conductive material.

21. The method for forming a semiconductor structure according to claim 19, characterized in that, It also includes performing a doping process to form a doped structure in the epitaxial layer that is in direct contact with the first vertical field plate structure.

22. The method for forming a semiconductor structure according to claim 21, characterized in that, It also includes forming a source electrode that is electrically connected to the doped structure.

23. The method for forming a semiconductor structure according to claim 19, characterized in that, The formation of this gate structure includes: A first gate dielectric layer is formed on the epitaxial layer; and The first gate portion and the second gate portion are formed on the first gate dielectric layer.

24. The method for forming a semiconductor structure according to claim 19, characterized in that, The formation of this gap field plate structure includes: A dielectric layer and a conductive layer are sequentially formed on the epitaxial layer and the gate structure; and A patterning process is performed to form a dielectric spacer layer and an electric field adjustment layer in the gap.

25. The method for forming a semiconductor structure according to claim 24, characterized in that, The patterning process removes the conductive layer above the top surfaces of the first gate portion and the second gate portion.

26. The method for forming a semiconductor structure according to claim 19, characterized in that, It also includes a second vertical field plate structure formed in the epitaxial layer that is separated from the first vertical field plate structure in the horizontal direction.

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