Semiconductor structure and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor structure and a preparation method thereof and an electronic device. The preparation method of the semiconductor structure comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises: a fin structure and a substrate stacked along a first direction, and the fin structure comprises: a first part and a second part stacked along the first direction; forming a front device layer based on the first part; bonding the front device layer with a first carrier wafer and turning over the first carrier wafer; removing the substrate; forming a back device layer based on the second part; and the method further comprises: forming a micro channel with an extension direction being not perpendicular to the first direction, wherein the micro channel comprises a channel inlet, a channel outlet and a channel body; the channel body is a hollow structure and is communicated with the channel inlet and the channel outlet; the channel inlet is arranged on the back device layer and is used for introducing a cooling medium; and the channel outlet is arranged on the front device layer and is used for discharging the cooling medium.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0002] With Moore's Law constantly evolving, 3D integration technology, which utilizes double-sided wafer fabrication of transistors, has great potential to improve system computing power and integration, as well as enhance the functionality of computing systems. It is an important direction for integrated circuit system integration.

[0003] In related technologies, heat dissipation structures for 3D integration technology are still implemented at the packaging or system level, causing heat to accumulate inside the transistor, which can easily lead to serious performance degradation and reliability problems. Summary of the Invention

[0004] This application provides a semiconductor structure and its fabrication method, as well as an electronic device, which can integrate heat dissipation structures at the transistor level and extend the heat dissipation structures to both sides of the wafer, thereby significantly reducing the risk of thermal runaway and improving the reliability of the semiconductor structure.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes: a fin structure and a substrate stacked along a first direction, the fin structure including: a first portion and a second portion stacked along the first direction; forming a front device layer based on the first portion; bonding the front device layer to a first carrier wafer and flipping the first carrier wafer; removing the substrate; forming a back device layer based on the second portion; the method further comprising: forming microchannels whose extension direction is not perpendicular to the first direction, wherein the microchannels include a channel inlet, a channel outlet, and a channel body; the channel body is a hollow structure connecting the channel inlet and the channel outlet; the channel inlet is disposed on the back device layer for introducing a cooling medium; the channel outlet is disposed on the front device layer for discharging the cooling medium.

[0007] This application provides a semiconductor structure fabricated using the above-described fabrication method, comprising: a front device layer and a back device layer stacked along a first direction; the front device layer and the back device layer are formed based on the same fin structure and are disposed opposite to each other; a microchannel extending in a direction not perpendicular to the first direction, wherein the microchannel includes a channel inlet, a channel outlet, and a channel body connecting the channel inlet and the channel outlet; the channel inlet is disposed on the back device layer for introducing a cooling medium; and the channel outlet is disposed on the front device layer for discharging the cooling medium.

[0008] This application provides an electronic device, including: a circuit board and the semiconductor structure described above.

[0009] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0010] In this embodiment, a front and back device layer can be 3D stacked back-to-back in a first direction using both sides of a wafer, achieving a symmetrical double-sided device. Furthermore, by forming microchannels whose extension direction is not perpendicular to the first direction, and placing the microchannel inlets on the back device layer and the outlets on the front device layer, cooling media can flow from the back to the front of the wafer, thus completing a double-sided heat dissipation channel within the transistor. This effectively reduces the risk of thermal runaway caused by heat accumulation inside the stacked transistor, improving the reliability of the semiconductor structure.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0013] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in an embodiment of this application.

[0014] Figures 2 to 8 This is a schematic diagram of a first fabrication process for a semiconductor structure provided in an embodiment of this application.

[0015] Figures 9 to 13 This is a schematic diagram of a second fabrication process for a semiconductor structure provided in an embodiment of this application.

[0016] The reference numerals and names in the figure are as follows:

[0017] 1. Substrate; 2. Shallow trench isolation structure; 3. Front-side transistor; 4. Front-side metal layer; 41. Front-side lower metal layer; 42. Front-side upper metal layer; 5. First carrier wafer; 6. First horizontal microchannel; 7. First opening; 8. First channel body; 9. Back-side transistor; 10. Second channel body; 11. Second horizontal microchannel; 12. Back-side metal layer; 121. Back-side lower metal layer; 122. Back-side upper metal layer; 13. Sacrificial layer; 14. Second carrier wafer; 15. Opening space; 16. Second opening; 17. Third carrier wafer; 21. Device region; 22. Channel region. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0020] In the following description, the terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0021] Flip FETs (FFETs), as a groundbreaking stacked transistor technology, have profound implications for sub-nanometer logic nodes. By stacking front-side N-type transistors (NFETs) and back-side P-type transistors (PFETs) back-to-back, they achieve symmetrical bifacial devices and interconnects, thus circumventing the complex process challenges of high aspect ratio vertical patterning required for Complementary Field-Effect Transistors (CFETs). Their potential lies in their superior process friendliness, such as naturally split gates, broad multi-threshold voltage adjustability, and design flexibility enabled by bifacial complementary metal-oxide-semiconductor (CMOS), while also supporting better scalability and routing capabilities, laying a solid foundation for future 3D integration technologies.

[0022] Flip 3D (F3D) integration technology, as a groundbreaking 3D integration solution, is significant because it innovatively utilizes both sides of a wafer to integrate 3D transistor stacking (such as FFET), 3D bi-sided interconnects, various 3D chip stacking methods (such as face-to-face, back-to-back, and face-to-face bonding), and bi-sided monolithic 3D (M3D) into one. This effectively solves the manufacturing challenges in traditional 3D integration and foreshadows its widespread application in high-density co-integration of logic or memory, 3D packaging expansion, and future heterogeneous computing, opening up a new dimension for semiconductor scaling.

[0023] However, heat dissipation solutions for the two technologies mentioned above have not been implemented at the device or wafer level, remaining at the package or system level. The semiconductor structures fabricated using F3D integration technology involve three-dimensional transistor stacking, double-sided interconnects, and multi-chip vertical integration, with heat sources originating at the transistor level and metal traces. If heat is dissipated only from the outside of the package, the heat must traverse complex multi-layered structures (including dielectric layers and bonding interfaces) to be dissipated, resulting in long paths and high thermal resistance. This leads to heat accumulation internally, forming localized hotspots, especially in high-power-density lower-layer transistor regions, potentially causing severe performance degradation and reliability issues. Therefore, elevating the heat dissipation solution to the transistor level is crucial to unlocking the full potential of F3D integration technology.

[0024] In a first aspect, embodiments of this application provide a method for preparing a semiconductor structure. Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in an embodiment of this application. See also... Figure 1 As shown, the method for preparing the semiconductor structure in the embodiments of this application may include steps 101 to 106.

[0025] Step 101: A semiconductor substrate is provided, wherein the semiconductor substrate includes: a fin structure and a substrate stacked along a first direction, and the fin structure includes: a first portion and a second portion stacked along the first direction.

[0026] Step 102: Based on the first part, form the front device layer.

[0027] Step 103: Bond the front device layer to the first carrier wafer and flip the first carrier wafer.

[0028] Step 104: Remove the substrate.

[0029] Step 105: Based on the second part, form the back device layer.

[0030] Step 106: Forming a microchannel whose extension direction is not perpendicular to the first direction. The microchannel includes a channel inlet, a channel outlet, and a channel body. The channel body is a hollow structure connecting the channel inlet and the channel outlet. The channel inlet is located on the back-side device layer for introducing the cooling medium; the channel outlet is located on the front-side device layer for discharging the cooling medium. Here, the back-side device layer refers to the device layer formed on the back side of the wafer, and the front-side device layer refers to the device layer formed on the front side of the wafer.

[0031] In this embodiment, after forming the front device layer using the first portion of the fin structure in the semiconductor substrate, the front device layer can be bonded to the first carrier wafer, and the first carrier wafer can be flipped. Then, the substrate is removed, and the back device layer is formed using the second portion of the fin structure. This results in a 3D stacked semiconductor structure arranged back-to-back along the first direction. Simultaneously, a microchannel is formed in the 3D stacked semiconductor structure. This microchannel extends entirely in a direction not perpendicular to the first direction, thus penetrating both the back and front device layers. The channel inlet is located on the back device layer, and the channel outlet is located on the front device layer. After a cooling medium is introduced into the 3D stacked semiconductor structure through the channel inlet, the cooling medium can sequentially remove the heat accumulated in the back and front device layers and discharge it from the channel outlet, thereby achieving heat dissipation of the 3D stacked semiconductor structure. Therefore, this embodiment can elevate the heat dissipation solution to the transistor level and form a double-sided heat dissipation channel in the 3D stacked semiconductor structure, effectively reducing the risk of thermal runaway caused by heat accumulation inside the stacked transistors and improving the reliability of the semiconductor structure.

[0032] In some embodiments, the front device layer includes a front device, which may be a CMOS logic transistor, a memory cell transistor, or the like, formed based on the first part of the fin structure.

[0033] In some embodiments, the cooling medium may be a liquid cooling medium (such as deionized water, fluorinated liquid, etc.), a gaseous cooling medium (such as nitrogen, air, etc.), or a phase change cooling medium (such as a refrigerant (i.e., hydrofluorocarbons, hydrofluoroolefins, etc.)).

[0034] In some embodiments, microchannels can be formed within the 3D stacked semiconductor structure by etching the dielectric structures in the front and back device layers using an etching process. Here, the microchannels are not connected to the active structures or conductive structures within the 3D stacked semiconductor structure, thus not affecting the circuit structure of the 3D stacked semiconductor structure.

[0035] In some embodiments, the flow channel inlet can be a structure connected to one end of the flow channel body, and the flow channel outlet can be a structure connected to the other end of the flow channel body. Here, the specific shapes of the flow channel inlet and outlet can be set according to actual needs, and this application embodiment does not limit them.

[0036] In some embodiments, the positions of the channel inlet and channel outlet can be adjusted. For example, the channel inlet can be located on the front device layer, and the channel outlet can be located on the back device layer. This application does not limit this.

[0037] In some embodiments, the first direction is the stacking direction (i.e., the vertical direction) of the 3D stacked semiconductor structure. The flow channel body extends along the first direction, making the flow channel body vertically arranged. On the one hand, this can enhance the flow intensity of the cooling medium; on the other hand, it makes the temperature distribution state within the 3D stacked semiconductor structure related to the flow path of the cooling medium, thereby achieving local temperature controllability.

[0038] In some embodiments, the flow channel body extends in a direction not perpendicular to the first direction and does not extend in the first direction, so that the flow channel body is inclined, thereby improving the spatial adaptability of the microchannel.

[0039] In some embodiments, microchannels can be formed by precisely controlling the etching process flow, and the main body of the channel is tilted as a whole.

[0040] In some embodiments, the inner wall of the microchannel can be coated with a protective material. This protective material can form an anti-corrosion coating, prepared from materials such as silicon nitride and alumina. Alternatively, the protective material can form a heat-enhancing coating, prepared from materials such as graphene and carbon nanotubes. In some embodiments, the inner wall of the microchannel can also be treated using a hydrophilic / hydrophobic modification process.

[0041] In this embodiment, a front and back device layer can be 3D stacked back-to-back in a first direction using both sides of a wafer, achieving a symmetrical double-sided device. Furthermore, by forming microchannels whose extension direction is not perpendicular to the first direction, and placing the microchannel inlets on the back device layer and the outlets on the front device layer, the cooling medium can flow from the back of the wafer to the front, thus completing a double-sided heat dissipation channel within the transistor. This effectively reduces the risk of thermal runaway caused by heat accumulation inside the stacked transistor, improving the reliability of the semiconductor structure.

[0042] In some embodiments, step 106 may include: forming a flow channel body in the flow channel region whose extension direction is not perpendicular to a first direction; forming a horizontal microchannel communicating with the flow channel body at least at one end of the flow channel body; and forming an opening communicating with the horizontal microchannel at the end of the horizontal microchannel away from the flow channel body, wherein the extension direction of the horizontal microchannel is perpendicular to the first direction; the opening communicates the horizontal microchannel with the external environment; and an opening and a horizontal microchannel constitute a flow channel inlet or a flow channel outlet.

[0043] In this embodiment, the 3D stacked semiconductor structure may include a device region and a channel region. The device region is used to fabricate the device structure, and the channel region is used to fabricate microchannels. The channel region and the device region are arranged adjacent to each other in a second direction, which is perpendicular to the first direction. In some embodiments, the second direction may be a plate Figure XThe direction can also be the Y direction of the layout, but this application does not limit this in the embodiments.

[0044] In some embodiments, to reduce fabrication difficulty and minimize damage to transistors within the 3D stacked semiconductor structure, a channel body extending in a direction not perpendicular to a first direction can be formed within the channel region, thereby penetrating at least partially through the 3D stacked semiconductor structure in the vertical direction. After forming the channel body, horizontal microchannels communicating with the channel body can be formed at one or both ends of the channel body. Furthermore, an opening communicating with the horizontal microchannel is formed at the end of the horizontal microchannel away from the channel body. Here, the opening connects the horizontal microchannel to the external environment. An opening and a horizontal microchannel communicating with the opening can constitute a channel inlet or a channel outlet.

[0045] For example, one end of the flow channel body may form a first horizontal microchannel and a first opening communicating with the first horizontal microchannel. The first horizontal microchannel and the first opening together constitute the flow channel outlet. And / or, the other end of the flow channel body may form a second horizontal microchannel and a first opening communicating with the second horizontal microchannel. The second horizontal microchannel and the second opening together constitute the flow channel inlet.

[0046] In some embodiments, the horizontal microchannel extends perpendicular to the first direction, meaning the horizontal microchannel can extend in any direction within a plane perpendicular to the vertical direction. By setting horizontal microchannels, the overall length of the microchannel can be increased, further improving heat dissipation performance.

[0047] In some embodiments, when the horizontal microchannel extends along the second direction, it can extend from the channel region to the device region, thereby getting closer to the transistors within the device region and improving heat dissipation performance. In some embodiments, when the horizontal microchannel extends along a third direction, it extends within the channel region, thereby forming a more independent heat dissipation system. Here, the third direction can be a direction perpendicular to the second direction or the first direction. In some embodiments, the horizontal microchannel extends along the second direction, which can be the channel direction. Thus, the horizontal microchannel can penetrate the source and / or drain regions of adjacent transistors, improving the uniformity of heat dissipation for multiple transistors.

[0048] In some embodiments, depending on the extension direction of the horizontal microchannel, the opening may be located in the device region and / or the channel region, and this application embodiment does not limit this.

[0049] In some embodiments, the flow channel body can be formed by an etching process. During the fabrication of the film layers in the front and / or back device layers, the flow channel body can be formed by etching the film layers. That is, step 106 in this embodiment can be performed during the execution of steps 102 to 105. In some embodiments, the film layer in the flow channel region is a dielectric structure. This dielectric structure is formed by the deposition of a dielectric material. The dielectric structure is a structure in a semiconductor structure used to achieve electrical isolation between structures.

[0050] In some embodiments, horizontal microchannels can be achieved by creating grooves in different film layers within the 3D stacked semiconductor structure; or, horizontal microchannels can be achieved by removing the sacrificial layer during the fabrication process of the 3D stacked semiconductor structure. This application does not limit the specific implementation of these embodiments.

[0051] In this embodiment, by setting a flow channel region and a device region, and forming a flow channel body within the flow channel region, the loss of the device layer during the fabrication of the flow channel body can be reduced. Secondly, by integrating the horizontal microchannel and the opening as the flow channel inlet and outlet, on the one hand, the overall length of the microchannel can be increased, improving heat dissipation performance; on the other hand, a heat dissipation path with a different extension direction than the flow channel body can be provided, increasing the overlap area between the microchannel and the transistor, and meeting the heat dissipation requirements of different parts of the transistor.

[0052] In some embodiments, step 106 may include: after removing the substrate, etching the dielectric structure in the flow channel region within the front device layer to form a first flow channel body; after forming the back device layer, etching the dielectric structure in the flow channel region within the back device layer until the first flow channel body is exposed to form a second flow channel body.

[0053] In this embodiment, the flow channel body can be formed by two etching processes. The first process is to form the first flow channel body by etching the dielectric structure in the flow channel region within the front device layer after wafer flipping and substrate removal. The second process is to form the second flow channel body by etching the dielectric structure in the flow channel region within the back device layer after the back device layer is formed based on the second part of the fin structure until the first flow channel body is exposed.

[0054] Here, the second flow channel body is connected to the first flow channel body. The first flow channel body and the second flow channel body together form the flow channel body. Accordingly, the flow channel inlet can be located at the first end of the second flow channel body, and the flow channel outlet can be located at the second end of the first flow channel body; the first end is the end of the second flow channel body that is far away from the first flow channel body, and the second end is the end of the first flow channel body that is far away from the second flow channel body.

[0055] In some embodiments, the first flow channel body has a shape that gradually tapers along the etching direction, and the second flow channel body also has a shape that gradually tapers along the etching direction. Here, a gradually tapering shape refers to a structure whose inner diameter gradually decreases. That is, the flow channel body includes two tapering sections, and the two tapering sections are connected. Thus, the flow channel body as a whole has a shape that changes from large to small, then large again, and finally small. Through this changing shape, the cooling medium can form micro-jet sprays within the first and second flow channel bodies, thereby scouring the inner surface of the flow channels and improving the local heat dissipation coefficient.

[0056] In some embodiments, the lengths of the first and second flow channel bodies in the first direction can be set according to actual needs, and this application embodiment does not limit this. In some embodiments, the length of the first flow channel body in the first direction is at least greater than the length of the transistor in the front device layer in the first direction. In some embodiments, the length of the second flow channel body in the first direction is at least greater than the length of the transistor in the back device layer in the first direction.

[0057] In the embodiments of this application, by forming the first flow channel body and the second flow channel body in steps, the fabrication process of the microchannel can be made compatible with the fabrication process of the 3D stacked semiconductor structure, thereby improving the application of microchannels in next-generation integrated circuits.

[0058] In some embodiments, the device region of the front device layer includes a front transistor and a front metal layer, the front metal layer being disposed on the side of the front transistor away from the back transistor; the device region of the back device layer includes a back transistor and a back metal layer, the back metal layer being disposed on the side of the back transistor away from the front transistor.

[0059] Understandably, a 3D stacked semiconductor structure can have a structure in which a front metal layer, a front transistor, a back transistor, and a back metal layer are stacked sequentially. The front transistor and the back transistor are arranged back-to-back, and an isolation structure is provided between them. Here, the isolation structure can be a shallow trench isolation structure and / or an intermediate dielectric isolation structure, etc., and this application embodiment does not limit this.

[0060] In some embodiments, the metal layer is a metal trace structure that provides signals and power to the transistor. There can be multiple metal layers, each with metal traces housed within a dielectric layer. Metal traces between adjacent layers can be configured to be perpendicular to each other, and adjacent metal traces can be connected via metal vias. In some embodiments, there can be 18 metal layers, comprising metals M0 through M17.

[0061] In some embodiments, a horizontal microchannel communicating with the main flow channel body is formed, including at least one of the following:

[0062] Within the flow channel region, a horizontal microchannel is formed that is connected to one end of the main flow channel body;

[0063] A horizontal microchannel is formed in the front metal layer, which is connected to one end of the main flow channel;

[0064] A horizontal microchannel is formed in the back metal layer, which is connected to one end of the main flow channel;

[0065] A horizontal microchannel is formed between the front metal layer and the first substrate wafer, which is connected to one end of the main flow channel;

[0066] A horizontal microchannel is formed between the back metal layer and the second carrier wafer, which is connected to one end of the main flow channel.

[0067] In this application embodiment, the horizontal microchannels can be formed in various locations. Based on the different formation locations, this application embodiment exemplarily illustrates three types of horizontal microchannels. The first type is where the horizontal microchannel is formed within the channel region, without affecting the fabrication of the structure within the device region, and can complete heat dissipation of the 3D stacked semiconductor structure on the sidewalls of the transistor. The second type is where the horizontal microchannel is positioned across regions, extending from the channel region to the device region, and is compatible with the metal layers in the device region, thereby completing heat dissipation of the 3D stacked semiconductor structure near the metal layers. Here, in the second type, the horizontal microchannel can be located in two places: either in the front metal layer or the back metal layer. The third type is where the horizontal microchannel is positioned across regions, extending from the channel region to the device region, and is compatible with the metal layers and the carrier wafer in the device region, thereby completing heat dissipation of the 3D stacked semiconductor structure near the metal layers. Here, in the third type, the horizontal microchannel can be located in two places: either between the front metal layer and the first carrier wafer, or between the back metal layer and the second carrier wafer.

[0068] It should be noted that the second type of horizontal microchannel is closer to the transistor than the third type, thus further improving heat dissipation efficiency. The third type of horizontal microchannel is connected to the carrier wafer. When the carrier wafer is further processed into transistors, this horizontal microchannel can dissipate heat for the transistor structures on both sides simultaneously, thereby achieving wafer-level built-in heat dissipation without adding process steps.

[0069] In some embodiments, the wafer bonded to a higher metal layer in the front metal layer is a first wafer, and the wafer bonded to a higher metal layer in the back metal layer is a second wafer. The materials of the first and second wafers can be set according to actual needs, and this application embodiment does not limit this. In some embodiments, a higher metal layer in the front metal layer is formed on the wafer, and the wafer used for bonding to a lower metal layer in the front metal layer is a third wafer.

[0070] In some embodiments, to effectively prevent damage to the metal layer from the horizontal microchannels, the extension direction of the horizontal microchannels should be consistent with the extension direction of the same-layer metal in the metal layer. Here, the same-layer metal is the metal located in the same film layer as the horizontal microchannels. For example, when the horizontal microchannels are located in the film layer containing the M4 metal, and the M4 metal extends along the second direction, the extension direction of the horizontal microchannels is the second direction.

[0071] In the embodiments of this application, the various placement positions of the horizontal microchannels meet the heat dissipation requirements of different application scenarios.

[0072] In some embodiments, forming a horizontal microchannel in a metal layer may include: forming a groove on the surface of a lower metal layer toward a higher metal layer; and / or forming a groove on the surface of a higher metal layer toward a lower metal layer.

[0073] In the embodiments of this application, the terms "lower metal layer" and "higher metal layer" are relative concepts. The lower metal layer refers to the metal layer that is closer to the transistor than the higher metal layer, while the higher metal layer refers to the metal layer that is farther away from the transistor than the lower metal layer.

[0074] For example, assuming there are ten metal layers in total, when the lower metal layers include metals M0 to M3, the higher metal layers may include metals M4 to M9. When the lower metal layers include metals M0 to M6, the higher metal layers may include metals M7 to M9.

[0075] In some embodiments, forming a horizontal microchannel includes: forming a groove on the surface of the lower metal layer facing the upper metal layer, forming a groove on the surface of the upper metal layer facing the lower metal layer, or simultaneously forming grooves on the surface of the lower metal layer facing the upper metal layer and the surface of the upper metal layer facing the lower metal layer.

[0076] In some embodiments, the lower metal layer and the higher metal layer are formed on different carrier wafers. After the lower metal layer and the higher metal layer are bonded, the grooves on the surface of the lower metal layer and / or the higher metal layer are closed to form horizontal microchannels. The lower metal layer is the metal layer closer to the transistor relative to the horizontal microchannels; the higher metal layer is the metal layer farther away from the transistor relative to the horizontal microchannels.

[0077] In some embodiments, the formation of the grooves can be configured according to actual needs, and this application embodiment does not limit this. For example, the cross-section of the groove can be rectangular, square, semi-circular, etc. In some embodiments, there can be multiple grooves, each groove forming a horizontal microchannel, or two grooves can be combined to form a horizontal microchannel.

[0078] In the embodiments of this application, grooves are formed by etching the surfaces of the lower metal layer and / or the higher metal layer, which can form horizontal microchannels after the lower metal layer and the higher metal layer are bonded.

[0079] In some embodiments, forming a horizontal microchannel between the metal layer and the wafer may include: forming a groove on the surface of the metal layer facing the wafer; and / or forming a groove on the surface of the wafer facing the metal layer.

[0080] In this embodiment of the application, forming a horizontal microchannel includes: forming a groove on the surface of the front metal layer facing the first wafer, forming a groove on the surface of the first wafer facing the front metal layer, or simultaneously forming grooves on both the surface of the front metal layer facing the first wafer and the surface of the first wafer facing the front metal layer.

[0081] In some embodiments, forming a horizontal microchannel includes: forming a groove on the surface of the back metal layer facing the second wafer, forming a groove on the surface of the second wafer facing the back metal layer, or simultaneously forming grooves on both the surface of the back metal layer facing the second wafer and the surface of the second wafer facing the back metal layer.

[0082] In some embodiments, a front metal layer is formed on a carrier wafer different from the first carrier wafer. After the front metal layer and the first carrier wafer are bonded, the grooves on the surface of the front metal layer and / or the first carrier wafer are closed to form horizontal microchannels. In some embodiments, a back metal layer is formed on a carrier wafer different from the second carrier wafer. After the back metal layer and the second carrier wafer are bonded, the grooves on the surface of the back metal layer and / or the second carrier wafer are closed to form horizontal microchannels.

[0083] In some embodiments, the shape and number of grooves can be set according to actual needs, and this application embodiment does not limit this.

[0084] In the embodiments of this application, by etching the surface of the metal layer and / or the wafer to form grooves, horizontal microchannels can be formed after the metal layer and the wafer are bonded.

[0085] In some embodiments, forming an opening communicating with the horizontal microchannel at the end of the horizontal microchannel away from the channel body may include: when the horizontal microchannel is located in the front metal layer and / or the back metal layer, using an etching process to etch a high-layer metal layer to form the opening, wherein the opening is not communicating with the metal in the high-layer metal layer; when the horizontal microchannel is located between the metal layer and the wafer, forming the opening in the wafer.

[0086] In this embodiment, when the horizontal microchannel is located in the front metal layer, an etching process can be used to etch the higher metal layers in the front metal layer until the horizontal microchannel is exposed, thereby forming an opening connecting the horizontal microchannel. Similarly, when the horizontal microchannel is located in the back metal layer, the same method can be used to form the opening. When the horizontal microchannel is located between the metal layer and the wafer, the opening can be etched in the wafer according to the position of the horizontal microchannel.

[0087] The semiconductor structure and its fabrication method in this application are described below with specific embodiments.

[0088] First embodiment.

[0089] Figures 2 to 8 This is a schematic diagram of a first fabrication process for a semiconductor structure provided in an embodiment of this application. Wherein, Figures 2 to 6 ,as well as Figures 7 to 8 (a) shows cross-sectional views of the semiconductor structure along the length of the source and drain regions. Figures 7 to 8 (b) shows a top view of the semiconductor structure. See also Figures 2 to 8 As shown, the method for fabricating the semiconductor structure in the embodiments of this application may include:

[0090] The first step involves constructing the logic circuit (i.e., the front-side transistor 3) and laying out the corresponding signal lines (i.e., the front-side metal layer 4) within the device region 21 on the front side of the silicon wafer, and reserving microchannel space in the flow channel region on one side of the device region 21 to obtain... Figure 2 The structure shown.

[0091] Here, forming logic circuits and corresponding signal lines on the front side of a silicon wafer may include: providing a silicon wafer, etching the upper portion of the silicon wafer to form a fin structure, and retaining the lower portion of the silicon wafer to form a substrate 1. The substrate 1 and the fin structure together constitute a semiconductor substrate 1. Here, the fin structure includes a first portion and a second portion. The first portion is farther away from the substrate 1 than the second portion. Then, a shallow trench isolation structure 2 is deposited on the substrate 1. The shallow trench isolation structure 2 surrounds the second portion of the fin structure, and the first portion is exposed outside the shallow trench isolation structure 2. Then, based on the first portion of the fin structure, a front-side transistor 3 and a front-side metal layer 4 are sequentially formed.

[0092] Here, the device region 21 and the flow channel region 22 are arranged adjacent to each other.

[0093] The second step involves bonding the first carrier wafer 5 (i.e., the carrier wafer bonded to the front metal layer 4) to the front metal layer 4, then flipping the first carrier wafer 5 and thinning the original wafer (i.e., removing the substrate 1). A first horizontal microchannel 6 is pre-formed on the surface of the first carrier wafer 5 facing the front metal layer 4, and a first opening 7 is pre-formed on one side of the first horizontal microchannel 6, resulting in... Figure 3 The structure shown.

[0094] Here, the first horizontal microchannel 6 and the first opening 7 together form the flow outlet of the microchannel. The first horizontal microchannel 6 can be a first groove on the first carrier wafer 5.

[0095] The third step involves etching the first flow channel body 8 within the flow channel region 22 to connect it to the first horizontal microchannel 6 on the first carrier wafer 5, resulting in... Figure 4 The structure shown.

[0096] Here, by bonding the front metal layer 4 to the first carrier wafer 5, the first groove on the surface of the first carrier wafer 5 can be closed as a first horizontal microchannel 6.

[0097] Step 4: Construct the logic circuit (i.e., the back-side transistor 9) and lay out the corresponding signal lines (i.e., the lower metal layer in the back metal layer, also referred to as the back low metal layer 121) within the device region 21 on the back side of the silicon wafer. Form a second horizontal microchannel 11 on the surface of the back low metal layer 121 facing the higher metal layer in the back metal layer (also referred to as the back high metal layer). Simultaneously, etch the second channel body 10 within the device region 21 to obtain... Figure 5 The structure shown.

[0098] Here, the second flow channel body 10 is connected to the second horizontal microchannel 11 and the first flow channel body 8. The contact surface between the second flow channel body 10 and the first flow channel body 8 is narrower at the top and wider at the bottom, which can create a micro-jet effect. The second flow channel body 10 and the first flow channel body 8 together form the flow channel body. The second horizontal microchannel 11 can be a second groove on the back low metal layer 121.

[0099] Step 5: On the second carrier wafer 14 (i.e., the carrier wafer bonded to the back metal layer 12), a sacrificial layer 13 and a back high metal layer 122 are sequentially prepared. Then, using a hybrid bonding process, the back low metal layer 121 and the back high metal layer 122 are bonded together to form the back metal layer 12, resulting in... Figure 6 The structure shown.

[0100] Here, by bonding the back lower metal layer 121 and the back upper metal layer 122, the second groove on the surface of the back lower metal layer 121 can be closed as a second horizontal microchannel 11.

[0101] Step 6: Remove the sacrificial layer 13 to separate the second carrier wafer 14 from the back high-layer metal layer 122, obtaining... Figure 7 The structure shown.

[0102] Here, as Figure 7 As shown in (b), the top view shows the layout of the rear high-level metal layer 122, which requires reserved opening space 15.

[0103] Step 7: At the location of the opening space 15, a second opening 16 connecting to the second horizontal microchannel 11 is formed through an etching process, resulting in... Figure 8 The structure shown.

[0104] Here, the second horizontal microchannel 11 and the second opening 16 together form the flow channel inlet. The flow channel inlet, flow channel outlet, and flow channel body together constitute the microchannel. Figure 8 As shown in (b), the top view shows that a second opening 16 can be formed at the opening space 15.

[0105] This completes the fabrication of the semiconductor structure.

[0106] The second embodiment.

[0107] Figures 9 to 13 This is a schematic diagram illustrating a second fabrication process for the semiconductor structure provided in an embodiment of this application. Wherein, Figures 9 to 13 The image shows a cross-sectional view of the semiconductor structure along the length of the source and drain regions. See also... Figures 9 to 13 As shown, the method for fabricating the semiconductor structure in the embodiments of this application may include:

[0108] The first step involves constructing the logic circuit (i.e., the front-side transistor 3) and laying out the corresponding signal lines (i.e., the lower metal layer in the front-side metal layer, also referred to as the front-side lower metal layer 41) within the device region 21 on the front side of the silicon wafer, and reserving microchannel space within the channel region 22 on one side of the device region 21. Then, a first horizontal microchannel 6 is formed on the surface of the front-side lower metal layer 41 facing the higher metal layer in the front-side metal layer (also referred to as the front-side higher metal layer), resulting in... Figure 9 The structure shown.

[0109] Here, the method for forming logic circuits and corresponding signal lines on the front side of the silicon wafer can be found in the first embodiment, and will not be repeated here for the sake of brevity. The first horizontal microchannel 6 can be the third groove on the front lower metal layer 41.

[0110] The second step involves sequentially fabricating a sacrificial layer 13 and a front-side high-layer metal layer 42 on the third carrier wafer 17. Then, using a hybrid bonding process, the front-side low-layer metal layer 41 and the front-side high-layer metal layer 42 are bonded together to form the front-side metal layer 4, resulting in... Figure 10 The structure shown.

[0111] Here, by bonding the front low metal layer 41 and the front high metal layer 42, the third groove on the surface of the front low metal layer 41 can be closed into a first horizontal microchannel 6.

[0112] The third step involves removing the sacrificial layer 13 to separate the third carrier wafer 17 from the front high-layer metal layer 42. Then, at the location of the pre-reserved opening space 15 in the front high-layer metal layer 42, an etching process is used to form the first opening 7 connecting to the first horizontal microchannel 6, resulting in... Figure 11 The structure shown.

[0113] Fourth step: Bond the first carrier wafer 5 to the front metal layer 4, then flip the first carrier wafer 5 and remove the substrate 1; then etch the first channel body 8 in the channel region 22 to connect the first horizontal microchannel 6 on the surface of the front low metal layer 41, to obtain Figure 12 The structure shown.

[0114] In some embodiments, the surface of the first carrier wafer 5 facing the front metal layer 4 also has a first opening 7. In some embodiments, the first carrier wafer 5 can be removed after the back device layer is fabricated.

[0115] Step 5: Using the same process as steps 4 to 7 in the first embodiment, obtain... Figure 13 The structure shown.

[0116] This completes the fabrication of the semiconductor structure.

[0117] In the above embodiments, by combining two vertical etching processes with hybrid bonding of the FFET standard process, the fabrication of horizontal microchannels in the FFET signal line layout and the interconnection of heat dissipation channels on both sides are achieved, thereby realizing a double-sided heat dissipation structure based on FFET. This helps reduce the risk of chip thermal runaway. The double-sided interconnect cooling scheme can ensure effective heat dissipation of transistors on both sides, solve the heat dissipation problem of transistor 9 on the back side and its wiring, and improve system lifespan and reliability.

[0118] This application's embodiments are also applicable to transistor structures adapted to FFET technology, such as GAA FETs, CFETs, and planar transistors. This application's embodiments are also applicable to structures where the metal trace layers are power supply networks, hybrid signal-power supply networks, and clock networks. This application's embodiments are also applicable to FFET structures where memory devices are flip-chip bonded to each other, or logic devices are flip-chip bonded to memory devices. Based on the FFET process background, this application's embodiments provide an efficient thermal management solution. Its successful application will directly unleash the enormous potential of 3D integration, paving the way for the creation of higher-density, more powerful logic chips, with broad application prospects.

[0119] The embedded microchannel structure proposed in this application has extremely high physical visibility, and its features can be obtained through standard semiconductor reverse engineering methods. For the packaged logic chip, longitudinal slicing using focused ion beam (FIB) combined with high-resolution scanning electron microscopy (SEM) or transmission electron microscopy (TEM) can clearly observe whether specific horizontal microchannel cavities and vertical via arrays exist in the transistor's adjacent region (such as deep within substrate 1 or between back-end interconnect layers). Furthermore, the inner walls of the microchannels typically involve special protective materials or hydrophilic / hydrophobic modification processes, which can be identified through energy dispersive spectroscopy (EELS).

[0120] Prior to costly destructive physical analysis, the embodiments of this application possess significant non-destructive features. Since microchannel heat dissipation acts directly on the vicinity of the heat source in the logic device, its heat conduction path differs fundamentally from that of traditional air-cooled or liquid-cooled heat sinks (cold plates). During chip operation, high-precision infrared thermal imaging (lock-in thermography) or transient thermal resistance testing techniques can capture the chip's specific temperature gradient distribution, exhibiting a lower thermal resistance coefficient and a more uniform heat distribution profile. Simultaneously, X-ray micro-CT technology allows for visualization of the internal structure without damaging the chip package, providing a preliminary indication of the existence of the microchannel network.

[0121] For example, see TEM images. Figure 8 As shown, the semiconductor structure in this embodiment has double-sided heat dissipation channels, with one heat dissipation channel on the wafer and connected to the double-sided heat dissipation channels. See also Figure 13 As shown, the semiconductor structure in this embodiment has double-sided heat dissipation channels, which are connected to each other in the signal line layout.

[0122] Secondly, embodiments of this application provide a semiconductor structure. The semiconductor structure can be fabricated using the method described in any embodiment of the first aspect. The semiconductor structure includes: a front device layer and a back device layer stacked along a first direction; the front device layer and the back device layer are formed based on the same fin structure and are disposed opposite to each other; a microchannel extending in a direction not perpendicular to the first direction, wherein the microchannel includes a channel inlet, a channel outlet, and a channel body connecting the channel inlet and the channel outlet; the channel inlet is disposed on the back device layer for introducing a cooling medium; the channel outlet is disposed on the front device layer for discharging the cooling medium.

[0123] In some embodiments, the semiconductor structure includes a device region 21 and a channel region 22; the channel region 22 and the device region 21 are arranged adjacent to each other in a second direction, which is perpendicular to the first direction; wherein the semiconductor structure further includes: a horizontal microchannel communicating with one end of the channel body, and an opening communicating with the horizontal microchannel at the end of the horizontal microchannel away from the channel body, wherein the extension direction of the horizontal microchannel is perpendicular to the first direction; the opening communicates the horizontal microchannel with the external environment; the opening is located in the device region 21 and / or the channel region 22; an opening and a horizontal microchannel constitute a channel inlet or a channel outlet.

[0124] In the embodiments of this application, the specific structure of the semiconductor structure can be found in the description of any embodiment of the first aspect, and will not be repeated here for the sake of brevity.

[0125] Thirdly, embodiments of this application provide an electronic device. It includes a circuit board and a semiconductor structure as described in the above embodiments, the semiconductor structure being disposed on the circuit board. The specific structure of the semiconductor structure can be found in the description of any embodiment of the first aspect; for the sake of brevity, it will not be repeated here.

[0126] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein the semiconductor substrate includes: a fin structure and a substrate stacked along a first direction, the fin structure including: a first portion and a second portion stacked along the first direction; Based on the first part, a front-side device layer is formed; The front-side device layer is bonded to the first carrier wafer, and the first carrier wafer is flipped. Remove the substrate; Based on the second part, a back-side device layer is formed; The method further includes: A microchannel is formed whose extension direction is not perpendicular to the first direction. The microchannel includes a channel inlet, a channel outlet, and a channel body. The channel body is a hollow structure that connects the channel inlet and the channel outlet. The channel inlet is disposed on the back device layer and is used to introduce cooling medium. The channel outlet is disposed on the front device layer and is used to discharge cooling medium.

2. The preparation method according to claim 1, characterized in that, The semiconductor structure includes a device region and a flow channel region; the flow channel region and the device region are arranged adjacent to each other in a second direction, which is perpendicular to the first direction; Wherein, forming a microchannel whose extension direction is not perpendicular to the first direction includes: Within the flow channel region, a flow channel body is formed whose extending direction is not perpendicular to the first direction; At least at one end of the main body of the flow channel, a horizontal microchannel is formed in communication with the main body of the flow channel, and at the end of the horizontal microchannel away from the main body of the flow channel, an opening is formed in communication with the horizontal microchannel, wherein the extension direction of the horizontal microchannel is perpendicular to the first direction; the opening connects the horizontal microchannel with the external environment; one opening and one horizontal microchannel constitute a flow channel inlet or a flow channel outlet.

3. The preparation method according to claim 1 or 2, characterized in that, in, The formation of microchannels whose extension direction is not perpendicular to the first direction includes: After removing the substrate, the dielectric structure within the flow channel region of the front-side device layer is etched to form the first flow channel body; After forming the back device layer, the dielectric structure within the back device layer in the channel region is etched until the first channel body is exposed to form the second channel body; The first flow channel body and the second flow channel body constitute the flow channel body. The flow channel inlet is located at the first end of the second flow channel body, and the flow channel outlet is located at the second end of the first flow channel body. The first end is the end of the second flow channel body that is away from the first flow channel body, and the second end is the end of the first flow channel body that is away from the second flow channel body.

4. The preparation method according to claim 2, characterized in that, The device region of the front device layer includes a front transistor and a front metal layer, the front metal layer being disposed on the side of the front transistor away from the back transistor; the device region of the back device layer includes a back transistor and a back metal layer, the back metal layer being disposed on the side of the back transistor away from the front transistor. The horizontal microchannels that communicate with the main flow channel include at least one of the following: Within the flow channel region, a horizontal microchannel is formed that communicates with one end of the flow channel body; A horizontal microchannel is formed in the metal layer, which is connected to one end of the main flow channel. A horizontal microchannel is formed between the metal layer and the carrier wafer, which is connected to one end of the main flow channel; The metal layer includes the front metal layer and the back metal layer.

5. The preparation method according to claim 4, characterized in that, The formation of a horizontal microchannel in the metal layer that communicates with one end of the main flow channel includes: A groove is formed on the surface of the lower metal layer facing the upper metal layer; and / or, a groove is formed on the surface of the upper metal layer facing the lower metal layer; The lower metal layer and the higher metal layer are formed on different wafers. After the lower metal layer and the higher metal layer are bonded, the groove is closed to form the horizontal microchannel. The lower metal layer is the metal layer closer to the transistor than the horizontal microchannel, which is one of the front metal layer and the back metal layer. The higher metal layer is the metal layer farther away from the transistor than the horizontal microchannel, which is one of the front metal layer and the back metal layer.

6. The preparation method according to claim 4, characterized in that, A horizontal microchannel is formed between the metal layer and the carrier wafer, including: A groove is formed on the surface of the metal layer facing the wafer; and / or, a groove is formed on the surface of the wafer facing the metal layer; The metal layer is formed on the wafers of different carrier wafers. After the metal layer and the carrier wafer are bonded, the groove is closed to form the horizontal microchannel.

7. The preparation method according to claim 4, characterized in that, The method of forming an opening communicating with the horizontal microchannel at the end of the horizontal microchannel away from the channel body includes: When the horizontal microchannel is located in the metal layer, an etching process is used to etch the upper metal layer to form the opening, wherein the opening is not connected to the metal in the upper metal layer; When the horizontal microchannel is located between the metal layer and the carrier wafer, the opening is formed in the carrier wafer.

8. A semiconductor structure, characterized in that, Prepared by the preparation method according to any one of claims 1 to 7, comprising: The front device layer and the back device layer are stacked along a first direction; the front device layer and the back device layer are fabricated based on the same fin structure, and the front device layer and the back device layer are arranged opposite to each other; A microchannel extending in a direction not perpendicular to the first direction, wherein the microchannel includes a channel inlet, a channel outlet, and a channel body connecting the channel inlet and the channel outlet; the channel inlet is disposed on the back device layer for introducing cooling medium; the channel outlet is disposed on the front device layer for discharging cooling medium.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure includes a device region and a flow channel region; the flow channel region and the device region are arranged adjacent to each other in a second direction, which is perpendicular to the first direction; The semiconductor structure further includes: a horizontal microchannel communicating with one end of the channel body, and an opening communicating with the horizontal microchannel at the end of the horizontal microchannel away from the channel body, wherein the extension direction of the horizontal microchannel is perpendicular to the first direction; the opening communicates the horizontal microchannel with the external environment; the opening is located in the device region and / or the channel region; one opening and one horizontal microchannel constitute a channel inlet or a channel outlet.

10. An electronic device, characterized in that, Includes a circuit board and a semiconductor structure as described in claim 8 or 9.

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