Semiconductor device and method of forming the same

Abstract

Semiconductor devices are fabricated on a wafer to include one or more buffer regions that can be used to singulate or dice the semiconductor devices from the wafer in a die singulation process. The buffer regions of the semiconductor devices can be located between scribe line regions of the wafer and seal ring regions of the semiconductor devices. Instead of cutting trenches in the scribe line regions of the wafer, trenches can be cut in the buffer regions of the semiconductor devices using a laser beam. The wafer can then be singulated or diced into individual semiconductor devices using another laser beam and / or a wafer saw to cut completely through the scribe line regions. Embodiments of the present disclosure provide semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Typically, multiple semiconductor devices are fabricated on a single wafer, such as a silicon (Si) wafer. Fabricating multiple semiconductor devices on the same wafer allows manufacturing operations such as deposition, photolithography patterning, and / or etching to be shared between semiconductor devices, which reduces processing time, cost, and complexity in high-volume semiconductor device manufacturing. Summary of the Invention

[0003] Some embodiments of this disclosure provide a method for forming a semiconductor device, the method comprising: forming a first semiconductor device including a first device region, a first sealing ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first sealing ring region; forming a second semiconductor device including a second device region, a second sealing ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second sealing ring region; forming a scribing region laterally located between the first buffer region and the second buffer region; forming a first trench in the first buffer region and a second trench in the second buffer region; and cutting through the scribing region between the first trench and the second trench.

[0004] Other embodiments of this disclosure provide a semiconductor device comprising: a device region; a sealing ring region laterally surrounding the device region, wherein the sealing ring region includes a plurality of metallization structures; and a buffer region laterally adjacent to one or more sides of the sealing ring region such that the sealing ring region is located between the buffer region and the device region, wherein the density of the plurality of metallization structures in the sealing ring region is greater than the density of the metallization structures in the buffer region.

[0005] Another embodiment of this disclosure provides a method for forming a semiconductor device, the method comprising: forming a first semiconductor die of the semiconductor device in a first substrate, wherein the first semiconductor die includes a first device region, a first sealing ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first sealing ring region, and wherein the first buffer region includes a first dielectric region without metallization; forming a second semiconductor die of the semiconductor device in a second substrate, wherein the second semiconductor die includes a second device region, a second sealing ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second sealing ring region, and wherein the second buffer region includes a second dielectric region without metallization; bonding the first substrate to the second substrate to form a substrate stack, wherein the first semiconductor die of the semiconductor device is bonded to the second semiconductor die of the semiconductor device; forming a trench through the second dielectric region of the second buffer region and into the first dielectric region of the first buffer region; and cutting through a scribing region of the substrate stack laterally adjacent to the trench. Attached Figure Description

[0006] The aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A and Figure 1B This is a schematic diagram of an example of the semiconductor device described in this article.

[0008] Figure 2A and Figure 2B An example of a semiconductor device formed on a wafer is shown.

[0009] Figures 3A to 3C This is a schematic diagram of an exemplary embodiment of forming a semiconductor device on a wafer as described herein.

[0010] Figures 4A to 4G This is a schematic diagram of an exemplary embodiment of the die-cutting process for cutting semiconductor devices from wafers as described herein.

[0011] Figures 5A to 5G This is a schematic diagram of an exemplary embodiment of the die-cutting process for cutting semiconductor devices from wafers as described herein.

[0012] Figures 6A to 6D This is a schematic diagram of an exemplary embodiment of a semiconductor device cut from a wafer as described herein.

[0013] Figures 7A to 7FThis is a schematic diagram of an exemplary embodiment of the die-cutting process for cutting semiconductor devices from wafers as described herein.

[0014] Figure 8 This is a flowchart of an exemplary process described herein related to forming multiple semiconductor devices on a wafer.

[0015] Figure 9 This is a flowchart of an exemplary process described herein related to forming multiple semiconductor devices on a wafer.

[0016] Figures 10A to 10F This is a schematic diagram of an exemplary embodiment of the die-cutting process for cutting semiconductor devices from wafers as described herein. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Additionally, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for clarity and simplicity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0019] At nodes during the fabrication of semiconductor devices on a wafer, the wafer can be diced or cut to create individual semiconductor devices. After dicing, additional processing of the semiconductor devices, such as testing and packaging, can be performed. The wafer may include scribe lines, which are areas on the wafer surrounding the semiconductor devices. These scribe lines are fabricated to provide dedicated areas on the wafer through which it can be diced. In some cases, the scribe lines on the wafer may include structures for other purposes, such as process control monitoring (PCM) structures for monitoring various aspects of the semiconductor device during manufacturing.

[0020] Various die-cutting techniques can be used to dic or cut wafers into individual semiconductor devices. For example, a diamond-coated saw can be used to cut through (e.g., by sawing) the scribe lines on the wafer. Another example is the use of a laser beam to cut through (e.g., by laser cutting) the scribe lines on the wafer. In some cases, a combination of laser cutting and sawing is used to cut through the scribe lines on the wafer, thereby cutting the wafer into individual semiconductor devices.

[0021] In other instances, the process of dicing a wafer into individual semiconductor devices can introduce manufacturing defects because sawing and / or laser dicing induce mechanical stresses in various regions of the semiconductor device. For example, the process generates debris by removing material from the scribe lines of the wafer, and this debris can damage the semiconductor device by mechanically abrading its layers and / or structures. As another example, the process generates heat and vibration in the structures within the scribe lines, which can propagate to the layers and / or structures of the functional regions of the semiconductor device, weakening and / or damaging these layers and / or structures. These and other mechanical stresses induced in various regions of the semiconductor device by the dicing process can cause cracks, delamination, and / or other types of physical damage to the layers and / or structures of the semiconductor device.

[0022] In some embodiments described herein, semiconductor devices are fabricated on a wafer to include one or more buffer regions that can be used in a die-cutting process to cleave or slice the semiconductor device from the wafer. The buffer regions of the semiconductor device may be located between a scribe line region on the wafer and a sealing ring region of the semiconductor device. The sealing ring region may laterally surround a device region of the semiconductor device, and the buffer regions may laterally surround the sealing ring region of the semiconductor device.

[0023] In die dicing, a laser beam can be used to cut trenches in the buffer region of a semiconductor device, rather than cutting trenches in the scribing region of the wafer. Another laser beam and / or a wafer saw can then be used to cut completely through the scribing region, dicing or cutting the wafer into individual semiconductor devices.

[0024] The pattern density (e.g., the density of the structure) in the buffer region is lower than that in the scribe region and the device region. The lower pattern density in the buffer region provides fewer paths through which heat and mechanical vibrations from laser dicing and / or sawing can propagate to the device region of the semiconductor device. In other words, the buffer region effectively buffers the device region from the thermal and mechanical stresses generated during the die-cutting process, reducing the likelihood that these mechanical stresses could cause cracking, delamination, and / or other types of physical damage to the layers and / or structure of the semiconductor device. In this way, the buffer region described herein can reduce defect rates, improve reliability, and / or increase the yield of semiconductor devices fabricated on wafers.

[0025] Figure 1A and Figure 1B This is a schematic diagram of example 100 of the semiconductor device 102 described herein. Figure 1A A top view of semiconductor device 102 is shown, and Figure 1B It shows along Figure 1A Cross-sectional view of semiconductor device 102 along center line AA.

[0026] like Figure 1A As shown, the semiconductor device 102 may include a device region 104, a sealing ring region 106 surrounding the device region 104, and a buffer region 108 surrounding the sealing ring region 106.

[0027] Device region 104 may correspond to the active region of semiconductor device 102. Semiconductor device 102 may be a system-on-a-chip (SoC) die, central processing unit (CPU) die, graphics processing unit (GPU) die, digital signal processing (DSP) die, application-specific integrated circuit (ASIC) GPU, image sensor die, HPC die, and / or other types of semiconductor dies including multiple functional regions 110-116 laterally distributed across device region 104. The top view layout and number, size, shape, and / or arrangement of functional regions 110-116 in semiconductor device 102 are examples, and other layouts, numbers, sizes, shapes, and / or arrangements are within the scope of this disclosure.

[0028] Each of functional regions 110-116 may be manufactured to include an integrated circuit configured to perform a specific set of functions of the semiconductor device 102. For example, functional region 110 may be a memory region (or memory core) of the semiconductor device 102, which includes an integrated circuit configured to perform memory functions of the semiconductor device 102. As another example, functional region 112 may be an analog circuit region (or analog core) of the semiconductor device 102, which includes an integrated circuit configured to perform analog functions of the semiconductor device 102. As yet another example, functional region 114 may be a radio frequency (RF) circuit region (or RF core) of the semiconductor device 102, which includes an integrated circuit configured to perform RF communication functions of the semiconductor device 102. As yet another example, functional region 116 may be a logic circuit region (or logic core) of the semiconductor device 102, which includes an integrated circuit configured to perform logic functions of the semiconductor device 102. In some embodiments, the semiconductor device 102 includes another type of functional region or different combinations of functional regions.

[0029] like Figure 1A As further shown, the sealing ring region 106 may laterally surround the functional regions 110-116 of the semiconductor device 102. The sealing ring region 106 may include a ring of interconnect layers with interconnect structures and metallization structures that provide enhanced structural rigidity to the semiconductor device 102, which can reduce the likelihood of cracking, warping, and / or other types of physical damage otherwise caused by physical stresses applied to the semiconductor device 102. Additionally and / or optionally, the interconnect layers of the sealing ring region 106 may be configured to provide a moisture seal to the semiconductor device 102, which can reduce the likelihood of moisture intrusion into the semiconductor package. The interconnect layers with metallization structures may form a continuous seal around the periphery of the device region 104 of the semiconductor device 102.

[0030] like Figure 1A As further shown, the buffer region 108 may laterally surround the sealing ring region 106. The buffer region 108 may include an annular region of the semiconductor device 102, which buffers the device region 104 and the sealing ring region 106 from the effects of scribe lines on the wafer on which the semiconductor device 102 is formed. The buffer region 108 may suppress interference such as vibration and heat from reaching the device region 104 and damaging the integrated circuit device therein.

[0031] Buffer region 108 may be a non-functional region of semiconductor device 102, which includes a ring of metallized structures surrounding sealing ring region 106. The density of metallized structures in buffer region 108 may be less than that in sealing ring region 106 to provide fewer paths through which vibration and heat can propagate to device region 104.

[0032] like Figure 1B As shown, the semiconductor device 102 may include a device layer 118 and an interconnect layer 120 located above the device layer 118. In some embodiments, the semiconductor device 102 includes interconnect layers 120 located on the top and bottom sides of the device layer 118, thereby allowing signals and / or power to be distributed on both sides of the device layer 118.

[0033] Device layer 118 may include substrate layer 122. Substrate layer 122 may correspond to a portion of a wafer on which semiconductor device 102 is formed. Substrate layer 122 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate (such as gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, or another type of wafer.

[0034] Device layer 118 may also include one or more integrated circuit devices 124 located on and / or on the front side of substrate layer 122. Integrated circuit devices 124 may each include transistors (e.g., planar transistors, FinFETs, gate-all-around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, diodes, and / or other types of passive and / or active integrated circuit devices.

[0035] The substrate 122 may also include isolation regions 126 to provide electrical isolation for the integrated circuit device 124. One or more isolation regions 126 may include implantation regions of the substrate 122, in which dopants are implanted. Dopants may include, for example, n-type dopants (such as phosphorus (P) and / or arsenic (As)) and / or p-type dopants (such as boron (B)). Additionally and / or optionally, one or more isolation regions 126 may include shallow trench isolation (STI) structures. The STI structure may be a dielectric structure extending into the front side of the substrate 122 and may include one or more dielectric materials, such as silicon oxide (SiO2). x Such as SiO2), silicon nitride materials (Si x N y Such as Si3N4), and / or other suitable dielectric materials.

[0036] Within the sealing ring region 106, the substrate layer 122 may include one or more isolation regions 128 to provide electrical isolation for the integrated circuit device 124 from external influences such as vibration and / or moisture. The one or more isolation regions 128 may include implantation regions of the substrate layer 122, in which dopants are implanted. The dopants may include, for example, n-type dopants (such as phosphorus (P) and / or arsenic (As)) and / or p-type dopants (such as boron (B)). Additionally and / or optionally, the one or more isolation regions 128 may include an STI structure.

[0037] Interconnect layer 120 includes a dielectric region 130 located above substrate layer 122. The dielectric region 130 may include one or more back-end dielectric layers (e.g., one or more inter-layer dielectric (ILD) layers, one or more inter-metal dielectric (IMD) layers) and one or more etch stop layers (ESL) arranged in an alternating pattern within interconnect layer 120. The dielectric layers may all comprise oxides (e.g., silicon oxide (SiO2)). x (and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorinated silicate glass (FSG), dielectric materials with extremely low dielectric constant (ELK) of less than about 2.5, silicon nitride (Si) x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials.

[0038] Interconnect layer 120 also includes one or more metallization structures 132 (e.g., conductive structures) located in dielectric region 130. The metallization structures 132 in device region 104 may be electrically coupled and / or physically coupled to one or more integrated circuit devices 124 in device layer 118, and / or the metallization structures 132 in device region 104 may be electrically interconnected. The metallization structures 132 may correspond to circuit wiring that provides signals and / or power to integrated circuit devices 124, and / or provides signals and / or power from integrated circuit devices 124. The metallization structures 132 may include a combination of metal lines and interconnect structures (e.g., vias), where the metal lines extend primarily horizontally in interconnect layer 120, and the interconnect structures (e.g., vias) extend primarily vertically in interconnect layer 120 and are electrically coupled to the metal lines. In other examples of conductive materials, the metallization structure 132 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof.

[0039] In device region 104, layers of metallization structure 132 may be arranged vertically to facilitate routing of electrical signals and / or power between device layer 118 and external interconnects coupled to semiconductor device 102. The metallization structure 132 may be arranged as alternating layers of metallization layers (referred to as "M" layers) and via layers (referred to as "V" layers). Each metallization layer may include one or more metallization structures 132 arranged laterally in interconnect layer 120, and each via layer may include one or more metallization structures 132 interconnecting the metallization layers in interconnect layer 120. For example, a via 0 (V0) layer may be located at the bottom of interconnect layer 120 (e.g., at the front boundary of device layer 118) and may be coupled to integrated circuit device 124 in substrate layer 122; a metal 0 (V0) layer may be located above and coupled to the V0 layer in interconnect layer 120; a via 1 (V1) layer may be located above and coupled to the M0 layer in interconnect layer 120; a metal 1 (M1) layer may be located above and coupled to the V1 layer in interconnect layer 120; a via 2 (V2) layer may be located above and electrically coupled to the M1 layer in interconnect layer 120, and so on. In some embodiments, interconnect layer 120 includes nine (9) stacked metallization layers (e.g., M0-M8). In other embodiments, a contact layer (referred to as a "CO" layer) may be located at the bottom of interconnect layer 120 and may be coupled to integrated circuit device 124 in substrate layer 122; a VO layer may be located above the CO layer in interconnect layer 120 and coupled to the CO layer, and so on. In some embodiments, interconnect layer 120 includes another number of stacked metallization layers.

[0040] The sealing ring region 106 may also extend vertically through the dielectric region 130 of the interconnect layer 120 and may extend laterally around the device region 104. The sealing ring region 106 may include a plurality of vertically arranged layers (e.g., in the z-direction) laterally surrounding the metallization structure 132 of the device region 104 of the semiconductor device 102. The plurality of vertically arranged layers of the metallization structure 132 may be located above the isolation region 128 of the sealing ring region 106, such that the electrical and / or environmental isolation provided by the sealing ring region 106 extends through the dielectric region 130 and into the substrate layer 122.

[0041] The sealing ring region 106 may be laterally located between the device region 104 and the buffer region 108. The buffer region 108 may extend vertically through the dielectric region 130 of the interconnect layer 120 and may extend laterally around the sealing ring region 106. The buffer region 108 may include a plurality of vertically arranged layers (e.g., in the z-direction) laterally surrounding the metallization structure 132 of the device region 104 of the semiconductor device 102. The density of the metallization structure 132 in the buffer region 108 may be less than the density of the metallization structure 132 in the sealing ring region 106 to provide fewer paths for vibration and heat to propagate to the device region 104.

[0042] In some embodiments, the plurality of vertically arranged layers of the metallization structure 132 in the buffer region 108 are spaced apart by portions of the dielectric region 130. In other words, vertically adjacent layers of the metallization structure 132 in the buffer region 108 may not be connected together. In some embodiments, vertically adjacent layers of the metallization structure 132 in the buffer region 108 are connected together.

[0043] As mentioned above, Figure 1A and Figure 1B Provided as an example only. Other examples can be found in the documentation. Figure 1A and Figure 1B The descriptions are different.

[0044] Figure 2A and Figure 2B An example 200 of a semiconductor device 102 formed on a wafer 202 is shown. Figure 2A A top view of wafer 202 is shown, and Figure 2B It shows along Figure 2A Cross-sectional view of wafer 202 with center line BB.

[0045] In other examples, wafer 202 may include a semiconductor wafer, such as a silicon (Si) wafer, a silicon carbide (SiC) wafer, and / or a germanium (Ge) wafer. In some embodiments, wafer 202 is a multilayer wafer, such as a silicon-on-insulator (SOI) wafer. In some embodiments, wafer 202 is a dielectric wafer, such as a glass wafer. In some embodiments, wafer 202 is substantially circular and has a diameter of about 200 mm, 300 mm, or other diameters. In some embodiments, wafer 202 has another shape.

[0046] like Figure 2A As shown, semiconductor devices 102a-102d can be formed on wafer 202 such that semiconductor devices 102a-102d are laterally spaced and separated by scribe regions 204. Figure 2A The layout and number of semiconductor devices 102a-102d shown are merely examples, and other layouts and numbers are within the scope of this disclosure.

[0047] The scribing region 204 is a region of wafer 202 located around semiconductor devices 102a-102d. The scribing region 204 provides spacing within which the wafer 202 can be cut or divided to slice the semiconductor devices 102a-102d into individual devices. Figure 2A The detailed view shown, in some embodiments, indicates that the scribe line region 204 may include various structures, such as test structure 206. In some embodiments, and in other instances, the scribe line region 204 may include other structures, such as pseudo-structures (e.g., non-functional structures). Test structure 206 may include a process control monitoring (PCM) structure to monitor aspects of the manufacturing process performed on wafer 202. In some embodiments, test structure 206 may include a wafer acceptance test (WAT) structure, a stress test structure, test pads, test circuitry, and / or other types of test structures.

[0048] like Figure 2A As further shown, semiconductor devices 102a-102d can be manufactured to include a plurality of buffer regions surrounding device region 104 of semiconductor devices 102a-102d, such as buffer region 108 surrounding sealing ring region 106, and another buffer region 208 surrounding buffer region 108. Buffer region 208 may be included around the periphery of buffer region 108 such that buffer region 208 laterally surrounds buffer region 108.

[0049] The buffer region 208 of the semiconductor device 102 (e.g., semiconductor device 102c) may be similar to buffer region 108 and may include a portion of the dielectric region 130 of the semiconductor device 102. The density of the metallization structure 132 in buffer regions 108 and 208 may both be less than the density of the metallization structure in the scribe region 204 and the sealing ring region 106. However, the density of the metallization structure 132 in buffer region 208 is less than the density of the metallization structure 132 in buffer region 108. In some embodiments, the density of the metallization structure 132 in buffer region 108 is about 25% to about 90% of the total area or volume of buffer region 108, while the density of the metallization structure 132 in buffer region 208 is at least about 5% less than the density of the metallization structure 132 in buffer region 108. In some embodiments, buffer region 208 does not contain the metallization structure 132, the test structure 206, and / or the dummy structure; and the density of the metallization structure 132 in buffer region 208 is about 0%.

[0050] The buffer region 208 of semiconductor devices 102a-102d provides an additional region through which dicing and / or sawing can be performed as part of a die-dicing process for dicing semiconductor devices 102a-102d from wafer 202. The lower pattern density (e.g., lower density of metallization structure 132) in the buffer region 208 of semiconductor devices 102a-102d provides fewer paths through which heat and mechanical vibrations from laser dicing and / or sawing can propagate to device regions 104 of semiconductor devices 102a-102d during the die-dicing process. In other words, the buffer region 208 effectively buffers device regions 104 from the thermal and mechanical stresses generated during the die-dicing process, reducing the likelihood that these additional mechanical stresses generated by the die-dicing process could cause cracking, delamination, and / or other types of physical damage to the layers and / or structures of semiconductor devices 102a-102d. In this way, the buffer region 208 can reduce the defect rate, improve reliability, and / or increase the yield of the semiconductor device 102 fabricated on the wafer 202.

[0051] like Figure 2A As further shown, the buffer region 108 may have a lateral width in a direction substantially perpendicular to the length of the buffer region 108 (in Figure 2A (This is marked as dimension D1). Buffer area 208 may have a lateral width in a direction generally perpendicular to the length of buffer area 208 (in... Figure 2A (marked as dimension D2). In some embodiments, the lateral widths of buffer regions 108 and 208 may be approximately equal before the semiconductor devices 102a-102d are cut from wafer 202. However, as combined with Figures 4A to 4F , Figures 5A to 5G , Figures 7A to 7F As described in other parts of this document, during the process of dicing or dicing semiconductor devices 102a-102d from wafer 202, trenches may be formed through buffer regions 208 of semiconductor devices 102a-102d. Thus, after the process of dicing or dicing semiconductor devices 102a-102d from wafer 202, one or more segments of buffer regions 208 of semiconductor devices 102a-102d may have a lateral width smaller than the lateral width of buffer region 108. In some embodiments, prior to dicing, buffer regions 108 and 208 may both have a lateral width ranging from about 50 micrometers to about 100 micrometers to provide effective buffering of device regions 104 of semiconductor devices 102a-102d from thermal and mechanical stresses generated during the die dicing process. However, other values ​​and ranges are within the scope of this disclosure.

[0052] like Figure 2BAs shown, the buffer region 208 of the semiconductor device 102 (e.g., semiconductor device 102c, semiconductor device 102d) may include a portion of the dielectric region 130 of the semiconductor device 102. In some embodiments, the buffer region 208 of the semiconductor device 102 (e.g., semiconductor device 102c, semiconductor device 102d) may include one or more metallization structures 132 located in the portion of the dielectric region 130. In some embodiments, the portion of the dielectric region 130 in the buffer region 208 of the semiconductor device 102 (e.g., semiconductor device 102c, semiconductor device 102d) does not contain metallization structures 132.

[0053] As mentioned above, Figure 2A and Figure 2B Provided as an example only. Other examples can be found in the documentation. Figure 2A and Figure 2B The descriptions are different.

[0054] Figures 3A to 3C This is a schematic diagram of an exemplary embodiment 300 of forming a semiconductor device 102 on a wafer 202 as described herein. In some embodiments, bonding may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, ion implantation tools, bonding tools, planarization tools, and / or another type of semiconductor processing tool. Figures 3A to 3C One or more operations described.

[0055] like Figure 3A As shown, wafer 202 can be provided. Wafer 202 can be provided in the form of a semiconductor wafer, SOI wafer, dielectric wafer (e.g., glass wafer) and / or another type of workpiece. A portion of wafer 202 can correspond to the substrate layer 122 of semiconductor device 102, in which device layer 118 of semiconductor device 102 is formed.

[0056] like Figure 3BAs shown, an integrated circuit device 124, in which device regions 104 of the semiconductor device 102 can be formed in and / or on the substrate layer 122 of the device layer 118 of the semiconductor device 102. One or more semiconductor processing tools can be used to form one or more portions of the integrated circuit device 124. For example, an ion implantation tool can be used to dope one or more regions in the substrate layer 122 with one or more types of dopants to form well regions, implantation regions, and / or other types of doped regions for the integrated circuit device 124 in the substrate layer 122. As another example, a deposition tool can be used to perform various deposition operations to deposit layers and / or structures of the integrated circuit device 124, and / or deposit a photoresist layer for etching portions of the substrate layer 122 and / or the deposited layer. As another example, an exposure tool can be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a development tool can be used to develop the pattern in the photoresist layer. As another example, an etching tool can be used to etch portions of the substrate layer 122 and / or the deposited layer to form the integrated circuit device 124. For example, a planarization tool can be used to planarize portions of the integrated circuit device 124. For example, a plating tool can be used to deposit the metal structure and / or layers of the integrated circuit device 124.

[0057] like Figure 3B As further shown, one or more isolation regions 126 may be formed in the substrate layer 122 in the device region 104 of the semiconductor device 102. Additionally and / or optionally, one or more isolation regions 128 may be formed in the substrate layer 122 in the sealing ring region 106 of the semiconductor device 102. In some embodiments, forming the isolation regions 126 and / or 128 may include: etching the substrate layer 122 (e.g., using an etching tool) to form a trench in the substrate layer 122, and depositing a dielectric material in the trench (e.g., using a deposition tool). In some embodiments, forming the isolation regions 126 and / or 128 may include implanting a dopant into the substrate layer 122 (e.g., using an ion implantation tool).

[0058] like Figure 3C As shown, an interconnect layer 120 of the semiconductor device 102 can be formed on the device layer 118 of the semiconductor device 102. In order to form the interconnect layer 120, one or more dielectric layers of dielectric region 130 can be deposited, and a layer of metallization structure 132 can be formed in one or more dielectric layers.

[0059] One or more dielectric layers can be deposited using deposition tools, employing physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. One or more dielectric layers can be deposited in one or more deposition operations. In some embodiments, after depositing one or more dielectric layers, a planarization operation (e.g., chemical mechanical planarization (CMP) operation) can be performed using planarization tools to planarize the one or more dielectric layers.

[0060] In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer to form grooves in the dielectric layer. In these embodiments, a deposition tool can be used to form the photoresist layer on the dielectric layer (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer based on the pattern to form the grooves. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an optional technique for pattern-based etching of the dielectric layer.

[0061] The conductive material of the first layer of the metallization structure 132 can be deposited using deposition tools and techniques such as CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The first layer of the metallization structure 132 can be deposited in device region 104, sealing ring region 106, and / or buffer region 108. In some embodiments, one or more metallization structures 132 of the first layer of the metallization structure 132 can be deposited in buffer region 208. The first layer of the metallization structure 132 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then the first layer of the metallization structure 132 is deposited on the seed layer. In some embodiments, after depositing the first layer of the metallization structure 132, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the first layer of the metallization structure 132.

[0062] Subsequent layers of the metallization structure 132 can be formed in device region 104, sealing ring region 106, and / or buffer region 108 in a similar manner. In some embodiments, one or more layers of the metallization structure 132 can be deposited in buffer region 208. Optionally, portions of the dielectric region 130 in buffer region 208 can be fabricated without the metallization structure 132.

[0063] As mentioned above, Figures 3A to 3C Provided as an example only. Other examples can be found in the documentation. Figures 3A to 3C The descriptions are different.

[0064] Figures 4A to 4G This is a schematic diagram of an exemplary embodiment 400 for a die-cutting process for cutting semiconductor devices 102 from wafer 202 as described herein. One or more semiconductor processing tools, such as wafer / die transfer tools, laser grooving tools, wafer dicing tools, and / or other semiconductor processing tools, can be used to perform the combined process. Figures 4A to 4G One or more operations described.

[0065] like Figure 4A As shown, semiconductor devices 102a-102d can be formed on wafer 202. They can be combined with... Figures 3A to 3C Semiconductor devices 102a-102d are formed on wafer 202 in a similar manner as described. Semiconductor devices 102a-102d can be manufactured to each include: a device region 104, a sealing ring region 106 laterally surrounding the device region 104, a buffer region 108 laterally surrounding the sealing ring region 106, and another buffer region 208 laterally surrounding the buffer region 108. Furthermore, semiconductor devices 102a-102d can be manufactured such that the density of the metallization structure 132 in the buffer region 208 of semiconductor devices 102a-102d is less than the density of the metallization structure 132 in the buffer region 108 of semiconductor devices 102a-102d. In some embodiments, semiconductor devices 102a-102d can be manufactured such that the buffer region 208 of semiconductor devices 102a-102d does not contain the metallization structure 132.

[0066] like Figure 4AAs further shown, semiconductor devices 102a-102d can be formed on wafer 202 such that semiconductor devices 102a-102d are spaced apart by scribe regions 204 laterally located between semiconductor devices 102a-102d. In some embodiments, test structures 206, dummy structures, and / or other structures including metallization structures 132 can be formed in one or more scribe regions 204, and the test structures 206, dummy structures, and / or other structures including metallization structures 132 are used to monitor the manufacturing process of semiconductor devices 102a-102d fabricated on wafer 202 and / or thereon.

[0067] Although Figure 4A Semiconductor devices 102a-102d are shown to be formed in a grid layout, and scribe regions 204 have a similar overall grid layout, but semiconductor devices 102a-102d and the associated scribe regions 204 between them may have another layout.

[0068] like Figure 4B and Figure 4C As shown, a first laser grooving operation can be performed on wafer 202 as part of a die dicing process. The first laser grooving operation includes forming trenches (e.g., narrow trenches) on opposite sides of the scribing region 204. The trenches can be formed in and / or through the buffer regions 208 of the semiconductor devices 102a-102d, such that the trenches are located between the buffer regions 108 and the scribing region 204.

[0069] Figure 4B A trench path 402 for forming a trench is shown. A laser grooving tool can be used to form the trench, wherein the laser grooving tool emits a laser beam that moves along the trench path 402 to form the trench. Thus, the trench can span one or more scribing regions 204 located between laterally adjacent semiconductor devices 102. For example, the laser beam can move along the trench path 402 through a buffer region 208 between semiconductor devices 102a and 102c, and this can cause the trench to extend across the scribing region 204 between semiconductor devices 102a and 102c.

[0070] like Figure 4C As shown, trench path 402 can cut through a portion of dielectric region 130 in buffer region 208 of semiconductor devices 102a-102d. Laser beam 404 of a laser grooving tool can also cut into a portion of substrate layer 122 of semiconductor devices 102a-102d. In some embodiments, the lateral cutting width of laser beam 404 includes a range of about 6 micrometers to about 12 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0071] Because the buffer region 208 includes a low-density metallization structure 132 (or no metallization structure 132), the heat and vibration generated by the laser beam 404 cutting through the dielectric region 130 are primarily confined within the dielectric region 130 and do not (or minimally) propagate to the metallization structure 132 of the semiconductor devices 102a-102d. This reduces and / or minimizes the likelihood of cracks, delamination, and / or other types of physical damage occurring in the device regions 104 of the semiconductor devices 102a-102d.

[0072] like Figure 4D and Figure 4E As shown, a second laser grooving operation can be performed on wafer 202 as part of the die dicing process. The second laser grooving operation includes forming trenches (e.g., wide trenches) in the scribing region 204 of wafer 202.

[0073] Figure 4D A trench path 408 for forming a trench is shown. A laser grooving tool can be used to form the trench, wherein the laser grooving tool emits a laser beam that moves along the trench path 408 to form the trench.

[0074] like Figure 4E As shown, trench path 408 can be cut through a portion of dielectric region 130 in scribe region 204 between semiconductor devices 102a-102d. Trench path 408 can be laterally located between and through trenches 410 formed in and / or through buffer regions 208 of semiconductor devices 102a-102d. Trenches 410 formed in buffer regions 208 of semiconductor devices 102a-102d can isolate semiconductor devices 102a-102d from heat and / or mechanical disturbances (e.g., vibration) generated during the formation of trenches through scribe region 204.

[0075] The laser beam 412 of the laser grooving tool can cut into portions of the substrate layer 122 of the semiconductor devices 102a-102d. In some embodiments, the lateral cutting width of the laser beam 412 includes a range of about 40 micrometers to about 50 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0076] like Figure 4F and Figure 4G As shown, a wafer saw can be used to cut through the remaining portion of the substrate layer 122 in the scribing region 204 to completely slicing single semiconductor devices 102a-102d from wafer 202. Figure 4F As shown, the cutting path 414 of the wafer sawing tool can pass through the scribing area 204 located laterally between semiconductor devices 102a-102d.

[0077] like Figure 4G As shown, the cutting path 414 of the wafer sawing tool can pass through the groove 416 formed during the second laser grooving operation. The blade 418 can cut along the cutting path 414 through the groove 416 to cut through the remaining portion of the substrate layer 122 in the scribing region 204.

[0078] As mentioned above, Figures 4A to 4G Provided as an example only. Other examples can be found in the documentation. Figures 4A to 4G The descriptions are different.

[0079] Figures 5A to 5G This is a schematic diagram of an exemplary embodiment 500 for a die-cutting process for cutting semiconductor devices 102 from wafer 202 as described herein. One or more semiconductor processing tools, such as wafer / die transfer tools, laser grooving tools, wafer dicing tools, and / or other semiconductor processing tools, can be used to perform the combined process. Figures 5A to 5G One or more operations described.

[0080] like Figures 5A to 5F As shown, an exemplary embodiment 500 of the die-cutting process is similar to... Figures 4A to 4G An exemplary embodiment 400 of the die-cutting process is shown. However, in an exemplary embodiment 500 of the die-cutting process, the buffer region 208 is not completely removed from the semiconductor devices 102a-102d.

[0081] like Figure 5D As shown, the lateral width of the trench 410 formed as a buffer region 208 passing through the semiconductor devices 102a-102d is ( Figure 4D The dimension D4 (as indicated in the diagram) is smaller than the lateral width of the buffer region 208, such that the portion of the dielectric region 130 removed from the buffer region 208 is smaller than the entire portion. The lateral width of the trench 410 formed through the buffer region 208 is smaller than the lateral width of the trench formed through the scribed region 204. Figure 5D The dimension is marked as D5.

[0082] like Figure 5G As shown, the resulting semiconductor device 102, diced from wafer 202, includes a portion of buffer region 208. The remaining portion of buffer region 208 may be included around buffer region 108. In other words, the remaining portion of buffer region 208 may be included on all four sides of semiconductor device 102.

[0083] The lateral width of the remaining portion of buffer area 208 ( Figure 5GThe dimension (D3) can be smaller than the lateral width (D1) of the buffer region 108. In some embodiments, the width of the remaining portion of the buffer region 208 may include a range of about 3 micrometers to about 50 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0084] As mentioned above, Figures 5A to 5G Provided as an example only. Other examples can be found in the documentation. Figures 5A to 5G The descriptions are different.

[0085] Figures 6A to 6D This is a schematic diagram illustrating an example of cutting a single semiconductor device 102 from wafer 202 as described in this article. It can be combined with... Figures 4A to 4G , Figures 5A to 5G The process described in other parts of this document is used to cut a single semiconductor device 102 from wafer 202.

[0086] Figure 6A An example 600 of cutting a single semiconductor device 102 from wafer 202 is shown. For example... Figure 6A As shown, trenches 410 can be formed through segments of the buffer region 208 of the semiconductor device 102 to remove the segments of the buffer region 208 from the semiconductor device 102. After the die-cutting process, the resulting semiconductor device 102 includes three remaining segments of the buffer region 208, which are joined together at their ends. The three remaining segments can be located on three sides of the semiconductor device 102.

[0087] Figure 6B An example 602 of cutting a single semiconductor device 102 from wafer 202 is shown. (As...) Figure 6B As shown, trenches 410 can be formed through two segments of the buffer region 208 of the semiconductor device 102 to remove the segments of the buffer region 208 from the semiconductor device 102. After the die-cutting process, the resulting semiconductor device 102 includes two remaining segments of the buffer region 208 located on adjacent sides of the semiconductor device 102.

[0088] Figure 6C An example 604 of cutting a single semiconductor device 102 from wafer 202 is shown. (As...) Figure 6C As shown, trenches 410 can be formed through two segments of the buffer region 208 of the semiconductor device 102 to remove the segments of the buffer region 208 from the semiconductor device 102. After the die-cutting process, the resulting semiconductor device 102 includes two remaining segments of the buffer region 208 located on opposite sides of the semiconductor device 102.

[0089] Figure 6D An example 606 of cutting a single semiconductor device 102 from wafer 202 is shown. (As...) Figure 6D As shown, trenches 410 can be formed through three segments of the buffer region 208 of the semiconductor device 102 to remove the segments of the buffer region 208 from the semiconductor device 102. After the die-cutting process, the resulting semiconductor device 102 includes a single segment of the buffer region 208 located on one side of the semiconductor device 102.

[0090] As mentioned above, Figures 6A to 6D Provided as an example only. Other examples can be found in the documentation. Figures 6A to 6D The descriptions are different.

[0091] Figures 7A to 7F This is a schematic diagram of an exemplary embodiment 700 of a die-cutting process for cutting semiconductor devices 102 from a wafer stack described herein. One or more semiconductor processing tools, such as wafer / die transfer tools, laser grooving tools, wafer dicing tools, and / or other semiconductor processing tools, can be used to perform the combined process. Figures 7A to 7F One or more operations described.

[0092] like Figures 7A to 7F As shown, an exemplary embodiment 700 of the die-cutting process is similar to... Figures 5A to 5G The exemplary embodiment 500 of the die-cutting process is shown. However, in the exemplary embodiment 700 of the die-cutting process, wafer 202 is bonded to another wafer 702 to form a wafer stack, and semiconductor devices 102a-102d are cut from the wafer stack by the die-cutting process.

[0093] like Figure 7B As shown, a semiconductor device 102 (e.g., semiconductor device 102a) can be formed by bonding semiconductor die 704a and another semiconductor die 704b, such that semiconductor dies 704a and 704b are stacked and vertically arranged in semiconductor device 102. This can be achieved by bonding... Figures 3A to 3C The described operation forms a semiconductor die 704a on wafer 202, and can be combined with... Figures 3A to 3C The described operation forms a semiconductor die 704b on wafer 702. Wafers 202 and 702 can be bonded together such that dielectric-to-dielectric bonds are formed between dielectric regions 130 of semiconductor dies 704a and 704b, and metal-to-metal bonds are formed between metallization structures 132 of semiconductor dies 704a and 704b.

[0094] Device region 104 of semiconductor device 102 (e.g., semiconductor device 102a) may be laterally surrounded by a sealing ring region 106 extending through semiconductor dies 704a and 704b. Buffer region 108 of semiconductor device 102 may extend through semiconductor dies 704a and 704b and may laterally surround the sealing ring region 106; and another buffer region 208 of semiconductor device 102 may extend through semiconductor dies 704a and 704b and laterally surround the buffer region 108.

[0095] like Figure 7D As shown, the trench 410 formed in the buffer region 208 of the semiconductor devices 102a-102d can extend through the semiconductor die 704b of the semiconductor devices 102a-102d and enter into the semiconductor die 704a of the semiconductor devices 102a-102d.

[0096] like Figure 7F As shown, the trench 416 formed in the scribe region 204 of the wafer stack can extend through the semiconductor die 704b of the semiconductor devices 102a-102d and enter into the semiconductor die 704a of the semiconductor devices 102a-102d. Figure 7F As further shown, the blade 418 can pass through the trench 416 and through the remainder of the substrate layer 122 of the wafer 202.

[0097] As mentioned above, Figures 7A to 7F Provided as an example only. Other examples can be found in the documentation. Figures 7A to 7F The descriptions are different.

[0098] Figure 8 This is a flowchart of an exemplary process 800 described herein related to the formation of multiple semiconductor devices on a wafer. In some embodiments, one or more semiconductor processing tools, such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, laser grooving tools, wafer dicing tools, and / or another type of semiconductor processing tool, are used to perform the process. Figure 8 One or more process frames.

[0099] like Figure 8As shown, process 800 may include forming a plurality of semiconductor devices on a wafer (block 810). For example, one or more semiconductor processing tools may be used to form a plurality of semiconductor devices (e.g., semiconductor device 102, semiconductor devices 102a-102d) on a wafer (e.g., wafer 202), as described herein. In some embodiments, each of the plurality of semiconductor devices is fabricated to include a device region (e.g., device region 104), a sealing ring region laterally surrounding the device region (e.g., sealing ring region 106), and a buffer region laterally surrounding the sealing ring region (e.g., buffer region 108, buffer region 208).

[0100] like Figure 8 As further shown, process 800 may include forming a plurality of scribe regions laterally located between a plurality of semiconductor devices (block 820). For example, one or more semiconductor processing tools may be used to form a plurality of scribe regions laterally located between a plurality of semiconductor devices (e.g., scribe region 204), as described herein. In some embodiments, a scribe region among the plurality of scribe regions is laterally located between a first buffer region (e.g., buffer region 208) of a first semiconductor device (e.g., semiconductor device 102c) and a second buffer region (e.g., buffer region 208) of a second semiconductor device (e.g., semiconductor device 102d).

[0101] like Figure 8 As further shown, process 800 may include forming a first trench in a first buffer region and forming a second trench in a second buffer region (block 830). For example, one or more semiconductor processing tools may be used to form a first trench (e.g., trench 410) in a first buffer region and a second trench (e.g., trench 410) in a second buffer region, as described herein.

[0102] like Figure 8 As further shown, process 800 may include cutting through a scribing region (box 840) between the first trench and the second trench. For example, one or more semiconductor processing tools may be used to cut through the scribing region between the first trench and the second trench, as described herein.

[0103] Process 800 may include additional embodiments, any combination or any single embodiment of embodiments such as those described below and / or combined with one or more other processes described in other parts of this document.

[0104] In the first embodiment, cutting through the scribing area includes cutting through the scribing area after forming the first and second grooves.

[0105] In the second embodiment, cutting through the scribing area, alone or in combination with the first embodiment, includes forming a third groove (e.g., groove 416) in the scribing area and cutting through the third groove.

[0106] In the third embodiment, forming the first groove and the second groove, alone or in combination with one or more of the first and second embodiments, includes performing a laser cutting operation to form the first groove and the second groove.

[0107] In the fourth embodiment, cutting through the scribing region, alone or in combination with one or more of the first to third embodiments, includes performing another laser cutting operation after the laser cutting operation to form a third groove in the scribing region.

[0108] In the fifth embodiment, cutting through the scribing area, alone or in combination with one or more of the first to fourth embodiments, includes performing a sawing operation after other laser cutting operations to cut through the third groove.

[0109] In the sixth embodiment, forming a plurality of semiconductor devices, either alone or in combination with one or more of the first to fifth embodiments, includes forming a first semiconductor device such that the density of the metallization structure in the first buffer region is less than the density of the metallization structure in the sealing ring region of the first semiconductor device, and such that the density of the metallization structure in the first buffer region is less than the density of the metallization structure in the scribing region.

[0110] although Figure 8 An exemplary block diagram of process 800 is shown, but in some embodiments, process 800 includes... Figure 8 Additional frames beyond the frame shown, fewer frames, different frames, or frames with different arrangements. Alternatively, two or more frames of process 800 can be executed in parallel.

[0111] Figure 9 This is a flowchart of an exemplary process 900 described herein related to the formation of multiple semiconductor devices on a substrate. In some embodiments, one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, bonding tools, wafer / die transfer tools, laser grooving tools, wafer dicing tools, and / or another type of semiconductor processing tool, may be used to perform the process. Figure 9 One or more process frames.

[0112] like Figure 9As shown, process 900 may include a first semiconductor die (block 910) on which a semiconductor device is formed on a first substrate. For example, one or more semiconductor processing tools may be used to form a first semiconductor die (e.g., semiconductor device 102) (e.g., semiconductor die 704a) on a first substrate (e.g., wafer 202), as described herein. In some embodiments, the first semiconductor die is fabricated to include a first device region (e.g., device region 104), a first sealing ring region laterally surrounding the first device region (e.g., sealing ring region 106), and a first buffer region laterally surrounding the first sealing ring region (e.g., buffer region 108, buffer region 208).

[0113] like Figure 9 As further shown, process 900 may include a second semiconductor die (block 920) on which a semiconductor device is formed on a second substrate. For example, one or more semiconductor processing tools may be used to form a second semiconductor die (e.g., semiconductor die 704b) on a second substrate (e.g., wafer 702), as described herein. In some embodiments, the second semiconductor die is fabricated to include a second device region (e.g., device region 104), a second sealing ring region laterally surrounding the second device region (e.g., sealing ring region 106), and a second buffer region laterally surrounding the second sealing ring region (e.g., buffer region 108, buffer region 208).

[0114] like Figure 9 As further shown, process 900 may include bonding a first substrate to a second substrate to form a substrate stack (block 930). For example, one or more semiconductor processing tools may be used to bond the first substrate to the second substrate to form a substrate stack (e.g., a wafer stack including wafers 202, 702), as described herein. In some embodiments, a first semiconductor die of a semiconductor device is bonded to a second semiconductor die of a semiconductor device.

[0115] like Figure 9 As further shown, process 900 may include forming a trench (block 940) that extends through a second buffer region of the second semiconductor die and into a first buffer region of the first semiconductor die. For example, one or more semiconductor processing tools may be used to form a trench (e.g., trench 410) that extends through a second buffer region of the second semiconductor die and into a first buffer region of the first semiconductor die, as described herein.

[0116] like Figure 9As further shown, process 900 may include cutting through a scribe region of a substrate stack laterally adjacent to the trench (box 950). For example, one or more semiconductor processing tools may be used to cut through a scribe region (e.g., scribe region 204) of a substrate stack laterally adjacent to the trench, as described herein.

[0117] Process 900 may include additional embodiments, any combination of or any single embodiment of embodiments such as those described below and / or combined with one or more other processes described in other parts of this document.

[0118] In a first embodiment, process 900 includes forming another trench that passes through a portion of the scribing region in the second substrate and enters a portion of the scribing region in the first substrate.

[0119] In the second embodiment, cutting through the scribed area, alone or in combination with the first embodiment, includes cutting through another groove in the scribed area.

[0120] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the lateral width of the trench (e.g., dimension D4) is smaller than the lateral width of another trench (e.g., dimension D5).

[0121] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 900 includes: forming a third buffer region (e.g., buffer region 108) laterally located between the first buffer region and the first sealing ring region, wherein the density of the metallization structure in the third buffer region is greater than the density of the metallization structure in the first buffer region; and forming a fourth buffer region (e.g., buffer region 108) laterally located between the second buffer region and the second sealing ring region, wherein the density of the metallization structure in the fourth buffer region is greater than the density of the metallization structure in the second buffer region.

[0122] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the first buffer region includes a dielectric region without metallization (e.g., dielectric region 130), and the second buffer region includes another dielectric region without metallization (e.g., dielectric region 130).

[0123] although Figure 9 An exemplary block diagram of process 900 is shown, but in some embodiments, process 900 includes... Figure 9 Additional frames beyond the frame shown, fewer frames, different frames, or frames with different arrangements. Alternatively or concurrently, two or more frames of process 900 may be executed.

[0124] Figures 10A to 10FThis is a schematic diagram of an exemplary embodiment 1000 for a die-cutting process for cutting semiconductor devices 102 from a wafer stack described herein. One or more semiconductor processing tools, such as wafer / die transfer tools, laser grooving tools, wafer dicing tools, and / or other semiconductor processing tools, can be used to perform the combined process. Figures 10A to 10F One or more operations described.

[0125] like Figures 10A to 10F As shown, an exemplary embodiment 1000 of the die-cutting process is similar to... Figures 7A to 7F An exemplary embodiment 700 of the die-cutting process is shown. However, in an exemplary embodiment 1000 of the die-cutting process, wafer 202 is bonded to another wafer 702, and wafer 702 is bonded to wafer 1002 to form a wafer stack, and semiconductor devices 102a-102d are cut from the wafer stack by the die-cutting process.

[0126] like Figure 10B As shown, semiconductor device 102 (e.g., semiconductor device 102a) can be formed by bonding semiconductor die 704a and another semiconductor die 704b such that semiconductor dies 704a and 704b are stacked and vertically arranged in semiconductor device 102, and by bonding semiconductor die 704b and another semiconductor die 704c such that semiconductor dies 704b and 704c are stacked and vertically arranged in semiconductor device 102.

[0127] According to the combination Figures 3A to 3C The described similar operation forms a semiconductor die 704a on wafer 202, which can be combined with Figures 3A to 3C The described similar operation forms a semiconductor die 704b on wafer 702, and can be combined with... Figures 3A to 3C The similar operation described herein forms a semiconductor die 704c on wafer 1002.

[0128] Wafers 202 and 702 can be bonded together to form dielectric-to-dielectric bonds between the dielectric regions 130 of semiconductor dies 704a and 704b, and metal-to-metal bonds between the metallization structures 132 of semiconductor dies 704a and 704b. Wafers 702 and 1002 can be bonded together to form dielectric-to-dielectric bonds between the dielectric regions 130 of semiconductor dies 704b and 704c, and metal-to-metal bonds between the metallization structures 132 of semiconductor dies 704b and 704c.

[0129] Device region 104 of semiconductor device 102 (e.g., semiconductor device 102a) may be laterally surrounded by a sealing ring region 106 extending through semiconductor dies 704a, 704b, and 704c. Buffer region 108 of semiconductor device 102 may extend through semiconductor dies 704a, 704b, and 704c and may laterally surround the sealing ring region 106. Another buffer region 208 of semiconductor device 102 may extend through semiconductor dies 704a, 704b, and 704c and laterally surround the buffer region 108.

[0130] like Figure 10D As shown, the trench 410 formed in the buffer region 208 of the semiconductor devices 102a-102d can extend through the semiconductor dies 704c and 704b of the semiconductor devices 102a-102d and enter into the semiconductor die 704a of the semiconductor devices 102a-102d.

[0131] like Figure 10F As shown, the trench 416 formed in the scribe region 204 of the wafer stack can extend through the semiconductor dies 704c and 704b of the semiconductor devices 102a-102d and enter into the semiconductor die 704a of the semiconductor devices 102a-102d. Figure 10F As further shown, the blade 418 can pass through the trench 416 and through the remainder of the substrate layer 122 of the wafer 202.

[0132] As mentioned above, Figures 10A to 10F Provided as an example only. Other examples can be found in the documentation. Figures 10A to 10F The descriptions differ. For example, the number of semiconductor dies stacked together to form the semiconductor device 102 described herein, such as the number of... Figures 7A to 7F and Figures 10A to 10F The number of semiconductor dies shown is for illustrative purposes only. Other numbers of semiconductor dies may be stacked together to form the semiconductor device 102 described herein, and diced using the techniques described herein.

[0133] In this way, semiconductor devices are fabricated on a wafer to include one or more buffer regions that can be used to cleave or cut the semiconductor devices from the wafer in a die-cutting process. The buffer region of the semiconductor device can be located between a scribe region on the wafer and a sealing ring region of the semiconductor device. The sealing ring region can laterally surround the device region of the semiconductor device, and the buffer region can laterally surround the sealing ring region of the semiconductor device. Instead of scribe regions on the wafer, trenches can be cut in the buffer region of the semiconductor device using a laser beam. Then, the wafer can be cleaved or cut into individual semiconductor devices using another laser beam and / or a wafer saw to cut completely through the scribe region. The pattern density (e.g., the density of structures) in the buffer region is lower than the pattern density in the scribe region and the device region. The lower pattern density in the buffer region provides fewer paths through which heat and mechanical vibrations from laser cutting and / or sawing can propagate to the device region of the semiconductor device. In other words, the buffer region effectively buffers the device area from the thermal and mechanical stresses generated during the die-cutting process. This reduces the likelihood that these additional mechanical stresses generated by the die-cutting process could cause cracks, delamination, and / or other types of physical damage to the layers and / or structure of the semiconductor device. In this way, the buffer region described herein can reduce defect rates, improve reliability, and / or increase the yield of semiconductor devices fabricated on wafers.

[0134] As described in more detail above, some embodiments described herein provide a method. The method includes forming a plurality of semiconductor devices on a wafer, wherein each of the plurality of semiconductor devices is fabricated to include a device region, a sealing ring region laterally surrounding the device region, and a buffer region laterally surrounding the sealing ring region. The method includes forming a plurality of scribe regions laterally located between the plurality of semiconductor devices, wherein a scribe region of the plurality of scribe regions is laterally located between a first buffer region of a first semiconductor device and a second buffer region of a second semiconductor device. The method includes forming a first trench in the first buffer region and forming a second trench in the second buffer region. The method includes dicing through the scribe regions between the first trench and the second trench.

[0135] As described in more detail above, some embodiments described herein provide semiconductor devices. A semiconductor device includes a device region. A semiconductor device includes a plurality of integrated circuit devices located within the device region. A semiconductor device includes a sealing ring region laterally surrounding the device region, wherein the sealing ring region includes a plurality of metallization structures. A semiconductor device includes a buffer region laterally adjacent to one or more sides of the sealing ring region such that the sealing ring region is laterally located between the buffer region and the device region, wherein the density of the plurality of metallization structures in the sealing ring region is greater than the density of the metallization structures in the buffer region.

[0136] As described in more detail above, some embodiments described herein provide a method. The method includes forming a first semiconductor die of a semiconductor device in a first substrate, wherein the first semiconductor die is fabricated to include a first device region, a first sealing ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first sealing ring region. The method includes forming a second semiconductor die of a semiconductor device in a second substrate, wherein the second semiconductor die is fabricated to include a second device region, a second sealing ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second sealing ring region. The method includes bonding a first substrate to a second substrate to form a substrate stack, wherein the first semiconductor die of the semiconductor device is bonded to the second semiconductor die of the semiconductor device. The method includes forming a trench through the second buffer region of the second semiconductor die and into the first buffer region of the first semiconductor die. The method includes cutting through a scribing region of the substrate stack laterally adjacent to the trench.

[0137] As described in more detail above, some embodiments described herein include a method. The method includes forming a first semiconductor die of a semiconductor device in a first substrate. The first semiconductor die is fabricated to include a first device region, a first sealing ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first sealing ring region. The first buffer region includes a first dielectric region without metallization. The method includes forming a second semiconductor die of a semiconductor device in a second substrate. The second semiconductor die is fabricated to include a second device region, a second sealing ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second sealing ring region. The second buffer region includes a second dielectric region without metallization. The method includes bonding a first substrate to a second substrate to form a substrate stack. The first semiconductor die of the semiconductor device is bonded to the second semiconductor die of the semiconductor device. The method includes forming a trench through the second dielectric region of the second buffer region and into the first dielectric region of the first buffer region. The method includes dicing through a scribing region of the substrate stack laterally adjacent to the trench.

[0138] As described in more detail above, some embodiments described herein include a method. The method includes forming a first semiconductor device to include a first device region, a first sealing ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first sealing ring region. The method includes forming a second semiconductor device to include a second device region, a second sealing ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second sealing ring region. The method includes forming a scribe region laterally located between the first and second buffer regions. The method includes forming a first trench in the first buffer region and a second trench in the second buffer region. The method includes cutting through the scribe region located between the first and second trenches.

[0139] According to one aspect of this application, a method of forming a semiconductor device is provided, the method comprising: forming a first semiconductor device including a first device region, a first sealing ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first sealing ring region; forming a second semiconductor device including a second device region, a second sealing ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second sealing ring region; forming a scribing region laterally located between the first buffer region and the second buffer region; forming a first trench in the first buffer region and a second trench in the second buffer region; and cutting through the scribing region between the first trench and the second trench. In some embodiments, cutting through the scribing region includes cutting through the scribing region after forming the first trench and the second trench. In some embodiments, cutting through the scribing region includes forming a third trench in the scribing region; and cutting through the third trench. In some embodiments, forming the first trench and the second trench includes performing a laser cutting operation to form the first trench and the second trench. In some embodiments, cutting through the scribing region includes performing another laser cutting operation after the laser cutting operation to form the third trench in the scribing region. In some embodiments, cutting through the scribe line region includes performing a sawing operation to cut through a third trench after another laser cutting operation. In some embodiments, forming the first semiconductor device includes forming the first semiconductor device such that the density of the metallization structure in the first buffer region is less than the density of the metallization structure in the first sealing ring region, and such that the density of the metallization structure in the first buffer region is less than the density of the metallization structure in the scribe line region.

[0140] According to another aspect of this application, a semiconductor device is provided, comprising: a device region; a sealing ring region laterally surrounding the device region, wherein the sealing ring region includes a plurality of metallization structures; and a buffer region laterally adjacent to one or more sides of the sealing ring region such that the sealing ring region is located between the buffer region and the device region, wherein the density of the plurality of metallization structures in the sealing ring region is greater than the density of the metallization structures in the buffer region. In some embodiments, the buffer region laterally surrounds the sealing ring region. In some embodiments, the buffer region is a first buffer region of the semiconductor device; and wherein the semiconductor device further includes a second buffer region laterally adjacent to one or more sides of the first buffer region, wherein the first buffer region is laterally located between the second buffer region and the sealing ring region. In some embodiments, the density of the metallization structures in the first buffer region is greater than the density of the metallization structures in the second buffer region. In some embodiments, the density of the metallization structures in the first buffer region and the density of the metallization structures in the second buffer region are substantially equal. In some embodiments, the width of the first buffer region in a direction substantially perpendicular to the length of the first buffer region is greater than the width of the second buffer region in a direction substantially perpendicular to the length of the second buffer region. In some embodiments, the first buffer region extends along a greater number of sides of the sealing ring region than the second buffer region.

[0141] According to another aspect of this application, a method for forming a semiconductor device is provided, the method comprising: forming a first semiconductor die of the semiconductor device in a first substrate, wherein the first semiconductor die includes a first device region, a first sealing ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first sealing ring region, and wherein the first buffer region includes a first dielectric region without metallization; forming a second semiconductor die of the semiconductor device in a second substrate, wherein the second semiconductor die includes a second device region, a second sealing ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second sealing ring region, and wherein the second buffer region includes a second dielectric region without metallization; bonding the first substrate to the second substrate to form a substrate stack, wherein the first semiconductor die of the semiconductor device is bonded to the second semiconductor die of the semiconductor device; forming a trench through the second dielectric region of the second buffer region and into the first dielectric region of the first buffer region; and cutting through a scriber region of the substrate stack laterally adjacent to the trench. In some embodiments, the method for forming a semiconductor device further comprises: forming another trench through a portion of the scriber region in the second substrate and into a portion of the scriber region in the first substrate. In some embodiments, cutting through the scribed region includes cutting through another trench within the scribed region. In some embodiments, the lateral width of the trench is smaller than the lateral width of the other trench. In some embodiments, the method of forming a semiconductor device further includes forming a third buffer region laterally located between a first buffer region and a first sealing ring region, wherein the density of the metallization structure in the third buffer region is greater than the density of the metallization structure in the first buffer region. In some embodiments, the method of forming a semiconductor device further includes forming a fourth buffer region laterally located between a second buffer region and a second sealing ring region, wherein the density of the metallization structure in the fourth buffer region is greater than the density of the metallization structure in the second buffer region.

[0142] The terms “about” and “substantially” can refer to the value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms “about” and “substantially” can refer to a percentage of the value of a given quantity.

[0143] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A first semiconductor device is formed, comprising a first device region, a first sealing ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first sealing ring region; A second semiconductor device is formed, comprising a second device region, a second sealing ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second sealing ring region; A horizontally defined area is formed between the first buffer area and the second buffer area; A first groove is formed in the first buffer region, and a second groove is formed in the second buffer region; as well as Cut through the scribed area between the first groove and the second groove.

2. The method according to claim 1, wherein, Cutting through the marked area includes: After the first and second grooves are formed, cutting is performed through the scribing area.

3. The method according to claim 1, wherein, Cutting through the marked area includes: A third groove is formed in the scribed area; and Cut through the third groove.

4. The method according to claim 1, wherein, Forming the first trench and the second trench includes: Perform a laser cutting operation to form the first groove and the second groove.

5. The method according to claim 4, wherein, Cutting through the marked area includes: After the laser cutting operation, another laser cutting operation is performed to form a third groove in the scribing area.

6. The method according to claim 5, wherein, Cutting through the marked area includes: After the other laser cutting operation, a sawing operation is performed to cut through the third groove.

7. The method according to claim 1, wherein, The first semiconductor device comprises: The first semiconductor device is formed such that the density of the metallization structure in the first buffer region is less than the density of the metallization structure in the first sealing ring region, and such that the density of the metallization structure in the first buffer region is less than the density of the metallization structure in the scribbled region.

8. A semiconductor device, comprising: Device area; A sealing ring region laterally surrounds the device region, wherein the sealing ring region includes multiple metallized structures; and A buffer region is laterally adjacent to one or more sides of the sealing ring region, such that the sealing ring region is located between the buffer region and the device region, wherein the density of the plurality of metallized structures in the sealing ring region is greater than the density of the metallized structures in the buffer region.

9. The semiconductor device according to claim 8, wherein, The buffer area surrounds the sealing ring area laterally.

10. A method of forming a semiconductor device, comprising: A first semiconductor die for forming a semiconductor device is formed in a first substrate, wherein the first semiconductor die includes a first device region, a first sealing ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first sealing ring region, and wherein the first buffer region includes a first dielectric region without metallization structure. A second semiconductor die of the semiconductor device is formed in a second substrate, wherein the second semiconductor die includes a second device region, a second sealing ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second sealing ring region, and wherein the second buffer region includes a second dielectric region without metallization structure; The first substrate is bonded to the second substrate to form a substrate stack. Wherein, the first semiconductor die of the semiconductor device is bonded to the second semiconductor die of the semiconductor device; Forming a trench in the first dielectric region of the first buffer region, passing through the second dielectric region of the second buffer region; and Cut through the scribing area of ​​the substrate stack that is laterally adjacent to the trench.

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