Wafer-level two-dimensional back-gate field effect transistor array and method of manufacturing the same

Abstract

The application discloses a wafer-level two-dimensional back-gate field effect transistor array and a preparation method thereof. The method comprises the following steps: providing a silicon wafer; depositing Al2O3 or HfO2 on the surface of the silicon wafer by adopting an atomic layer deposition process, and then forming a bottom passivation insulating layer by rapid annealing; spin-coating an ammonium tetrathiomolybdate precursor solution on the surface of the bottom passivation insulating layer, and curing a precursor film by heat treatment; annealing the wafer with the precursor film to generate a layered MoS2 two-dimensional material layer in situ; treating the layered MoS2 two-dimensional material layer by adopting a low-power oxygen plasma to generate a two-dimensional MoO3 film in situ by oxidation, so as to form an Al2O3 / MoO3 or HfO2 / MoO3 double-layer composite dielectric layer; preparing a two-dimensional semiconductor channel layer on the two-dimensional MoO3 film, and then preparing a source-drain metal electrode array by adopting a photolithography and electron beam evaporation process, so as to obtain a two-dimensional back-gate field effect transistor array. The method can solve the problems of large leakage current and weak gate control ability of the field effect transistor, and has the advantages of high efficiency, low cost and suitability for large-scale production.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a wafer-level two-dimensional back-gate field-effect transistor array and its fabrication method. Background Technology

[0002] As electronic devices evolve towards miniaturization and high integration, traditional silicon dioxide (SiO2) dielectric layers, due to their low dielectric constant, require continuous thinning. This leads to intensified tunneling effects and increased leakage current. Therefore, they are gradually being replaced by high-k dielectric (high-κ) materials to enhance gate control capabilities and suppress short-channel effects. In related technologies, atomic layer deposition (ALD) high-κ dielectric layers (such as Al2O3 and HfO2) exhibit surface dangling bonds and interface defects at sub-nanometer equivalent oxide thickness (EOT), resulting in decreased carrier mobility and a sharp increase in leakage current in two-dimensional channels.

[0003] The commonly used two-dimensional dielectric layer hBN has a low dielectric constant (~5), which cannot meet the requirements of sub-nanometer EOT; while two-dimensional MoO3 has a high dielectric constant (κ≈40), it is difficult to achieve wafer-level large-area uniform preparation using traditional physical methods such as physical vapor deposition (PVD), and it is prone to excessive leakage current in the extremely thin state.

[0004] Therefore, there is a lack of dielectric layer integration schemes in related technologies that can achieve wafer-level uniform fabrication while also taking into account sub-nanometer EOT, ultra-low leakage current, and no dangling bond van der Waals interface.

[0005] The information disclosed in this background section was already known to the inventors prior to the implementation of this application or was acquired during the implementation of this disclosure. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the Invention

[0006] To address the aforementioned issues, this invention provides a wafer-level two-dimensional back-gate field-effect transistor array and its fabrication method. This method achieves a dual-layer composite dielectric layer structure by using an ALD high-κ bottom layer and an in-situ spin-coating to convert the MoO3 top layer, combined with a low-power oxygen plasma oxidation process, thus achieving a balance between sub-nanometer EOT, ultra-low leakage current, and wafer-level large-area fabrication.

[0007] According to one or more embodiments of the present invention, a method for fabricating a wafer-level two-dimensional back-gate field-effect transistor array is provided, comprising the following steps: S1. Provide silicon wafers and preprocess the silicon wafers; S2. An atomic layer deposition process is used to deposit a 6 nm to 15 nm thick Al2O3 or HfO2 layer on the surface of the silicon wafer in step S1, followed by rapid annealing at 400 ℃ to 500 ℃ in a nitrogen atmosphere for 60 s to 120 s to form a bottom passivation insulating layer covering the silicon wafer. S3. Spin-coat the ammonium tetrathiomolybdate precursor solution onto the surface of the underlying passivation insulating layer, and heat-treat it at 120~160℃ for 2~5 min to solidify it into a precursor film. S4. The wafer with the precursor film is annealed in a nitrogen atmosphere at 400 ℃~500 ℃ for 5 min~15 min to generate a layered MoS2 two-dimensional material layer in situ. S5. Under the conditions of oxygen flow rate of 20 sccm and cavity pressure of 1.5 Pa, the layered MoS2 two-dimensional material layer is treated with 5~15 W low-power oxygen plasma for 10 s~50 s to generate a two-dimensional MoO3 thin film in situ, so as to form an Al2O3 / MoO3 or HfO2 / MoO3 double-layer composite dielectric layer on the silicon wafer. S6. A two-dimensional semiconductor channel layer is prepared on the two-dimensional MoO3 thin film in step S5. Then, a source-drain metal electrode array is prepared on the two-dimensional semiconductor channel layer by photolithography and electron beam evaporation to obtain a two-dimensional back gate field effect transistor array.

[0008] According to the present invention, a method for fabricating a wafer-level two-dimensional back-gate field-effect transistor array overcomes the technical bottleneck of the incompatibility between high dielectric performance, interface quality, and large-area fabrication in existing two-dimensional dielectric layers. By passivating the bottom layer with Al2O3 and converting the top layer to high κ through in-situ spin coating, combined with low-power plasma oxidation, the method simultaneously achieves sub-nanometer equivalent oxide layer thickness, ultra-low leakage current, and wafer-level uniformity under the same process path. In the Al2O3 / MoO3 or HfO2 / MoO3 bilayer composite dielectric layer, the bottom passivated insulating layer provides excellent breakdown resistance and suppresses vertical leakage current. The top MoO3 provides a high dielectric constant and a van der Waals interface without dangling bonds, solving the defects of multiple interface defects in single ALD dielectric and large leakage current in single MoO3. The use of low-power oxygen plasma instead of traditional high-temperature annealing oxidation avoids damage to the bottom dielectric and wafer caused by high-temperature processes, and is fully compatible with existing CMOS manufacturing lines. This fabrication method is highly efficient, low-cost, and suitable for large-scale mass production.

[0009] According to another aspect of one or more embodiments of the present invention, a two-dimensional back-gate field-effect transistor array prepared by the above-described fabrication method is provided, the two-dimensional back-gate field-effect transistor array comprising, from bottom to top, stacked as follows: Silicon wafers; A high dielectric constant bottom passivation insulating layer; The layered MoO3 top dielectric layer, together with the bottom passivation insulating layer, constitutes a double-layer composite dielectric layer; A two-dimensional semiconductor channel layer is in direct contact with the layered MoO3 top dielectric layer; and Source / drain metal electrode array.

[0010] According to a two-dimensional back-gate field-effect transistor array of the present invention, its double-layer composite dielectric layer achieves functional synergy: the Al2O3 or HfO2 bottom layer prepared by ALD has a dense amorphous structure that can block the tunneling transport of charge carriers; the in-situ generated layered MoO3 top layer has an intrinsically flat surface without dangling bonds, forming van der Waals contacts with the two-dimensional semiconductor channel, reducing charge carrier scattering. The combined effect of these two layers achieves comprehensive performance superior to existing single dielectric layers or conventional composite dielectric layers. Compared with a single Al2O3 dielectric of the same thickness, this structure has a reduced equivalent oxide layer thickness, a reduced interface state density, and a subthreshold swing reduced from 190 mV / dec to 130 mV / dec, significantly improving the device's gate control capability. This effectively solves the problems of high leakage current and weak gate control capability in field-effect transistors of related technologies; furthermore, the breakdown field strength of the composite dielectric layer is improved, meeting the reliability requirements of low-power devices. Attached Figure Description

[0011] Figure 1 This is a flowchart (cross-section) of a two-dimensional back-gate field-effect transistor based on an Al2O3 / MoO3 or HfO2 / MoO3 double-layer gate dielectric according to an embodiment of the present invention, wherein: 1 is the substrate; 2 is ALD deposition of Al2O3 or HfO2; 3 is precursor solution coating and heat treatment; 4 is nitrogen annealing and low-power short-time oxygen plasma oxidation; 5 is transferring a two-dimensional semiconductor material layer on the surface of the MoO3 thin film; 6 is preparing a photoresist electrode pattern; 7 is electron beam evaporation of metal electrodes; 8 is stripping and removing the photoresist. Figure 2 The transfer curves of back-gate field-effect transistors based on Al2O3 monolayer and Al2O3 / MoO3 bilayer gate dielectrics are shown in this embodiment of the invention. Figure 3 The transfer curves of the back-gate field-effect transistor based on HfO2 monolayer and HfO2 / MoO3 double-layer gate dielectric are shown in the embodiments of the present invention. Figure 4 The leakage current density and breakdown electric field characteristic curves are based on Al2O3 monolayer and Al2O3 / MoO3 bilayer gate dielectrics in embodiments of the present invention.

[0012] Figure 5 The leakage current density and breakdown electric field characteristic curves are based on HfO2 single-layer, HfO2 / MoO3 and MoO3 / HfO2 double-layer gate dielectrics according to embodiments of the present invention. Detailed Implementation

[0013] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0014] This application is proposed by the inventors based on the following considerations: To address the issues of surface dangling bonds and interface defects in ALD high-κ dielectric layers at sub-nanometer equivalent oxide thicknesses, an attempt was made to optimize performance through composite dielectric layer structures. One approach employs a high-κ dielectric and a two-dimensional buffer layer structure, such as an HfO2 / Sb2O3 stack, placing the two-dimensional material between the high-κ dielectric and the two-dimensional channel as an interface buffer layer. While this reduces interface states, the dielectric constant of the two-dimensional buffer layer itself is lower than that of the high-κ inorganic dielectric, limiting the improvement of the overall equivalent κ value. Furthermore, the buffer layer's attraction... Increasing the total dielectric thickness makes it difficult to achieve ultra-small EOT. Another approach uses a two-dimensional nucleation layer and a high-κ dielectric structure, such as a MoO3 / HfO2 stack. Two-dimensional MoO3 is used as a nucleation layer to promote uniform deposition of the high-κ dielectric in ALD on the substrate surface. However, its core objective is to solve the problem of uneven nucleation on inert surfaces during ALD processing. In this structure, MoO3 is located at the bottom of the dielectric layer, only playing a process auxiliary role and failing to leverage its high dielectric constant for gate modulation. Furthermore, the interface leakage current problem between MoO3 and the substrate needs to be addressed. In other words, this understanding holds that two-dimensional MoO3, due to its small intrinsic bandgap, can only be used as an interface buffer layer or as an ALD nucleation layer; using it as the main dielectric layer would lead to excessive leakage current.

[0015] In addition, the commonly used two-dimensional dielectric layer hBN has a low dielectric constant (~5), which cannot meet the requirements of sub-nanometer EOT; while two-dimensional MoO3 has a high dielectric constant (κ≈40), it relies on the "growth-transfer" process, and the transfer process is prone to introducing defects such as wrinkles, damage, contaminants and interface gaps, making it difficult to achieve wafer-level large-area uniform preparation; and it is easy to cause excessive leakage current in the extremely thin state; although the monolayer MoO3 prepared by the liquid phase method can achieve low interface states, its intrinsic breakdown resistance is poor, and when used alone as a gate dielectric, the leakage current is difficult to meet the requirements of low power devices.

[0016] Therefore, according to one or more embodiments of the present invention, a method for fabricating a wafer-level two-dimensional back-gate field-effect transistor array is provided, which includes the following steps: S1. Provide silicon wafers and preprocess the silicon wafers; S2. An atomic layer deposition process is used to deposit a 6 nm to 15 nm thick Al2O3 or HfO2 layer on the surface of the silicon wafer in step S1, followed by rapid annealing at 400 ℃ to 500 ℃ in a nitrogen atmosphere for 60 s to 120 s to form a bottom passivation insulating layer covering the silicon wafer. S3. Spin-coat the ammonium tetrathiomolybdate precursor solution onto the surface of the underlying passivation insulating layer, and heat-treat it at 120~160℃ for 2~5 min to solidify it into a precursor film. S4. The wafer with the precursor film is annealed in a nitrogen atmosphere at 400 ℃~500 ℃ for 5 min~15 min to generate a layered MoS2 two-dimensional material layer in situ. S5. Under the conditions of oxygen flow rate of 20 sccm and cavity pressure of 1.5 Pa, the layered MoS2 two-dimensional material layer is treated with 5~15 W low-power oxygen plasma for 10 s~50 s to generate a two-dimensional MoO3 thin film in situ, so as to form an Al2O3 / MoO3 or HfO2 / MoO3 double-layer composite dielectric layer on the silicon wafer. S6. A two-dimensional semiconductor channel layer is prepared on the two-dimensional MoO3 thin film in step S5. Then, a source-drain metal electrode array is prepared on the two-dimensional semiconductor channel layer by photolithography and electron beam evaporation to obtain a two-dimensional back gate field effect transistor array.

[0017] This application employs an in-situ two-step process. First, a precursor is spin-coated onto the ALD (Alternating Layer Deposition) bottom passivation insulating layer, followed by pyrolysis to generate a MoS2 intermediate phase. Then, low-power, short-duration oxygen plasma is used to achieve gentle and uniform in-situ layered oxidation. The entire process requires no physical transfer, avoiding structural damage caused by external forces. This method stably yields high-quality layered two-dimensional thin films, significantly improving the overall device performance. In other words, this method first utilizes an ALD to deposit a flat and dense bottom passivation insulating layer, and then prepares a high-quality two-dimensional MoO3 layer on its surface. The two layers work synergistically and complementaryly. The bottom passivation insulating layer provides excellent interface passivation and breakdown resistance, while the two-dimensional MoO3 layer provides a high dielectric constant, effectively suppressing interface defects and significantly improving gate control capability and device stability.

[0018] Specifically, this application employs an ALD deposition method to deposit Al2O3 or HfO2, followed by spin-coating of ammonium tetrathiomolybdate and its conversion into two-dimensional MoO3 to prepare Al2O3 / MoO3 or HfO2 / MoO3 bilayer gate dielectrics. These dielectrics exhibit a dense and uniform structure, excellent interfacial properties, and precisely controllable thickness. Compared to single-layer dielectrics or traditional composite dielectrics, this bilayer gate dielectric significantly reduces interfacial defects, suppresses leakage current, and improves breakdown resistance.

[0019] The fabrication method provided in this application is highly efficient, low-cost, and highly compatible, making it suitable for large-area device fabrication. The first annealing step (i.e., step S4) can be performed in a tube furnace under atmospheric pressure or low vacuum, with equipment costs and process complexity far lower than traditional methods such as molecular beam epitaxy (MBE) and chemical vapor deposition (CVD). The second oxidation conversion step (i.e., step S5) employs a low-power, short-time oxygen plasma oxidation process. This process has a fast oxidation rate and short processing time, and can be completed under low-temperature and low-vacuum conditions, eliminating the need for prolonged high-temperature annealing and avoiding damage to the underlying dielectric and wafer caused by high-temperature processes. Therefore, the fabrication method provided in this application has a simple overall process, low equipment requirements, and is easy to implement for large-area, mass production. While ensuring high-quality thin films, it also possesses the potential for high-efficiency and low-cost industrial applications.

[0020] In summary, the wafer-level two-dimensional back-gate field-effect transistor array fabrication method provided in this application addresses the technical pain points of existing devices, such as high leakage current and weak gate control capability, while simultaneously considering fabrication efficiency and cost control to achieve large-scale production. An in-situ two-step method is employed, transforming the precursor into a layered MoS2 mesophase through annealing, followed by gentle plasma oxidation to prepare a high-quality two-dimensional MoO3 thin film, effectively avoiding defects and damage in traditional processes. Simultaneously, Al2O3 or HfO2 is prepared via ALD, combining with the two-dimensional MoO3 to form a bilayer gate dielectric structure. The synergistic effect of these two methods significantly improves device stability and gate control performance. The overall process is simple, efficient, and low-cost, meeting the demands of large-scale production while optimizing device electrical performance.

[0021] According to a specific embodiment of the present invention, in step S3, before spin-coating the ammonium tetrathiomolybdate precursor solution, the surface of the underlying passivation insulating layer is treated with an ultraviolet ozone cleaner for 15 min to 30 min. This ultraviolet ozone pretreatment enhances the surface hydrophilicity of the underlying passivation insulating layer, ensuring uniform coating of the ammonium tetrathiomolybdate precursor solution, avoiding defects such as uneven film formation and pinholes during spin-coating, and improving the wafer-level uniformity of the dielectric layer.

[0022] Furthermore, the processing conditions set for the ultraviolet ozone cleaning machine are: ultraviolet intensity of 14.76 MW / cm². 2 The wavelength of the high-intensity ultraviolet lamp source is 254 nm.

[0023] According to a specific embodiment of the present invention, in step S3, the preparation method of the ammonium tetrathiomolybdate precursor solution is as follows: N,N-dimethylformamide, n-butylamine, and ethanolamine are mixed in a volume ratio of 5:2:1 and ultrasonically treated to obtain an organic solvent. Ammonium tetrathiomolybdate is dissolved in the organic solvent and ultrasonically treated for 30 min until uniformly dispersed. This precursor is prepared using a solution method, which is simple and inexpensive. Furthermore, the use of a specific ratio of ternary organic solvent system can achieve high solubility and dispersion stability of ammonium tetrathiomolybdate, avoiding precursor precipitation or aggregation, and providing a foundation for the subsequent preparation of high-quality MoS2 mesophase.

[0024] Furthermore, the mass concentration of ammonium tetrathiomolybdate in the ammonium tetrathiomolybdate precursor solution is 5 mg / mL to 10 mg / mL. By controlling the precursor concentration within the range of 5 mg / mL to 10 mg / mL, the thickness of the final MoO3 film can be precisely controlled within the range of 3 nm to 5 nm, adapting to the dielectric layer thickness requirements of different application scenarios.

[0025] According to a specific embodiment of the present invention, in step S3, the spin coating includes a first spin coating and a second spin coating. The first spin coating speed is 400 rpm to 600 rpm, and the time is 5 s to 15 s; the second spin coating speed is 2000 rpm to 3000 rpm, and the time is 20 s to 40 s. This two-step spin coating process ensures uniform spreading of the precursor on the wafer surface by using low-speed spin coating, while high-speed spin coating controls the film thickness, achieving a large-area film thickness deviation of <±0.5 nm, thus meeting the uniformity requirements of wafer-level fabrication.

[0026] According to a specific embodiment of the present invention, in step S6, the two-dimensional semiconductor channel layer is a 4-inch monolayer MoS2 transferred as a whole. Using a 4-inch monolayer MoS2 as the channel layer avoids the low efficiency and alignment errors of transferring small-sized samples one by one, improves the performance consistency of the device array, and is suitable for large-scale array fabrication.

[0027] According to one or more embodiments of the present invention, a two-dimensional back-gate field-effect transistor array fabricated using the above-described method is also provided, the two-dimensional back-gate field-effect transistor array comprising, from bottom to top, stacked as follows: Silicon wafers; A high dielectric constant bottom passivation insulating layer; The layered MoO3 top dielectric layer, together with the bottom passivation insulating layer, constitutes a double-layer composite dielectric layer; A two-dimensional semiconductor channel layer is in direct contact with the layered MoO3 top dielectric layer; and Source / drain metal electrode array.

[0028] In this two-dimensional back-gate field-effect transistor array, the bottom passivation insulating layer of the double-layer composite dielectric layer provides excellent interface passivation and breakdown resistance characteristics, while the top two-dimensional MoO3 layer provides a high dielectric constant, which can effectively suppress interface defects and significantly improve gate control capability and device stability. The two work together to significantly improve device stability and gate control performance.

[0029] According to a specific embodiment of the present invention, the bottom passivation insulating layer is Al2O3 or HfO2, and the bottom passivation insulating layer is formed by atomic layer deposition and subjected to rapid annealing; the thickness of the bottom passivation insulating layer is 6 nm. Limiting the thickness of the bottom passivation insulating layer to 6 nm balances the withstand voltage capability of the dielectric layer and the requirement for reducing the equivalent oxide layer thickness, and is the optimal thickness range that takes into account both leakage current suppression and gate control capability.

[0030] According to a specific embodiment of the present invention, the layered MoO3 top dielectric layer is generated on the bottom passivation insulating layer by spin coating of ammonium tetrathiomolybdate precursor, sulfurization annealing, and low-power oxygen plasma oxidation. The thickness of the layered MoO3 top dielectric layer is 4 nm. Limiting the thickness of the top MoO3 to 4 nm ensures sufficient dielectric constant improvement while avoiding increased leakage current caused by excessive MoO3 thickness, thus achieving optimal matching of dielectric properties.

[0031] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0032] Example 1 refer to Figure 1 A method for fabricating a wafer-level Al2O3 / MoO3 double-layer gate dielectric two-dimensional back-gate field-effect transistor array includes the following steps: S1. Silicon Substrate Pretreatment: Select a 4-inch silicon wafer and perform standard RCA cleaning sequentially. First, use a mixed solution with a volume ratio of H2SO4:H2O2 = 1:1-4:1, at 120 ℃-150 ℃. o Soak for 10 minutes under C conditions, then rinse thoroughly with plenty of deionized water. Then soak for 1 minute in a dilute hydrofluoric acid solution of HF:H2O=1:10-1:50 to remove the natural oxide layer on the wafer surface, rinse thoroughly with deionized water, and finally dry with nitrogen (N2).

[0033] S2. Preparation of the underlying passivation insulating layer: A 6 nm thick Al2O3 layer was deposited on the silicon substrate wafer treated in step S1 using the ALD method as the gate dielectric and passivation layer. The growth temperature was 300 ℃. The underlying precursors were trimethylaluminum (TMA) and H2O; TMA was used as the aluminum source, and H2O was used as the oxidant. The wafer with the ALD-deposited underlying passivation insulating layer was annealed for 90 s at 500 ℃ in a N2 atmosphere using a rapid thermal processing (RTP) furnace, with a heating rate of 10 ℃ / s and a nitrogen flow rate of 3 SLM.

[0034] S3. Spin-coating the top layer precursor solution: Prepare the top layer precursor solution by adding N,N-dimethylformamide (DMF), n-butylamine, and ethanolamine sequentially in a reagent bottle at a volume ratio of 5:2:1. Sonicate for 10 min to obtain a homogeneous organic solvent. Add ammonium tetrathiomolybdate (ATTM) to the above organic solvent and sonicate for 30 min to obtain a homogeneously dispersed precursor solution. The mass concentration of ammonium tetrathiomolybdate in the precursor solution is 6 mg / mL.

[0035] The wafer with the ALD deposited bottom passivation insulating layer obtained in step S2 was treated with a UV ozone cleaner for 20 min; the treatment conditions were: UV intensity 14.76 MW / cm². 2 A high-intensity ultraviolet lamp with a wavelength of 254 nm was used to enhance the surface hydrophilicity of the underlying passivation insulating layer. Then, the aforementioned top-layer precursor solution was spin-coated onto the wafer surface of the ALD-deposited underlying passivation insulating layer. The spin-coating parameters were 500 rpm for 10 s in the first step and 2500 rpm for 30 s in the second step, resulting in a wafer covered with a precursor liquid film. The wafer covered with the precursor liquid film was then heated to 150 °C for 3 min using a hot plate to solidify ATTM onto the surface of the underlying passivation insulating layer and evaporate the organic solvent, thereby solidifying the precursor liquid film to form a precursor thin film.

[0036] S4, First step of conversion (sulfidation): The wafer with the precursor film obtained in step S3 is annealed at 450 °C in N2 atmosphere for 20 min to obtain a two-dimensional material layer formed by multiple layers of MoS2.

[0037] S5. Second step of conversion (plasma oxidation): Using a reactive ion etching system, multilayer MoS2 is oxidized into a transparent two-dimensional MoO3 film. The reactive ion etching system is set with an oxygen (O2) flow rate of 20 sccm, an O2 pressure of 1.5 Pa in the plasma chamber, and an oxygen plasma maintained at 10 W for 30 s, forming a top layer of MoO3 dielectric with a thickness of approximately 4 nm. Thus, an Al2O3 / MoO3 bilayer composite dielectric layer is formed on the wafer.

[0038] S6. Fabrication of the Two-Dimensional Back-Gate Field-Effect Transistor: The channel layer is fabricated by transferring a two-dimensional semiconductor material (such as a CVD-grown monolayer MoS2) onto the MoO3 thin film processed in step S5. Electrode patterning involves spin-coating AZ5214E ​​photoresist onto a wafer covered with the two-dimensional semiconductor material, performing UV exposure through a mask, and developing in a developer (such as a TMAH-based developer) to obtain the photoresist electrode pattern. Then, an electron beam evaporation is used to deposit a 50 nm Au electrode on the surface of the two-dimensional semiconductor material layer with the photoresist electrode pattern. Finally, the sample with the electrode material layer is immersed in acetone or N-methylpyrrolidone (NMP) to peel off the photoresist electrode pattern, obtaining the two-dimensional back-gate field-effect transistor. It should be noted that... Figure 1 The diagram illustrates a single two-dimensional back-gate field-effect transistor (i.e., FET device). In this embodiment, a two-dimensional back-gate field-effect transistor array can be obtained by transferring a single layer of large-area two-dimensional semiconductor material, followed by photolithography and electron beam evaporation steps to form a source-drain metal electrode array.

[0039] In this embodiment, a back-gate field-effect transistor with an Al2O3 monolayer is also formed as a comparison. That is, an Al2O3 monolayer dielectric layer with a thickness of 10 nm is prepared in step S2, and then the back-gate field-effect transistor is prepared directly in step S6.

[0040] The back-gate field-effect transistors prepared in this embodiment with Al2O3 / MoO3 double-layer gate dielectric (Al2O3 thickness approximately 6 nm, MoO3 thickness approximately 4 nm, total thickness approximately 10 nm) and Al2O3 single-layer dielectric (thickness approximately 10 nm) were subjected to electrical performance tests: The transfer curve of the back-gate field-effect transistor is as follows: Figure 2 As shown, electrical results indicate that the subthreshold swing of the Al2O3 / MoO3 double-layer gate dielectric device is 130 mV / dec, and the interface state density is [missing information]. D it Approximately 8.8 × 10 12 cm 2 eV 1 The migration rate can reach 40 cm. 2 / (V (s), superior to Al2O3 single-layer gate dielectric devices (190 mV / dec, 1.3×10 s), 13 cm 2 eV 1 22 cm 2 / (V The results show that the gate control capability and carrier transport of the Al2O3 / MoO3 bilayer gate dielectric are significantly improved. This Al2O3 / MoO3 bilayer gate dielectric effectively passivates the surface dangling bonds of the ALD high-κ dielectric, forming a low-defect van der Waals interface.

[0041] Leakage current performance test such as Figure 4 As shown: The leakage current-electric field characteristics of the dielectric layer were tested using a metal-insulator-metal (MIM) structure. Under an electric field strength of 1 MV / cm, the leakage current density of the Al2O3 / MoO3 double-layer gate dielectric was 5.9 × 10⁻⁶. -9 A / cm 2 Compared to the leakage current density of a single Al2O3 layer of the same thickness (9.1×10⁻⁶), -8 A / cm 2 The breakdown field strength was reduced by approximately 94%; the breakdown field strength reached 12.3 MV / cm, which is 50% higher than the 8.2 MV / cm of the Al2O3 monolayer medium.

[0042] Equivalent oxide layer thickness measurement: The maximum accumulated capacitance of the Al2O3 / MoO3 double-layer gate dielectric at 1 MHz was obtained by high-frequency capacitance-voltage (CV) measurement, which was 1.2 μF / cm. 2 The equivalent oxide layer thickness (EOT) of the Al2O3 / MoO3 double-layer gate dielectric was calculated to be 2.9 nm, which is a significant reduction compared to the EOT of a single Al2O3 dielectric of the same thickness (~3.9 nm).

[0043] This embodiment introduces MoO3 with a higher dielectric constant as the top layer. Under the premise of keeping the total physical thickness unchanged, the equivalent oxide layer thickness is reduced compared with Al2O3 monolayer. At the same time, the leakage current is reduced by one order of magnitude, which proves that the Al2O3 / MoO3 double-layer gate structure achieves a synergistic improvement in EOT reduction and leakage current suppression. This composite dielectric layer can achieve a smaller equivalent oxide layer thickness while keeping the total physical thickness unchanged, which is more conducive to device size miniaturization.

[0044] Example 2 refer to Figure 1A method for fabricating a wafer-level HfO2 / MoO3 double-layer gate dielectric two-dimensional back-gate field-effect transistor array includes the following steps: S1. Silicon Substrate Pretreatment: Select a 4-inch silicon wafer and perform standard RCA cleaning sequentially. First, use a mixed solution with a volume ratio of H2SO4:H2O2 = 1:1-4:1, at 120 ℃-150 ℃. o Soak for 10 minutes under C conditions, then rinse thoroughly with plenty of deionized water. Then soak for 1 minute in a dilute hydrofluoric acid solution of HF:H2O=1:10-1:50 to remove the natural oxide layer on the wafer surface, rinse thoroughly with deionized water, and finally dry with nitrogen (N2).

[0045] S2. Preparation of the underlying passivation insulating layer: A 6 nm thick HfO2 layer was deposited on the silicon substrate wafer after step S1 using the ALD method as the gate dielectric and passivation layer. The growth temperature was 250 °C. The underlying precursors were tetra(ethylmethylamino)hafnium (TEMAHf) and H2O; TEMAHf served as the hafnium source, and H2O served as the oxidant. The wafer with the ALD-deposited underlying passivation insulating layer was annealed for 100 s at 500 °C in a N2 atmosphere using a rapid thermal processing (RTP) furnace with a heating rate of 10 °C / s and a nitrogen flow rate of 4 SLM.

[0046] S3. Spin-coating the top layer precursor solution: Prepare the top layer precursor solution by adding N,N-dimethylformamide (DMF), n-butylamine, and ethanolamine sequentially in a reagent bottle at a volume ratio of 5:2:1. Sonicate for 10 min to obtain a homogeneous organic solvent. Add ammonium tetrathiomolybdate (ATTM) to the above organic solvent and sonicate for 30 min to obtain a homogeneously dispersed precursor solution. The mass concentration of ammonium tetrathiomolybdate in the precursor solution is 6 mg / mL.

[0047] The wafer with the ALD deposited bottom passivation insulating layer obtained in step S2 was treated with a UV ozone cleaner for 30 min; the treatment conditions were: UV intensity 14.76 MW / cm². 2A high-intensity ultraviolet lamp with a wavelength of 254 nm was used to enhance the surface hydrophilicity of the underlying passivation insulating layer. Then, the aforementioned top-layer precursor solution was spin-coated onto the wafer surface of the ALD-deposited underlying passivation insulating layer. The spin-coating parameters were 500 rpm for 10 s in the first step and 2500 rpm for 30 s in the second step, resulting in a wafer covered with a precursor liquid film. The wafer covered with the precursor liquid film was then heated to 150 °C for 3 min using a hot plate to solidify ATTM onto the surface of the underlying passivation insulating layer and evaporate the organic solvent, thereby solidifying the precursor liquid film to form a precursor thin film.

[0048] S4, First step of conversion (sulfidation): The wafer with the precursor film obtained in step S3 is annealed at 450 °C in N2 atmosphere for 20 min to obtain a two-dimensional material layer formed by multiple layers of MoS2.

[0049] S5. Second step of conversion (plasma oxidation): Using a reactive ion etching system, multilayer MoS2 is oxidized into a transparent two-dimensional MoO3 film. The reactive ion etching system is set with an oxygen (O2) flow rate of 20 sccm, an O2 pressure of 1.5 Pa in the plasma chamber, and an oxygen plasma maintained at 10 W for 30 s, forming a top layer of MoO3 dielectric with a thickness of approximately 4 nm. Thus, an HfO2 / MoO3 bilayer composite dielectric layer is formed on the wafer.

[0050] S6. Fabrication of the Two-Dimensional Back-Gate Field-Effect Transistor: The channel layer is fabricated by transferring a two-dimensional semiconductor material (such as a CVD-grown monolayer MoS2) onto the MoO3 thin film processed in step S5. Electrode patterning involves spin-coating AZ5214E ​​photoresist onto a wafer covered with the two-dimensional semiconductor material, performing UV exposure through a mask, and developing in a developer (such as a TMAH-based developer) to obtain the photoresist electrode pattern. Then, an electron beam evaporation is used to deposit a 50 nm Au electrode on the surface of the two-dimensional semiconductor material layer with the photoresist electrode pattern. Finally, the sample with the electrode material layer is immersed in acetone or N-methylpyrrolidone (NMP) to peel off the photoresist electrode pattern, obtaining the two-dimensional back-gate field-effect transistor. It should be noted that... Figure 1 The diagram illustrates a single two-dimensional back-gate field-effect transistor (i.e., FET device). In this embodiment, a two-dimensional back-gate field-effect transistor array can be obtained by transferring a single layer of large-area two-dimensional semiconductor material, followed by photolithography and electron beam evaporation steps to form a source-drain metal electrode array.

[0051] In this embodiment, back-gate field-effect transistors with HfO2 monolayer and MoO3 / HfO2 double-layer gate dielectrics are also formed as a comparison. That is, a 10 nm thick HfO2 monolayer dielectric layer is prepared in step S2, and then the back-gate field-effect transistor is prepared directly in step S6. A 6 nm thick MoO3 monolayer dielectric layer is prepared in steps S1, S3-S5, and then a 4 nm thick HfO2 monolayer dielectric layer is prepared on the 6 nm thick MoO3 monolayer dielectric layer in step S2. Finally, the back-gate field-effect transistor is prepared in step S6.

[0052] The back-gate field-effect transistors prepared in this embodiment with HfO2 / MoO3 double-layer gate dielectric (HfO2 thickness approximately 6 nm, MoO3 thickness approximately 4 nm, total thickness approximately 10 nm), HfO2 single-layer dielectric (thickness approximately 10 nm), and MoO3 / HfO2 double-layer gate dielectric (MoO3 thickness approximately 6 nm, HfO2 thickness approximately 4 nm, total thickness approximately 10 nm) were subjected to electrical performance tests: The transfer curve of the back-gate field-effect transistor is as follows: Figure 3 As shown, electrical results indicate that the subthreshold swing of the HfO2 / MoO3 double-layer gate dielectric device is 83 mV / dec, and the interface state density is... D it Approximately 4.9 × 10 12 cm 2 eV 1 The migration rate can reach 56 cm. 2 / (V (s), superior to HfO2 single-layer gate dielectric devices (114 mV / dec, 1.0×10 s), 13 cm 2 eV 1 30 cm 2 / (V The results show that the gate control capability and carrier transport of the HfO2 / MoO3 bilayer gate dielectric are significantly improved. The HfO2 / MoO3 bilayer gate dielectric effectively passivates the surface dangling bonds of the ALD high-κ dielectric, forming a low-defect van der Waals interface.

[0053] Leakage current performance test such as Figure 5 As shown: The leakage current-electric field characteristics of the dielectric layer were tested using a metal-insulator-metal (MIM) structure. Under an electric field strength of 1 MV / cm, the leakage current density of the HfO2 / MoO3 double-layer gate dielectric was 2.4 × 10⁻⁶. -8 A / cm 2Compared to the leakage current density of a single-layer HfO2 dielectric of the same thickness (7.9 × 10⁻⁶), -7 A / cm 2 The leakage current density is reduced by approximately 97% compared to that of a MoO3 / HfO2 double-layer gate dielectric of the same thickness (1.4 × 10⁻⁶). -6 A / cm 2 The breakdown field strength is reduced by approximately 98%; the breakdown field strength reaches 6.5 MV / cm, which is 59% higher than the 4.1 MV / cm of the same thickness HfO2 monolayer dielectric and 63% higher than the 4.0 MV / cm of the same thickness MoO3 / HfO2 bilayer gate dielectric.

[0054] Equivalent oxide layer thickness test: The maximum accumulated capacitance of the HfO2 / MoO3 double-layer gate dielectric at 1 MHz was found to be 2.0 μF / cm² using high-frequency capacitance-voltage (CV) testing. 2 The equivalent oxide layer thickness (EOT) of the HfO2 / MoO3 double-layer gate dielectric was calculated to be 1.7 nm, which is a slight reduction compared to the EOT (~2 nm) of the single HfO2 dielectric of the same thickness.

[0055] This embodiment introduces MoO3 with a higher dielectric constant as the top layer. Under the premise of keeping the total physical thickness unchanged, the equivalent oxide layer thickness is reduced compared with HfO2 monolayer. At the same time, the leakage current is reduced by 1-2 orders of magnitude compared with HfO2 monolayer and MoO3 / HfO2 double-layer gate dielectric. This proves that the HfO2 / MoO3 double-layer gate structure achieves a synergistic improvement in EOT reduction and leakage current suppression. This composite dielectric layer can achieve a smaller equivalent oxide layer thickness while keeping the total physical thickness unchanged, which is more conducive to device size miniaturization.

[0056] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0058] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0059] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0061] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for fabricating a wafer-level two-dimensional back-gate field-effect transistor array, characterized in that, Includes the following steps: S1. Provide silicon wafers and preprocess the silicon wafers; S2. An atomic layer deposition process is used to deposit a 6 nm to 15 nm thick Al2O3 or HfO2 layer on the surface of the silicon wafer in step S1, followed by rapid annealing at 400 ℃ to 500 ℃ in a nitrogen atmosphere for 60 s to 120 s to form a bottom passivation insulating layer covering the silicon wafer. S3. Spin-coat the ammonium tetrathiomolybdate precursor solution onto the surface of the underlying passivation insulating layer, and heat-treat it at 120~160℃ for 2~5 min to solidify it into a precursor film. S4. The wafer with the precursor film is annealed in a nitrogen atmosphere at 400 ℃~500 ℃ for 5 min~15 min to generate a layered MoS2 two-dimensional material layer in situ. S5. Under the conditions of oxygen flow rate of 20 sccm and cavity pressure of 1.5 Pa, the layered MoS2 two-dimensional material layer is treated with 5~15 W low-power oxygen plasma for 10 s~50 s to generate a two-dimensional MoO3 thin film in situ, so as to form an Al2O3 / MoO3 or HfO2 / MoO3 double-layer composite dielectric layer on the silicon wafer. S6. A two-dimensional semiconductor channel layer is prepared on the two-dimensional MoO3 thin film in step S5. Then, a source-drain metal electrode array is prepared on the two-dimensional semiconductor channel layer by photolithography and electron beam evaporation to obtain a two-dimensional back gate field effect transistor array.

2. The preparation method according to claim 1, characterized in that, In step S3, before spin-coating the ammonium tetrathiomolybdate precursor solution, the surface of the underlying passivation insulating layer is treated with an ultraviolet ozone cleaner for 15 min to 30 min.

3. The preparation method according to claim 2, characterized in that, The ultraviolet ozone cleaning machine is set to the following conditions: ultraviolet intensity of 14.76 MW / cm². 2 The wavelength of the high-intensity ultraviolet lamp source is 254 nm.

4. The preparation method according to claim 1, characterized in that, In step S3, the preparation method of the ammonium tetrathiomolybdate precursor solution is as follows: N,N-dimethylformamide, n-butylamine and ethanolamine are mixed in a volume ratio of 5:2:1 and ultrasonically treated to obtain an organic solvent. Ammonium tetrathiomolybdate is dissolved in the organic solvent and ultrasonically treated for 30 min until it is evenly dispersed.

5. The preparation method according to claim 4, characterized in that, The mass concentration of ammonium tetrathiomolybdate in the ammonium tetrathiomolybdate precursor solution is 5 mg / mL to 10 mg / mL.

6. The preparation method according to claim 1, characterized in that, In step S3, the spin coating includes a first spin coating and a second spin coating. The first spin coating speed is 400 rpm to 600 rpm and the time is 5 s to 15 s. The second spin coating speed is 2000 rpm to 3000 rpm and the time is 20 s to 40 s.

7. The preparation method according to claim 1, characterized in that, In step S6, the two-dimensional semiconductor channel layer is a 4-inch monolayer MoS2 transferred as a whole.

8. A two-dimensional back-gate field-effect transistor array prepared by the method described in any one of claims 1-7, characterized in that, The two-dimensional back-gate field-effect transistor array comprises, from bottom to top, stacked sequentially: Silicon wafers; A high dielectric constant bottom passivation insulating layer; The layered MoO3 top dielectric layer, together with the bottom passivation insulating layer, constitutes a double-layer composite dielectric layer; A two-dimensional semiconductor channel layer is in direct contact with the layered MoO3 top dielectric layer; and Source / drain metal electrode array.

9. The two-dimensional back-gate field-effect transistor array as described in claim 8, characterized in that, The underlying passivation insulating layer is Al2O3 or HfO2, and is formed by atomic layer deposition followed by rapid annealing; the thickness of the underlying passivation insulating layer is 6 nm.

10. The two-dimensional back-gate field-effect transistor array as described in claim 8, characterized in that, The layered MoO3 top dielectric layer is generated on the bottom passivation insulating layer by spin coating of ammonium tetrathiomolybdate precursor, sulfurization annealing and low-power oxygen plasma oxidation. The thickness of the layered MoO3 top dielectric layer is 4 nm.

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