A semiconductor device and a manufacturing method thereof
By forming cavities in the silicide barrier layer and adjusting the etching amount to accommodate the etching of different contact holes, the process window mismatch problem caused by different etching amounts in the BCD process is solved, reducing etching difficulty and improving the yield and performance of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RONGXIN SEMICON (HUAIAN) CO LTD
- Filing Date
- 2026-05-20
- Publication Date
- 2026-06-16
AI Technical Summary
In the BCD process, the etching amounts of field plate contact holes and shared contact holes are different, which means that the same etching formula cannot simultaneously meet the process window requirements of all contact holes, increasing the difficulty of developing contact hole etching processes.
A cavity is formed in the silicide barrier layer, and the position of the cavity corresponds to the first contact hole to be formed later. The etching amount is adjusted by the cavity, rather than simply adjusting the thickness of the silicide barrier layer, so as to achieve both etching of the first contact hole and the second contact hole.
It reduces the difficulty of developing contact hole etching processes and significantly reduces leakage current in semiconductor devices, thereby improving device yield.
Smart Images
Figure CN122227658A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] BCD (Bipolar-CMOS-DMOS) is a monolithic integration process that fabricates bipolar transistors, complementary metal-oxide-semiconductor (CMOS) devices, and double-diffused metal-oxide-semiconductor (DMOS) devices on the same chip.
[0003] In BCD (Browser-Chip-Device) processes, there are typically three types of contact holes: ordinary contact holes, field contact holes, and shared contact holes. Field contact holes need to contact the silicide barrier layer at their bottom, while shared contact holes connect multiple regions simultaneously. For example, the bottom of a shared contact hole may simultaneously contact the gate and the active region. This results in different etching amounts when forming field contact holes and shared contact holes. The difference in etching amounts means that the same etching formula cannot simultaneously meet the process windows of all contact holes. In other words, while ensuring product quality, it is impossible to ensure that the process parameters of all contact holes are within the allowable fluctuation range, thus making the development of contact hole etching processes highly difficult. Summary of the Invention
[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0005] To address the existing problems, this application provides a method for manufacturing a semiconductor device, the method comprising: A semiconductor structure is provided, the semiconductor structure including a substrate, an active region formed therein, and a gate structure formed on the active region; A silicide barrier layer is formed, the silicide barrier layer extending from the active region to a portion of the top surface of the adjacent gate structure, wherein the silicide barrier layer includes a cavity, the orthographic projection of the cavity on the substrate being located within the orthographic projection of the subsequently formed first contact hole on the substrate; An interlayer dielectric layer is formed to cover the silicide barrier layer and the exposed areas of the semiconductor structure; The interlayer dielectric layer and a portion of the silicide barrier layer are etched to form a first contact hole that exposes a portion of the remaining silicide barrier layer.
[0006] In one embodiment, a second contact hole is formed simultaneously with the formation of the first contact hole, wherein the second contact hole exposes a portion of the surface of the active region and a portion of the top surface of the gate structure.
[0007] In one embodiment, the silicide barrier layer includes a first barrier layer on a substrate and a second barrier layer on the first barrier layer.
[0008] In one embodiment, the method of forming the silicide barrier layer includes: A first dielectric layer is formed on the substrate, the first dielectric layer covering the surface of the substrate and conformally covering the gate structure; A second dielectric layer is formed covering the first dielectric layer; A third dielectric layer is formed on the second dielectric layer at least in the first contact hole region; A fourth dielectric layer is formed, which covers the top surface and sidewalls of the second dielectric layer and the third dielectric layer; At least a portion of the fourth dielectric layer is removed to expose a portion of the third dielectric layer; Remove the third dielectric layer to form the cavity between the second dielectric layer and the fourth dielectric layer; The first dielectric layer and the second barrier layer are etched to form the first barrier layer located in the first contact hole region and a portion of the top surface of the gate structure, and the second barrier layer located on the first barrier layer.
[0009] In one embodiment, the second dielectric layer and the fourth dielectric layer are made of the same material, but are made of a different material than the first dielectric layer and the third dielectric layer.
[0010] In one embodiment, the first dielectric layer is made of silicon oxide, and the second dielectric layer and / or the fourth dielectric layer is made of silicon nitride.
[0011] In one embodiment, removing the third dielectric layer to form a cavity between the second dielectric layer and the fourth dielectric layer includes: removing the third dielectric layer using a wet etching process.
[0012] In one embodiment, the thickness of the first dielectric layer ranges from 500 angstroms to 1500 angstroms, the thickness of the second dielectric layer ranges from 100 angstroms to 1000 angstroms, the thickness of the third dielectric layer ranges from 100 angstroms to 1000 angstroms, and the thickness of the fourth dielectric layer ranges from 100 angstroms to 1000 angstroms.
[0013] In one embodiment, removing at least a portion of the fourth dielectric layer to expose a portion of the third dielectric layer includes: A patterned mask layer is formed on the fourth dielectric layer, the patterned mask layer at least covering the fourth dielectric layer on the first contact hole region; Using the patterned mask layer as a mask, the fourth dielectric layer is etched to expose a portion of the third dielectric layer.
[0014] This application also provides a semiconductor device, which is manufactured using the above-described manufacturing method.
[0015] The semiconductor device and manufacturing method of the present application embodiment form a cavity in the silicide barrier layer, and the position of the cavity corresponds to the first contact hole to be formed subsequently. Instead of adjusting the etching amount during the etching of the first contact hole by simply adjusting the thickness of the silicide barrier layer, the etching amount during the etching of the first contact hole is adjusted by the cavity. This avoids increasing the thickness of the interlayer dielectric layer while making it easier to simultaneously etch the first contact hole (e.g., field plate contact hole) and the second contact hole (e.g., shared contact hole), thereby reducing the difficulty of developing the etching process for the contact hole. Attached Figure Description
[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0017] In the attached image: Figure 1 A partial cross-sectional view of a semiconductor structure with conventional contact holes, field plate contact holes, and shared contact holes in the related art is shown. Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown; Figures 3A-3J A cross-sectional view of a semiconductor device obtained by sequentially performing a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown. Figure 4A A cross-sectional view of a semiconductor device fabricated using a manufacturing method employing related technologies is shown. Figure 4B A cross-sectional view of a semiconductor device manufactured using a semiconductor device manufacturing method according to a specific embodiment of this application is shown. Figure 5A The leakage current distribution statistics of a semiconductor device are shown after contact holes are formed using an etching method based on relevant technologies. Figure 5BThe diagram illustrates the leakage current distribution statistics of a semiconductor device after a contact hole is formed using a manufacturing method according to a specific embodiment of this application. Detailed Implementation
[0018] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0020] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.
[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0024] BCD (Bipolar-CMOS-DMOS) is a monolithic integration process that fabricates bipolar transistors, complementary metal-oxide-semiconductor (CMOS) devices, and double-diffused metal-oxide-semiconductor (DMOS) devices on the same chip.
[0025] In the BCD process, such as Figure 1 As shown, there are typically three types of contact holes: conventional contact hole 10, field plate contact hole 11, and shared contact hole 12. Figure 1In this context, Oxide represents oxide, serving as the interlayer dielectric layer; SION represents silicon oxynitride, serving as the etch stop layer; SIN represents silicon nitride; SAB represents silicide barrier layer, both of which together serve as the field plate dielectric layer; and Poly represents polysilicon gate. The field plate contact hole 11 is associated with the field plate structure and is located above the drift region of the power device. It connects the field plate to a specific potential (usually the source). When forming the field plate contact hole, it needs to pass through a relatively thick interlayer dielectric layer and stop on the silicide barrier layer 101. That is, the bottom of the field plate contact hole 11 needs to contact the silicide barrier layer 101. The shared contact hole 12 connects multiple regions at the same time. For example, the bottom of the shared contact hole 12 needs to contact the gate 121, the active region of the power device, and part of the sidewall 122 at the same time. Since the etching stop layers of the field plate contact hole 11 and the shared contact hole 12 are different, this will result in different etching amounts when forming the field plate contact hole 11 and the shared contact hole 12. The difference in etching amount will cause the same etching formula to be unable to meet the process window of all contact holes at the same time. That is, under the premise of ensuring product qualification, it is impossible to ensure that the process parameters of all contact holes are within the allowable fluctuation range, which leads to high difficulty in developing the contact hole etching process.
[0026] Therefore, in view of the aforementioned technical problems, this application proposes a semiconductor device and a method for manufacturing the same.
[0027] The method for manufacturing a semiconductor device according to embodiments of this application includes the following steps: Step S1: Provide a semiconductor structure, the semiconductor structure including a substrate, an active region formed in the substrate, and a gate structure formed on the substrate; Step S2: Form a silicide barrier layer extending from the active region to a portion of the top surface of the adjacent gate structure, wherein the silicide barrier layer includes a cavity, and the orthographic projection of the cavity onto the substrate lies within the orthographic projection of the subsequently formed first contact hole onto the substrate. Step S3: Form an interlayer dielectric layer that covers the silicide barrier layer and the exposed areas of the semiconductor structure; Step S4: Etch the interlayer dielectric layer and a portion of the silicide barrier layer to form the first contact hole that exposes a portion of the remaining silicide barrier layer.
[0028] The semiconductor device and manufacturing method of the present application embodiment form a cavity in the silicide barrier layer, and the position of the cavity corresponds to the first contact hole to be formed subsequently. Instead of adjusting the etching amount during the etching of the first contact hole by simply adjusting the thickness of the silicide barrier layer, the etching amount during the etching of the first contact hole is adjusted by the cavity. In this way, the etching of the first contact hole (e.g., field plate contact hole) and the etching of the second contact hole (e.g., shared contact hole) can be more easily taken into account without increasing the thickness of the interlayer dielectric layer, thereby reducing the difficulty of developing the etching process of the contact hole.
[0029] Below, in conjunction with Figure 2 , Figures 3A-3J , Figures 4A-4B as well as Figures 5A-5B The method for manufacturing the semiconductor structure of this application is described in detail.
[0030] The method for manufacturing a semiconductor device according to embodiments of this application includes the following steps: refer to Figure 2 Step S1 is executed to provide a semiconductor structure, the semiconductor structure including a substrate, an active region formed in the substrate, and a gate structure formed on the substrate.
[0031] For example, such as Figure 3A As shown, the semiconductor structure includes a substrate 300, which is any suitable substrate material known in the art, such as a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, epitaxial silicon substrate, silicon-on-insulator (SoI) substrate, or germanium-on-insulator (GoI) substrate, or other suitable materials, but is not limited thereto.
[0032] A gate structure 301 is formed on a substrate 300. The gate structure 301 includes a gate 3011 and a sidewall 3012. An active region is formed in the substrate 300, including a drain region 303 and a source region 302 located on opposite sides of the gate structure 301. The gate structure 301 can be formed using any suitable process known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The source region 302 and drain region 303 can be formed using any suitable process known to those skilled in the art, such as ion implantation. The sidewall 3012 can be a stacked structure comprising silicon oxide, silicon nitride, and silicon oxide.
[0033] A gate oxide layer 321 is also formed between the gate structure 301 and the substrate 300. The gate oxide layer 321 can be formed by any suitable process known to those skilled in the art, such as thermal oxidation, in-situ water vapor generation, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
[0034] A drift region 304 and a body region 305 are formed in the substrate 300, extending from the top surface of the substrate 300 into its interior. The body region 305 is located below one side of the gate structure 301, the drain region 303 is located in the drift region 304 below the other side of the gate structure 301, and the source region 302 is located in the body region 305. A contact region 320 is also formed in the body region 305, which is spaced apart from the source region 302.
[0035] For example, an inversion doped layer 306 extending from the bottom of the substrate 300 into the interior of the substrate 300 is formed on one side of the bottom surface of the substrate 300. The doping type of the inversion doped layer 306 is opposite to that of the drift region 304, so as to reduce the peak value of the surface electric field, increase the breakdown voltage and block the leakage path between devices with different potentials, thereby achieving potential isolation.
[0036] Next, continue to refer to Figure 2 Step S2 is performed to form a silicide barrier layer, which extends from the active region to a portion of the top surface of the adjacent gate structure, wherein the silicide barrier layer includes a cavity, the orthographic projection of the cavity on the substrate being located within the orthographic projection of the subsequently formed first contact hole on the substrate.
[0037] For example, the silicide barrier layer includes a first barrier layer on a substrate and a second barrier layer on the first barrier layer, with the cavity located in the second barrier layer.
[0038] Specifically, firstly, continue as follows Figure 3A As shown, a first dielectric layer 307 is formed on the substrate 300, for example, by chemical vapor deposition. The first dielectric layer 307 covers the surface of the substrate 300 and conformally covers the gate structure 301. Exemplarily, the material of the first dielectric layer 307 includes, but is not limited to, silicon oxide.
[0039] Then, continue as follows Figure 3A As shown, a second dielectric layer 308 covering the first dielectric layer is formed on the first dielectric layer 307. Exemplarily, the material of the second dielectric layer includes, but is not limited to, silicon nitride.
[0040] Next, as Figure 3B As shown, a third dielectric material layer 3091 covering the second dielectric layer 308 is formed on the second dielectric layer 308, and then as follows Figure 3CAs shown, a third dielectric material layer 3091 is etched to form a third dielectric layer 309 on the second dielectric layer 308 at least in the first contact hole region (the region corresponding to the first contact hole). For example, the first contact hole region is located above the drain region 303, and the third dielectric layer 309 is formed on the second dielectric layer 308 above a portion of the drain region 303. It is worth mentioning that the third dielectric layer 309 can also be formed on the sidewall of the gate structure 301 adjacent to the drain region 303. For example, a dry etching process can be used to remove the third dielectric material layer 3091 on the drain region and in areas other than the sidewall adjacent to the drain region to form the third dielectric layer 309.
[0041] Next, as Figure 3D As shown, a fourth dielectric layer 310 is formed, which covers the top surface and sidewalls of the second dielectric layer 308 and the third dielectric layer 309. Exemplarily, the material of the second dielectric layer is the same as that of the fourth dielectric layer, but different from the materials of the first and third dielectric layers. The material of the fourth dielectric layer includes, but is not limited to, silicon nitride, and the materials of the first and third dielectric layers can be the same or different.
[0042] For example, the thickness of the first dielectric layer ranges from 500 angstroms to 1500 angstroms, for example, the thickness of the first dielectric layer is 500 angstroms, 1000 angstroms, or 1500 angstroms; the thickness of the second dielectric layer ranges from 100 angstroms to 1000 angstroms, for example, the thickness of the second dielectric layer is 100 angstroms, 500 angstroms, or 1000 angstroms; the thickness of the third dielectric layer ranges from 100 angstroms to 1000 angstroms, for example, the thickness of the third dielectric layer is 100 angstroms, 500 angstroms, or 1000 angstroms; the thickness of the fourth dielectric layer ranges from 100 angstroms to 1000 angstroms, for example, the thickness of the fourth dielectric layer is 100 angstroms, 500 angstroms, or 1000 angstroms.
[0043] Next, as Figure 3E As shown, a patterned mask layer 311 is formed on the fourth dielectric layer 310. The patterned mask layer 311 at least covers the fourth dielectric layer 310 in the first contact hole region and a portion of the top surface of the adjacent gate structure 301. For example, the patterned mask layer 311 at least covers the fourth dielectric layer 310 on a portion of the drain region of the first contact hole region and a portion of the top surface of the adjacent gate structure 301. Exemplarily, the patterned mask layer 311 includes a photoresist layer or a hard mask layer. Next, using the patterned mask layer 311 as a mask, a portion of the fourth dielectric layer 310 is etched using, for example, a dry etching process to expose a portion of the third dielectric layer 309, for example, exposing the sidewalls of the third dielectric layer 309 (e.g., exposing the end regions perpendicular to the substrate extension direction and perpendicular to the extension direction of the gate structure 301).
[0044] Next, as Figure 3FAs shown, a process such as wet etching is used to remove the third dielectric layer 309 to form a cavity 312 between the second dielectric layer 308 and the fourth dielectric layer 310. The orthographic projection of the cavity 312 on the substrate is located within the orthographic projection of the subsequently formed first contact hole on the substrate.
[0045] Next, as Figure 3G As shown, using a patterned mask layer 311 as a mask, a process such as dry etching is employed to etch the first dielectric layer 307, the second dielectric layer 308, and the remaining fourth dielectric layer 310 (if the fourth dielectric layer 310 was not completely etched away in the previous steps) to form a first barrier layer 313 located on a portion of the drain region 303 in the first contact hole region and a portion of the top surface of the gate structure 301, and a second barrier layer 314 located on the first barrier layer 313. The first barrier layer 313 includes the etched first dielectric layer 307, and the second barrier layer 314 includes the etched second dielectric layer 308 and the etched fourth dielectric layer 310. At this time, the cavity 312 is located between the second dielectric layer 308 and the fourth dielectric layer 310, that is, the cavity 312 is located in the second barrier layer 314.
[0046] Next, as Figure 3H As shown, the patterned mask layer is removed.
[0047] Thus, a silicide barrier layer is formed, which extends from the active region to a portion of the top surface of the adjacent gate structure. The silicide barrier layer includes a cavity, the orthographic projection of which onto the substrate lies within the orthographic projection of the subsequently formed first contact hole onto the substrate.
[0048] Next, continue to refer to Figure 2 Step S3 is executed to form an interlayer dielectric layer that covers the silicide barrier layer and the exposed areas of the semiconductor structure.
[0049] For example, such as Figure 3I As shown, an interlayer dielectric layer 315 is formed using, for example, a chemical vapor deposition process. The interlayer dielectric layer 315 covers the silicide barrier layer and the areas where the semiconductor structure is exposed.
[0050] Next, continue to refer to Figure 2 Step S4 is executed to etch the interlayer dielectric layer and a portion of the silicide barrier layer to form a first contact hole that exposes a portion of the remaining silicide barrier layer.
[0051] For example, such as Figure 3JAs shown, the interlayer dielectric layer 315 and the second barrier layer 314 are etched using an etching process such as dry etching and the etching stops at the first barrier layer 313, forming a first contact hole 316 that exposes a portion of the first barrier layer 313. The bottom exposed portion of the first contact hole 316 is located above the active region and on the adjacent sidewall 3012 of the first barrier layer 313. After the first contact hole 316 is filled with metal material, a first contact plug is formed. The first contact hole can be located in the DMOS region and serve as a field plate contact hole for the DMOS device to form a field plate.
[0052] For example, while forming the first contact hole 316, a second contact hole 317 is simultaneously formed, exposing a portion of the surface of the active region and a portion of the top surface of the adjacent gate structure 301. For instance, the first contact hole 316 and the second contact hole 317 can be formed in the same etching process. The bottom of the second contact hole 317 exposes a portion of the active region and a portion of the top surface of the adjacent gate structure 301. The first contact hole 316 and the second contact hole 317 are not connected. Both the first contact hole 316 and the second contact hole 317 can be filled with a conductive material, such as a metal material, to form a first contact plug and a second contact plug, respectively. Optionally, the metal material can be at least one of copper, aluminum, tungsten, etc. The second contact hole can be a shared contact hole distributed in the SRAM region. The shared contact hole can be used to connect the gate and its adjacent active region, such as the source region, and to connect to external circuitry.
[0053] It should be noted that the first contact hole is usually located in the DMOS region, and the silicide barrier layer including the cavity is located in the region corresponding to the first contact hole. The second contact hole is usually distributed in the SRAM region. In order to illustrate the first contact hole and the second contact hole at the same time, the schematic diagrams show the first contact hole and the second contact hole as being located on the same gate side. However, in reality, the two types of contact holes are used on different devices, and the first contact hole and the second contact hole are located on different gate sides.
[0054] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.
[0055] The semiconductor device manufacturing method of this application embodiment forms a cavity in the silicide barrier layer, and the position of the cavity corresponds to the first contact hole to be formed subsequently. Instead of adjusting the etching amount during the etching of the first contact hole by simply adjusting the thickness of the silicide barrier layer, the etching amount during the etching of the first contact hole is adjusted by the cavity. This avoids increasing the overall thickness of the interlayer dielectric layer while making it easier to simultaneously address the etching of the first contact hole (e.g., field plate contact hole) and the second contact hole (e.g., shared contact hole), thereby reducing the difficulty of developing the etching process for the contact hole.
[0056] This application also provides a semiconductor device, which is manufactured using the above-described semiconductor device manufacturing method.
[0057] like Figure 4A and Figure 4B As shown, Figure 4A It is a cross-sectional view of a semiconductor device manufactured using related technologies. Figure 4B This is a cross-sectional view of a semiconductor device manufactured using the manufacturing method described in the embodiments of this application. Figure 4B As can be seen from the structure within the ellipse A shown, in this embodiment of the application, the first barrier layer 313 and the second barrier layer 314 extend from the active region to a portion of the top surface of the adjacent gate structure 301, and a cavity 312 is formed in the second barrier layer 314, and as... Figure 4A As shown, in related technologies, there is no cavity between the first barrier layer 313 and the second barrier layer 314, making it difficult to effectively control the amount of etching of the second barrier layer 314 when forming the first contact hole, making it difficult to simultaneously achieve the etching of the first contact hole and the second contact hole.
[0058] In addition, such as Figure 5A and Figure 5B As shown, Figure 5A The leakage current distribution statistics of a semiconductor device are shown after contact holes are formed using an etching method based on relevant technologies. Figure 5B This paper illustrates the statistical analysis of leakage current distribution in a semiconductor device after forming contact holes using the manufacturing method described in this application. Figure 5A and Figure 5B As can be seen from the comparison, the semiconductor devices manufactured by the related technology have high leakage current. The semiconductor devices manufactured by the manufacturing method of the present application embodiment can significantly reduce leakage current, thereby effectively improving the yield of semiconductor devices.
[0059] Therefore, the semiconductor device of this application embodiment has the beneficial effects of the above-described semiconductor device manufacturing method. That is, the semiconductor device of this application embodiment forms a cavity in the silicide barrier layer, and the position of the cavity corresponds to the first contact hole to be formed subsequently. Instead of simply adjusting the thickness of the silicide barrier layer to adjust the etching amount during the etching of the first contact hole, the etching amount during the etching of the first contact hole is adjusted by the cavity. This avoids increasing the thickness of the interlayer dielectric layer while making it easier to balance the etching of the first contact hole (e.g., field plate contact hole) and the etching of the second contact hole (e.g., shared contact hole), thereby reducing the difficulty of developing the etching process for the contact hole. In addition, the leakage current of the semiconductor device of this application embodiment is significantly reduced, thereby improving the yield of the semiconductor device.
[0060] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A semiconductor structure is provided, the semiconductor structure including a substrate, an active region formed therein, and a gate structure formed on the active region; A silicide barrier layer is formed, the silicide barrier layer extending from the active region to a portion of the top surface of the adjacent gate structure, wherein the silicide barrier layer includes a cavity, the orthographic projection of the cavity on the substrate being located within the orthographic projection of the subsequently formed first contact hole on the substrate; An interlayer dielectric layer is formed, which covers the silicide barrier layer and the exposed areas of the semiconductor structure; The interlayer dielectric layer and a portion of the silicide barrier layer are etched to form a first contact hole that exposes a portion of the remaining silicide barrier layer.
2. The manufacturing method as described in claim 1, characterized in that, A second contact hole is formed simultaneously with the formation of the first contact hole, wherein the second contact hole exposes a portion of the surface of the active region and a portion of the top surface of the gate structure.
3. The manufacturing method as described in claim 1, characterized in that, The silicide barrier layer includes a first barrier layer on the substrate and a second barrier layer on the first barrier layer, and the cavity is located in the second barrier layer.
4. The manufacturing method as described in claim 3, characterized in that, The method for forming the silicide barrier layer includes: A first dielectric layer is formed on the substrate, the first dielectric layer covering the surface of the substrate and conformally covering the gate structure; A second dielectric layer is formed covering the first dielectric layer; A third dielectric layer is formed on the second dielectric layer at least in the first contact hole region; A fourth dielectric layer is formed, which covers the top surface and sidewalls of the second dielectric layer and the third dielectric layer; At least a portion of the fourth dielectric layer is removed to expose a portion of the third dielectric layer; Remove the third dielectric layer to form the cavity between the second dielectric layer and the fourth dielectric layer; The first dielectric layer and the second dielectric layer are etched to form a first barrier layer located in the first contact hole region and a portion of the top surface of the gate structure, and a second barrier layer located on the first barrier layer.
5. The manufacturing method as described in claim 4, characterized in that, The second dielectric layer and the fourth dielectric layer are made of the same material, but are made of a different material than the first dielectric layer and the third dielectric layer.
6. The manufacturing method as described in claim 5, characterized in that, The first dielectric layer is made of silicon oxide, and the second dielectric layer and / or the fourth dielectric layer is made of silicon nitride.
7. The manufacturing method as described in claim 4, characterized in that, The removal of the third dielectric layer to form a cavity between the second dielectric layer and the fourth dielectric layer includes: removing the third dielectric layer using a wet etching process.
8. The manufacturing method as described in claim 4, characterized in that, The thickness of the first dielectric layer ranges from 500 angstroms to 1500 angstroms, the thickness of the second dielectric layer ranges from 100 angstroms to 1000 angstroms, the thickness of the third dielectric layer ranges from 100 angstroms to 1000 angstroms, and the thickness of the fourth dielectric layer ranges from 100 angstroms to 1000 angstroms.
9. The manufacturing method as described in claim 4, characterized in that, The removal of at least a portion of the fourth dielectric layer to expose a portion of the third dielectric layer includes: A patterned mask layer is formed on the fourth dielectric layer, the patterned mask layer at least covering the fourth dielectric layer of the first contact hole region; Using the patterned mask layer as a mask, the fourth dielectric layer is etched to expose a portion of the third dielectric layer.
10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the manufacturing method described in any one of claims 1-9.