Integrated circuit structure with uniform grid metal gate and trench contact footprint filled with backside trench contact

Abstract

Integrated circuit structures with uniform grid metal gates and trench contact placeholder cutouts filled with backside trench contact fill are described. The integrated circuit structures include vertical stacks or fins of horizontal nanowires. A gate electrode is over the vertical stacks or fins of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure being laterally spaced apart from and parallel to the first dielectric cut plug structure, wherein the conductive trench contact includes a conductive fill that is separated from the first and second dielectric cut plug structures by a liner.

Description

Background Technology

[0001] Over the past few decades, feature scaling in integrated circuits has been a driving force behind the continued growth of the semiconductor industry. Scaling to increasingly smaller features allows for increased density of functional units within the limited footprint of a semiconductor chip. For example, shrinking transistor size allows for the integration of an increased number of memory or logic devices on a single chip, facilitating the manufacture of products with increased capacity. However, the pursuit of ever-increasing capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly important.

[0002] In the fabrication of integrated circuit devices, multi-gate transistors (e.g., tri-gate transistors) have become increasingly prevalent as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator (SiI) substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and the ability to implement less complex tri-gate fabrication processes. On the other hand, as microelectronic device dimensions scale down to below the 10-nanometer (nm) node, maintaining improved mobility and short-channel control presents challenges in device fabrication. Nanowires used to fabricate devices offer improved short-channel control.

[0003] However, scaling up multi-gate and nanowire transistors is not without its consequences. As the size of these basic building blocks of microelectronic circuit systems decreases, and as the absolute number of basic building blocks fabricated in a given area increases, limitations on the photolithography processes used to pattern these building blocks become unavoidable. In particular, there may be a trade-off between the minimum size (critical size) of a feature patterned in a semiconductor stack and the spacing between such features. Attached Figure Description

[0004] Figures 1A-1D An angled cross-sectional view is shown, illustrating various operations in a method of manufacturing an integrated circuit structure having uniform grid metal gates and trench contact cutouts according to embodiments of the present disclosure.

[0005] Figure 1E-Figure 1J An angled cross-sectional view is shown of various operations in a method of manufacturing an integrated circuit structure having a uniform grid metal gate and a trench contact berth cutout filled with a rear trench contact according to an embodiment of the present disclosure.

[0006] Figure 2A A cross-sectional view of an integrated circuit structure having fins and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0007] Figure 2BA cross-sectional view of an integrated circuit structure having fins and a cut-metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0008] Figure 3A A cross-sectional view of an integrated circuit structure having nanowires and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0009] Figure 3B A cross-sectional view of an integrated circuit structure having nanowires and diced metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0010] Figure 4A A cross-sectional view of an integrated circuit structure having nanowires and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0011] Figure 4B A cross-sectional view of an integrated circuit structure having nanowires and diced metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0012] Figures 5A-5C A plan view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown.

[0013] Figures 6A-6C A cross-sectional view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown.

[0014] Figures 7A-7J Cross-sectional views of various operations in a method of manufacturing a gate-all-around integrated circuit structure according to embodiments of the present disclosure are shown.

[0015] Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure is shown.

[0016] Figure 9 A cross-sectional view through nanowires and fins is shown of a non-end cap architecture (left-hand side (a)) according to an embodiment of the present disclosure relative to a self-aligned gate end cap (SAGE) architecture (right-hand side (b)).

[0017] Figure 10 Cross-sectional views are shown of various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a fully surrounding gate device, according to embodiments of the present disclosure.

[0018] Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0019] Figure 11B An embodiment according to this disclosure is shown. Figure 11AA cross-sectional view of the source or drain of a nanowire-based integrated circuit structure taken along the a-a' axis.

[0020] Figure 11C An embodiment according to this disclosure is shown. Figure 11A A cross-sectional channel view of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0021] Figure 12 A computing device according to one embodiment of the present disclosure is shown.

[0022] Figure 13 An intermediary layer including one or more embodiments of the present disclosure is shown. Detailed Implementation

[0023] An integrated circuit structure having a uniform grid metal gate and trench contact footprint notch is described, as well as a method for manufacturing an integrated circuit structure having a uniform grid metal gate and trench contact footprint notch. In the following description, numerous specific details, such as specific integration and material systems, are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features (e.g., integrated circuit design layouts) have not been described in detail to avoid unnecessarily obscuring embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0024] For reference purposes only, certain terms may also be used in the following description and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to orientations in the referenced figures. Terms such as “front,” “rear,” “back,” and “side” describe the orientation and / or position of portions of a component within a consistent but arbitrary frame of reference, which are readily apparent from the text describing the component under discussion and the associated figures. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0025] The embodiments described herein are applicable to front-end process (FEOL) semiconductor fabrication and structures. FEOL is the first part of integrated circuit (IC) manufacturing, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses all processes up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0026] The embodiments described herein are applicable to back-end process (BEOL) semiconductor fabrication and structures. BEOL is the second part of IC manufacturing, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding areas for chip-to-package connections. During the fabrication phase of the BEOL, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0027] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme can be illustrated using the FEOL processing scenario, such a method can also be applied to BEOL processing. Similarly, although an exemplary processing scheme can be illustrated using the BEOL processing scenario, such a method can also be applied to FEOL processing.

[0028] One or more embodiments described herein relate to an integrated circuit structure fabricated as a uniform grid of metal gates and trench contact berths, which may be referred to as a pixel-first structure. One or more embodiments described herein relate to a pixel-first structure fabricated using a rear trench contact fill. One or more embodiments described herein relate to a full-around gate device fabricated using multiple common and extended metal gate cutout (MGC) trench contact (TCN) cutout plug structures. It should be understood that, unless otherwise stated, references to nanowires herein may refer to nanowires, nanoribbons, or nanosheets. One or more embodiments described herein relate to a FinFET structure fabricated using multiple common and extended metal gate cutout (MGC) trench contact (TCN) cutout plug structures. In the embodiments, a pixel-first method is described that may be more robust than pixel-first methods involving direct trench contact methods.

[0029] To provide background, it may be advantageous to simplify the trench contact and polysilicon notch (gate notch) processes, for example, to improve device performance and reduce process variations.

[0030] According to one or more embodiments of this disclosure, a metal gate process is performed, and a trench contact process is performed without the need for plugs. All possible trench contact plugs and gate cutout plugs (as a uniform dielectric cutout plug) are then generated using a single, "infinitely" long grid. The resulting structure may be referred to as a pixel structure. The pixel structure may then undergo partial plug removal to effectively reconnect or re-connect the cutout gate portions and / or reconnect the cutout contact portions.

[0031] As an example processing scheme, Figures 1A-1D An angled cross-sectional view is shown of various operations in a method of manufacturing an integrated circuit structure having uniform grid metal gates and trench contact cutouts, according to an embodiment of the present disclosure.

[0032] refer to Figure 1A A start-up structure 100 is shown prior to the nanowire release and gate replacement process. The start-up structure 100 includes sub-fins 104 extending from a substrate 102, such as silicon sub-fins extending from a silicon substrate. The sub-fins 104 extend through a shallow trench isolation (STI) structure 106, such as a silicon oxide or silicon dioxide trench isolation structure. One or more stacks of horizontal nanowires 108 (e.g., stacks of horizontal silicon nanowires) lie on the corresponding sub-fins 104. At this stage, a sacrificial intermediary layer 110 (e.g., a sacrificial silicon-germanium intermediary layer) alternates with the horizontal nanowires 108 in the nanowire stacks. A sacrificial gate oxide 112 (e.g., a silicon oxide or silicon dioxide sacrificial gate oxide) lies on the stacks of horizontal silicon nanowires 108. A sacrificial gate structure 114 (e.g., a polysilicon sacrificial gate structure) lies on the sacrificial gate oxide 112 and on the channel regions of the stacks of horizontal nanowires 108. As depicted, a hard mask layer 116 (e.g., a silicon nitride hard mask layer) may be included on the sacrificial gate structure 114. A gate spacer forming material 118 (e.g., a silicon nitride gate spacer forming material 118) is included on the sacrificial gate structure 114 and along the sidewalls of the sacrificial gate structure 114.

[0033] Refer again Figure 1A The epitaxial source or drain structure 120 (e.g., epitaxial silicon or epitaxial silicon-germanium source or drain structure) is located at the end of the stack of horizontal nanowires 108 between adjacent sacrificial gate structures 114. An internal gate spacer 126 (e.g., an internal silicon nitride internal gate spacer 126) can be formed by recessing the sacrificial intercalary layer 110 and depositing the internal gate spacer material prior to forming the epitaxial source or drain structure 120. The epitaxial source or drain structure 120 can be formed on top of the lower spacer recess filler 122 (e.g., a silicon nitride spacer filler), which can be formed simultaneously with the internal gate spacer 126 and / or the gate spacer forming material 118. A contact insulator structure 128 (e.g., a silicon oxide or silicon dioxide structure) is included on top of the epitaxial source or drain structure 120 and can occupy the location where the conductive trench contact is ultimately formed.

[0034] refer to Figure 1BThe initial structure 100 undergoes a replacement gate and nanowire release process. Specifically, structure 100 is planarized and / or etched to expose the sacrificial gate structure 114. Planarization may remove the hard mask layer 116, form the gate spacer 118A from the gate spacer forming material 118, and form a planarized contact insulator structure 128A. Selective etching is then used to remove the sacrificial gate structure 114 and the sacrificial gate oxide 112. Selective etching is then used to remove the sacrificial intermediary layer 110. A permanent gate dielectric structure 132 (e.g., a gate dielectric structure including a high-k dielectric layer) is then formed in the resulting trenches and cavities (including around the channel regions of each nanowire in the nanowires 108). A permanent gate electrode 134 (e.g., a gate electrode including a metal) is formed on top of the permanent gate dielectric structure 132 (including at locations around the channel regions of the nanowires 108). For example, a gate insulating capping layer 136 (e.g., a silicon nitride capping layer) can be formed by recessing the gate structure and backfilling it with a dielectric on the resulting permanent gate electrode structure 134.

[0035] refer to Figure 1C and Figure 1D The cross-sectional view of the exposed trench contact part is adopted. Figure 1C ) and cross-sectional view of the exposed gate structure ( Figure 1D The pixel structure 149 is shown. The pixel structure 149 is formed by first replacing the planarized contact insulator structure 128A with a trench contact material. At this stage, the trench contact material is “infinite” along each contact trench, extending over all source / drain structures along a given trench contact line, effectively shorting all trench contacts along a single trench contact line. Similarly, at this stage, the gate electrode material is “infinite” along each gate trench, extending over all nanowire stack channel regions along a given gate line, effectively shorting all gates along a single gate line contact line. At this stage, the gate insulating cap layer 136 may have been removed.

[0036] Subsequently, non-selective cuts are made along a direction orthogonal to the gate and trench contact lines, effectively cutting and isolating all trench contacts along a single trench contact line and cutting and isolating all gate electrodes along a single gate line. The cuts are then filled with dielectric plugs 148 extending through all trench contact lines and all gate lines. The resulting “pixel” structure 149 includes multiple isolated / cut trench contact structures 140, which may include insulating caps 142 located thereon. The trench contact structures 140 may contact a silicide layer 146 located on the corresponding epitaxial source or drain structure 120 at locations exposed by the etch stop layer 144. The resulting “pixel” structure 149 also includes multiple isolated / cut gate structures, for example, structures including cut gate dielectrics 132A and 134A.

[0037] Refer again Figure 1C and Figure 1D According to embodiments of the present disclosure, the integrated circuit structure 149 includes a vertical stack of horizontal nanowires 108. A gate electrode 134A is located above the vertical stack of horizontal nanowires 108. A conductive trench contact 140 is adjacent to the gate electrode 134A. A dielectric sidewall spacer 118A is located between the gate electrode 134A and the conductive trench contact 140. A first dielectric notch plug structure 148 extends through the gate electrode 134A, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. A second dielectric notch plug structure 148 extends through the gate electrode 140, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. The second dielectric notch plug structure 148 is laterally spaced from and parallel to the first dielectric notch plug structure 148.

[0038] It should be understood that pixel structure 149 may then undergo selective reconnection or re-linking of the respective trench contact structures in the isolated / cut trench contact structure 140 and / or selective reconnection or re-linking of the respective gate structures in the isolated / cut gate structures 132A / 134A. For example, one or more embodiments described herein are for integrated circuit structures manufactured using trench contact (TCN) plug removal and / or metal gate cut (MGC) plug removal (e.g., removal as a selective portion of a dielectric cut plug structure). Conductive bonding or linking structures are then formed in the grooves formed by such removal.

[0039] The above method can be considered a pixel-last method because both the gate and the trench contact are cut after formation. In another embodiment, a pixel-first method is implemented, wherein the metal gate, rather than the occupying trench contact, is cut before the final trench contact is formed. In this embodiment, a pixel-first method involving post-contact filling is described, which can be more robust than pixel-first methods involving direct trench contact.

[0040] As an example processing scheme, Figure 1E-Figure 1J Angled cross-sectional views are shown of various operations in a method of manufacturing an integrated circuit structure having a uniform grid metal gate and trench contact berth cutouts filled with rear trench contacts, according to embodiments of the present disclosure. It should be understood that the described and illustrated embodiments are applicable not only to stacks of nanowires, nanoribbons, or nanosheets, but also to fin structures.

[0041] refer to Figure 1E The initial structure 150 includes a stack of alternating nanowires 156 and intervening sacrificial layers 158 on corresponding sub-fins 152 separated by an intervening isolation structure 154. The sacrificial gate dielectric layer 160 is conformal to the stack of alternating nanowires 156 and intervening sacrificial layers 158 and the isolation structure 154.

[0042] refer to Figure 1F ,exist Figure 1E A dummy gate structure is formed on top of the structure, for example, a structure including a polysilicon gate 162 and a silicon nitride hard mask 164. Then, the dummy gate structure 162 / 164 is used as a mask to pattern the sacrificial gate dielectric layer 160 to form a patterned sacrificial gate dielectric layer 160A.

[0043] refer to Figure 1G ,exist Figure 1F A gate spacer layer 166 is formed over the structure. The region of the stack of alternating nanowires 156 and intervening sacrificial layers 158 exposed by the gate spacer layer 166 is removed (leaving sub-fin portions 152A), and then the alternating nanowires 156 are laterally recessed. An inner gate spacer can then be formed, with its residue 168 as shown. An epitaxial source or drain structure 170 is then grown at the ends of the remaining portions of the nanowires 156. An etch stop layer 172 is then formed over the epitaxial source or drain structure 170. A dielectric occupancy structure 174 is formed over the epitaxial source or drain structure 170.

[0044] refer to Figure 1H From the perspective of the gate ( Figure 1G(Within the page) The structure is shown after the replacement of the metal gate process but before the trench contact metallization process. The initial structure includes a gate dielectric layer 176, an "infinite" metal gate electrode 178, a gate spacer 166, and an "infinite" trench contact occupancy dielectric layer 174.

[0045] refer to Figure 1I From the perspective of source or drain ( Figure 1H The structure is shown outside the page. This structure is what makes... Figure 1H The structure undergoes a masking and etching process that cuts an “infinite” number of gate electrodes 178, an “infinite” number of trench contact occupancy dielectric layers 174, a gate spacer layer 166, and a gate dielectric layer 176 to form a gate electrode 178A, a trench contact occupancy dielectric structure 168A, a gate spacer 166A, and a gate dielectric layer 176A. A dielectric notch plug structure 180 (e.g., SiN, SiON, SiO, SiO2, and / or SiC dielectric plug) is formed in the notch, effectively cutting and completely isolating the location of the gate electrode 178A (as a gate notch plug portion), and extending into and completely isolating the trench contact occupancy dielectric structure 166A, for example, as shown in a pixel structure that does not yet include trench contact metallization.

[0046] refer to Figure 1JThe trench contact portion occupies the dielectric structure 166A. A silicide layer 184 can be formed on the resulting exposed epitaxial source or drain structure 170A. A conductive material or a stack of conductive materials is formed in the resulting trench to form a conductive trench contact 182. In an embodiment, each conductive trench contact 182 includes a conductive filler and a conductive barrier layer. In one such embodiment, the conductive barrier layer or liner of the trench contact 182 (instead of the conductive trench contact filler) is in physical contact with the sidewalls of the dielectric notch plug structure 180, which distinguishes this structure from a notch-shaped structure formed in the final pixel process flow after the trench contact material is formed. For example, in one embodiment, the conductive trench contact (center 182) includes conductive filler separated from the first and second dielectric notch plug structures 180 by a liner, for example, at location 192. In one embodiment, as shown, a residual etch stop layer portion 194 extends over the top of the epitaxial source or drain structure and may even extend to the top of the structure. In this embodiment, regardless of whether the residual etch stop layer portion 194 extends to the top of the structure, the conductive trench contact filler of the trench contact portion 182 (e.g., at location 192) does not physically contact the sidewall of the dielectric cut-out plug structure 180. If the residual etch stop layer portion 194 extends to the top of the structure, the conductive filler is separated from the first and second dielectric cut-out plug structures 180 by either the liner or both the liner and the residual etch stop layer portion 194.

[0047] Referring again to structure 190, in one embodiment, the liner surrounds the cut-out wall. In one embodiment, the conductive trench contact 182 has a tapered contact etching profile because this profile is defined by the etched via in the trench contact occupies the dielectric structure 166A. In one embodiment, the etching of the trench contact occupies the dielectric structure 166A has a V-shape, rather than completely surrounding the EPI (due to the lack of a wall before etching in the pixel-final approach).

[0048] It should be understood that pixel structure 190 may then undergo selective re-bonding / reconnection of the respective isolation / cut trench contact structures in isolation / cut trench contact structure 182 and / or selective re-bonding / reconnection of the respective isolation / cut gate structures in isolation / cut gate structure 178A. For example, one or more embodiments described herein are for integrated circuit structures manufactured using trench contact portion (TCN) plug removal and / or metal gate cut (MGC) plug removal (e.g., removal as a selective portion of a dielectric cut plug structure). Conductive bonding or linking structures are then formed in the grooves formed by such removal.

[0049] On the other hand, to reduce cell height in future or scaled-up technology nodes, both gate cap and gate cutout sizes need to be reduced. Gate cutouts prior to gate metal filling can limit the effective cap size available for the work function, and metal-filling capability can be challenged in smaller spaces. The defects are exacerbated for any gate end-to-end mismatch that results in even smaller cap space.

[0050] According to one or more embodiments of this disclosure, to address the problems outlined above, a metal gate notching process is performed after the gate dielectric and work function metal deposition and patterning are completed, and this metal gate notching process can be used in conjunction with the above. Figures 1A-1J Described gate / contact plug.

[0051] Advantages of implementing the methods described herein can include the so-called "plug-last" method, which avoids depositing a gate dielectric layer (e.g., a high-k gate dielectric layer) on the gate plug sidewalls, thereby effectively saving additional space for work function metal deposition. In contrast, during the so-called conventional "plug-first" method, the metal gate fill material can be sandwiched between the plug and the fin. In the latter approach, the space for metal filling may be narrower due to plug mismatch and may result in voids during metal filling. In the embodiments described herein, by using the "plug-last" method, work function metal deposition can be seamless (e.g., void-free).

[0052] According to one or more embodiments of this disclosure, an integrated circuit structure has a clean interface between the gate plug dielectric and the gate metal. It should be understood that many embodiments can benefit from the methods described herein (e.g., the plug-last method). For example, the following is combined with... Figure 2B To describe the metal gate cutout on a fin field-effect transistor device. For example, the following combination Figure 3B and Figure 4B As described, a metal gate notch scheme can be implemented for a gate all-around (GAA) device. Furthermore, the metal gate notch and plug formation may appear different based on the initial structure. For example, the plug may be located on a shallow trench isolation (STI) structure, such as in combination with... Figure 2B and Figure 3B As described; or it may be located on a prefabricated gate wall made of dielectric material, for example, in combination Figure 4B The described metal gate notching method can have selectivity for the gate spacer body dielectric, for example, by combining... Figure 5B and Figure 6B As described; or it may not be selective for the gate spacer material, for example, combined with Figure 5C and Figure 6CAs described, non-selective metal gate notch embodiments may require alternative contact metal solutions to accommodate a dielectric plug between the epitaxial source / drain. Plug etching selectivity for the epitaxial source / drain material is optional. However, in one embodiment, if the epitaxial source / drain is exposed to plug etching (e.g., due to device size), the etching can anisotropically trim the source / drain, as described below. Figure 5C As described, such a method can be implemented to achieve a tight end cap spacing.

[0053] Dielectric gate plugs for fin field-effect transistor devices can be manufactured. As a comparative example, Figure 2A A cross-sectional view of an integrated circuit structure having fins and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown. Figure 2B A cross-sectional view of an integrated circuit structure having fins and a cut-metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0054] refer to Figure 2A The integrated circuit structure 200 includes a fin 202 having a portion protruding above a shallow trench isolation (STI) structure 204. A gate dielectric material layer 206 (e.g., a high-k gate dielectric layer) is above the protruding portion of the fin 202 and above the STI structure 204. It should be understood that, although not shown, an oxide portion of the fin 202 may be between the protruding portion of the fin 202 and the gate dielectric material layer 206, and may be included together with the gate dielectric material layer 206 to form a gate dielectric structure. As shown, a conductive gate layer 208 (e.g., a work function metal layer) is above the gate dielectric material layer 206, and may be directly on the gate dielectric material layer 206. As shown, a conductive gate fill material 210 is above the conductive gate layer 208, and may be directly on the conductive gate layer 208. A dielectric gate cap 212 is on the conductive gate fill material 210. The dielectric gate plug 214 is laterally spaced from the fin 202 and is located on the STI structure 204. The gate dielectric material layer 206 and the conductive gate layer 208 are located along the sidewalls of the dielectric gate plug 214.

[0055] refer to Figure 2BThe integrated circuit structure 250 includes a fin 252 having a portion protruding above a shallow trench isolation (STI) structure 254. A gate dielectric material layer 256 (e.g., a high-k gate dielectric layer) is above the protruding portion of the fin 252 and above the STI structure 254. It should be understood that, although not shown, an oxide portion of the fin 252 may be between the protruding portion of the fin 252 and the gate dielectric material layer 256, and may be included together with the gate dielectric material layer 256 to form a gate dielectric structure. As shown, a conductive gate layer 258 (e.g., a work function metal layer) is above the gate dielectric material layer 256, and may be directly on the gate dielectric material layer 256. As shown, a conductive gate fill material 260 is above the conductive gate layer 258, and may be directly on the conductive gate layer 258. A dielectric gate cap 262 is on the conductive gate fill material 260.

[0056] In one embodiment, the dielectric gate plug 264 is laterally spaced from the fin 252 and is on but does not penetrate the STI structure 254. As used throughout this disclosure, a dielectric plug referred to as “on but not through the STI structure” can refer to a dielectric plug located on the top or uppermost surface of the STI, or it can refer to a plug that extends into but does not penetrate the STI. In other embodiments, the plug described herein may extend completely through or penetrate the STI.

[0057] In this embodiment, the gate dielectric material layer 256 and the conductive gate layer 258 do not lie along the sides of the dielectric gate plug 264. Instead, the conductive gate fill material 260 contacts the sides of the dielectric gate plug 264. As a result, the region between the dielectric gate plug 264 and the fin 252 comprises only one layer of gate dielectric material 256 and only one layer of conductive gate layer 258, thereby alleviating the space constraints in such a small area of ​​structure 250. Alleviating space constraints can improve metal filling and / or facilitate the patterning of multiple VTs.

[0058] Refer again Figure 2B In one embodiment, the dielectric gate plug 264 is formed after the formation of the gate dielectric material layer 256, the conductive gate layer 258, and the conductive gate fill material 260. As a result, the gate dielectric material layer 256 and the conductive gate layer 258 are not formed along the sidewalls of the dielectric gate plug 264. In one embodiment, as shown, the dielectric gate plug 264 has an uppermost surface coplanar with the uppermost surface of the dielectric gate cap 262. In another embodiment not depicted, the dielectric gate cap 262 is not included, and the dielectric gate plug 264 has, for example, an uppermost surface coplanar with the uppermost surface of the conductive gate fill material 260 along a plane 280.

[0059] Dielectric gate plugs can be used to fabricate nanowire devices. As a comparative example... Figure 3A A cross-sectional view of an integrated circuit structure having nanowires and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown. Figure 3B A cross-sectional view of an integrated circuit structure having nanowires and diced metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0060] refer to Figure 3A The integrated circuit structure 300 includes a sub-fin 302 having a portion protruding above a shallow trench isolation (STI) structure 304. Multiple horizontally stacked nanowires 305 are on the sub-fin 302. A gate dielectric material layer 306 (e.g., a high-k gate dielectric layer) is on the protruding portion of the sub-fin 302, on the STI structure 304, and surrounding the horizontally stacked nanowires 305. It should be understood that, although not shown, oxidized portions of the sub-fin 302 and the horizontally stacked nanowires 305 may be included between the protruding portion of the sub-fin 302 and the gate dielectric material layer 306, and between the horizontally stacked nanowires 305 and the gate dielectric material layer 306, and may be included together with the gate dielectric material layer 306 to form a gate dielectric structure. As shown, a conductive gate layer 308 (e.g., a work function metal layer) is on the gate dielectric material layer 306 and may be directly on the gate dielectric material layer 306. As shown in the figure, the conductive gate filler 310 is on top of the conductive gate layer 308 and can be directly on the conductive gate layer 308. The dielectric gate cap 312 is on the conductive gate filler 310. The dielectric gate plug 314 is laterally spaced from the sub-fins 302 and multiple horizontally stacked nanowires 305, and is on the STI structure 304. The gate dielectric material layer 306 and the conductive gate layer 308 are along the side of the dielectric gate plug 314.

[0061] refer to Figure 3BThe integrated circuit structure 350 includes a sub-fin 352 having a portion protruding above a shallow trench isolation (STI) structure 354. Multiple horizontally stacked nanowires 355 are on the sub-fin 352. A gate dielectric material layer 356 (e.g., a high-k gate dielectric layer) is on the protruding portion of the sub-fin 352, on the STI structure 354, and surrounding the horizontally stacked nanowires 355. It should be understood that, although not shown, oxidized portions of the sub-fin 352 may be included between the protruding portion of the sub-fin 352 and the gate dielectric material layer 356, and between the horizontally stacked nanowires 355 and the gate dielectric material layer 356, and may be included together with the gate dielectric material layer 356 to form a gate dielectric structure. As shown, a conductive gate layer 358 (e.g., a work function metal layer) is on the gate dielectric material layer 356 and may be directly on the gate dielectric material layer 356. As shown, the conductive gate filler 360 is on top of the conductive gate layer 358 and can be directly on the conductive gate layer 358. The dielectric gate cap 362 is on the conductive gate filler 360. The dielectric gate plug 364 is laterally spaced from the sub-fins 352 and the plurality of horizontally stacked nanowires 355, and is on the STI structure 354 but does not penetrate the STI structure 354. However, the gate dielectric material layer 356 and the conductive gate layer 358 are not along the sides of the dielectric gate plug 364. Instead, the conductive gate filler 360 contacts the sides of the dielectric gate plug 364. As a result, the region between the dielectric gate plug 364 and the combination of the sub-fins 352 and the plurality of horizontally stacked nanowires 355 includes only one layer of gate dielectric material layer 356 and only one layer of conductive gate layer 358, thereby alleviating the space constraints in such a small region of structure 350.

[0062] Refer again Figure 3B In one embodiment, the dielectric gate plug 364 is formed after the formation of the gate dielectric material layer 356, the conductive gate layer 358, and the conductive gate fill material 360. As a result, the gate dielectric material layer 356 and the conductive gate layer 358 are not formed along the sidewalls of the dielectric gate plug 364. In one embodiment, as shown, the dielectric gate plug 364 has an uppermost surface coplanar with the uppermost surface of the dielectric gate cap 362. In another embodiment not depicted, the dielectric gate cap 362 is not included, and the dielectric gate plug 364 has, for example, an uppermost surface coplanar with the uppermost surface of the conductive gate fill material 360 along a plane 380.

[0063] A dielectric gate plug can be fabricated on the gate end cap wall of a nanowire device. As a comparative example, Figure 4A A cross-sectional view of an integrated circuit structure having nanowires and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown. Figure 4B A cross-sectional view of an integrated circuit structure having nanowires and diced metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0064] refer to Figure 4A The integrated circuit structure 400 includes a sub-fin 402 having a portion protruding above a shallow trench isolation (STI) structure 404. A plurality of horizontally stacked nanowires 405 are situated above the sub-fin 402. A gate cap structure 403 (e.g., a self-aligned gate cap structure) is situated on the STI structure 404 and laterally spaced from the sub-fin 402 and the plurality of horizontally stacked nanowires 405. A gate dielectric material layer 406 (e.g., a high-k gate dielectric layer) is situated above the protruding portion of the sub-fin 402, above the STI structure 404, along the sidewalls of the gate cap structure 403, and surrounding the horizontally stacked nanowires 405. It should be understood that, although not shown, the oxidized portions of the sub-fins 402 and the horizontally stacked nanowires 405 may be included between the protruding portions of the sub-fins 402 and the gate dielectric material layer 406, and between the horizontally stacked nanowires 405 and the gate dielectric material layer 406, and may be included together with the gate dielectric material layer 406 to form a gate dielectric structure. As shown, a conductive gate layer 408 (e.g., a work function metal layer) is on top of the gate dielectric material layer 406, and may be directly on the gate dielectric material layer 406. As shown, a conductive gate fill material 410 is on top of the conductive gate layer 408, and may be directly on the conductive gate layer 408. A dielectric gate cap 412 is on the conductive gate fill material 410. A dielectric gate plug 414 is on the gate end cap structure 403. The gate dielectric material layer 406 and the conductive gate layer 408 are along the side of the dielectric gate plug 414.

[0065] refer to Figure 4BThe integrated circuit structure 450 includes a sub-fin 452 having a portion protruding above a shallow trench isolation (STI) structure 454. A plurality of horizontally stacked nanowires 455 are situated above the sub-fin 452. A gate cap structure 453 (e.g., a self-aligned gate cap structure) is on the STI structure 454 but does not penetrate it, and is laterally spaced from the sub-fin 452 and the plurality of horizontally stacked nanowires 455. A gate dielectric material layer 456 (e.g., a high-k gate dielectric layer) is situated above the protruding portion of the sub-fin 452, above the STI structure 454, along the sidewalls of the gate cap structure 453, and surrounding the horizontally stacked nanowires 455. It should be understood that, although not shown, the oxidized portion of the sub-fin 452 may be included between the protruding portion of the sub-fin 452 and the gate dielectric material layer 456, and between the horizontally stacked nanowires 455 and the gate dielectric material layer 456, and may be included together with the gate dielectric material layer 456 to form a gate dielectric structure. As shown, the conductive gate layer 458 (e.g., a work function metal layer) is on the gate dielectric material layer 456 and may be directly on the gate dielectric material layer 456. As shown, the conductive gate fill material 460 is on the conductive gate layer 458 and may be directly on the conductive gate layer 458. The dielectric gate cap 462 is on the conductive gate fill material 460. The dielectric gate plug 464 is on the gate end cap structure 453. However, the gate dielectric material layer 456 and the conductive gate layer 458 are not along the side of the dielectric gate plug 464. Instead, the conductive gate fill material 460 contacts the side of the dielectric gate plug 464.

[0066] Refer again Figure 4B In one embodiment, the dielectric gate plug 464 is formed after the formation of the gate dielectric material layer 456, the conductive gate layer 458, and the conductive gate fill material 460. As a result, the gate dielectric material layer 456 and the conductive gate layer 458 are not formed along the sidewalls of the dielectric gate plug 464. In one embodiment, as shown, the dielectric gate plug 464 has an uppermost surface coplanar with the uppermost surface of the dielectric gate cap 462. In another embodiment not depicted, the dielectric gate cap 462 is not included, and the dielectric gate plug 464 has, for example, an uppermost surface coplanar with the uppermost surface of the conductive gate fill material 460 along a plane 480.

[0067] On the other hand, selective or non-selective versions of the metal gate cutout can be implemented. As an example, Figures 5A-5C A plan view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 5A This illustrates the conventional "plug-first" method for two gate plugs in adjacent gates. Figure 5BThis illustrates a selective metal gate notching method for two gate plugs in adjacent gates. Figure 5C This illustrates a non-selective metal gate cutting method for a long gate plug on multiple gates.

[0068] refer to Figure 5A The integrated circuit structure 500 includes gate lines between a dielectric spacer 517 and a power or drain contact 518. Each gate line includes a gate dielectric material layer 506, a conductive gate layer 508 (e.g., a work function metal layer), and a conductive gate fill material 510. A dielectric gate plug 514 can separate a portion of the corresponding gate line. The dielectric gate plug 514 contacts the conductive gate layer 508 but not the gate dielectric material layer 506 or the conductive gate fill material 510. Figure 5A The floor plan can correspond to Figure 2A , Figure 3A or Figure 4A The structure in the text. It should be understood that although referred to as the power supply or drain contact 518 above, in the early stages of the process or at other locations in the integrated circuit structure, a placeholder dielectric or dielectric plug may replace the power supply or drain contact 518.

[0069] refer to Figure 5B The integrated circuit structure 550 includes gate lines between a dielectric spacer 567 and a conductive power or drain contact 568. Each gate line includes a gate dielectric material layer 556, a conductive gate layer 558 (e.g., a work function metal layer), and a conductive gate fill material 560. A dielectric gate plug 564 can separate a portion of the corresponding gate line. The dielectric gate plug 564 is in contact with the conductive gate fill material 560. Figure 5B The floor plan can correspond to Figure 2B , Figure 3B or Figure 4B The structure in the text. It should be understood that although referred to as power supply or drain contact 568 above, in the early stages of the process or at other locations in the integrated circuit structure, a placeholder dielectric or dielectric plug may replace power supply or drain contact 568.

[0070] refer to Figure 5CThe integrated circuit structure 570 includes gate lines between a dielectric spacer 587 and a power supply or drain contact 588. Each gate line includes a gate dielectric material layer 576, a conductive gate layer 578 (e.g., a work function metal layer), and a conductive gate fill material 580. Individual dielectric gate plugs 584 can partially separate the gate lines and can extend through the dielectric spacer 587, and even partially or completely into one or more power supply or drain contacts 588. The dielectric gate plugs 584 are in contact with the conductive gate fill material 580. Figure 5C The floor plan can correspond to Figure 2B , Figure 3B or Figure 4B The structure in.

[0071] Refer again Figure 5C It should be understood that although referred to as power or drain contact 588 above, a placeholder dielectric or dielectric plug may replace power or drain contact 588 in the early stages of the process or at other locations in the integrated circuit structure. In an embodiment, the etching used to form the opening in which a single dielectric gate plug 584 is ultimately formed is referred to as non-selective etching. Where power or drain contact 588 has been formed, non-selective etching may etch into the conductive material of power or drain contact 588. In other embodiments, where a placeholder dielectric or dielectric plug replaces power or drain contact 588, non-selective etching may etch into the placeholder dielectric or dielectric plug. In either case, non-selective etching may etch through and potentially separate the epitaxial semiconductor material of the source or drain region formed below the location of power or drain contact 588. Where power or drain contact 588 has been formed, the epitaxial semiconductor material of the source or drain region may include a silicided portion.

[0072] Figures 6A-6C A cross-sectional view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 6A This indicates the conventional "plug first" method. Figure 6B This indicates a selective metal gate cutting method. Figure 6C This indicates a non-selective metal gate cutting method.

[0073] refer to Figure 6A The integrated circuit structure 600 includes a dielectric gate plug 614 between a dielectric spacer 617 and a power supply or drain contact 618. Figure 6A The cross-sectional view can be corresponding to Figure 2A , Figure 3A , Figure 4A or Figure 5A An orthogonal view of the structure in the image.

[0074] refer to Figure 6B The integrated circuit structure 650 includes a dielectric gate plug 664 between a dielectric spacer 667 and a power supply or drain contact 668. Figure 6B The cross-sectional view can be corresponding to Figure 2B , Figure 3B , Figure 4B or Figure 5B An orthogonal view of the structure in the image.

[0075] refer to Figure 6C The integrated circuit structure 670 includes a single dielectric gate plug 684 between a power supply or drain contact 688. The dashed box 690 illustrates... Figure 6B In this case, the corresponding discrete gate plug (e.g., gate plug 664) will be aligned at the desired position. Dashed box 692 shows the alignment position in... Figure 6B In this case, the non-recessed source or drain contact 668 will be aligned at the desired position. The area between dashed boxes 690 and 692 shows the position where... Figure 6B In this case, the dielectric spacer 667 will be in the following position. Figure 6C The cross-sectional view can be corresponding to Figure 2B , Figure 3B , Figure 4B or Figure 5C An orthogonal view of the structure in the image.

[0076] In embodiments, the metal work function can be: (a) the same metal system in NMOS and PMOS, (b) different metal systems between NMOS and PMOS, and / or (c) a single material or multilayer metal (e.g., W, TiN, TixAlyCz, TaN, Mo, MoN). In embodiments, the metal notch etching chemical includes chlorine- or fluorine-containing etchants, which may have additional carbon- or silicon-containing components to provide passivation.

[0077] It should be understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials (including but not limited to Si, SiGe). For example, group III-V materials may be used.

[0078] It should be understood that, in certain embodiments, nanowires or nanoribbons or sacrificial intercalary layers may be made of silicon. As used throughout, a silicon layer can be used to describe a silicon material composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form, and therefore may include very small percentages of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition, or may “contaminate” Si during diffusion during post-deposition processing. Thus, the embodiments for silicon layers described herein may include silicon layers containing relatively small amounts (e.g., “impurity” levels) of non-Si atoms or substances (e.g., Ge, C, or Sn). It should be understood that silicon layers as described herein may be undoped or may be doped with dopant atoms (e.g., boron, phosphorus, or arsenic).

[0079] It should be understood that, in certain embodiments, the nanowires or nanoribbons or sacrificial intercalary layer may be composed of silicon-germanium. As used throughout, a silicon-germanium layer can be used to describe a silicon-germanium material composed of a majority (e.g., at least 5% of both) of silicon and germanium. In some embodiments, the amount of germanium is greater than the amount of silicon. In a particular embodiment, the silicon-germanium layer comprises approximately 60% germanium and approximately 40% silicon (Si). 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer comprises approximately 30% germanium and approximately 70% silicon (Si). 70 Ge 30 It should be understood that, in practice, 100% pure silicon germanium (generally referred to as SiGe) may be difficult to form, and therefore may include a very small percentage of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may “contaminate” SiGe during diffusion during post-deposition processing. Thus, the embodiments for silicon germanium layers described herein may include silicon germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Si atoms or substances (e.g., carbon or tin). It should be understood that silicon germanium layers as described herein may be undoped or may be doped with dopant atoms (e.g., boron, phosphorus, or arsenic).

[0080] The following describes various apparatuses and fabrication methods that can be used to fabricate devices that can be integrated with diced metal gates. It should be understood that exemplary embodiments do not necessarily require all the features described, or may include more features than described. For example, nanowire release fabrication can be performed by replacing the gate trench. Examples of such release processes are described below. Additionally, in another aspect, back-side (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to patterning complexity. Embodiments described herein can be implemented to achieve front-side and back-side interconnect integration for nanowire transistors. The embodiments described herein can provide methods for achieving relatively wider interconnect pitches. The result can be improved product performance and lower patterning costs. Embodiments can be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0081] One or more embodiments described herein pertain to biepitaxy (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In these embodiments, the integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor that is partially filled with SD epitaxy. The remaining portion of the opening is filled with a conductive material. A deep trench is formed on one of the source or drain sides to enable direct contact with the back-side interconnect layer.

[0082] This is an exemplary process flow for manufacturing a gate-all-around integrated circuit structure. Figures 7A-7J Cross-sectional views are shown of various operations in a method of manufacturing a gate-all-around integrated circuit structure according to embodiments of the present disclosure.

[0083] refer to Figure 7A A method for fabricating an integrated circuit structure includes forming a starting stack comprising alternating sacrificial layers 704 and nanowires 706 above fins 702 (e.g., silicon fins). The nanowires 706 may be referred to as a vertically arranged nanowire structure. As depicted, a protective cap 708 may be formed above the alternating sacrificial layers 704 and nanowires 706. Also as depicted, a relaxation buffer layer 752 and a defect modification layer 750 may be formed beneath the alternating sacrificial layers 704 and nanowires 706.

[0084] refer to Figure 7B A gate stack 710 is formed on top of the vertically arranged structure of horizontal nanowires 706. For example... Figure 7C As depicted, a portion of the vertically arranged structure of the horizontal nanowires 706 is then released by removing a portion of the sacrificial layer 704 to provide a recessed sacrificial layer 704' and a cavity 712.

[0085] It should be understood that the fabrication can be completed without first performing the deep etching and asymmetric contact machining described below. Figure 7C The structure. In either case (e.g., with or without asymmetric contact processing), in the embodiments, the manufacturing process involves using a process scheme that provides a fully all-around gate integrated circuit structure with epitaxial bumps, which can be vertically discrete source or drain structures.

[0086] refer to Figure 7D An upper gate spacer 714 is formed at the sidewall of the gate structure 710. A cavity spacer 716 is formed in the cavity 712 located below the upper gate spacer 714. Optionally, deep trench contact etching is then performed to form a trench 718 and a recessed nanowire 706'. As depicted, a patterned relaxation buffer layer 752' and a patterned defect modification layer 750' may also be present.

[0087] like Figure 7E As depicted, sacrificial material 720 is then formed in trench 718. In other process options, an isolated trench bottom or a silicon trench bottom can be used.

[0088] refer to Figure 7F A first epitaxial source or drain structure (e.g., left-handed feature 722) is formed at the first end of the vertically arranged structure of the horizontal nanowire 706'. A second epitaxial source or drain structure (e.g., right-handed feature 722) is formed at the second end of the vertically arranged structure of the horizontal nanowire 706'. In embodiments, as depicted, the epitaxial source or drain structure 722 is a vertically discrete source or drain structure and may be referred to as an epitaxial bump.

[0089] like Figure 7G As depicted, an interlayer dielectric (ILD) material 724 is then formed on the side of the gate electrode 710 and adjacent to the source or drain structure 722. (See reference...) Figure 7H The gate replacement process is used to form the permanent gate dielectric 728 and the permanent gate electrode 726. For example... Figure 7I As depicted in the diagram, the ILD material 724 is then removed. The sacrificial material 720 is then removed from one of the source and drain locations (e.g., the right-hand side) to form the trench 732, but the sacrificial material 720 is not removed from the other source and drain location to form the trench 730.

[0090] refer to Figure 7JA first conductive contact structure 734 is formed coupled to a first epitaxial source or drain structure (e.g., left-handed feature 722). A second conductive contact structure 736 is formed coupled to a second epitaxial source or drain structure (e.g., right-handed feature 722). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In an embodiment, although... Figure 7J Not depicted, but the method also includes forming an exposed surface of a second conductive contact structure 736 at the bottom of the fin 702. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, wherein examples may include Ti, Ni, Co (for the former, and W, Ru, Co for the latter).

[0091] In one embodiment, as depicted, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734. In one such embodiment, as depicted, the first conductive contact structure 734 is not along the fin 702. In another such embodiment not depicted, the first conductive contact structure 734 partially follows the fin 702.

[0092] In one embodiment, the second conductive contact structure 736 extends along the entire fin 702. In another embodiment, although not shown, the second conductive contact structure 736 has an exposed surface at the bottom of the fin 702 when the bottom of the fin 702 is exposed via a backside substrate removal process.

[0093] In an embodiment, Figure 7J The structure or Figures 7A-7J The relevant structures can be formed using methods such as the offset gate notch method described above.

[0094] In another aspect, to enable access to two conductive contacts in a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be fabricated using a back-side exposure fabrication method for front-side structures. In some exemplary embodiments, back-side exposure of transistors or other device structures requires wafer-level back-side processing. Compared to conventional TSV-type techniques, back-side exposure of transistors as described herein can be performed at device cell densities and even within sub-regions of the device. Furthermore, such back-side exposure of transistors can be performed to substantially remove all donor substrates on which device layers are disposed during front-side device processing. Thus, micrometer-deep TSVs become unnecessary when the semiconductor thickness in the device cell may be only tens or hundreds of nanometers after back-side exposure of the transistor.

[0095] The exposure techniques described in this paper enable a shift in manufacturing paradigms from "bottom-up" device fabrication to "center-out" fabrication, where "center" refers to any layer that is employed in front-side fabrication, exposed from the back side, and reused in back-side fabrication. While relying primarily on front-side processing, fabricating both the front and exposed back sides of the device structure can address many of the challenges associated with manufacturing 3D ICs.

[0096] Exposing the back side of the transistor can be employed, for example, to remove at least a portion of the carrier layer and intercalary layer of the donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a group IV semiconductor (e.g., silicon), a CMP paste known to be suitable for thinning the semiconductor can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can also be used.

[0097] In some embodiments, prior to the steps described above, the carrier layer is cleaved along a fracture plane substantially parallel to the intercalary layer. Cleavage or fracture processes can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved away by practicing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted into the carrier layer at a desired uniform target depth with a fracture plane. After such a cleavage process, the remaining thickness of the carrier layer in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the absence of fracture in the carrier layer, grinding, polishing, and / or etching operations can be used to remove a carrier layer of greater thickness.

[0098] Next, the exposure of the intermediate layer is detected. Detection is used to identify the point at which the back surface of the donor substrate has advanced to near the device layer. Any known endpoint detection technique suitable for detecting the transition between the materials used in the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on changes in light absorption or emission detected on the back surface of the donor substrate during polishing and / or etching. In some other embodiments, the endpoint criteria are associated with changes in light absorption or emission of byproducts during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelengths associated with carrier layer etching byproducts can vary as a function of the different components of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of the material in the byproducts of polishing or etching the back surface of the donor substrate. For example, the processed byproducts can be sampled using a quadrupole mass analyzer, and the change in mass can be related to the different components of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in the frictional force between the back surface of the donor substrate and the polished surface in contact with the back surface of the donor substrate.

[0099] Since the inhomogeneity in the carrier removal process can be mitigated by the difference in etching rates between the carrier layer and the intermediate layer, the detection of the intermediate layer can be enhanced when the removal process is selective for the carrier layer relative to the intermediate layer. If the grinding, polishing, and / or etching operations remove the intermediate layer at a rate sufficiently lower than that of the carrier layer, the detection can even be skipped. Without an endpoint criterion, grinding, polishing, and / or etching operations of a predetermined fixed duration can be stopped on the intermediate layer material if the thickness of the intermediate layer is sufficient for the selectivity of the etching. In some examples, the carrier etching rate:intermediate layer etching rate is 3:1 to 10:1 or greater.

[0100] After exposing the intercalary layer, at least a portion of the intercalary layer can be removed. For example, one or more component layers within the intercalary layer can be removed. The thickness of the intercalary layer can be uniformly removed, for example, by polishing. Alternatively, a mask or blanket etching process can be used to remove the thickness of the intercalary layer. This process can employ the same polishing or etching process used for thinning the carrier, or it can be a different process with different process parameters. For example, in cases where the intercalary layer provides an etch stop for the carrier removal process, the latter operation can employ a different polishing or etching process that is more favorable for the removal of the intercalary layer than for the removal of the device layer. When removing an intercalary layer thickness of less than a few hundred nanometers, the removal process can be relatively slow, optimized for uniformity across the entire wafer, and can be more precisely controlled than the process used to remove the carrier layer. The CMP process employed can, for example, use a paste that provides very high selectivity (e.g., 100:1-300:1 or greater) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) surrounding the device layer and embedded within the intercalary layer (e.g., as electrical isolation between adjacent device regions).

[0101] For embodiments in which the device layer is exposed by completely removing the intervening layer, back-side processing can begin on the exposed back side of the device layer or on a specific device region therein. In some embodiments, back-side device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intervening layer and a device region (e.g., a source or drain region) previously fabricated in the device layer.

[0102] In some embodiments where wet and / or plasma etching is used to recess the back side of the carrier layer, intermediary layer, or device layer, such etching can be patterned etching or material-selective etching, which imparts significant non-planarity or morphology to the back side surface of the device layer. As further described below, patterning can be performed within a device cell (i.e., “intra-cell” patterning) or across device cells (i.e., “inter-cell” patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediary layer is used as a hard mask for patterning the back side device layer. Therefore, the mask etching process can precede the corresponding mask device layer etching.

[0103] The fabrication scheme described above can produce a donor-host substrate assembly including an IC device that exposes the back side of the intermediary layer, the back side of the device layer, and / or the back side and / or front side metallization of one or more semiconductor regions within the device layer. Further back-side processing can then be performed on any of these exposed regions during downstream processing.

[0104] It should be understood that the structure produced by the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete device fabrication (e.g., PMOS and / or NMOS device fabrication). As an example of the completed device, Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure is shown.

[0105] refer to Figure 8 The semiconductor structure or device 800 includes a nonplanar active region (e.g., a fin structure including an extended fin portion 804 and a sub-fin region 805) located within a trench isolation region 806. In an embodiment, as shown by dashed lines, the nonplanar active region is partitioned into nanowires (e.g., nanowires 804A and 804B) above the sub-fin region 805 instead of a solid fin. In either case, for ease of description of the nonplanar integrated circuit structure 800, the nonplanar active region 804 is hereinafter referred to as the extended fin portion. In an embodiment, as depicted, the sub-fin region 805 also includes a relaxation buffer layer 842 and a defect modification layer 840.

[0106] Gate line 808 is disposed over an extension 804 of a non-planar active region (including, if applicable, surrounding nanowires 804A and 804B) and a portion of a trench isolation region 806. As shown, gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, gate line 808 may further include a dielectric capping layer 854. From this viewpoint, it can also be seen that gate contact 814 and overlying gate contact via 816, together with overlying metal interconnect 860, are all disposed within an interlayer dielectric stack or layer 870. Figure 8 From this perspective, it can also be seen that in one embodiment, the gate contact 814 is disposed above the trench isolation region 806, but not above the non-planar active region. In another embodiment, the gate contact 814 is located above the non-planar active region.

[0107] In an embodiment, the semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is constituted by or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 808 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body.

[0108] For example Figure 8As depicted, in an embodiment, interface 880 exists between the protruding fin portion 804 and the sub-fin region 805. Interface 880 may be a transition region located between the doped sub-fin region 805 and the lightly doped or undoped upper fin portion 804. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally supplied from an adjacent solid-state doped layer located at the sub-fin site. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0109] although Figure 8 Not depicted, but it should be understood that the source or drain region of the protruding fin portion 804, or the source or drain region adjacent to the protruding fin portion 804, is located on either side of the gate line 808, i.e., inside or outside the page. In one embodiment, the material in the source or drain location of the protruding fin portion 804 is removed and replaced by another semiconductor material (e.g., by epitaxial deposition) to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 806, i.e., into the sub-fin region 805. According to embodiments of this disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below interface 880) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin. In embodiments, as described above... Figure 7J As described, the source and drain regions have associated asymmetric source and drain contact structures.

[0110] Refer again Figure 8 In the embodiments, the fins 804 / 805 (and possibly the nanowires 804A and 804B) are composed of a crystalline silicon-germanium layer that may be doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0111] In embodiments, trench isolation region 806 and trench isolation regions (trench isolation structures or trench isolation layers) as described throughout may be made of materials suitable for ultimately electrically isolating portions of the permanent gate structure from the underlying body substrate or contributing to the isolation of portions of the permanent gate structure from the underlying body substrate, or suitable for isolating active regions (e.g., isolation fin active regions) formed within the underlying body substrate. For example, in one embodiment, trench isolation region 806 is made of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0112] Gate line 808 may be formed of a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack is formed of a metal gate, and the gate dielectric layer is formed of a high-k material. For example, in one embodiment, the gate dielectric layer 852 is formed of, but is not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer 852 may include a layer of native oxide formed from the top layers of the substrate fin 804. In an embodiment, the gate dielectric layer 852 is formed of a top high-k portion and a lower portion formed of an oxide of semiconductor material. In one embodiment, the gate dielectric layer 852 is formed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0113] In one embodiment, the gate electrode layer 850 is composed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode layer 850 is composed of a non-work function filling material formed above the metal work function setting layer. Depending on whether the transistor is a PMOS transistor or an NMOS transistor, the gate electrode layer 850 may be composed of a P-type work function metal or an N-type work function metal. In some embodiments, the gate electrode layer 850 may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will enable the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). An N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may consist of a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include the sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments of this disclosure, the gate electrode may consist of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0114] The spacer associated with the gate electrode stack can be made of a material suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts (e.g., self-aligned contacts) or contributing to the isolation of the permanent gate structure from adjacent conductive contacts. For example, in one embodiment, the spacer is made of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0115] The gate contact 814 and the overlying gate contact via 816 may be made of a conductive material. In an embodiment, one or more of the contacts or vias may be made of a metallic material. The metallic material may be a pure metal (e.g., tungsten, nickel, or cobalt) or an alloy (e.g., a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material)).

[0116] In an embodiment (although not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 808, while eliminating the use of photolithography steps with extremely tight registration budgets. In an embodiment, for example, combined with Figure 7J The contact patterns described are either vertically symmetrical or asymmetrical. In other embodiments, all contacts are front-connected and not asymmetrical. In one such embodiment, the self-aligned method enables the generation of contact openings using inherently highly selective wet etching (e.g., compared to conventional dry or plasma etching). In an embodiment, the contact patterns are formed by utilizing existing gate patterns in conjunction with contact plug lithography operations. In one such embodiment, the method eliminates the need for additional critical lithography operations used in conventional methods to generate the contact patterns. In an embodiment, the trench contact grid is not patterned separately but formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid patterning but before the gate grid notch.

[0117] In an embodiment, providing structure 800 relates to fabricating a gate stack structure 808 using a gate replacement process. In such an approach, a dummy gate material (e.g., polysilicon or silicon nitride pillar material) can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, in contrast to that performed from an earlier fabrication. In an embodiment, the dummy gate is removed using a dry etching or wet etching process. In one embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a dry etching process including the use of SF6. In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed using a wet etching process including aqueous phosphoric acid.

[0118] Refer again Figure 8The arrangement of the semiconductor structure or device 800 places the gate contact over an isolation region. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed over an active region (e.g., over fin 805) and located in the same layer as the trench contact via.

[0119] In an embodiment, Figure 8 The structure can be formed using methods such as the offset gate notch described above.

[0120] It should be understood that not all aspects of the above-described processes are required to fall within the spirit and scope of the embodiments of this disclosure. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. A semiconductor device can be a transistor or similar device. For example, in embodiments, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic cells or memory, or a bipolar transistor. Additionally, in embodiments, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessible dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0121] In embodiments, as used throughout this specification, the interlayer dielectric (ILD) material comprises, or includes, layers of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0122] In embodiments, and as used throughout this specification, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures, which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term "metal" includes alloys, stacks, and other combinations of various metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect may be a single layer of material or may be formed of several layers, including conductive substrates and filler layers. Any suitable deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In embodiments, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes referred to in the art as traces, wires, lines, metals, or simply as interconnects.

[0123] In embodiments, as used throughout this specification, the hard mask material, capping layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, capping, or plug materials can be used in different regions to provide different growth or etching selectivity relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping layer, or plug layer comprises a layer of silicon nitride (e.g., silicon nitride), or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, capping, or plug layers known in the art may be used. The hard mask, capping, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0124] In this embodiment, as used throughout this specification, 193nm immersion lithography (i193), EUV, and / or EBDW lithography are used to perform the lithography operation. Positive or negative photoresist can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topography mask portion, an antireflective coating (ARC) layer, and a photoresist layer. In a particular embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the antireflective coating layer is a silicon ARC layer.

[0125] In another aspect, one or more embodiments target adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may target the integration of multi-width (multiple Wsi) nanowires and nanoribbons within a SAGE architecture and separated by SAGE walls. In embodiments, multiple Wsi are integrated within a portion of the SAGE architecture in a front-end process flow. Such a process flow can involve the integration of nanowires and nanoribbons with different Wsi to provide robust functionality for next-generation transistors with low power and high performance. The associated epitaxial source or drain regions may be embedded (e.g., removing portions of the nanowire and then performing source or drain (S / D) growth).

[0126] To provide further background, the advantages of the self-aligned gate endcap (SAGE) architecture can include achieving higher layout density, and specifically, scaling diffusion to the diffusion pitch. For illustrative comparison, Figure 9 A cross-sectional view through nanowires and fins is shown of a non-end cap architecture (left-hand side (a)) according to an embodiment of the present disclosure relative to a self-aligned gate end cap (SAGE) architecture (right-hand side (b)).

[0127] refer to Figure 9 On the left-hand side (a), the integrated circuit structure 900 includes a substrate 902 with fins 904 extending an amount 906 above an isolation structure 908 laterally surrounding the lower portion of the fins 904. As depicted, the upper portion of the fins may include a relaxation buffer layer 922 and a defect modification layer 920. Corresponding nanowires 905 are located above the fins 904. A gate structure can be formed on the integrated circuit structure 900 to fabricate a device. However, breakpoints in such a gate structure can be accommodated by increasing the spacing between the fin 904 / nanowire 905 pairs.

[0128] In comparison, refer to Figure 9On the right-hand side (b), the integrated circuit structure 950 includes a substrate 952 having fins 954 that extend an amount 956 over an isolation structure 958 laterally surrounding the lower portion of the fins 954. As depicted, the upper portion of the fins may include a relaxation buffer layer 972 and a defect modification layer 970. Corresponding nanowires 955 are located above the fins 954. Isolation SAGE walls 960 (which may include a hard mask, as depicted) are included within the isolation structure 952 and between adjacent pairs of fins 954 / nanowires 955. The distance between the isolation SAGE wall 960 and the nearest pair of fins 954 / nanowires 955 defines the gate cap pitch 962. Gate structures may be formed on the integrated circuit structure 900 between the isolation SAGE walls to fabricate a device. Breakpoints in such a gate structure are caused by the isolation SAGE walls. Because the isolation SAGE wall 960 is self-aligned, limitations from conventional methods can be minimized to achieve more aggressive diffusion to the diffusion pitch. Furthermore, because the gate structure includes breakpoints at all locations, individual gate structure portions can be layered via local interconnects formed on the isolation SAGE wall 960. In embodiments, as depicted, each SAGE wall 960 includes a lower dielectric portion and a dielectric cap located on the lower dielectric portion. According to embodiments of this disclosure, for use with… Figure 9 The manufacturing process of the associated structure involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0129] In an embodiment, Figure 9 The structure in part (a) can be formed using an offset gate notch method as described above. In an embodiment, Figure 9 The structure in part (b) can be formed using methods such as the offset gate notch described above.

[0130] The self-aligned gate end cap (SAGE) fabrication scheme involves forming a gate / trench contact end cap that is self-aligned to the fin without requiring additional length to accommodate mask mismatch. Therefore, embodiments can be implemented to achieve a reduction in transistor layout area. The embodiments described herein may relate to the fabrication of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolated gate wall, or a self-aligned gate end cap (SAGE) wall.

[0131] In an exemplary processing scheme for a structure having SAGE walls that separate adjacent devices, Figure 10 Cross-sectional views are shown illustrating various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a fully surrounding gate device, according to embodiments of the present disclosure.

[0132] refer to Figure 10In part (a), the initial structure includes a nanowire patterned stack 1004 located above a substrate 1002. A photolithographic patterned stack 1006 is formed above the nanowire patterned stack 1004. As depicted, the nanowire patterned stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be located above a relaxation buffer layer 1082 and a defect modification layer 1080. A protective mask 1014 is located between the nanowire patterned stack 1004 and the photolithographic patterned stack 1006. In one embodiment, the photolithographic patterned stack 1006 is a three-layer mask consisting of a topography mask portion 1020, an antireflective coating (ARC) 1022, and a photoresist layer 1024. In a particular such embodiment, the topography mask portion 1020 is a carbon hard mask (CHM) layer, and the antireflective coating 1022 is a silicon ARC layer.

[0133] refer to Figure 10 In part (b), the stack of part (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 1002 and trench 1030.

[0134] refer to Figure 10 The structures of parts (c) and (b) have an isolation layer 1040 and a SAGE material 1042 formed in the trench 1030. The structure is then planarized to leave a patterned topographic mask layer 1020' as the exposed upper layer.

[0135] refer to Figure 10 In part (d), the isolation layer 1040 is recessed below the upper surface of the patterned substrate 1002, for example, to define the protruding fin portion and provide a trench isolation structure 1041 below the SAGE wall 1042.

[0136] refer to Figure 10 In part (e), at least in the channel region, the sacrificial layer 1010 is removed to release nanowires 1012A and 1012B. During the formation... Figure 10 Following the structure of portion (e), a gate stack can be formed around nanowires 1012B or 1012A, above the protruding fins of substrate 1002, and between SAGE walls 1042. In one embodiment, the remainder of the protective mask 1014 is removed before forming the gate stack. In another embodiment, the remainder of the protective mask 1014 is retained as an insulating fin cap, which is an artificial product of the processing scheme.

[0137] Refer again Figure 10Part (e) of the diagram should be understood to depict a channel view in which the source or drain regions are located inside or outside the page. In an embodiment, the channel region including nanowire 1012B has a smaller width than the channel region including nanowire 1012A. Therefore, in an embodiment, the integrated circuit structure includes nanowires of multiple widths (multiple Wsi). Although the structures of 1012B and 1012A can be distinguished as nanowires and nanoribbons, respectively, both such structures are generally referred to as nanowires herein. It should also be understood that references or descriptions of fin / nanowire pairs throughout the text may refer to fins and one or more overlying nanowires (e.g., Figure 10 The structure of two overlying nanowires is shown. According to embodiments of this disclosure, it is used with... Figure 10 The manufacturing process of the associated structure involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0138] In an embodiment, Figure 10 The structure in part (e) can be formed using methods such as the offset gate notch method described above.

[0139] In embodiments, as described throughout, the self-aligned gate end cap (SAGE) isolation structure may be composed of one or more materials suitable for ultimately electrically isolating portions of the permanent gate structure from each other or contributing to the isolation of portions of the permanent gate structure from each other. Exemplary materials or combinations of materials include single-material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multilayer stacks having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride, and an upper portion of a material with a higher dielectric constant (e.g., hafnium oxide).

[0140] To highlight the exemplary integrated circuit structure with three vertically arranged nanowires, Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 11B It shows Figure 11A A cross-sectional view of the source or drain of a nanowire-based integrated circuit structure taken along the a-a' axis. Figure 11C It shows Figure 11A A cross-sectional channel view of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0141] refer to Figure 11AThe integrated circuit structure 1100 includes one or more vertically stacked nanowires (group 1104) located above a substrate 1102. In the depicted embodiments, as depicted, a relaxation buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are included in the substrate 1102. For illustrative purposes, to emphasize the nanowire portion, optional fins located below the bottommost nanowire and formed by the substrate 1102 are not depicted. The embodiments herein pertain to both single-wire devices and multi-wire devices. As an example, for illustrative purposes, three nanowire-based devices having nanowires 1104A, 1104B, and 1104C are shown. For ease of description, nanowire 1104A is used as an example, wherein the description focuses on one nanowire among the nanowires. It should be understood that, in the case of describing the properties of a single nanowire, embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire among the nanowires.

[0142] Each nanowire in nanowire 1104 includes a channel region 1106. The channel region 1106 has a length (L). Reference Figure 11C The channel region also has a perimeter (Pc) orthogonal to its length (L). (See reference) Figure 11A and Figure 11C Both, the gate electrode stack 1108 surrounds the entire perimeter (Pc) of each channel region in the channel regions 1106. The gate electrode stack 1108 includes a gate electrode and a gate dielectric layer located between the channel regions 1106 and the gate electrode (not shown). In embodiments, the channel regions are discrete because they are completely surrounded by the gate electrode stack 1108 without any intervening material (e.g., a lower substrate material or an overlying channel fabrication material). Therefore, in embodiments with multiple nanowires 1104, the channel regions 1106 of the nanowires are also relatively discrete from each other.

[0143] refer to Figure 11A and Figure 11BBoth, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. This pair of non-discrete source or drain regions 1110 / 1112 is located on either side of a channel region 1106 of a plurality of vertically stacked nanowires 1104. Furthermore, this pair of non-discrete source or drain regions 1110 / 1112 is adjacent to the channel region 1106 of the plurality of vertically stacked nanowires 1104. In one such embodiment (not depicted), since epitaxial growth is performed on and between nanowire portions extending beyond the channel region 1106, this pair of non-discrete source or drain regions 1110 / 1112 is directly and perpendicularly adjacent to the channel region 1106, wherein the nanowire ends are shown as being within the source or drain structure. In another embodiment, as... Figure 11A As depicted, because they are formed at the ends of the nanowires rather than between the nanowires, this pair of non-discrete source or drain regions 1110 / 1112 are indirectly and perpendicularly adjacent to the channel region 1106.

[0144] In the embodiments, as depicted, since there is no single and discrete source or drain region for each channel region 1106 of the nanowire 1104, the source or drain regions 1110 / 1112 are non-discrete. Therefore, in embodiments with multiple nanowires 1104, contrary to the case where they are discrete for each nanowire, the source or drain regions 1110 / 1112 of the nanowires are global or uniform source or drain regions. That is, the non-discrete source or drain regions 1110 / 1112 are global in the sense that a single uniform feature is used for the source or drain regions of multiple (in this case, three) nanowires 1104, and more specifically for the source or drain regions of more than one discrete channel region 1106. In one embodiment, viewed from a cross-sectional view orthogonal to the length of the discrete channel region 1106, as... Figure 11B As depicted, each of the pair of non-discrete source or drain regions 1110 / 1112 is generally rectangular in shape, with a bottom pyramidal portion and a top vertex portion. However, in other embodiments, the source or drain regions 1110 / 1112 of the nanowire are relatively larger and discretely non-vertically merged epitaxial structures, such as those combined with... Figures 7A-7J The described protrusion.

[0145] According to embodiments of this disclosure, and as Figure 11A and Figure 11BAs depicted, the integrated circuit structure 1100 also includes a pair of contacts 1114, each contact 1114 located on one of the source or drain regions 1110 / 1112 of the pair of non-discrete source or drain regions 1110 / 1112. In one such embodiment, in a vertical sense, each contact 1114 completely surrounds the corresponding non-discrete source or drain region 1110 / 1112. In another aspect, as... Figure 11B As depicted, the entire perimeter of the non-discrete source or drain regions 1110 / 1112 may not be in contact with the contact portion 1114, and the contact portion 1114 therefore only partially surrounds the non-discrete source or drain regions 1110 / 1112. In a comparative embodiment not depicted, as truncated along the a-a' axis, the entire perimeter of the non-discrete source or drain regions 1110 / 1112 is surrounded by the contact portion 1114.

[0146] Refer again Figure 11A In one embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As depicted, the outer portions of these spacers 1116 may partially overlap with non-discrete source or drain regions 1110 / 1112, thereby providing an "embedded" portion of the non-discrete source or drain regions 1110 / 1112 beneath these spacers 1116. Also as depicted, the embedded portion of the non-discrete source or drain regions 1110 / 1112 may not extend beneath the entirety of these spacers 1116.

[0147] Substrate 1102 may be made of a material suitable for manufacturing integrated circuit structures. In one embodiment, substrate 1102 includes a lower body substrate made of a single-crystal material, which may include, but is not limited to, silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin, or III-V compound semiconductor materials. An upper insulating layer is located on the lower body substrate and may be made of a material including, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. Therefore, structure 1100 can be fabricated from a semiconductor-on-insulator substrate. Alternatively, structure 1100 is formed directly from the body substrate, and localized oxidation is used to form electrically insulating portions instead of the aforementioned upper insulating layer. In another alternative embodiment, structure 1100 is formed directly from the body substrate, and doping is used to form electrically isolated active regions (e.g., nanowires) thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an Ω-FET type structure.

[0148] In embodiments, the nanowire 1104 may be sized as a line or strip (as described below) and may have square or rounded corners. In embodiments, the nanowire 1104 is made of a material such as, but not limited to, silicon, germanium, or combinations thereof. In one such embodiment, the nanowire is single-crystal. For example, for silicon nanowire 1104, the single-crystal nanowire may be based on a (100) global orientation, for example, having […] in the z-direction. <100> Planar. Other orientations may also be considered, as described below. In the embodiments, the nanowires 1104 are nanometer-sized when viewed from a cross-sectional perspective. For example, in a particular embodiment, the minimum size of the nanowires 1104 is less than approximately 20 nanometers. In the embodiments, the nanowires 1104 are made of strained material, particularly strained material in the channel region 1106.

[0149] refer to Figure 11C In this embodiment, each channel region 1106 has a width (Wc) and a height (Hc), which are approximately the same. That is, in both cases, the cross-sectional profile of the channel region 1106 is square, or if it is rounded, the cross-sectional profile of the channel region 1106 is circular. In another aspect, for example, as described throughout for nanoribbons, the width and height of the channel regions do not need to be the same.

[0150] In embodiments, as described throughout, the integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate device having one or more corresponding overlying nanowire structures. In such embodiments, the corresponding semiconductor channel region is constituted by or formed in a three-dimensional body, wherein one or more discrete nanowire channel portions are overlying the three-dimensional body. In one such embodiment, the gate structure surrounds at least the top surface and a pair of sidewalls of the three-dimensional body, and also surrounds each of the one or more discrete nanowire channel portions.

[0151] In an embodiment, Figures 11A-11C The structure can be formed using methods such as the offset gate notch described above.

[0152] In embodiments, as described throughout, the underlying substrate may be made of a semiconductor material capable of withstanding fabrication processes and in which charge can migrate. In embodiments, the substrate is a bulk substrate comprising a layer of crystalline silicon, silicon / germanium, or germanium doped with charge carriers to form active regions, such charge carriers being, for example, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate comprises an epitaxial layer grown on top of a different crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single-crystal substrate. The bulk substrate may alternatively be made of a Group III-V material. In embodiments, the bulk substrate is made of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is made of a group III-V material, and the charge carrier dopant impurity atoms are, for example, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0153] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, etc. Integrated circuits can be coupled to buses and other components in a system. For example, a processor can be coupled to memory, chipsets, etc., via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0154] Figure 12 A computing device 1200 according to one embodiment of the present disclosure is shown. The computing device 1200 houses a board 1202. The board 1202 may include multiple components, including but not limited to a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the board 1202. In some embodiments, at least one communication chip 1206 is also physically and electrically coupled to the board 1202. In a further embodiment, the communication chip 1206 is part of the processor 1204.

[0155] Depending on the application of computing device 1200, computing device 1200 may include other components that may or may not be physically coupled and electrically coupled to board 1202. These other components include, but are not limited to: volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (e.g., hard disk drive, optical disc (CD), digital versatile optical disc (DVD), etc.).

[0156] Communication chip 1206 enables wireless communication for transmitting data to and from computing device 1200. The term "wireless" and its derivatives can be used to describe circuits, apparatuses, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. This term does not imply that the associated apparatus does not contain any wires, although in some embodiments they may not contain wires. Communication chip 1206 can implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and derivatives thereof, as well as any other wireless protocol designated as 3G, 4G, 5G, and higher. Computing device 1200 may include multiple communication chips 1206. For example, the first communication chip 1206 can be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, while the second communication chip 1206 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0157] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures constructed according to embodiments of the present disclosure, such as a gate-all-around integrated circuit structure having a uniform grid metal gate and trench contact berths. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0158] The communication chip 1206 also includes an integrated circuit die packaged within the communication chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures constructed according to embodiments of the present disclosure, such as a gate-all-around integrated circuit structure having a uniform grid metal gate and trench contact cutouts.

[0159] In a further embodiment, another component housed within the computing device 1200 may contain an integrated circuit die comprising one or more structures constructed according to embodiments of the present disclosure, such as a full-around-gate integrated circuit structure having a uniform grid metal gate and trench contact occupancy cutouts.

[0160] In various embodiments, the computing device 1200 may be a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), super mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, the computing device 1200 may be any other electronic device that processes data.

[0161] Figure 13 An interposer 1300, comprising one or more embodiments of the present disclosure, is illustrated. The interposer 1300 is an intermediary substrate for bridging a first substrate 1302 to a second substrate 1304. For example, the first substrate 1302 may be an integrated circuit die. The second substrate 1304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 1300 is to extend connections to a wider pitch or to rewire connections to different connections. For example, the interposer 1300 may couple an integrated circuit die to a ball grid array (BGA) 1306, which may then be coupled to the second substrate 1304. In some embodiments, the first substrate 1302 and the second substrate 1304 are attached to opposite sides of the interposer 1300. In other embodiments, the first substrate 1302 and the second substrate 1304 are attached to the same side of the interposer 1300. And in a further embodiment, three or more substrates are interconnected through the interposer 1300.

[0162] Intermediate layer 1300 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymer material (e.g., polyimide). In other embodiments, intermediate layer 1300 may be formed of alternative rigid or flexible material, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials.

[0163] Interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1312. Interposer 1300 may also include embedded devices 1314, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 1300. According to embodiments of this disclosure, the apparatus or processes disclosed herein may be used in the manufacture of interposer 1300 or in the manufacture of components included in interposer 1300.

[0164] Therefore, embodiments of this disclosure include an integrated circuit structure having a uniform grid metal gate and trench contact space cutouts, and a method for manufacturing an integrated circuit structure having a uniform grid metal gate and trench contact space cutouts.

[0165] The above description of the illustrated embodiments of this disclosure (including the content described in the abstract) is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. Although specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art. These modifications may be made to this disclosure in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific embodiments disclosed in the specification and claims.

[0166] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even though only a single embodiment has been described with respect to a particular feature. Unless otherwise stated, the examples of features provided in this disclosure are intended to be illustrative rather than restrictive. The above description is intended to cover such alternatives, modifications, and equivalents that will be apparent to those skilled in the art as to benefit from this disclosure.

[0167] The scope of this disclosure (express or implicit) includes any feature or combination of features disclosed herein, or any generalization thereof, whether or not it alleviates any or all of the problems described herein. Therefore, new claims may be made against any such combination of features during the examination of this application (or an application claiming priority thereto). In particular, with reference to the appended claims, features from dependent claims may be combined with features from independent claims, and features from the respective independent claims may be combined in any suitable manner, not just in the specific combinations listed in the appended claims.

[0168] This document describes various embodiments or aspects of this disclosure. In some embodiments, different embodiments are implemented separately. However, the embodiments are not limited to individually implemented embodiments. For example, two or more different embodiments may be combined together to be implemented as a single apparatus, process, structure, etc. In some cases, the entirety of various embodiments may be combined together. In other cases, a portion of a first embodiment may be combined with portions of one or more different embodiments. For example, a portion of a first embodiment may be combined with a portion of a second embodiment, or a portion of a first embodiment may be combined with a portion of a second embodiment and a portion of a third embodiment. The following examples relate to further embodiments. Various features of different embodiments may be combined in different ways with some included and excluded features to suit a variety of different applications.

[0169] Exemplary Example 1: An integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is located on the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact. A first dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric notch plug structure being laterally spaced and parallel to the first dielectric notch plug structure, wherein the conductive trench contact includes a conductive filler that is separated from the first and second dielectric notch plug structures by a liner.

[0170] Exemplary Example 2: According to the integrated circuit structure of Exemplary Example 1, the conductive trench contact portion has an uppermost surface that is at the same level as the uppermost surface of the gate electrode.

[0171] Exemplary Example 3: An integrated circuit structure according to Exemplary Example 1, wherein the conductive trench contact portion has an uppermost surface that is at the same level as the uppermost surface of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

[0172] Exemplary Example 4: An integrated circuit structure according to Exemplary Example 1, wherein the gate electrode has an uppermost surface that is at the same level as the uppermost surface of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

[0173] Exemplary Example 5: An integrated circuit structure according to Exemplary Example 1, wherein the conductive trench contact portion has an uppermost surface that is at the same level as the uppermost surface of the gate electrode, and wherein the uppermost surface of the conductive trench contact portion is at the same level as the uppermost surfaces of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

[0174] Exemplary Example 6: An integrated circuit structure includes a fin. A gate electrode is on the fin. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric notch plug structure being laterally spaced and parallel to the first dielectric notch plug structure, wherein the conductive trench contact includes a conductive filler, the conductive filler being separated from the first and second dielectric notch plug structures by a liner.

[0175] Exemplary Example 7: An integrated circuit structure according to Exemplary Example 6, wherein the conductive trench contact has an uppermost surface that is at the same level as the uppermost surface of the gate electrode.

[0176] Exemplary Example 8: An integrated circuit structure according to Exemplary Example 6, wherein the conductive trench contact portion has an uppermost surface that is at the same level as the uppermost surface of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

[0177] Exemplary Example 9: An integrated circuit structure according to Exemplary Example 6, wherein the gate electrode has an uppermost surface that is at the same level as the uppermost surface of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

[0178] Exemplary Example 10: An integrated circuit structure according to Exemplary Example 6, wherein the conductive trench contact portion has an uppermost surface that is at the same level as the uppermost surface of the gate electrode, and wherein the uppermost surface of the conductive trench contact portion is at the same level as the uppermost surfaces of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

[0179] Exemplary Example 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure comprising a vertical stack or fin of horizontal nanowires. A gate electrode is located above the vertical stack or fin of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact. A first dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric notch plug structure being laterally spaced and parallel to the first dielectric notch plug structure, wherein the conductive trench contact includes a conductive filler separated from the first and second dielectric notch plug structures by a liner.

[0180] Exemplary Example 12: A computing device according to Exemplary Example 11 includes a vertical stack of horizontal nanowires.

[0181] Exemplary Example 13: A computing device according to Exemplary Example 11 includes fins.

[0182] Exemplary Example 14: The computing device according to Exemplary Example 11, 12 or 13 further includes a memory coupled to the board.

[0183] Exemplary Example 15: The computing device according to Exemplary Example 11, 12, 13 or 14 further includes a communication chip coupled to the board.

[0184] Exemplary Example 16: The computing device according to Exemplary Example 11, 12, 13, 14 or 15 further includes a battery coupled to the plate.

[0185] Exemplary Example 17: The computing device according to Exemplary Example 11, 12, 13, 14, 15 or 16 further includes a camera coupled to the plate.

[0186] Exemplary Example 18: The computing device according to Exemplary Example 11, 12, 13, 14, 15, 16 or 17 further includes a display coupled to the board.

[0187] Exemplary Example 19: A computing device according to Exemplary Example 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0188] Exemplary Example 20: A computing device according to Exemplary Example 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the components are selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: Vertical stacking of horizontal nanowires; A gate electrode, which is located on the vertical stack of the horizontal nanowires; A conductive trench contact portion, wherein the conductive trench contact portion is adjacent to the gate electrode; A dielectric sidewall spacer, the dielectric sidewall spacer being located between the gate electrode and the conductive trench contact portion; A first dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact portion; as well as A second dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact portion. The second dielectric notch plug structure is laterally spaced and parallel to the first dielectric notch plug structure. The conductive trench contact portion includes a conductive filler, which is separated from the first dielectric notch plug structure and the second dielectric notch plug structure by a liner.

2. The integrated circuit structure according to claim 1, wherein, The conductive trench contact portion has an uppermost surface that is at the same level as the uppermost surface of the gate electrode.

3. The integrated circuit structure according to claim 1, wherein, The conductive trench contact portion has an uppermost surface that is on the same horizontal plane as the uppermost surfaces of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

4. The integrated circuit structure according to claim 1, wherein, The gate electrode has an uppermost surface that is on the same horizontal plane as the uppermost surfaces of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

5. The integrated circuit structure according to claim 1, wherein, The conductive trench contact portion has an uppermost surface that is at the same level as the uppermost surface of the gate electrode, and wherein the uppermost surface of the conductive trench contact portion is at the same level as the uppermost surfaces of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

6. An integrated circuit structure, comprising: Fin-like structures; A gate electrode, the gate electrode being located on the fin; A conductive trench contact portion, wherein the conductive trench contact portion is adjacent to the gate electrode; A dielectric sidewall spacer, the dielectric sidewall spacer being located between the gate electrode and the conductive trench contact portion; A first dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact portion; as well as A second dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact portion. The second dielectric notch plug structure is laterally spaced and parallel to the first dielectric notch plug structure. The conductive trench contact portion includes a conductive filler, which is separated from the first dielectric notch plug structure and the second dielectric notch plug structure by a liner.

7. The integrated circuit structure according to claim 6, wherein, The conductive trench contact portion has an uppermost surface that is at the same level as the uppermost surface of the gate electrode.

8. The integrated circuit structure according to claim 6, wherein, The conductive trench contact portion has an uppermost surface that is on the same horizontal plane as the uppermost surfaces of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

9. The integrated circuit structure according to claim 6, wherein, The gate electrode has an uppermost surface that is on the same horizontal plane as the uppermost surfaces of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

10. The integrated circuit structure according to claim 6, wherein, The conductive trench contact portion has an uppermost surface that is at the same level as the uppermost surface of the gate electrode, and wherein the uppermost surface of the conductive trench contact portion is at the same level as the uppermost surfaces of the first dielectric cut-out plug structure and the second dielectric cut-out plug structure.

11. A computing device, comprising: plate; as well as A component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising: Vertical stacks or fins of horizontal nanowires; A gate electrode, which is located on the vertical stack of the horizontal nanowires or the fin; A conductive trench contact portion, wherein the conductive trench contact portion is adjacent to the gate electrode; A dielectric sidewall spacer, the dielectric sidewall spacer being located between the gate electrode and the conductive trench contact portion; A first dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact portion; and A second dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact portion. The second dielectric notch plug structure is laterally spaced and parallel to the first dielectric notch plug structure. The conductive trench contact portion includes a conductive filler, which is separated from the first dielectric notch plug structure and the second dielectric notch plug structure by a liner.

12. The computing device of claim 11, comprising a vertical stack of the horizontal nanowires.

13. The computing device of claim 11, comprising the fin.

14. The computing device according to claim 11, 12 or 13, further comprising: A memory coupled to the board.

15. The computing device according to claim 11, 12 or 13, further comprising: A communication chip coupled to the board.

16. The computing device according to claim 11, 12 or 13, further comprising: The battery is coupled to the plate.

17. The computing device according to claim 11, 12 or 13, further comprising: A camera coupled to the plate.

18. The computing device according to claim 11, 12 or 13, further comprising: A display coupled to the board.

19. The computing device according to claim 11, 12 or 13, wherein, The component is a packaged integrated circuit die.

20. The computing device according to claim 11, 12 or 13, wherein, The component is selected from a group consisting of a processor, a communication chip, and a digital signal processor.

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