Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a display area; a first middle line, the width of the display panel in a first direction is D, the first middle line extends along a second direction, the distance between the first middle line and the first edge of the display panel in the first direction is d1, d1=D / 4, at least one gate drive circuit is arranged on both sides of the first middle line in the first direction; the first direction and the second direction intersect; and the gate drive circuit is located in the display area. According to the embodiment of the application, frameless display can be realized, and display uniformity can be improved.

Description

[0001] This application is a divisional application of Chinese Patent No. 202411177934.2, filed on August 26, 2024, entitled "Display Panel and Display Device". Technical Field

[0002] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0003] With the development of display technology, display panels are becoming increasingly common, and users have higher and higher requirements for them. Display panels are gradually moving towards thinner and lighter designs, higher screen-to-body ratios, and even borderless designs. How to achieve borderless designs is an important problem faced by those skilled in the art. Summary of the Invention

[0004] This application provides a display panel and display device that can achieve borderless display and improve display uniformity.

[0005] In a first aspect, embodiments of this application provide a display panel, including a display area; a first center line, the width of the display panel in a first direction is D, the first center line extends along a second direction, the distance between the first center line and the first edge of the display panel in the first direction is d1, d1=D / 4, at least one gate driving circuit is provided on each side of the first center line in the first direction; the first direction and the second direction intersect; the gate driving circuit is located in the display area.

[0006] Secondly, embodiments of this application provide a display device, including a display panel as described in any embodiment of the first aspect.

[0007] The display panel and display device provided in this application embodiment break with conventional design thinking. Instead of confining the gate driving circuit to the edge display area, the gate driving circuit is distributed on both sides of the first center line. In this way, even if there are many gate driving circuits, there is enough display area to accommodate them, thereby achieving a borderless design. In addition, compared with confining the gate driving circuit to the edge display area, distributing the gate driving circuit on both sides of the first center line can shorten the distance between at least part of the gate driving circuit and the center of the display area, thereby shortening the distance for the gate driving circuit to charge the center of the display area, thereby improving signal delay and voltage drop, and improving display uniformity. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application; Figure 2 This illustration shows another structural diagram of the display panel provided in an embodiment of this application; Figure 3 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 4 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 5 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application; Figure 6 This illustration shows another structural diagram of the pixel circuit in the display panel provided in an embodiment of this application; Figure 7 This illustration shows yet another structural diagram of the pixel circuit in the display panel provided in an embodiment of this application; Figure 8 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 9 Show Figure 8 A schematic diagram of a structure in the central region Q1; Figure 10 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 11 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 12 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 13 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 14 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 15 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 16 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 17 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 18 This is a schematic diagram of a display device provided in an embodiment of this application.

[0010] Explanation of some figure labels: 100. Display panel; AA, Display area; A1, First sub-display area; A2, Second sub-display area; L1, first median line; L2, second median line; C1, First Edge; 10. Gate driving circuit; 10a. Type I gate driving circuit; 10b. Type II gate driving circuit; 10c. Type III gate driving circuit; 10d. Other types of gate driving circuits; 11. First gate driving circuit; 12. Second gate driving circuit; 13. Third gate driving circuit; 14. Fourth gate driving circuit; 15. Fifth gate driving circuit; 16. Sixth gate driving circuit; 17. Seventh gate driving circuit; 20. Pixel circuit; 201. Pixel circuit array; 21. Amplitude modulation sub-circuit; 22. Pulse width modulation sub-circuit; 30. Light-emitting elements; 41. First signal line; 42. Second signal line. Detailed Implementation

[0011] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0012] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0013] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0014] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0015] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components. The term "drive" can refer to "control" or "operation". The term "part" can refer to "locality". The term "pattern" can refer to "component".

[0016] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0017] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies: The display panel includes pixel circuits, light-emitting elements, and gate driving circuits. The pixel circuits generate driving current under the control of the gate driving circuits to drive the light-emitting elements to emit light.

[0018] Pixel circuits and light-emitting elements are located in the display area of ​​the display panel. In related technologies, pixel circuits in the edge display area are recessed to make room for gate driving circuits. This design can achieve a borderless display when the gate driving architecture required for the pixel circuits is not complex (i.e., the number of gate driving circuits is small). However, as the requirements for driving performance increase, the number of gate driving circuits increases, making the design method of simply reserving space for gate driving circuits by recessing pixel circuits in the edge display area insufficient for the architecture design of multiple gate driving circuits. Furthermore, since the gate driving circuits are located in the edge display area, their output signals charge the center display area from the edge. For the center display area, the charging distance is relatively long, resulting in signal delay and voltage drop, leading to poor charging uniformity of the pixel circuits and affecting display uniformity.

[0019] To address the aforementioned technical problems, this application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0020] like Figure 1 As shown, the display panel 100 provided in this embodiment includes a display area AA. It is understood that the display area AA includes pixel circuits and light-emitting elements. Figure 1 (Not shown in the image), the display area AA is used to display the screen.

[0021] For example, in this embodiment of the application, the display panel is a borderless display panel with a narrow bezel, that is, in the first direction X, the non-display areas on the left and right sides of the display area AA are very small, or even non-display areas. For example, the accompanying drawings of this application all use a borderless display panel as an example.

[0022] Display area AA includes the first sub-display area A1 and the second sub-display area A2 that are adjacent in the first direction X. Figure 1 The diagram illustrates the display area with the first sub-display area A1 as the left side and the second sub-display area A2 as the right side. The display panel includes a first edge C1 extending along the second direction Y, with the two first edges C1 facing each other in the first direction X. For ease of distinction, Figure 1 C11 is the first edge of the first sub-display area A1, and C12 is the first edge of the second sub-display area A2.

[0023] The width of the display panel in the first direction X is D. The first center line L1 extends along the second direction Y. The distance between the first center line L1 and the first edge C1 is d1, where d1 = D / 4. It can be understood that the display panel is divided into left and right halves in the first direction, and the first center line L1 is the center line of each half. For ease of distinction, Figure 1L11 is the center line of the first sub-display area A1, and the distance between L11 and C11 is equal to D / 4. L12 is the center line of the second sub-display area A2, and the distance between L12 and C12 is equal to D / 4.

[0024] In this text, the first direction X intersects with the second direction Y. For example, the first direction X is the row direction, and the second direction Y is the column direction.

[0025] It should be noted that the first center line is located in the display area, and the first center line is parallel or approximately parallel to the first edge. The first center line does not represent the actual wiring of the display panel; it can be understood as a virtually defined center line of the display panel, that is, the first center line is used to indicate the position. The terms "equal to," "equal to," or "=" used to define two or more parameters in this document do not mean absolute equality, and a certain degree of error is allowed. It should be noted that the equality of distances mentioned in this disclosure refers to distance values ​​being equal within an allowable error range (±5%).

[0026] The gate driving circuit 10 of the display panel is located in the display area AA, and at least one gate driving circuit 10 is provided on each side of the first center line L1 in the first direction X.

[0027] For example, at least one gate driving circuit is disposed between the first center line L11 of the first sub-display area A1 and the first center line L12 of the second sub-display area A2.

[0028] As an example, in the first sub-display area A1, a first gate driving circuit 11 and a second gate driving circuit 12 are respectively arranged on both sides of the first center line L11 of the first sub-display area A1. In the second sub-display area A2, a first gate driving circuit 11 and a second gate driving circuit 12 are also respectively arranged on both sides of the first center line L12 of the second sub-display area A2.

[0029] The display panel provided in this application breaks with conventional design thinking. Instead of confining the gate driving circuit to the edge display area, the gate driving circuit is distributed on both sides of the first center line. This way, even if there are a large number of gate driving circuits, there is enough display area to accommodate them, thereby achieving narrow bezels or even bezel-less displays. In addition, compared with confining the gate driving circuit to the edge display area, distributing the gate driving circuit on both sides of the first center line can shorten the distance between at least part of the gate driving circuit and the center of the display area, thereby shortening the distance for the gate driving circuit to charge the center of the display area, thus improving signal delay and voltage drop, and improving display uniformity.

[0030] In some embodiments, such as Figure 1As shown, the distance between the second center line L2 and the first edge C1 in the first direction X of the display panel is d2, where d2 = D / 2. At least one gate driving circuit 10 is disposed between the first center line L1 and the second center line L2.

[0031] The second center line L2 is the dividing line between the first sub-display area A1 and the second sub-display area A2, and the widths of the first sub-display area A1 and the second sub-display area A2 are equal in the first direction X. It can be understood that the distance between the second center line L2 and the first edge C11 of the first sub-display area A1 is d2, and the distance between the second center line L2 and the first edge C12 of the second sub-display area A2 is also d2. This is equivalent to dividing the display panel into two half-screens in the first direction, with gate driving circuits provided on both sides of the first center line of each half-screen.

[0032] For example, the gate drive circuitry within each half-screen may be positioned close to its first centerline.

[0033] For example, Figure 1 In the first sub-display area A1, the two gate driving circuits are positioned close to its first center line L11, and in the second sub-display area A2, the two gate driving circuits are positioned close to its first center line L12.

[0034] in addition, Figure 1 The diagram illustrates a second gate driving circuit 12 disposed between the second center line L2 and the first center line L1. It can be understood that a second gate driving circuit 12 is disposed between the second center line L2 and the first center line L11 in the first sub-display area A1, and another second gate driving circuit 12 is disposed between the second center line L2 and the first center line L12 in the second sub-display area A2. Figure 1 The dashed line with arrows indicates the transmission path of the signal output by the second gate driving circuit 12. It can be seen that the transmission distance of the signal output by the second gate driving circuit 12 is only about one-quarter of the width D of the display panel.

[0035] Understandably, for any first gate driving circuit 11 or any second gate driving circuit 12, the transmission distance of its output signal is only about one-quarter of the width D of the display panel, which can more effectively shorten the charging distance of the gate driving circuit, thereby improving signal delay and voltage drop, and improving display uniformity.

[0036] The technical concept of this application can also be explained using the positional relationship between the gate driving circuit and the pixel.

[0037] In some embodiments, such as Figure 2As shown, the display panel 100 includes N pixel circuit columns 201 arranged in the first direction X, where N is an integer, and the pixel circuit columns 201 include a plurality of pixel circuits 20 arranged in the first direction X. The N / 4th pixel circuit column 201 (1 / 4) has at least one gate driving circuit 10 on each side in the first direction X, where N / 4 is an integer part.

[0038] In other words, the display panel includes N pixel columns arranged in a first direction, where N is an integer, and each pixel column includes multiple pixel circuits arranged in the first direction. At least one gate driving circuit is disposed on each side of the N / 4th pixel column in the first direction, where N / 4 is an integer.

[0039] like Figure 2 As shown, the pixel circuit columns are marked from left to right, with the N / 4th pixel circuit column 201 (1 / 4) and the 3N / 4th pixel circuit column 201 (3 / 4) marked respectively. It can be understood that the 3N / 4th pixel circuit column 201 (3 / 4) from left to right is the same as the N / 4th pixel circuit column 201 from right to left.

[0040] The N / 4th pixel circuit column 201 may include the N / 4th pixel circuit column 201 from left to right, and the N / 4th pixel circuit column 201 from right to left.

[0041] For example, in the direction from left to right, the N / 4th pixel circuit column 201 has at least one gate driving circuit 10 on each side of the first direction X, and in the direction from right to left, the N / 4th pixel circuit column 201 has at least one gate driving circuit 10 on each side of the first direction X.

[0042] For example, N=240, in the left-to-right direction, the 60th pixel circuit column has at least one gate driving circuit on each side of the first direction, and in the left-to-right direction, the 180th pixel circuit column has at least one gate driving circuit on each side of the first direction. Alternatively, N=240, in the right-to-left direction, the 60th pixel circuit column has at least one gate driving circuit on each side of the first direction, and in the right-to-left direction, the 180th pixel circuit column has at least one gate driving circuit on each side of the first direction.

[0043] This application embodiment improves the positional relationship between the gate driving circuit and the pixel circuit column, no longer confining the gate driving circuit to the edge display area, but distributing the gate driving circuit on both sides of the N / 4th pixel circuit column. In this way, even if there are a large number of gate driving circuits, there is enough display area to accommodate them, thereby achieving a borderless display. In addition, compared to confining the gate driving circuit to the edge display area, distributing the gate driving circuit on both sides of the N / 4th pixel circuit column can shorten the distance between at least part of the gate driving circuit and the center of the display area, thereby shortening the distance for the gate driving circuit to charge the center of the display area, thereby improving signal delay and voltage drop, and improving display uniformity.

[0044] In some embodiments, such as Figure 2 As shown, along the first direction X, at least one gate driving circuit 10 is included between the N / 4th pixel circuit column 201(1 / 4) and the N / 2th pixel circuit column 201(1 / 2), wherein N / 2 is an integer part.

[0045] In other words, along the first direction X, at least one gate driving circuit 10 is included between the N / 4th pixel column and the N / 2th pixel column, wherein N / 2 is an integer part.

[0046] The N / 2nd pixel circuit column can be understood as the pixel circuit column located at the center of the entire display area. The N / 4th pixel circuit column of the left half of the display area can be understood as the pixel circuit column located at the center of the left half of the display area, and the N / 4th pixel circuit column of the right half of the display area can be understood as the pixel circuit column located at the center of the right half of the display area.

[0047] For example, Figure 2 In the left half of the display area, two gate driving circuits are respectively arranged on both sides of pixel circuit column 201 (1 / 4), and in the right half of the display area, two gate driving circuits are respectively arranged on both sides of pixel circuit column 201 (3 / 4). For example, a second gate driving circuit 12 is arranged between pixel circuit column 201 (1 / 4) and pixel circuit column 201 (1 / 2), and a second gate driving circuit 12 is arranged between pixel circuit column 201 (3 / 4) and pixel circuit column 201 (1 / 2). Figure 2 The dashed line with arrows indicates the transmission path of the signal output by the second gate driving circuit 12. It can be seen that the transmission distance of the signal output by the second gate driving circuit 12 is only about one-quarter of the width D of the display panel.

[0048] Similarly, for any first gate driving circuit 11 or any second gate driving circuit 12, the transmission distance of its output signal is only about one-quarter of the width D of the display panel, which can more effectively shorten the charging distance of the gate driving circuit, thereby improving signal delay and voltage drop and improving display uniformity.

[0049] Understandably, the signal output by the gate drive circuit is transmitted to the pixel circuit, and the signal output by the gate drive circuit is used to control the transistors in the pixel circuit to turn on or off.

[0050] The gate drive circuit may include multiple cascaded shift registers, which are arranged along the second direction in the same gate drive circuit.

[0051] In some embodiments, such as Figure 3 As shown, the display panel includes a partition area Q, a first center line L1 located in the partition area Q, and at least one gate driving circuit 10 is provided on each side of the partition area Q in the first direction X. The width of the partition area Q in the first direction X is less than or equal to 625um.

[0052] For example, the partition area within the first sub-display area A1 is a first partition area Q1, with the center line L11 located in the first partition area Q1, and at least one gate driving circuit 10 is provided on each of the left and right sides of the first partition area Q1. The partition area within the second sub-display area A2 is a second partition area Q2, with the center line L11 located in the second partition area Q2, and at least one gate driving circuit 10 is provided on each of the left and right sides of the second partition area Q2.

[0053] In this embodiment, the gate driving circuits on the left and right sides of the partition are separated, that is, the gate driving circuits are not arranged adjacent to each other, which can reduce signal interference between different gate driving circuits.

[0054] In some embodiments, such as Figure 4 As shown, the display panel includes N pixel circuit columns 201 arranged in the first direction X, and the pixel circuit columns 201 include a plurality of pixel circuits 20 arranged in the second direction Y; the N / 4th pixel circuit column 201 (1 / 4) is located in the partition area Q1.

[0055] Figure 4 The 3N / 4th pixel circuit column 201(3 / 4) from left to right is the N / 4th pixel circuit column from right to left. Figure 4 The middle dividing area Q may also include a first dividing area Q1 and a second dividing area Q2, with pixel circuit column 201 (1 / 4) located in the first dividing area Q1 and pixel circuit column 201 (3 / 4) located in the second dividing area Q2.

[0056] In this embodiment, the gate driving circuits on the left and right sides of the partition are separated, and the pixel circuit is set in the partition, which can avoid wasting space.

[0057] In some embodiments, such as Figures 5 to 7As shown in any of the accompanying drawings, the pixel circuit 20 of the display panel includes an amplitude modulation sub-circuit 21 and a pulse width modulation sub-circuit 22, and the gate driving circuit includes a first gate driving circuit 11 and a second gate driving circuit 12. The gate signal output by the first gate driving circuit 11 is used to control the first data signal PAM_data to be written into the amplitude modulation sub-circuit 21, and the gate signal output by the second gate driving circuit 12 is used to control the second data signal PWM_data to be written into the pulse width modulation sub-circuit 22.

[0058] To meet the driving requirements of high-resolution display panels, such as micro LED or organic light-emitting diode (OLED) display panels, a pixel circuit combining pulse amplitude modulation (PAM) and pulse width modulation (PWM) is used to control the driving current intensity and duration to control the light-emitting state of the light-emitting element.

[0059] Amplitude modulation sub-circuit 21 and pulse width modulation sub-circuit 22 are connected. Pixel circuit 20 generates drive current under the control of amplitude modulation sub-circuit 21 and pulse width modulation sub-circuit 22. Amplitude modulation sub-circuit 21 can be used to control the amplitude of the drive current, and pulse width modulation sub-circuit 22 can be used to adjust the pulse width of the voltage applied to the first electrode of light-emitting element 30.

[0060] The pulse width modulation sub-circuit 22 adjusts the pulse width of the voltage applied to the first electrode of the light-emitting element 30, that is, it adjusts the actual emission period of the driving current applied to the light-emitting element 30. Simultaneously, it maintains the driving current applied to the light-emitting element at a constant level to adjust the grayscale or brightness displayed by the light-emitting element, rather than simply adjusting the magnitude of the driving current applied to the light-emitting element. Therefore, the amplitude modulation sub-circuit 21 can provide driving current to the light-emitting element so that the light-emitting element is driven with optimal luminous efficiency, and the pulse width modulation sub-circuit 22 adjusts the emission duty cycle (i.e., the emission period of the light-emitting element) of the light-emitting element to adjust the grayscale or brightness displayed by the light-emitting element.

[0061] In the accompanying drawings of this application, PAM_S2 represents the gate signal output by the first gate drive circuit 11, PWM_S2 represents the gate signal output by the second gate drive circuit 12, PAM_data represents the first data signal, and PWM_data represents the second data signal.

[0062] It should be noted that, Figures 5 to 7The circuit structure shown is merely exemplary and is not intended to limit this application. Regardless of the specific structure of the amplitude modulation sub-circuit and pulse width modulation sub-circuit in the pixel circuit, both typically require the writing of data signals. Therefore, the design concept of the gate drive circuit in this application can also be applied to... Figures 5 to 7 Pixel circuits with other structural forms besides the circuit structure shown.

[0063] In some embodiments, such as Figure 8 As shown, in the first direction X, the first gate driving circuit 11 is located on the side of the first center line L1 closer to the second center line L2, and the second gate driving circuit 12 is located on the side of the first center line L1 away from the second center line L2.

[0064] Or, such as Figure 1 As shown, in the first direction X, the first gate driving circuit 11 is located on the side of the first center line L1 away from the second center line L2, and the second gate driving circuit 12 is located on the side of the first center line L1 close to the second center line L2.

[0065] For example, such as Figure 1 or Figure 8 As shown, a first gate driving circuit 11 and a second gate driving circuit 12 are provided on both sides of the second center line L2. The two first gate driving circuits 11 on both sides of the second center line L2 are symmetrical about the second center line L2, and the two second gate driving circuits 12 on both sides of the second center line L2 are symmetrical about the second center line L2. In this way, the signal output by the first gate driving circuit and the second gate driving circuit can be distributed relatively evenly, thereby improving the display uniformity.

[0066] like Figure 8 As shown, in the first direction X, the distance between the first gate driving circuit 11 and the first center line L1 is marked as d3, and the distance between the second gate driving circuit 12 and the first center line L1 is marked as d4. It should be noted that... Figure 8 In this context, d3 and d4 are only used to indicate the distance between the gate drive circuit and the first center line, and are not used to define the size of d3 and d4.

[0067] In some embodiments, d3 = d4.

[0068] For example, if the signals output by the first gate driving circuit and the second gate driving circuit are the same, and d3=d4, the first gate driving circuit and the second gate driving circuit can be distributed relatively evenly. For the entire display area, the signal delay and voltage drop output by the first gate driving circuit and the second gate driving circuit will be relatively uniform, thereby improving the display uniformity.

[0069] In other embodiments, d3 ≠ d4.

[0070] The driving requirements of the amplitude modulation sub-circuit and the pulse width modulation sub-circuit can be different, so the output signals of the first gate driving circuit and the second gate driving circuit can be different. In the case of d3≠d4, the relative distribution positions of the first gate driving circuit and the second gate driving circuit can be flexibly adjusted to flexibly match the different driving requirements of the amplitude modulation sub-circuit and the pulse width modulation sub-circuit.

[0071] As an example, d3 < d4.

[0072] The closer the gate driving circuit is to the first center line, the closer its output signal path is to one-quarter of the display panel width, resulting in lower signal delay and voltage drop. The amplitude modulation sub-circuit has a relatively large impact on luminous brightness, and the gate signal output by the first gate driving circuit is used to control the writing of data signals to the amplitude modulation sub-circuit; therefore, the signal of the first gate driving circuit has a relatively large impact on luminous brightness. When d3 < d4, placing the first gate driving circuit closer to the first center line results in relatively lower signal delay and voltage drop, thus improving display uniformity.

[0073] Understandably, in other examples, if a relatively low signal delay and voltage drop are required for the second gate drive circuit, the second gate drive circuit can be positioned closer to the first centerline.

[0074] Both the first and second gate driving circuits include input and output terminals. The input terminal of the gate driving circuit can be used to receive at least one of the following: a clock signal (CK, CKB), a trigger signal (STV), a fixed voltage signal (VGH and / or VGL), and a reset signal (Reset). The output terminal of the gate driving circuit outputs a gate signal used to control the pixel circuit. The output terminal of the gate driving circuit is electrically connected to the pixel circuit. For example, one output terminal of the gate driving circuit is electrically connected to multiple pixel circuits located in the same row.

[0075] Understandably, when first gate driving circuits are provided on both sides of the second center line, the closer the output terminal of the first gate driving circuit is to the first center line, the closer the path of the signal output by the first gate driving circuit is to one-quarter of the width of the display panel, and the same applies to the second gate driving circuit.

[0076] In some embodiments, in the first direction, the input terminal of the first gate driving circuit is closer to the first center line, and the input terminal of the second gate driving circuit is closer to the first center line. This also makes the path of the signal transmitted at the output terminal of the first gate driving circuit closer to one-quarter of the width of the display panel.

[0077] In some embodiments, such as Figure 9 As shown, the first gate driving circuit 11 is connected to multiple first signal lines 41. In the first direction X, the number of first signal lines 41 distributed on the side of the first gate driving circuit 11 close to the first center line L1 is n1, and the number of first signal lines 41 distributed on the side of the first gate driving circuit 11 away from the first center line L1 is n2, where n1 < n2.

[0078] The second gate driving circuit 12 is connected to multiple second signal lines 42. In the first direction X, the number of second signal lines 42 distributed on the side of the second gate driving circuit 12 closer to the first center line L1 is n3, and the number of second signal lines 42 distributed on the side of the second gate driving circuit 12 away from the first center line L1 is n4, where n3 < n4.

[0079] The first signal line 41 and the second signal line 42 both extend along the second direction Y. At least a portion of the signals of the multiple signal lines connected to the gate drive circuit are connected to the drive chip, and the signals output by the drive chip are transmitted to the gate drive circuit to control the gate drive circuit.

[0080] Figure 9 In this diagram, the signal lines distributed on the side of the first gate driving circuit 11 closest to the first neutral line L1 are labeled as signal lines 411, and the signal lines distributed on the side of the first gate driving circuit 11 furthest from the first neutral line L1 are labeled as signal lines 412 and 413, respectively. For example, signal line 411 can be used for fixed voltage signals or other signals, and signal lines 412 and 413 can be used to transmit two clock signals or other signals with misaligned timing.

[0081] Figure 9 In this diagram, the signal lines distributed on the side of the second gate driving circuit 12 closest to the first neutral line L1 are labeled as signal lines 421, and the signal lines distributed on the side of the second gate driving circuit 12 furthest from the first neutral line L1 are labeled as signal lines 422 and 423, respectively. For example, signal line 421 can be used for fixed voltage signals or other signals, while signal lines 422 and 423 can be used to transmit two clock signals or other signals with misaligned timing.

[0082] It should be noted that, Figure 9The number of signal lines shown is merely exemplary and is not intended to limit this application.

[0083] In this embodiment, the number of first signal lines distributed on the side of the first gate driving circuit closest to the first neutral line is relatively small. This allows for a smaller space between the first gate driving circuit and the first neutral line, meaning the first gate driving circuit can be positioned closer to the first neutral line, thereby reducing the delay and voltage drop of the output signal. Similarly, the number of second signal lines distributed on the side of the second gate driving circuit closest to the first neutral line is relatively small. This allows for a smaller space between the second gate driving circuit and the first neutral line, meaning the second gate driving circuit can be positioned closer to the first neutral line, thereby reducing the delay and voltage drop of the output signal.

[0084] The pixel circuit may include a data writing module, a gate reset module, an anode reset module, etc. The data writing module is used to write data signals, and the degree of writing of data signals directly affects the brightness. That is, compared with other functional modules, the data writing module has a greater impact on the brightness. Therefore, the signal of the gate drive circuit that controls the data writing module has a greater impact on the brightness.

[0085] In response to this, in some embodiments, such as Figure 10 The gate driving circuit 10 includes a first type of gate driving circuit 10a and other types of gate driving circuits 10d. The gate signal output by the first type of gate driving circuit 10a is used to control the writing of data signals into the pixel circuit. In the first direction X, the distance between the first type of gate driving circuit 10a and the first center line L1 is smaller than the distance between the other types of gate driving circuits 10d and the first center line L1. This makes the first type of gate driving circuit closer to the first center line, resulting in relatively lower delay and voltage drop of the output signal of the first type of gate driving circuit, thereby improving display uniformity.

[0086] For example, for the first type of gate driving circuit 10a and other type of gate driving circuit 10d located on the same side of the first center line L1, the first type of gate driving circuit 10a is located between the first center line L1 and other type of gate driving circuit 10d.

[0087] For example, the first type of gate driving circuit 10a includes the first gate driving circuit 11 and the second gate driving circuit 12 described above. At least one other type of gate driving circuit 10d may be distributed on the side of the first gate driving circuit 11 away from the first center line L1, and at least one other type of gate driving circuit 10d may also be distributed on the side of the second gate driving circuit 12 away from the first center line L1. At least two other type of gate driving circuits 10d on the same side of the second center line L2 are used to control different functional modules in the pixel circuit. For example, one other type of gate driving circuit 10d is used to control the writing of a reset signal to the pixel circuit, another other type of gate driving circuit 10d is used to control the writing of a light emission control signal to the pixel circuit, and another other type of gate driving circuit 10d is used to provide a sweep frequency signal (SWEEP), etc.

[0088] In some embodiments, such as Figure 11 As shown, the gate driving circuit 10 includes a first type of gate driving circuit 10a, a second type of gate driving circuit 10b, and a third type of gate driving circuit 10c. The gate signal output by the first type of gate driving circuit 10a is used to control the writing of data signals into the pixel circuit. The gate signal output by the second type of gate driving circuit 10b is used to control the writing of reset signals into the pixel circuit. The third type of gate driving circuit 10c is used to output a sweep frequency signal and / or a light emission control signal. The third type of gate driving circuit 10c is spaced between the first type of gate driving circuit 10a and the second type of gate driving circuit 10b in the first direction X.

[0089] For example, please refer to the reference. Figure 11 ,as well as Figures 5 to 7 Any of the following: the gate signals output by the first type of gate drive circuit 10a include PAM_S2 and PWM_S2; the gate signals output by the second type of gate drive circuit 10b include PAM_S1 and PWM_S1; and the gate signals output by the third type of gate drive circuit 10c include PAM_EM, PWM_EM, and SWEEP. PAM_REF1, PAM_REF2, PWM_REF1, and PWM_REF2 represent reset signals.

[0090] For example, please refer to Figure 11In the first direction X, the display area AA is divided into four sub-areas: the first sub-area A11, the second sub-area A12, the third sub-area A22, and the fourth sub-area A21. The first sub-area A11 and the second sub-area A12 are separated by the center line L11, the third sub-area A22 and the fourth sub-area A21 are separated by the center line L12, and the second sub-area A12 and the third sub-area A22 are separated by the second center line L2. Each sub-area may contain a first type of gate driving circuit 10a, a second type of gate driving circuit 10b, and a third type of gate driving circuit 10c. The distribution pattern within each sub-area is as follows: the third type of gate driving circuit 10c is located between the first type of gate driving circuit 10a and the second type of gate driving circuit 10b.

[0091] As described above, the closer the gate driving circuit is to the first center line, the shorter the distance the output signal can travel. The writing of data signals directly affects the magnitude of the driving current, having the greatest impact on brightness. The light emission control signal and the frequency sweep signal affect the light emission duration of the light-emitting element, with a secondary impact on brightness. The reset signal has the least impact on brightness. In this embodiment, the first type of gate driving circuit, which has the greatest impact on brightness, is positioned closest to the first center line; the second type of gate driving circuit, which has the least impact on brightness, is positioned furthest from the first center line; and the third type of gate driving circuit is positioned in between. This arrangement matches the importance of each type of gate driving circuit in terms of brightness, which is more conducive to optimizing display uniformity.

[0092] In some embodiments, please refer to Figure 11 and Figure 5 The pixel circuit 20 includes an amplitude modulation sub-circuit 21 and a pulse width modulation sub-circuit 22. The second type of gate driving circuit 10b includes a third gate driving circuit 13 and a fourth gate driving circuit 14. The gate signal output by the third gate driving circuit 13 is PAM_S1, and the gate signal output by the fourth gate driving circuit 14 is PWM_S1. The gate signal output by the third gate driving circuit 13 is used to control the reset signal PAM_REF1 to be written into the amplitude modulation sub-circuit 21, and the gate signal output by the fourth gate driving circuit 14 is used to control the reset signal PWM_REF1 to be written into the pulse width modulation sub-circuit 22. In the first direction X, the third gate driving circuit 13 and the fourth gate driving circuit 14 are located on both sides of the first centerline L1.

[0093] For example, such as Figure 11As shown, for the display area on the same side of the second center line L2, the third gate driving circuit 13 is located on the side of the first center line L1 closer to the second center line L2, and the fourth gate driving circuit 14 is located on the side of the first center line L1 farther from the second center line L2. In other examples, the third gate driving circuit 13 may be located on the side of the first center line L1 farther from the second center line L2, and the fourth gate driving circuit 14 may be located on the side of the first center line L1 closer to the second center line L2.

[0094] For example, such as Figure 5 As shown, the writing of the reset signal PAM_REF2 can be controlled by the gate signal PAM_S2 or PAM_S1, and the writing of the reset signal PWM_REF2 can be controlled by the gate signal PWM_S2 or PWM_S1. As described above, the gate signal PAM_S2 is provided by the first gate drive circuit, and the gate signal PWM_S2 is provided by the second gate drive circuit.

[0095] In this embodiment, for the display area on the same side of the second center line L2, the third gate driving circuit 13 and the fourth gate driving circuit 14, which have the least impact on brightness, are located on both sides of the first center line L1. This provides space on both sides of the first center line L1 to place other gate driving circuits that have a relatively large impact on brightness, thus optimizing the overall layout.

[0096] In some embodiments, please refer to Figure 11 and Figure 5 The pixel circuit 20 includes an amplitude modulation sub-circuit 21 and a pulse width modulation sub-circuit 22. The third type of gate driving circuit 10c includes a fifth gate driving circuit 15, a sixth gate driving circuit 16, and a seventh gate driving circuit 17. The fifth gate driving circuit 15 is used to output a first light emission control signal PAM_EM, the sixth gate driving circuit 16 is used to output a second light emission control signal PWM_EM, and the seventh gate driving circuit 17 is used to output a sweep frequency signal SWEEP. The fifth gate driving circuit 15 is electrically connected to the amplitude modulation sub-circuit 21, and the sixth gate driving circuit 16 and the seventh gate driving circuit 17 are electrically connected to the pulse width modulation sub-circuit 22. In the first direction X, the fifth gate driving circuit 15 and the sixth gate driving circuit 16 are adjacent to each other.

[0097] The gate signals output by the fifth gate driving circuit 15 and the sixth gate driving circuit 16 are both used to control the light emission time. The two circuits are arranged adjacent to each other, which makes their signal delay and voltage drop more consistent, thereby avoiding large differences in their control of the light emission time.

[0098] For example, a fifth gate driving circuit 15 and a sixth gate driving circuit 16 are respectively provided on both sides of the second center line L2, and the fifth gate driving circuit 15 and the sixth gate driving circuit 16 are adjacent to each other on either side of the second center line L2.

[0099] In some embodiments, please refer to Figure 11 In the first direction X, the fifth gate drive circuit 15 and the sixth gate drive circuit 16 are located on one side of the first center line L1, and the seventh gate drive circuit 17 is located on the other side of the first center line L1.

[0100] For example, the fifth gate driving circuit 15 and the sixth gate driving circuit 16 are located on the side of the first center line L1 closer to the second center line L2, and the seventh gate driving circuit 17 is located on the side of the first center line L1 away from the second center line L2. Of course, in other examples, the fifth gate driving circuit 15 and the sixth gate driving circuit 16 may be located on the side of the first center line L1 away from the second center line L2, and the seventh gate driving circuit 17 may be located on the side of the first center line L1 closer to the second center line L2.

[0101] The fifth gate driving circuit 15, the sixth gate driving circuit 16, and the seventh gate driving circuit 17 have a similar impact on brightness. If all three are located on the same side of the first center line, one of them will inevitably be farther from the first center line. The farther away from the first center line, the greater the signal delay and voltage drop. However, in this embodiment, the three are distributed on both sides of the first center line, so that the distances of the three from the first center line tend to be consistent, thereby making the signal delay and voltage drop of the three tend to be consistent as well, thus optimizing display uniformity.

[0102] In some embodiments, such as Figure 12 As shown, the display panel 100 includes two sub-display areas arranged in the first direction X, each sub-display area including a first center line L1. The two sub-display areas are a first sub-display area A1 and a second sub-display area A2, the first center line of the first sub-display area A1 is L11, and the first center line of the second sub-display area A2 is L12.

[0103] The gate driving circuit includes a target gate driving circuit 101. The same sub-display area includes n target gate driving circuits 101 that output the same gate signal. The n target gate driving circuits 101 in the sub-display area are evenly distributed in the first direction X, and n≥2.

[0104] Figure 12The diagram illustrates that each sub-display area includes two target gate driving circuits 101. For the first sub-display area A1, it includes a one-third line L31 and a two-thirds line L32. The distance between the one-third line L31 and the two-thirds line L32 is d31. The distance between the one-third line L31 and the edge C11 is d31. The distance between the two-thirds line L32 and the second center line L2 is d31. d31 is one-third of the display panel width D. One target gate driving circuit 101 can be located at the one-third line L31, and the other target gate driving circuit 101 can be located at the two-thirds line L32.

[0105] Similarly, for the second sub-display area A2, it includes a one-third line L41 and a two-thirds line L42. The distance between the one-third line L41 and the two-thirds line L42 is d31. The distance between the one-third line L41 and the edge C12 is d31. The distance between the two-thirds line L42 and the second center line L2 is d31. d31 is one-third of the width D of the display panel. One target gate driving circuit 101 may be disposed at the one-third line L41, and the other target gate driving circuit 101 may be disposed at the two-thirds line L42.

[0106] The more gate drive circuits that output the same gate signal, the stronger the driving capability. Furthermore, the uniform distribution of n target gate drive circuits 101 can minimize the delay and voltage drop of the output signal of the target gate drive circuit 101.

[0107] The more gate drive circuits that output the same gate signal, the stronger the driving capability, but the more space they occupy. For example, considering both driving capability and layout design, n can be no greater than 4.

[0108] In some embodiments, all n target gate driving circuits 101 are used to output a sweep frequency signal SWEEP; or, all n target gate driving circuits 101 are used to output a first emission control signal PAM_EM for the amplitude modulation sub-circuit in the control pixel circuit.

[0109] In other words, the target gate driving circuit 101 can be the seventh gate driving circuit 17 mentioned above, or the target gate driving circuit 101 can be the fifth gate driving circuit 15 mentioned above.

[0110] Compared to other gate driving circuits, the seventh gate driving circuit 17 and the fifth gate driving circuit 15 have relatively large parasitic capacitances. Parasitic capacitances affect their driving capabilities. Therefore, by setting multiple seventh gate driving circuits 17 or multiple fifth gate driving circuits 15 in the sub-display area, the driving capabilities of each gate driving circuit can be balanced.

[0111] In some embodiments, the n target gate driving circuits 101 include n first gate driving circuits 11, and the gate signal PAM_S2 output by the n first gate driving circuits 11 is used to control the first data signal PAM_data to be written into the amplitude modulation sub-circuit 21; and / or, the n target gate driving circuits 101 include n second gate driving circuits 12, and the gate signal PWM_S2 output by the n second gate driving circuits 12 is used to control the second data signal PWM_data to be written into the pulse width modulation sub-circuit.

[0112] As mentioned above, the writing of data signals has a significant impact on brightness. Therefore, setting multiple first gate driving circuits and / or multiple second gate driving circuits in the sub-display area can enhance the driving capability of the first gate driving circuits and / or the second gate driving circuits, enabling more effective control over the writing of data signals.

[0113] As an example, such as Figure 13 As shown, each sub-display area includes two first gate driving circuits 11 and two second gate driving circuits 12, arranged in the order of second gate driving circuit 12, first gate driving circuit 11, first center line L1, first gate driving circuit 11, and second gate driving circuit 12.

[0114] As another example, such as Figure 14 As shown, each sub-display area includes two first gate driving circuits 11 and two second gate driving circuits 12, arranged in the order of first gate driving circuit 11, second gate driving circuit 12, first center line L1, first gate driving circuit 11, and second gate driving circuit 12.

[0115] As yet another example, such as Figure 15 As shown, each sub-display area includes two first gate driving circuits 11 and two second gate driving circuits 12, arranged in the order of first gate driving circuit 11, second gate driving circuit 12, first center line L1, second gate driving circuit 12, and first gate driving circuit 11.

[0116] As yet another example, such as Figure 16 As shown, each sub-display area includes two first gate driving circuits 11 and two second gate driving circuits 12, arranged in the order of second gate driving circuit 12, first gate driving circuit 11, first center line L1, second gate driving circuit 12, and first gate driving circuit 11.

[0117] The above are merely examples and are not intended to limit this application. The arrangement order of multiple first gate drive circuits and multiple second gate drive circuits can also be set in other ways, which will not be listed here.

[0118] In some embodiments, such as Figure 11 As shown, the display panel 100 includes two sub-display areas arranged in the first direction X, each sub-display area including a first center line L1. The two sub-display areas are a first sub-display area A1 and a second sub-display area A2, the first center line of the first sub-display area A1 is L11, and the first center line of the second sub-display area A2 is L12.

[0119] Along the first direction X, each of the two sub-display areas includes m gate driving circuits 10, the m gate driving circuits 10 are respectively the K1 gate driving circuit to the Km gate driving circuit, the gate signals output by the Kj gate driving circuit in the first sub-display area and the Kj gate driving circuit in the second sub-display area are the same, m≥2, and Kj is any one of K1 to Km; In the first direction X, the gate driving circuits from K1 to Km in the first sub-display area are arranged close to the second center line L2, and the gate driving circuits from K1 to Km in the second sub-display area are arranged away from the second center line L2. The second center line L2 is the dividing line between the two sub-display areas.

[0120] Figure 11 In the diagram, m is represented as 7. The fourth gate drive circuit 14 is the K1 gate drive circuit, and the third gate drive circuit 13 is the Km gate drive circuit.

[0121] It is understood that in the embodiments of this application, the arrangement order of the gate driving circuits of the two sub-display areas is symmetrical, so the transmission path of the output signal of the gate driving circuits of the two sub-display areas is also symmetrical, which is more conducive to optimizing display uniformity.

[0122] Of course, the gate drive circuits can also be arranged in other orders.

[0123] As an example, within the same sub-display area, in the first direction, the third gate drive circuit 13 (output signal PAM_S1), the seventh gate drive circuit 17 (output signal SWEEP), the second gate drive circuit 12 (output signal PWM_S2), the first neutral line L1, the first gate drive circuit 11 (output signal PAM_S2), the sixth gate drive circuit 16 (output signal PWM_EM), the fifth gate drive circuit 15 (output signal PAM_EM), and the fourth gate drive circuit 14 (output signal PWM_S1) are arranged in that order.

[0124] As another example, within the same sub-display area, in the first direction, the circuits are arranged in the following order: fourth gate drive circuit 14 (output signal PWM_S1), second gate drive circuit 12 (output signal PWM_S2), first neutral line L1, first gate drive circuit 11 (output signal PAM_S2), seventh gate drive circuit 17 (output signal SWEEP), sixth gate drive circuit 16 (output signal PWM_EM), fifth gate drive circuit 15 (output signal PAM_EM), and third gate drive circuit 13 (output signal PAM_S1).

[0125] As another example, within the same sub-display area, in the first direction, the fourth gate drive circuit 14 (output signal PWM_S1), the sixth gate drive circuit 16 (output signal PWM_EM), the fifth gate drive circuit 15 (output signal PAM_EM), the second gate drive circuit 12 (output signal PWM_S2), the first neutral line L1, the first gate drive circuit 11 (output signal PAM_S2), the seventh gate drive circuit 17 (output signal SWEEP), and the third gate drive circuit 13 (output signal PAM_S1) are arranged in that order.

[0126] The above only shows some of the layout methods; the layout order of each gate drive circuit will not be listed here.

[0127] In some embodiments, such as Figure 11 As shown, the display panel 100 includes two sub-display areas arranged in the first direction X, each sub-display area including a first center line L1. The two sub-display areas are a first sub-display area A1 and a second sub-display area A2, the first center line of the first sub-display area A1 is L11, and the first center line of the second sub-display area A2 is L12.

[0128] The sub-display area includes multiple gate driving circuits 10, which are arranged at unequal intervals in the first direction X.

[0129] The circuit architecture of gate drive circuits used to provide different gate signals will differ. Therefore, the layout area required for gate drive circuits with different functions or the number of signal lines required to be connected will differ. When the gate drive circuits are arranged at unequal intervals, it is easier to make the arrangement of each gate drive circuit achieve a reasonable design.

[0130] As an example, any two adjacent gate drive circuits 10 constitute a circuit group, the distance between the two gate drive circuits 10 in at least one circuit group in the first direction X is d11, and the distance between the two gate drive circuits 10 in at least another circuit group in the first direction X is d12, where d11 ≠ d12.

[0131] Specifically, the spacing between each gate drive circuit can be set according to actual needs, and this application does not limit this.

[0132] As another example, any two adjacent gate drive circuits constitute a circuit group, and at least one pixel circuit column is distributed between the two gate drive circuits in the circuit group. Figure 17 The number of pixel circuit columns distributed between the two gate drive circuits in at least another circuit group is m1 (not shown in the diagram), and m2 is m1 ≠ m2.

[0133] When multiple gate driving circuits 10 within the same sub-display area are arranged at unequal intervals, the space between the gate driving circuits varies. For circuits with larger intervals, the space between the gate driving circuits is larger, allowing for the placement of more pixel circuit columns, thus making efficient use of every space. For circuits with smaller intervals, the space between the gate driving circuits is smaller, allowing for the placement of fewer pixel circuit columns. However, placing too many pixel circuit columns in a small space would make the pixel circuit columns too crowded, leading to crosstalk or interference in the signal; or it would necessitate reducing the size of the pixel circuits, resulting in a decrease in pixel circuit performance. The embodiments of this application avoid these situations.

[0134] In some embodiments, such as Figure 2 or Figure 4 As shown, the display area includes a pixel circuit 20, and the orthographic projection of the pixel circuit 20 on the plane where the display panel is located and the orthographic projection of the gate driving circuit 10 on the plane where the display panel is located do not overlap.

[0135] In this embodiment, the pixel circuits are no longer arranged in close rows, but rather space is left between the columns of pixel circuits, so that there is space in the display area to place the gate driving circuit, thus enabling the gate driving circuit to be placed in the display area and achieving a borderless design.

[0136] In some embodiments, the pixel circuits 20 in different areas have the same size. For example, the size of the pixel circuits in the entire display area is reduced overall. After the size of the pixel circuits is reduced, there is a certain space between the columns of pixel circuits, and the gate driving circuit is disposed in the gap between the columns of pixel circuits.

[0137] If the size of the pixel circuits in only a portion of the area is reduced, the driving capability of the pixel circuits in different areas will vary, resulting in poor display uniformity. However, in this embodiment, the size of the pixel circuits throughout the entire display area is reduced, but the size of each pixel circuit remains the same after the reduction. Therefore, the driving capability of the pixel circuits in each area remains consistent and will not affect display uniformity.

[0138] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 18 , Figure 18 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 18 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 18 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0139] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, include: Display area; A pixel circuit, the pixel circuit including an amplitude modulation sub-circuit and a pulse width modulation sub-circuit; A gate driving circuit, wherein the gate driving circuit is located in the display area; The gate driving circuit includes a first type of gate driving circuit, a second type of gate driving circuit, and a third type of gate driving circuit. The first type of gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit is connected to the amplitude modulation sub-circuit and transmits a first data signal to the amplitude modulation sub-circuit. The second gate driving circuit is connected to the pulse width modulation sub-circuit and transmits a second data signal to the pulse width modulation sub-circuit. The second type of gate driving circuit includes a third gate driving circuit and a fourth gate driving circuit. The third gate driving circuit is connected to the amplitude modulation sub-circuit and transmits a reset signal to the amplitude modulation sub-circuit. The fourth gate driving circuit is connected to the pulse width modulation sub-circuit and transmits a reset signal to the pulse width modulation sub-circuit. The third type of gate driving circuit includes a fifth gate driving circuit, a sixth gate driving circuit, and a seventh gate driving circuit. The fifth gate driving circuit is connected to the amplitude modulation sub-circuit and transmits a first light emission control signal to the amplitude modulation sub-circuit. The sixth gate driving circuit and the seventh gate driving circuit are connected to the pulse width modulation sub-circuit. The sixth gate driving circuit transmits a second light emission control signal to the pulse width modulation sub-circuit, and the seventh gate driving circuit transmits a sweep frequency signal to the pulse width modulation sub-circuit. Within the display area, the first gate driving circuit, the second gate driving circuit, the third gate driving circuit, the fourth gate driving circuit, the fifth gate driving circuit, the sixth gate driving circuit, and the seventh gate driving circuit are arranged along a first direction; The gate driving circuit includes multiple cascaded shift registers. In the same gate driving circuit, the multiple shift registers are arranged along a second direction, and the first direction intersects with the second direction.

2. The display panel according to claim 1, characterized in that, Along the first direction, the fifth gate driving circuit and the sixth gate driving circuit are adjacent to each other.

3. The display panel according to claim 1, characterized in that, Along the first direction, the third type of gate driving circuit is spaced between the first type of gate driving circuit and the second type of gate driving circuit.

4. The display panel according to claim 1, characterized in that, The display panel includes a first sub-display area and a second sub-display area arranged along the first direction; The first sub-display area includes a first gate driving circuit, a second gate driving circuit, a third gate driving circuit, a fourth gate driving circuit, a fifth gate driving circuit, a sixth gate driving circuit, and a seventh gate driving circuit arranged along the first direction. The second sub-display area includes a first gate driving circuit, a second gate driving circuit, a third gate driving circuit, a fourth gate driving circuit, a fifth gate driving circuit, a sixth gate driving circuit, and a seventh gate driving circuit arranged along the first direction.

5. The display panel according to claim 4, characterized in that, The arrangement order of the gate driving circuits in the first sub-display area and the second sub-display area is symmetrical.

6. The display panel according to claim 1, characterized in that, The display panel includes two sub-display areas arranged along the first direction; Within the same sub-display area, along the first direction, the third gate driving circuit, the seventh gate driving circuit, the second gate driving circuit, the first gate driving circuit, the sixth gate driving circuit, the fifth gate driving circuit, and the fourth gate driving circuit are arranged in sequence.

7. The display panel according to claim 1, characterized in that, The display panel includes two sub-display areas arranged along the first direction; Within the same sub-display area, along the first direction, the fourth gate driving circuit, the second gate driving circuit, the first gate driving circuit, the seventh gate driving circuit, the sixth gate driving circuit, the fifth gate driving circuit, and the third gate driving circuit are arranged in sequence.

8. The display panel according to claim 1, characterized in that, The display panel includes two sub-display areas arranged along the first direction; Within the same sub-display area, along the first direction, the fourth gate driving circuit, the sixth gate driving circuit, the fifth gate driving circuit, the second gate driving circuit, the first gate driving circuit, the seventh gate driving circuit, and the third gate driving circuit are arranged in sequence.

9. The display panel according to claim 1, characterized in that, The display panel includes two sub-display areas arranged along the first direction; The gate driving circuit includes a target gate driving circuit, and the same sub-display area includes n target gate driving circuits that output the same type of gate signal, where n≥2.

10. The display panel according to claim 1, characterized in that, The display panel includes two sub-display areas arranged along the first direction; The gate driving circuit includes a target gate driving circuit, and the same sub-display area includes at least two of the target gate driving circuits. The display panel satisfies at least one of the following: The target gate driving circuit is the fifth gate driving circuit; or, The target gate driving circuit is the seventh gate driving circuit.

11. The display panel according to claim 1, characterized in that, The display panel includes two sub-display areas arranged along the first direction; The gate driving circuit includes a target gate driving circuit, and the same sub-display area includes at least two of the target gate driving circuits. The display panel satisfies at least one of the following: The target gate driving circuit is the first gate driving circuit; or, The target gate driving circuit is the second gate driving circuit.

12. The display panel according to claim 1, characterized in that, The display panel includes two sub-display areas arranged in a first direction; Along the first direction, a plurality of gate driving circuits within the same sub-display area are arranged at unequal intervals along the first direction.

13. The display panel according to claim 1, characterized in that, The display panel includes two sub-display areas arranged in a first direction; Within the same sub-display area, any two adjacent gate driving circuits constitute a circuit group. The spacing between two gate driving circuits in at least one circuit group in the first direction is d11, and the spacing between two gate driving circuits in at least another circuit group in the first direction is d12, where d11 ≠ d12.

14. The display panel according to claim 1, characterized in that, The display panel includes two sub-display areas arranged in a first direction; Within the same sub-display area, any two adjacent gate driving circuits constitute a circuit group. The number of pixel circuit columns distributed between the two gate driving circuits in at least one circuit group is m1, and the number of pixel circuit columns distributed between the two gate driving circuits in at least another circuit group is m2, where m1 ≠ m2.

15. The display panel according to claim 1, characterized in that, The orthographic projection of the pixel circuit on the plane of the display panel and the orthographic projection of the gate driving circuit on the plane of the display panel do not overlap.

16. The display panel according to claim 1, characterized in that, The pixel circuits in different display areas have the same size.

17. The display panel according to claim 1, characterized in that, The display area also includes: The first center line has a width D in the first direction, extends along the second direction, and the distance between the first center line and the first edge of the display panel in the first direction is d1, where d1 = D / 4.

18. The display panel according to claim 17, characterized in that, The display area includes a second center line, and the distance between the second center line and the first edge of the display panel in the first direction is d2, where d2 = D / 2; Along the first direction, the first gate driving circuit is located on the side of the first center line closer to the second center line, and the second gate driving circuit is located on the side of the first center line away from the second center line; or, the first gate driving circuit is located on the side of the first center line away from the second center line, and the second gate driving circuit is located on the side of the first center line closer to the second center line.

19. The display panel according to claim 18, characterized in that, In the first direction, the distance between the first gate driving circuit and the first center line is d3, and the distance between the second gate driving circuit and the first center line is d4, where d3 = d4.

20. The display panel according to claim 18, characterized in that, In the first direction, the distance between the first gate driving circuit and the first center line is d3, and the distance between the second gate driving circuit and the first center line is d4, where d3 ≠ d4.

21. The display panel according to claim 20, characterized in that, d3 < d4.

22. The display panel according to claim 18, characterized in that, In the first direction, among the input and output terminals of the first gate driving circuit, the input terminal of the first gate driving circuit is closer to the first center line, and among the input and output terminals of the second gate driving circuit, the input terminal of the second gate driving circuit is closer to the first center line.

23. The display panel according to claim 18, characterized in that, The first gate driving circuit is connected to multiple first signal lines. In the first direction, the number of first signal lines distributed on the side of the first gate driving circuit closer to the first center line is n1, and the number of first signal lines distributed on the side of the first gate driving circuit farther from the first center line is n2, where n1 < n2. The second gate driving circuit is connected to multiple second signal lines. In the first direction, the number of second signal lines distributed on the side of the second gate driving circuit closer to the first center line is n3, and the number of second signal lines distributed on the side of the second gate driving circuit farther from the first center line is n4, where n3 < n4.

24. The display panel according to claim 17, characterized in that, Along the first direction, the third gate driving circuit and the fourth gate driving circuit are respectively located on both sides of the first center line.

25. The display panel according to claim 17, characterized in that, Along the first direction, the fifth gate driving circuit and the sixth gate driving circuit are located on one side of the first center line, and the seventh gate driving circuit is located on the other side of the first center line.

26. The display panel according to claim 17, characterized in that, Along the first direction, the distance between the first type of driving circuit and the first center line is less than the distance between the second type of driving circuit and the first center line and the distance between the third type of driving circuit and the first center line.

27. The display panel according to claim 1, characterized in that, The display panel includes N pixel circuit columns arranged in the first direction, and the pixel circuit columns include multiple pixel circuits arranged in the second direction; The N / 4th pixel circuit column has at least one gate driving circuit on each side of the first direction, wherein N / 4 is an integer part.

28. The display panel according to claim 27, characterized in that, Along the first direction, at least one gate driving circuit is included between the N / 4th pixel circuit column and the N / 2th pixel circuit column, wherein N / 2 is an integer part.

29. The display panel according to claim 1, characterized in that, The display panel includes a partition area, the first center line is located in the partition area, and at least one gate driving circuit is provided on each side of the partition area in the first direction. The width of the partition area in the first direction is less than or equal to 625um.

30. The display panel according to claim 29, characterized in that, The display panel includes N pixel circuit columns arranged along the first direction, and the pixel circuit columns include multiple pixel circuits arranged along the second direction. The N / 4th pixel circuit column is located in the separation area.

31. A display device, characterized in that, Includes the display panel as described in any one of claims 1-30.

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