Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate and a plurality of drain contacts. The substrate has an active region. The active region includes a gate active region, a source active region, and a drain active region. The source active region and the drain active region are located on opposite sides of the gate active region, respectively. The drain active region includes a plurality of drain active region blocks that are spaced apart from each other. The drain contacts are disposed on some of the drain active region blocks. The drain active region blocks have a first number, the drain contacts have a second number, and the first number is not equal to the second number.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices with electrostatic discharge protection capabilities. Background Technology

[0002] To prevent integrated circuits from being damaged by electrostatic discharge (ESD) during manufacturing and / or use, ESD protection components are typically incorporated within the integrated circuit. These components provide an ESD current path to prevent current from flowing into the internal circuitry of the integrated circuit and causing damage during ESD. Generally, under normal operation of the integrated circuit, the ESD protection components are inactive (turn off) and only turn on (turn on) when an ESD event occurs.

[0003] Since no component can turn on faster than an initial-on component, known ESD protection components cannot effectively protect initially-on components. Furthermore, for ESD protection of ultra-high voltage (UHV) components, adding ESD protection components increases the layout area, which is detrimental to the need for component miniaturization. Summary of the Invention

[0004] This disclosure provides a semiconductor device according to some embodiments. The semiconductor device includes a substrate and a plurality of drain contacts. The substrate has an active region. The active region includes a gate active region, a source active region, and a drain active region. The source active region and the drain active region are located on opposite sides of the gate active region. The drain active region includes a plurality of drain active region blocks spaced apart from each other. Drain contacts are disposed on the drain active region blocks. The drain active region blocks have a first number, and the drain contacts have a second number, wherein the first number is not equal to the second number.

[0005] The semiconductor device of this disclosure includes a plurality of laterally spaced drain active blocks, which can serve as electrostatic discharge (ESD) protection elements for the semiconductor device itself. This does not occupy layout area, facilitating device miniaturization, and avoids the problem of known ESD protection elements turning on slower than initially conductive semiconductor devices. Furthermore, these drain blocks can act as small resistors, electrically connected in parallel to the drain electrode via their respective drain contacts, thereby dispersing ESD current. This enhances the ESD resistance of the disclosed semiconductor device, providing superior ESD protection, which is beneficial for ultra-high voltage (UHV) device applications. Additionally, the drain contacts only connect the inner (farthest from the gate electrode) drain active blocks. Therefore, the number of drain contacts is less than the number of drain active blocks. Compared to the outer (closer to the gate electrode) drain active block 207, the inner (farthest from the gate electrode) drain active block has a lower surface electric field. Therefore, when electrostatic discharge (ESD) occurs, the above connection method can prevent the drain contact located on the outer drain active block from being attacked by the ESD current and burned out, further enhancing the ability of the semiconductor device to withstand ESD. Attached Figure Description

[0006] Figure 1 This is a top view schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0007] Figure 2 For along Figure 1 A schematic cross-sectional view of the semiconductor device along line A-A' of some embodiments of the present invention.

[0008] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H This is an enlarged top view of a portion of the active source region of a semiconductor device according to some embodiments of the present invention, showing different embodiments of the active drain region and their corresponding contact with the drain.

[0009] Figure 4A , Figure 4B , Figure 4C This is an enlarged top view of a portion of the active drain region and drain contact of a semiconductor device according to some embodiments of the present invention, showing the correspondence between the active drain region and the drain contact.

[0010] Figure 5 This is a top view schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0011] Figure 6This is a top view schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0012] Figure 7 This is a top view schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0013] Symbol Explanation

[0014] 200: Base

[0015] 200T: Top surface

[0016] 202, 202-1, 202-2, 202-3: Isolation components

[0017] 204: First Well Area

[0018] 206: Second Well Area

[0019] 207, 207A1, 207A2, 207A3, 207A4, 207B1, 207B2, 207B3, 207B4: Drain Active Blocks

[0020] 208: Drain doped region

[0021] 210: Source doped region

[0022] 212: Matrix doped region

[0023] 214: Drain contact

[0024] 216: Source Contact

[0025] 218: Matrix Contact

[0026] 220: Gate electrode

[0027] 224: Drain electrode

[0028] 226: Source electrode

[0029] 228: Substrate Electrode

[0030] 230, 240: Bordered area

[0031] 500A, 500B, 500C, 500D: Semiconductor devices

[0032] A-A': Tangent line

[0033] AR: Active Zone

[0034] AR-B: Active region of matrix

[0035] AR-D: Drain Active Region

[0036] AR-G: Gate Active Region

[0037] AR-S: Source Active Region

[0038] A1, A2, A3, A4, B1, B2, B3, B4: Area

[0039] CH: Passage area

[0040] CR1, CR2: Rounded corners

[0041] DA: Distribution Area

[0042] DA-1, DA-2, DA-3: U-shaped area

[0043] DA-S1: First side

[0044] DA-S2: Second side

[0045] D1, D2, D3: Depth

[0046] EL1, EL2: Straight extensions

[0047] F1: Interface

[0048] X, Y, Z: Direction Detailed Implementation

[0049] The present disclosure is described more fully below with reference to the accompanying drawings of embodiments of the invention. However, the present disclosure may be implemented in various different ways and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numerals in the drawings denote the same or similar elements. It is understood that additional steps may be provided before, during, and after the method, and some described steps may be replaced or omitted for other embodiments of the method.

[0050] Various embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. When the description refers to a first component being formed on top of a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, the embodiments of the invention may use repeated component symbols in many examples. These repetitions are for simplification and clarity only and do not represent a specific relationship between the various embodiments and / or configurations discussed.

[0051] Furthermore, spatially related terms such as "below," "under," "below," "above," "above," and other similar expressions may be used in the following description to simplify the statement of the relationship between an element or component and other elements or components as shown in the figure. These spatially related terms include not only the direction depicted in the figure but also the different orientations of the device during use or operation. The device may be positioned in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted accordingly.

[0052] This disclosure relates to improving the electrostatic discharge (ESD) protection capability of initial conduction semiconductor devices. The embodiments disclosed herein divide the drain region into multiple drain blocks that are laterally separated from each other, and use multiple drain contacts to electrically connect to the drain regions. Each drain block corresponds to at least one drain contact, and these drain contacts are electrically connected to the drain electrode in parallel. This allows the ESD current to be distributed throughout the entire drain region, thereby improving the ESD protection capability of the semiconductor device itself without increasing the layout area of ​​the semiconductor device.

[0053] Figure 1 This is a top view (or layout diagram) of a semiconductor device 500A according to some embodiments of the present invention. In some embodiments, the semiconductor device 500A is a depletion mode metal oxide semiconductor field effect transistor (D-mode MOSFET), which is an initial-on type semiconductor device.

[0054] Semiconductor device 500A includes a substrate 200, an isolation component 202, an active region AR, a gate electrode 220, a source contact 216, and a drain contact 214. For illustration, Figure 1 Only the above components are shown; the remaining components can be found in [the following locations]. Figure 2 A cross-sectional schematic diagram, Figure 2 Along Figure 1 The tangent line A-A' is intercepted.

[0055] like Figure 1 , Figure 2As shown, the substrate 200 can be a semiconductor substrate. The semiconductor substrate includes elemental semiconductors, such as silicon (Si), germanium (Ge), etc.; compound semiconductors, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc.; alloy semiconductors, such as silicon-germanium alloy (SiGe), gallium arsenide-phosphide alloy (GaAsP), aluminum-indium arsenide alloy (AlInAs), aluminum-gallium arsenide alloy (AlGaAs), indium-gallium arsenide alloy (GaInAs), indium-gallium phosphide alloy (GaInP), indium-gallium arsenide-phosphide alloy (GaInAsP), or combinations of the above materials. Furthermore, the substrate 200 can also be a semiconductor on insulator (SOI). In some embodiments, the substrate 200 has a first conductivity type, such as P-type. For example, the substrate 200 can be a p-type silicon substrate (PSUB).

[0056] The semiconductor device 500A also includes a first well region 204 and a second well region 206 located in a substrate 200. Both the first well region 204 and the second well region 206 extend from the top surface 200T of the substrate 200 into a portion of the substrate 200. The first well region 204 and the second well region 206 are arranged side-by-side and adjacent to each other along the X-axis (lateral) direction, which is substantially parallel to the top surface 200T of the substrate 200. Furthermore, the second well region 206 may surround the first well region 204. In some embodiments, the depth D1 of the first well region 204 along the Z-axis (longitudinal) direction, which is substantially perpendicular to the top surface 200T of the substrate 200, is greater than the depth D2 of the second well region 206 along the Z-axis direction. In other words, in the Z-axis direction, the bottom surface of the first well region 204 is below the bottom surface of the second well region 206. In some embodiments, the first well region 204 has a second conductivity type opposite to a first conductivity type, such as a high voltage n-type well region (HVNW). The second well region 206 has a first conductivity type, such as a p-type well region (PW).

[0057] In some embodiments, a multi-channel ion implantation process can be used to implant P-type and N-type dopants into the substrate 200 to form a first well region 204 and a second well region 206, respectively. In some embodiments, the N-type dopant may include phosphorus, arsenic, nitrogen, antimony, or a combination thereof. In some embodiments, the P-type dopant may include boron, gallium, aluminum, indium, boron trifluoride ions (BF3+), or a combination thereof.

[0058] The isolation components 202 (including isolation components 202-1, 202-2, and 202-3) are disposed in the substrate 200 and extend from the top surface 200T of the substrate 200 into a portion of the substrate 200, such as... Figure 1 , Figure 2 As shown, isolation component 202 is used to define multiple active regions AR (including substrate active region AR-B, drain active region AR-D, and source active region AR-S). Specifically, isolation component 202-1 can be disposed in a portion of the first well region 204 and separated from the interface F1 between the first well region 204 and the second well region 206. Isolation component 202-1 can surround the drain active region AR-D to define the drain active region AR-D. Isolation components 202-2 and 202-3 can be disposed in a portion of the second well region 206 and separated from each other along the X-axis direction (lateral). In the Z-axis direction, isolation component 202-2 is located between isolation components 202-1 and 202-3. Furthermore, isolation component 202-2 is separated from the interface F1 between the first well region 204 and the second well region 206 and from isolation component 202-1. Isolation component 202-2 may surround isolation component 202-1 and may define a gate active region AR-G and a source active region AR-S together with isolation component 202-1. The source active region AR-S is connected to and surrounds the gate active region AR-G. The gate active region AR-G and the source active region AR-S together surround the drain active region AR-D. The gate active region AR-G is closer to the interface F1 between the first well region 204 and the second well region 206 than the source active region AR-S. Furthermore, the source active region AR-S and the drain active region AR-D are located on opposite sides of the gate active region AR-G. Isolation component 202-3 may be located outside isolation component 202-2 and may surround isolation component 202-2. Figure 1 (Isolation component 202-3 is not shown). Isolation component 202-3, together with isolation component 202-2, defines the substrate active region AR-B. The substrate active region AR-B may surround the gate active region AR-G, the source active region AR-S, and the drain active region AR-D.

[0059] In some embodiments, the drain active region AR-D includes a plurality of drain active region blocks 207 spaced apart from each other. In some embodiments, the drain active region blocks 207 include rectangular, circular, or elliptical shapes. In this embodiment, the drain active region blocks 207 are, for example, rectangular blocks.

[0060] like Figure 1As shown, the drain active region AR-D has a distribution area DA. In some embodiments, the top view shape of the distribution area DA of the drain active region AR-D may include an annular shape (including racetrack shape, circular annular shape, and square-circular annular shape) or a fork shape. The gate active region AR-G and the source active region AR-S are continuously distributed, and their top view shapes may correspond to (be the same as or similar to) the top view shape of the distribution area DA. In this embodiment, the distribution area DA of the drain active region AR-D may be racetrack shaped. Furthermore, the distribution area DA of the drain active region AR-D may include a U-shaped region DA-1. The U-shaped region DA-1 has a rounded corner portion CR1 and a straight extension portion EL1 connected to the rounded corner portion CR1. In this embodiment, the gate active region AR-G may be racetrack shaped, and it may have a U-shaped region DA-2. Furthermore, the U-shaped region DA-2 is disposed corresponding to the U-shaped region DA-1. For example, the U-shaped region DA-2 is located outside the U-shaped region DA-1 and is disposed parallel to each other. In this embodiment, the source active region AR-S can be racetrack-shaped, and it can have a U-shaped region DA-3. Furthermore, the U-shaped region DA-3 is positioned corresponding to the U-shaped region DA-2. For example, the U-shaped region DA-3 is located outside the U-shaped region DA-2 and is arranged parallel to it.

[0061] In some embodiments, the isolation component 202 is a field oxide (FOX) formed using a local oxidation of silicon (LOCOS) process, a shallow trench isolation (STI) structure formed using a deposition process, or other suitable isolation structures. In some embodiments, a thermal oxidation process, including a dry oxidation process, a wet oxidation process, or other suitable thermal oxidation processes, is used to form the isolation component 202.

[0062] The semiconductor device 500A also includes a drain doped region 208 located on a first well region 204, and a source doped region 210 and a substrate doped region 212 located on a second well region 206. The drain doped region 208, the source doped region 210, and the source active region AR-S extend from the top surface 200T of the substrate 200 into a portion of the substrate 200. The drain doped region 208 is located in the drain active region AR-D, adjacent to and surrounded by the isolation component 202-1. The source doped region 210 is located in the source active region AR-S, adjacent to and surrounded by the isolation component 202-2. Furthermore, the source doped region 210 may be separated from the isolation component 202-1. The substrate doped region 212 is located in the substrate active region AR-B, adjacent to and surrounded by the isolation components 202-2 and 202-3. Furthermore, the matrix doped region 212 may surround the isolation component 202-2.

[0063] In some embodiments, the drain doped region 208, the source doped region 210, and the substrate doped region 212 have the same depth D3 along the Z-axis. The drain doped region 208 may have an impurity concentration greater than that of the first well region 204, and the substrate doped region 212 may have an impurity concentration greater than that of the second well region 206. Both the drain doped region 208 and the source doped region 210 have a second conductivity type, such as an N-type heavily doped region (N+). The substrate doped region 212 has a first conductivity type, such as a P-type heavily doped region (P+).

[0064] In some embodiments, a multi-channel ion implantation process can be used to implant P-type and N-type dopants into the substrate 200 to form a drain doped region 208, a source doped region 210, and a substrate doped region 212. In some embodiments, the N-type dopant may include phosphorus, arsenic, nitrogen, antimony, or a combination thereof. In some embodiments, the P-type dopant may include boron, gallium, aluminum, indium, boron trifluoride ions (BF3+), or a combination thereof. In some embodiments, the same ion implantation process can be used to form the drain doped region 208 and the source doped region 210 simultaneously, or different ion implantation processes can be used to form them separately.

[0065] The semiconductor device 500A also includes a gate electrode 220 located on the gate active region AR-G of the substrate 200. The gate electrode 220 is disposed on and spans the first well region 204 and the second well region 206. A portion of the gate electrode 220 extends from the side of the isolation member 202-1 near the interface F1 to the top surface of the isolation member 202-1, and another portion of the gate electrode 220 is adjacent to the source doped region 210. The drain doped region 208 and the gate electrode 220 are spaced apart along the X-axis, and the isolation member 202-1 is located between the drain doped region 208 and the gate electrode 220. In the X-axis direction, the distance between the drain doped region 208 and the gate electrode 220 is greater than the distance between the source doped region 210 and the gate electrode 220. The top view shape of the gate electrode 220 may correspond to the top view shape of the distribution region DA. In some embodiments, the gate electrode 220 includes a gate dielectric layer (not shown) disposed on the substrate 200, a gate electrode layer (not shown) disposed above the gate dielectric layer, and gate spacers (not shown) disposed on the sidewalls of the gate dielectric layer and the gate electrode layer.

[0066] In some embodiments, the gate dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material, other suitable dielectric materials, and / or combinations thereof. The high dielectric constant materials described above include, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, and / or combinations thereof or similar materials. In some embodiments, the gate dielectric layer may be formed on the substrate 200 using an oxidation process, a deposition process, or other suitable processes. In some embodiments, the gate electrode layer comprises polycrystalline silicon, amorphous silicon, metals (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, other suitable metals, or combinations thereof), metal alloys, metal nitrides (e.g., tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, other suitable metal nitrides, or combinations thereof), metal oxides (ruthenium oxide, indium tin oxide, other suitable metal oxides, or combinations thereof), other suitable materials, or combinations thereof. In some embodiments, the gate electrode layer may be implanted with dopants using in-situ doping. In some embodiments, the gate spacer comprises silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant materials, other suitable dielectric materials, and / or combinations thereof. In some embodiments, oxidation processes, deposition processes, or other suitable processes may be used to form the gate spacer on the sidewalls of the gate dielectric layer and the gate electrode layer.

[0067] The semiconductor device 500A also includes a drain contact 214, a source contact 216, a substrate contact 218, a drain electrode 224, a source electrode 226, and a substrate electrode 228 located on the substrate 200.

[0068] The drain contact 214 of the semiconductor device 500A is disposed on a portion (but not all) of the drain active blocks 207. In some embodiments, the drain contact 214 is disposed on a portion of the drain active blocks 207 away from the gate active regions AR-G, but not on a portion of the drain active blocks 207 close to the gate active regions AR-G. In some embodiments, each drain active block 207 away from the gate active regions AR-G may correspond to one drain contact 214, and each portion of the drain active blocks 207 close to the gate active regions may correspond to zero drain contacts 214 (electrically floating). In some embodiments, the drain active blocks 207 have a first number, and the drain contacts 214 have a second number, and the first number is not equal to the second number. For example, the first number is greater than the second number. In some embodiments, the drain contacts 214 are disposed on the second number of drain active blocks 207, and the remaining drain active blocks 207 are electrically floating.

[0069] In this embodiment, the distribution area DA of the active drain region AR-D is racetrack shaped. The first side DA-S1 (or the first side DA-S1 of the U-shaped region DA-1) of the distribution area DA is located outside the racetrack shaped distribution area DA, and the second side DA-S2 (or the second side DA-S2 of the U-shaped region DA-1) of the distribution area DA is located inside the racetrack shaped distribution area DA.

[0070] The distribution region DA (or the U-shaped region DA-1 of the distribution region DA) has a first side (outer side) DA-S1 close to the gate active region AR-G and a second side (inner side) DA-S2 far from the gate active region AR-G. The first side (outer side) DA-S1 and the second side (inner side) DA-S2 are opposite to each other. The drain contact 214 is disposed on the drain active block 207 close to the second side (inner side) DA-S2, and is not disposed on the drain active block 207 close to the first side (outer side) DA-S1. In some embodiments, the drain contact 214 is disposed on the drain active block 207 of the rounded corner CR1 and the straight extension EL1 of the U-shaped region DA-1 close to the second side (inner side) DA-S2, and has a one-to-one correspondence with the drain active block 207 of the above-mentioned portion. For clarity of the diagram, Figure 2 The diagram only shows a simplified representation of the active drain block 207 (and the drain doped region 208) and the drain contact 214. For a detailed representation of the correspondence between the active drain block 207 (and the drain doped region 208) and the drain contact 214 in the framed region 230, please refer to subsequent sections. Figures 3A to 3H and Figures 4A to 4C Explanation.

[0071] Drain electrode 224 is disposed on substrate 200. Drain contacts 214 can be electrically connected to drain electrode 224 in parallel. In some embodiments, the top view shape of drain electrode 224 corresponds to... Figure 1 The diagram shows the top view shape of the distribution area DA of the drain active region AR-D. In this embodiment, the top view shape of the drain electrode 224 can be racetrack-shaped. These drain active regions 207 and these drain contacts 214 are located within the racetrack-shaped region of the drain electrode 224.

[0072] like Figure 1 , Figure 2 As shown, at least one source contact 216 is disposed on the source active region AR-S of the substrate 200, and is electrically connected to the source doped region 210 of the source active region AR-S. Figure 1 In the top view layout shown, the top view shape of the source contact 216 corresponds to the top view shape of the source active region AR-S. In this embodiment, the top view shapes of the source active region AR-S and the source contact 216 can be racetrack-shaped.

[0073] A source electrode 226 is disposed on a substrate 200 and electrically connected to the source electrode 226. In some embodiments, the top view shape of the source electrode 226 corresponds to... Figure 1 The top view of the source active region AR-S is shown. In this embodiment, the top view of the source electrode 226 can be racetrack-shaped and surrounds the drain electrode 224. The racetrack-shaped source contact 216 is located within the racetrack-shaped block of the source contact 216.

[0074] like Figure 2 As shown, a substrate contact 218 is disposed on the substrate active region AR-B of the substrate 200 and is electrically connected to the substrate doped region 212 of the substrate active region AR-B. The substrate doped region 212 is electrically connected to the substrate electrode 228 disposed on the substrate 200 via the substrate contact 218. Furthermore, the source electrode 226 is located between the substrate electrode 228 and the drain electrode 224.

[0075] In some embodiments, the semiconductor device 500A is an N-channel depleted metal-oxide-semiconductor field-effect transistor. When no voltage is applied to the gate electrode 220, the source doped region 210 and the drain doped region 208 can be turned on through the N-type channel region CH. That is, this depleted metal-oxide-semiconductor field-effect transistor is an initially turned-on semiconductor device.

[0076] According to some embodiments disclosed herein, the drain active region AR-D of the semiconductor device 500A is divided by isolation component 202-1 into a plurality of drain active region blocks 207 that are laterally spaced from each other. Only a portion of the drain active region blocks 207 of the drain active region AR-D have drain doped regions 208 electrically connected to drain contacts 214. For example, the drain doped regions 208 of the drain active region blocks 207 that are far from the gate active region AR-G (or gate electrode 220) can each correspond to and be electrically connected to a drain contact 214. The drain doped regions 208 of the aforementioned drain active region blocks 207 are electrically connected to the drain electrode 224 in parallel via these drain contacts 214, and the drain doped region 208 of each of the aforementioned drain active region blocks 207 can be considered as a small resistor. When electrostatic discharge (ESD) occurs, the small resistance formed by the drain doped region 208 of each of the above-mentioned active drain blocks 207 can independently withstand the ESD energy, and the ESD current can be uniformly conducted through each drain contact 214 to each drain doped region 208 of the active drain block 207 that is far away from the gate active region AR-G (or gate electrode 220), so that the ESD current is dispersed to the drain doped region 208 of each of the above-mentioned active drain blocks 207, resulting in a smaller potential of the drain doped region 208. Furthermore, compared to the drain active block 207 which is close to the gate active region AR-G (or gate electrode 220), the drain active block 207 which is far from the gate active region AR-G (or gate electrode 220) has a lower surface electric field. Therefore, when electrostatic discharge (ESD) occurs, the above connection method can prevent the drain contact 214 located on the outer drain active block 207 (close to the first side DA-S1 of the distribution region DA) from being attacked by the electrostatic discharge current and burned out, further enhancing the ability of the semiconductor device 500A to withstand electrostatic discharge.

[0077] Furthermore, according to some embodiments of this disclosure, the electrostatic discharge (ESD) protection mechanism of the semiconductor device 500A remains in the on state under normal operation. Therefore, for initially conductive semiconductor devices, there is no issue of the ESD protection element turning on slowly. Additionally, according to some embodiments of this disclosure, the ESD protection element of the semiconductor device 500A is provided by multiple drain active blocks 207 (and drain doped regions 208 therein). Therefore, the ESD protection element does not occupy the layout area of ​​the semiconductor device, which is beneficial for miniaturization of the device size. Moreover, the semiconductor device disclosed herein has its own ESD protection capability, which is beneficial for the application of ultra-high voltage (UHV) devices.

[0078] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F, Figure 3G , Figure 3H for Figure 1 An enlarged top view of the frame region 240 of a semiconductor device 500A according to some embodiments of the present invention shows different embodiments of the active drain block and their corresponding contacts with the drain. Figure 3A , Figure 3B , Figure 3C , Figure 3D Taking the rectangular drain active block 207 as an example, and Figure 3E , Figure 3F , Figure 3G , Figure 3H Take the circular drain active block 207 as an example. Figures 3A to 3H The active drain block 207 shown may have other shapes and is not limited to the embodiments described herein.

[0079] like Figure 3A As shown, the drain active block 207 may include multiple rectangular drain active blocks 207A1 and multiple rectangular drain active blocks 207A2. The drain active blocks 207A1 and 207A2 may be arranged periodically along the tangent and normal directions of the distribution region DA. In this embodiment, the drain active block 207A1 is positioned near the first side (outer side) DA-S1 of the distribution region DA, and the drain active block 207A2 is positioned near the second side (inner side) DA-S2 of the distribution region DA. Furthermore, the drain active block 207A1 may surround the drain active block 207A2. In this embodiment, the drain contact 214 may be disposed on the drain active block 207A2, but not on the drain active block 207A1. In some embodiments, the area A1 of each drain active block 207A1 is not equal to the area A2 of each drain active block 207A2. For example... The area A1 of each active drain block 207A1 is smaller than the area A2 of each active drain block 207A2.

[0080] In such Figure 3B In the illustrated embodiment, the rectangular drain active block 207A1 is positioned near the second side (inner side) DA-S2 of the distribution region DA, and the rectangular drain active block 207A2 is positioned near the first side (outer side) DA-S1 of the distribution region DA. Furthermore, the drain active block 207A2 may surround the drain active block 207A1. In this embodiment, the drain contact 214 may be disposed on the drain active block 207A1, but not on the drain active block 207A2.

[0081] In such Figure 3CIn the illustrated embodiment, the drain active block 207 may include multiple rectangular drain active blocks 207A3. The drain active blocks 207A3 may be arranged periodically along the tangent and normal directions of the distribution region DA. In this embodiment, each drain active block 207A3 has a uniform area A3. The drain contact 214 may be disposed on the drain active block 207A3 on the second side (inner side) DA-S2 of the distribution region DA, and not on the drain active block 207A3 on the first side (outer side) DA-S1 of the distribution region DA.

[0082] In such Figure 3D In the illustrated embodiment, the drain active block 207 may include multiple rectangular drain active blocks 207A4. Each drain active block 207A4 has a uniform area A4. In this embodiment, the area A4 of each drain active block 207A4 is larger than the area A3 of each drain active block 207A3. Figure 3C Therefore, the active drain blocks 207A4 can be arranged periodically only along the tangential direction of the distribution region DA. In this embodiment, drain contacts 214 can be disposed on each active drain block 207A4.

[0083] like Figure 3E As shown, the drain active block 207 may include multiple circular drain active blocks 207B1 and multiple circular drain active blocks 207B2. The drain active blocks 207B1 and 207B2 may be arranged periodically along the tangent and normal directions of the distribution region DA. In this embodiment, the drain active block 207B1 is positioned near the first side (outer side) DA-S1 of the distribution region DA, and the drain active block 207B2 is positioned near the second side (inner side) DA-S2 of the distribution region DA. Furthermore, the drain active block 207B1 may surround the drain active block 207B2. In this embodiment, the drain contact 214 ( Figure 1 This can be set on the active drain block 207B2, but not on the active drain block 207B1. In some embodiments, the area B1 of each active drain block 207B1 is not equal to the area B2 of each active drain block 207B2. For example, the area B1 of each active drain block 207B1 is smaller than the area B2 of each active drain block 207B2.

[0084] In such Figure 3F In the illustrated embodiment, the circular drain active block 207B1 is positioned near the second side (inner side) DA-S2 of the distribution region DA, and the circular drain active block 207B2 is positioned near the first side (outer side) DA-S1 of the distribution region DA. Furthermore, the drain active block 207B2 may surround the drain active block 207B1. In this embodiment, the drain contact 214 ( Figure 1 It can be set on the active drain block 207B1, but not on the active drain block 207B2.

[0085] In such Figure 3G In the illustrated embodiment, the drain active block 207 may include multiple circular drain active blocks 207B3. The drain active blocks 207B3 may be arranged periodically along the tangent and normal directions of the distribution region DA. In this embodiment, each drain active block 207B3 has a uniform area B3. Drain contact 214 ( Figure 1 It can be set on the drain active block 207B3 of the second side (inner side) DA-S2 near the distribution area DA, and not on the drain active block 207B3 of the first side (outer side) DA-S1 near the distribution area DA.

[0086] In such Figure 3H In the illustrated embodiment, the drain active block 207 may include a plurality of circular drain active blocks 207B4. Each drain active block 207B4 has a uniform area B4. In this embodiment, the area B4 of each drain active block 207B4 may be larger than the area B3 of each drain active block 207B3. Figure 3G Therefore, the active drain block 207B4 can be arranged periodically only along the tangential direction of the distribution region DA. In this embodiment, the drain contact 214 ( Figure 1 It can be set on each drain active block 207B4.

[0087] In some embodiments, the corners (rounded or sharp corners) of the drain active region distribution area have a larger surface electric field. Therefore, the drain contact can be avoided on the drain active block located at the corner of the drain active region distribution area to further improve the protection against electrostatic discharge (ESD).

[0088] Figure 4A , Figure 4B , Figure 4C for Figure 1 An enlarged top view of the active drain block 207 and drain contact 214 in a portion of the U-shaped region DA-1 of the semiconductor device 500A according to some embodiments of the present invention shows the connection relationship between the active drain block 207 and the drain contact 214. Figure 4A , Figure 4B , Figure 4C The shape and arrangement of the active drain block 207 in the middle are similar to Figure 3C The shape and arrangement of the active drain block 207A3. However, Figure 4A , Figure 4B , Figure 4C The shape and arrangement of the drain active block 207 can also be similar to Figure 3A , Figure 3B , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H The shape and arrangement of the active drain blocks 207A1, 207A2, 207A4, 207B1, 207B2, 207B3, and 207B4 will not be described again here.

[0089] like Figure 4A As shown, the drain contact 214 can be disposed on the rounded corner portion CR1 of the U-shaped region DA-1 and the drain active block 207 of the straight extension portion EL1.

[0090] like Figure 4B As shown, in other embodiments, the drain contact 214 may be disposed on the drain active block 207 of the straight extension EL1, and not on the drain active block 207 of the rounded corner CR1. Figure 4A compared to, Figure 4B The placement of the drain contact 214, as shown, further enhances protection against electrostatic discharge (ESD).

[0091] like Figure 4C As shown, in other embodiments, the drain contact 214 may be disposed on the drain active block 207 of the straight extension EL1 away from the rounded corner portion CR1. Figure 4B compared to, Figure 4C The placement of the drain contact 214, as shown, further enhances protection against electrostatic discharge (ESD).

[0092] Figure 5 This is a top view schematic diagram of a semiconductor device 500B according to some embodiments of the present invention. (The figure is related to...) Figure 1 The same or similar component symbols represent the same or similar components. For example... Figure 5 As shown, the difference between semiconductor device 500B and semiconductor device 500A is that the distribution area DA of the drain active region AR-D in semiconductor device 500B can be annular. Furthermore, the top-view shapes of the gate active region AR-G, source active region AR-S, and gate electrode 220 in semiconductor device 500B can correspond to the top-view shape (annular) of the distribution area DA.

[0093] In this embodiment, the distribution area DA of the active drain region AR-D is annular. The first side DA-S1 (or the first side DA-S1 of the U-shaped region DA-1) of the distribution area DA is located outside the annular distribution area DA, and the second side DA-S2 (or the second side DA-S2 of the U-shaped region DA-1) of the distribution area DA is located inside the annular distribution area DA.

[0094] Figure 6 This is a top view schematic diagram of a semiconductor device 500C according to some embodiments of the present invention. (The figure is related to...) Figure 1 The same or similar component symbols represent the same or similar components. For example... Figure 6 As shown, the difference between semiconductor device 500C and semiconductor device 500A is that the distribution area DA of the drain active region AR-D in semiconductor device 500C can be square or circular. Furthermore, the top-view shapes of the gate active region AR-G, source active region AR-S, and gate electrode 220 in semiconductor device 500C can be the same as or similar to the top-view shape (square or circular) of the distribution area DA.

[0095] Figure 7 This is a top view schematic diagram of a semiconductor device 500D according to some embodiments of the present invention. (The image is related to...) Figure 1 The same or similar component symbols represent the same or similar components. For example... Figure 7 As shown, the difference between semiconductor device 500D and semiconductor device 500A is that the distribution area DA of the drain active region AR-D in semiconductor device 500D can be finger-shaped. Furthermore, the top-view shapes of the gate active region AR-G, source active region AR-S, and gate electrode 220 in semiconductor device 500C can correspond to the top-view shape (finger-shaped) of the distribution area DA. To make the diagrams clearer and easier to understand, Figure 7 The source electrode contact, active region of the substrate, and substrate contact are not shown in the figure.

[0096] In this embodiment, the distribution area DA of the drain active region AR-D can be forked. The first side DA-S1 of the U-shaped region DA-1 of the distribution area DA is located at the edge of the forked distribution area DA, and the second side DA-S2 of the distribution area DA is located in the middle part of the forked distribution area DA.

[0097] The gate active region AR-G can be finger-shaped, and it can have a U-shaped region DA-2. In this embodiment, the U-shaped regions DA-1 and DA-2 are arranged opposite to each other. Furthermore, the plurality of straight extensions EL1 of the U-shaped region DA-1 and the plurality of straight extensions EL2 of the U-shaped region DA-2 are arranged alternately. The straight extensions EL1 of the U-shaped region DA-1 point to the rounded corners CR2 of the U-shaped region DA-2, and the straight extensions EL2 of the U-shaped region DA-2 point to the rounded corners CR1 of the U-shaped region DA-1.

[0098] In some embodiments, the drain active region block 207 of the drain active region AR-D of semiconductor devices 500B, 500C, and 500D may have Figures 3A to 3H The shapes and arrangements shown will not be described again here. The active drain block 207 and drain contact 214 of semiconductor devices 500B, 500C, and 500D may have… Figures 4A to 4C The connections shown will not be repeated here.

[0099] This invention provides a semiconductor device. The semiconductor device includes a substrate and a plurality of drain contacts. The substrate has an active region. The active region includes a gate active region, a source active region, and a drain active region. The source active region and the drain active region are located on opposite sides of the gate active region. The drain active region includes a plurality of drain active region blocks spaced apart from each other. Drain contacts are disposed on a portion of the drain active region blocks. The drain active region blocks have a first number, and the drain contacts have a second number, wherein the first number is not equal to the second number.

[0100] In some embodiments, the first quantity is greater than the second quantity.

[0101] In some embodiments, the drain contact is disposed on a second number of drain active blocks, and the remaining drain active blocks are electrically floating.

[0102] In some embodiments, the distribution area of ​​the active drain block includes a first U-shaped region.

[0103] In some embodiments, the first U-shaped region has a first side close to the gate active region and a second side away from the gate active region, and the drain contact is disposed on the drain active region block close to the second side, but not on the drain active region block close to the first side.

[0104] In some embodiments, the first U-shaped region has a first rounded corner and a first straight extension connected to the first rounded corner, and the drain contact is disposed on the drain active block of the first straight extension, but not on the drain active block of the first rounded corner.

[0105] In some embodiments, the drain contact is disposed on the drain active block of the first straight extension of the first rounded corner portion.

[0106] In some embodiments, the distribution area includes a ring or fork shape.

[0107] In some embodiments, when the distribution area is annular, the first side is located outside the annular distribution area, and the second side is located inside the annular distribution area.

[0108] In some embodiments, when the distribution area is forked, the first side is located at the edge of the forked distribution area, and the second side is located in the middle part of the forked distribution area.

[0109] In some embodiments, the gate active regions are continuously distributed and have a second U-shaped region, which is disposed corresponding to the first U-shaped region.

[0110] In some embodiments, the second U-shaped region is located outside the first U-shaped region and is arranged parallel to each other.

[0111] In some embodiments, the second U-shaped region has a second rounded corner and a second straight extension connected to the second rounded corner. The first straight extension of the first U-shaped region and the second straight extension of the second U-shaped region are staggered. The first straight extension of the first U-shaped region points to the second rounded corner of the second U-shaped region, and the second straight extension of the second U-shaped region points to the first rounded corner of the first U-shaped region.

[0112] In some embodiments, the distribution regions of the gate active region and the drain active region have the same or similar shapes.

[0113] In some embodiments, the active regions are continuously distributed and have a third U-shaped region, which is provided corresponding to the second U-shaped region.

[0114] In some embodiments, the source active region surrounds the gate active region.

[0115] In some embodiments, the source active region is connected to the gate active region.

[0116] In some embodiments, the active drain block includes a rectangle, a circle, or an ellipse.

[0117] In some embodiments, the active drain block includes a plurality of first active drain blocks and a plurality of second active drain blocks, and the first area of ​​each first active drain block is not equal to the second area of ​​each second active drain block.

[0118] In some embodiments, the semiconductor device further includes a gate electrode, a source contact, a drain electrode, and a source electrode. The gate electrode is disposed on the gate active region. The source contact is electrically connected to the source active region. The drain electrode is electrically connected to the drain contact. The source electrode is electrically connected to the source contact region.

[0119] The semiconductor device of this disclosure includes a plurality of laterally spaced drain active blocks, which can serve as electrostatic discharge (ESD) protection elements for the semiconductor device itself. This does not occupy layout area, facilitating device miniaturization, and avoids the problem of known ESD protection elements turning on slower than initially conductive semiconductor devices. Furthermore, these drain blocks can act as small resistors, electrically connected in parallel to the drain electrode via their respective drain contacts, thereby dispersing ESD current. This enhances the ESD resistance of the disclosed semiconductor device, providing superior ESD protection, which is beneficial for ultra-high voltage (UHV) device applications. Additionally, the drain contacts only connect the inner (farthest from the gate electrode) drain active blocks. Therefore, the number of drain contacts is less than the number of drain active blocks. Compared to the outer (closer to the gate electrode) drain active block 207, the inner (farthest from the gate electrode) drain active block has a lower surface electric field. Therefore, when electrostatic discharge (ESD) occurs, the above connection method can prevent the drain contact located on the outer drain active block from being attacked by the ESD current and burned out, further enhancing the ability of the semiconductor device to withstand ESD.

[0120] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate having an active region, wherein the active region includes: One gate active region; and A source active region and a drain active region are located on opposite sides of the gate active region, wherein the drain active region includes a plurality of drain active regions spaced apart from each other; and Multiple drain contacts are disposed on a portion of the multiple active drain blocks, wherein the multiple active drain blocks have a first number, the multiple drain contacts have a second number, and the first number is not equal to the second number.

2. The semiconductor device as claimed in claim 1, characterized in that, The first quantity is greater than the second quantity.

3. The semiconductor device as claimed in claim 2, characterized in that, The plurality of drain contacts are disposed on the second number of plurality of drain active blocks, and the remaining plurality of drain active blocks are electrically floating.

4. The semiconductor device as claimed in claim 1, characterized in that, One distribution area of ​​the plurality of active drain blocks includes a first U-shaped region.

5. The semiconductor device as claimed in claim 4, characterized in that, The first U-shaped region has a first side close to the gate active region and a second side away from the gate active region, and the plurality of drain contacts are disposed on the plurality of drain active blocks close to the second side, but not on the plurality of drain active blocks close to the first side.

6. The semiconductor device as claimed in claim 5, characterized in that, The first U-shaped region has a first rounded corner and a first straight extension connected to the first rounded corner. The plurality of drain contacts are disposed on the plurality of active drain blocks of the first straight extension, but not on the plurality of active drain blocks of the first rounded corner.

7. The semiconductor device as claimed in claim 6, characterized in that, The plurality of drain contacts are disposed on the plurality of active drain blocks on the first straight extension portion away from the first rounded corner portion.

8. The semiconductor device as claimed in claim 6, characterized in that, The distribution area includes ring-shaped or forked shapes.

9. The semiconductor device as claimed in claim 8, characterized in that, When the distribution area is ring-shaped, the first side is located outside the ring-shaped distribution area, and the second side is located inside the ring-shaped distribution area.

10. The semiconductor device as claimed in claim 8, characterized in that, When the distribution area is forked, the first side is located at an edge of the forked distribution area, and the second side is located in the middle part of the forked distribution area.

11. The semiconductor device as claimed in claim 8, characterized in that, The active gate region is continuously distributed and has a second U-shaped region, which is disposed corresponding to the first U-shaped region.

12. The semiconductor device as claimed in claim 11, characterized in that, The second U-shaped area is located outside the first U-shaped area and is arranged parallel to it.

13. The semiconductor device as claimed in claim 11, characterized in that, The second U-shaped area has a second rounded corner and a second straight extension connected to the second rounded corner. The first straight extension of the first U-shaped area and the second straight extension of the second U-shaped area are interleaved. The first straight extension of the first U-shaped area points to the second rounded corner of the second U-shaped area, and the second straight extension of the second U-shaped area points to the first rounded corner of the first U-shaped area.

14. The semiconductor device as claimed in claim 11, characterized in that, The gate active region has the same or similar shape as the distribution area of ​​the plurality of drain active regions.

15. The semiconductor device as claimed in claim 11, characterized in that, The active source region is continuously distributed and has a third U-shaped region, which is set in accordance with the second U-shaped region.

16. The semiconductor device as claimed in claim 15, characterized in that, The source active region surrounds the gate active region.

17. The semiconductor device as claimed in claim 15, characterized in that, The source active region is connected to the gate active region.

18. The semiconductor device as claimed in claim 1, characterized in that, The plurality of active drain blocks include rectangular, circular or elliptical shapes.

19. The semiconductor device as claimed in claim 1, characterized in that, The plurality of active drain blocks include a plurality of first active drain blocks and a plurality of second active drain blocks, wherein a first area of ​​each first active drain block is not equal to a second area of ​​each second active drain block.

20. The semiconductor device as claimed in claim 1, characterized in that, Including: A gate electrode is disposed on the active gate region; One source contact is electrically connected to the active region of that source. A drain electrode, electrically connected to the plurality of drain contacts; and A source electrode is electrically connected to the source contact area.

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