A tiled integration method of a modular reusable sensor readout circuit
By using a modular and reusable sensor readout circuit splicing and integration method, the problems of process bundling, low yield and rigid design in image sensor integration are solved. The optimization of sensing and readout units is achieved, improving chip yield and system flexibility, reducing costs, and making it suitable for high-end applications such as large-area image sensors and infrared focal plane arrays.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- DALIAN UNIV OF TECH
- Filing Date
- 2026-01-27
- Publication Date
- 2026-06-16
AI Technical Summary
Existing technologies for integrating image sensors suffer from problems such as complex process binding, low yield, rigid design, and performance bottlenecks, especially in large-size, high-performance applications.
A modular and reusable sensor readout circuit splicing and integration method is adopted. By setting multiple readout circuit sub-modules under the optical photosensitive element, heterogeneous integration is achieved through steps such as passivation layer opening, global planarization, high-density interconnection and bonding, abandoning the traditional single-chip or "one-to-one" integration mode.
The performance of the sensing and readout units has been optimized, improving the overall chip yield, enhancing system flexibility and the reusability of core IP, significantly reducing manufacturing and mask costs, shortening the R&D cycle, and improving production line utilization and market competitiveness.
Smart Images
Figure CN122227692A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of circuit design, and relates to a splicing integration method of a modular reusable sensor readout circuit. BACKGROUND
[0002] With the Internet of Things entering a new development period, the market has higher requirements for the functional diversity and development convenience of chips, and the standard for the integration level of chips is further improved. At present, image sensor technology is evolving towards three-dimensional vertical integration. In order to realize efficient fusion of sensing units and readout circuits, related existing technologies are constantly being upgraded and optimized. The current mainstream technical path mainly falls into two categories: "All-in-One" monolithic integration scheme and "one-to-one" stacked integration scheme. However, both of these two technical modes have inherent limitations that are difficult to break through, thereby limiting the development and application of high-performance and cost-effective image sensors, especially in the field of large array image sensors or special purpose image sensors, the restricting effect is more prominent.
[0003] "All-in-One" is the traditional monolithic integration mode, which requires that the sensor and the readout circuit (ROIC) must share the same silicon substrate and adopt a unified manufacturing process. This mode directly limits the performance of the chip. In the manufacturing process of the sensor layer, in order to optimize the quantum efficiency and reduce the dark current as much as possible, special doping profiles or dielectric layer structures are often required. In order to achieve high speed and low noise performance, advanced readout circuit ROIC pursues smaller feature sizes. Therefore, bundling the sensor and ROIC processes not only limits the improvement of chip performance, but also increases the complexity and cost of manufacturing due to the introduction of non-standard steps. At the same time, with the expansion of the sensor size, the area of the monolithic chip will also increase sharply, and the defect density distribution problem existing in the semiconductor manufacturing process will have a significant impact on the yield of large-size chips, thereby causing the manufacturing cost to increase super-linearly. In addition, this integration mode has poor design flexibility. Once the sensor or ROIC specifications change, the entire chip needs to be redesigned and verified. Therefore, this integration mode has a long development cycle and cannot quickly reuse mature and verified ROIC modules for different sensor product lines, resulting in repeated investment of research and development resources.
[0004] Currently, three-dimensional vertical integration of image sensing units and readout circuits, i.e. three-dimensional stacking technology, has become the mainstream technology direction to improve system performance and reduce power consumption. This technology mode is to manufacture Sensor Die and ROIC Die respectively, and then complete interconnection through through-silicon via (TSV) and hybrid bonding technology. However, the current mainstream stacking mode usually adopts a "one-to-one" rigid architecture in which one sensor chip corresponds to one complete readout circuit chip. When applied to large-size sensors, the disadvantages of this architecture will be magnified. First, the ROIC chip itself belongs to a large-scale digital-analog hybrid circuit with complex structure, and the loss of transmission signal caused by ultra-long distance wiring, serious clock and power distribution noise, and inconsistent performance of chip edge and center will all affect the performance of the chip. Second, the yield of the large-size readout circuit chip of this mode is also limited, greatly increasing the cost of qualified products. Finally, this large readout circuit chip designed for a specific large-size sensor means a long research and development cycle, high engineering cost and mask cost for each design iteration, and any design error or specification adjustment will bring huge economic cost. Therefore, although the three-dimensional stacking solves the problem of process binding, the "one-to-one" architecture is still limited by poor scalability, poor economy and slow design iteration when facing large-size and high-performance applications. SUMMARY
[0005] In order to solve the core problems of process binding, low yield, design rigidity and performance bottleneck existing in the industry for a long time, the technical scheme adopted by the present application is: a splicing integration method of a modular reusable sensor readout circuit, the sensor comprising an optical photosensitive element and a plurality of readout circuit sub-modules arranged below the optical photosensitive element, a fixed connection method of the optical photosensitive element and the plurality of readout circuit sub-modules, comprising the following steps:
[0006] The wafer surface of the readout circuit sub-module is opened to the passivation layer, the top layer metal pad and the bottom layer metal pad are exposed in turn, and a pad opening structure is formed; The wafer surface of the plurality of opened readout circuit sub-modules is globally planarized, so that the surface of the dielectric layer and the surface of the copper pad reach the same height plane; The readout circuit sub-module after planarization of the surface is high-density interconnected; The interconnected readout circuit sub-module and the optical photosensitive element wafer are bonded, and the formed sensor whole after bonding is solidified; The sensor whole is standard wafer-level packaged, and solder balls are planted to complete electrical lead-out.
[0007] Further, the process of opening the passivation layer on the wafer surface of the readout circuit sub-module, sequentially exposing the top layer metal pad and the bottom layer metal pad, and forming a pad opening structure is as follows: After the front-end process is completed, the passivation layer on the wafer surface of the readout circuit sub-module is opened to expose the top layer metal pad; Photoresist is spin-coated on the wafer surface, and deep ultraviolet or a photoetching machine is used for exposure; A bonding window pattern defining the readout circuit sub-unit area is exposed, and after developing, the photoresist in the window area is removed, thereby forming a photoresist mask pattern on the passivation layer; Using the photoresist pattern as a mask, the passivation layer in the window area is removed by reactive ion etching or inductively coupled plasma etching method until the bottom layer copper metal pad surface is completely exposed; Then, the photoresist is removed and cleaned to form a pad opening structure.
[0008] Further, the process of high-density interconnection on the readout circuit sub-module after planarization is as follows: A layer of dielectric material is deposited on the entire wafer surface of the readout circuit sub-module after opening; The deposited dielectric layer is globally chemically mechanically polished to remove the dielectric material above the copper pad surface, and the dielectric layer surface and the copper pad surface are brought to the same height plane, thereby achieving global planarization; Finally, the dielectric material is only retained in the gap area of the readout circuit sub-module.
[0009] Further, the method of depositing a layer of dielectric material on the entire area uses plasma enhanced chemical vapor deposition.
[0010] Further, the dielectric material uses organic-inorganic hybrid dielectric material, the dielectric constant of the organic-inorganic hybrid dielectric material is between 2.5 and 3.5, and the thin film stress is less than 100 MPa.
[0011] Further, the surface roughness of the dielectric material is Ra<0.5 nm.
[0012] Further, the process of high-density interconnection on the readout circuit sub-module after planarization uses a semi-additive method to prepare a copper redistribution layer, which is as follows: First, a titanium Ti or copper Cu seed layer is sputtered, and then a redistribution layer RDL pattern is defined by photoetching, Then, copper electroplating is performed to form interconnection traces; Finally, the photoresist is removed and the excess seed layer is etched.
[0013] Furthermore: the process of bonding the interconnected readout circuit submodule to the optical photosensitive element wafer, and then solidifying the bonded sensor assembly, is as follows: The optical sensor wafer is subjected to plasma activation treatment, and surface organic contaminants are removed in a vacuum environment; Interconnect pad openings are fabricated at corresponding locations on the sensor wafer; Multiple standardized ROIC chips are pre-aligned with the entire sensor wafer; Then, by using infrared transmission alignment or optical microscopy alignment systems, submicron-level precise alignment of the μbump array and the sensor metal pad is achieved. Under vacuum or inert atmosphere protection, apply a pressure of 1-10 MPa and perform hot-press bonding at a temperature of 250-350℃; Subsequently, capillary underfill or molding underfill processes are used to inject epoxy resin into the gap between the readout circuit submodule and the optical sensor wafer, and then cure it.
[0014] A sensor includes an optical photosensitive element and a plurality of readout circuit sub-modules disposed below the optical photosensitive element. The fixed connection between the optical photosensitive element and the plurality of readout circuit sub-modules is achieved by splicing and integrating any of the modular and reusable sensor readout circuits described herein.
[0015] Furthermore, the number of readout circuit submodules is determined based on the surface area of the optical photosensitive element and the surface area of the readout circuit submodules.
[0016] This invention proposes a scalable and reconfigurable modular design method for readout circuits to adapt to sensors of different array sizes. It also proposes an innovative, modular, scalable three-dimensional stacking architecture, aiming to fundamentally reshape the integration paradigm of high-performance image sensors. The core idea of this architecture is to abandon the traditional monolithic or "one-to-one" integration mode and instead adopt a flexible "one-to-many" heterogeneous integration strategy.
[0017] This method completely breaks free from process constraints, optimizes the performance of the sensing and readout units, significantly improves the overall chip yield, enhances the system's flexibility and the reusability of core IP, effectively reduces the high cost of photomasks, improves production line utilization and market competitiveness, opens up a new path of high performance and high reliability, and provides a powerful driving force for cost reduction and product iteration at the commercial level.
[0018] This invention is not merely a simple improvement on existing technical approaches, but rather a revolutionary advantage at the system level, specifically manifested in the following aspects: First, this invention completely breaks free from process constraints, achieving optimal performance for both the sensing and readout units. The sensor layer (optical photosensitive element layer) and the ROIC layer (readout circuit submodule layer) can be manufactured separately on independent and optimized semiconductor process lines. This means that the sensor can employ customized special processes, focusing on achieving ultimate quantum efficiency, low dark current, and other optoelectronic properties; while the ROIC unit can utilize the most advanced and cost-effective standard CMOS processes, focusing on achieving high-speed, low-noise readout and complex digital processing functions. Finally, electrical connection is achieved at the bonding interface, maximizing the performance of both.
[0019] Secondly, this invention can significantly improve the overall yield of chips and drastically reduce manufacturing costs, which is the most direct and commercially attractive economic advantage. By using wafer-level heterogeneous integration and chip partitioning strategies, replacing a single large-area ROIC with multiple small-sized standardized ROIC chip units can fully utilize the statistical distribution characteristics of defect density to achieve a leap in system-level yield.
[0020] Furthermore, small-size standardized cells can perform known good chip (KGD) screening at the wafer level, eliminating defective cells through wafer acceptance testing (WAT) and die sorting, and using only qualified chips for subsequent hybrid bonding, fundamentally preventing defects from propagating to the system level. This defect decoupling mechanism transforms back-end process yield losses from the wafer level to the chip level, greatly reducing effective chip costs and significantly improving supply chain flexibility and economies of scale.
[0021] Third, this design significantly enhances the system's flexibility and the reusability of its core IP. By employing standardized ROIC units as the basic building blocks, the system design shifts from traditional fully customized approaches to flexible modular combinations. By simply increasing or decreasing the number of ROIC units and adjusting their planar arrangement, sensor products of different specifications and resolutions can be quickly constructed, drastically shortening the new product development cycle. Simultaneously, the repetitive production of standardized chips can significantly reduce the high cost of photomasks, greatly improving production line utilization and market competitiveness.
[0022] Finally, this invention also helps optimize overall reliability. Each small-sized ROIC unit is responsible for signal readout in a local area, achieving localization and minimization of the signal path. This effectively reduces parasitic parameters, signal crosstalk, and transmission delay caused by long-distance global wiring, providing a physical basis for achieving higher frame rates and lower noise. Simultaneously, the distributed, small-unit power supply and thermal management scheme is more feasible and efficient compared to centralized large-chip solutions, helping to reduce local heat density, alleviate thermal crosstalk problems, and thus improve the overall reliability of the system during long-term operation.
[0023] In summary, the modular three-dimensional stacked structure proposed in this invention, through modular design, cross-process node integration, and advanced packaging, not only opens up a new path for high performance and high reliability at the technical level, but also provides a powerful driving force for cost reduction and accelerated product iteration at the commercial level. It is particularly suitable for cutting-edge high-end application fields such as large-area image sensors, infrared focal plane arrays, and event vision sensors, which have stringent requirements for size, performance, and cost. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the "one-to-many" heterogeneous integration strategy proposed in this invention; wherein (a) is a schematic diagram of the substrate and readout integrated circuit structure; (b) is an oxide filling diagram between readout integrated circuit modules; (c) is a schematic diagram of the redistribution and pad formation structure before bonding; and (d) is a detailed diagram of the vertical interconnect structure. Figure 2 This is a schematic diagram of the layout of the ROIC standardized unit in a specific embodiment of the present invention; Figure 3 This is a schematic diagram of signal interconnection and transmission in a specific embodiment of the present invention; Figure 4 This is a schematic diagram of the sensor layer and ROIC layer in a specific embodiment of the present invention; wherein (a) is the sensor photosensitive module, and (b) is the sensor readout circuit. Detailed Implementation
[0026] It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0028] A method for splicing and integrating modular and reusable sensor readout circuits, wherein the sensor includes an optical photosensitive element and multiple readout circuit sub-modules disposed below the optical photosensitive element. The data of the readout circuit submodule is determined based on the surface area of the optical photosensitive element.
[0029] The number of readout circuit submodules is determined by dividing the surface area of the optical photosensitive element by the surface area of the readout circuit submodule; A large-area sensor chip is interconnected with multiple smaller, standardized readout circuit chip units below it using industry-leading high-density hybrid bonding technology. In other words, during the preparation stage before bonding, modular standard ROIC units are designed to expand, reconstruct, and integrate sensors of different array sizes.
[0030] A method for fixing an optical photosensitive element to multiple readout circuit submodules includes the following steps: The passivation layer of the readout circuit submodule is made into a hole, exposing the top metal pad and the bottom metal pad in sequence, forming a pad hole structure. Global planarization is performed on the wafer surface of the readout circuit submodule after multiple openings, so that the surface of the dielectric layer and the surface of the copper pad are at the same height plane. High-density interconnection is performed on the readout circuit submodules after the surface is planarized; The interconnected readout circuit submodules are bonded to the optical photosensitive element wafer, and the bonded sensor as a whole is solidified. The sensor is packaged using standard wafer-level packaging and solder balls are added to complete the electrical lead-out.
[0031] Furthermore: the process of creating passivation layer openings on the wafer surface of the readout circuit submodule to sequentially expose the top-layer metal pads and the bottom-layer metal pads, and forming a pad opening structure, is as follows: Passivation layer openings are made on the wafer surface of the readout circuit submodule after the front-end process has been completed to expose the top metal pads. Photoresist is spin-coated onto the wafer surface and then exposed using deep ultraviolet light or a photolithography machine. Define the bonding window pattern of the readout circuit sub-unit region, expose it and then treat it with a developer to remove the photoresist in the window region, thereby forming a photoresist mask pattern on the passivation layer; Using a photoresist pattern as a mask, reactive ion etching or inductively coupled plasma etching methods are used to selectively remove the passivation layer in the window area until the surface of the underlying copper metal pads is fully exposed. The adhesive is then removed and cleaned to create the pad opening structure.
[0032] Furthermore, the process of performing high-density interconnection on the readout circuit submodules after planarization is as follows: A dielectric material is deposited over the entire wafer surface of the readout circuit submodule after the aperture is opened. Global chemical mechanical polishing is performed on the deposited dielectric layer to remove the dielectric material that protrudes above the surface of the copper pads and to make the surface of the dielectric layer and the surface of the copper pads reach the same height plane, thereby achieving global planarization. Ultimately, the dielectric material is only retained in the gap area of the readout circuit submodule.
[0033] Furthermore, the entire deposition of a medium material is performed using plasma-enhanced chemical vapor deposition.
[0034] Furthermore, the dielectric material is an organic-inorganic hybrid dielectric material with a dielectric constant between 2.5 and 3.5 and a film stress of less than 100 MPa. The specific dielectric constant depends on the process node and performance requirements; a lower dielectric constant means less "impedance" to electrical signals. The film stress is below 100 MPa and tends towards micro-compressive stress or near-zero stress. Improper stress control may cause wafer warping, film cracking or delamination, and affect device reliability.
[0035] Organic-inorganic hybrid media materials refer to a single composite / hybrid material that simultaneously contains organic and inorganic components at the molecular / nanoscale.
[0036] Furthermore, the surface roughness Ra of the dielectric material is <0.5 nm. The target final thickness of the dielectric layer is typically in the range of 100-500 nm. Furthermore: the readout circuit submodule after planarization is subjected to high-density interconnection, and a copper redistribution layer is prepared using a semi-additive method, as detailed below: First, a titanium (Ti) or copper (Cu) seed layer is sputtered, and then the redistribution layer (RDL) pattern is defined by photolithography. Next, copper electroplating is performed to form interconnect traces; Finally, the photoresist is removed and the excess seed layer is etched away.
[0037] Furthermore: the process of bonding the interconnected readout circuit submodule to the optical photosensitive element wafer, and then solidifying the bonded sensor assembly, is as follows: The optical sensor wafer is subjected to plasma activation treatment, and surface organic contaminants are removed in a vacuum environment; Interconnect pad openings are fabricated at corresponding locations on the sensor wafer; Multiple standardized ROIC chips are pre-aligned with the entire sensor wafer; Then, by using infrared transmission alignment or optical micro-alignment systems, submicron-level precise alignment of the μbump array and the metal pads of the sensor pad can be achieved. Under vacuum or inert atmosphere protection, apply a pressure of 1-10 MPa and perform hot pressing bonding at a temperature of 250-350℃; Subsequently, capillary underfill or molding underfill processes are used to inject epoxy resin into the gap between the readout circuit submodule and the optical sensor wafer, and then cure it.
[0038] Example 1 Reference Figure 1 , Figure 1 This is a schematic diagram of the "one-to-many" heterogeneous integration strategy proposed in this invention; wherein (a) is a schematic diagram of the substrate and readout integrated circuit structure; (b) is an oxide filling diagram between readout integrated circuit modules; (c) is a schematic diagram of the redistribution and pad formation structure before bonding; and (d) is a detailed diagram of the vertical interconnect structure. Figure 2 This is a schematic diagram of the layout of the ROIC standardized unit in a specific embodiment of the present invention; Figure 3 This is a schematic diagram of signal interconnection and transmission in a specific embodiment of the present invention. Figure 4 This is a schematic diagram of the sensor layer and ROIC layer in a specific embodiment of the present invention; wherein (a) is the sensor photosensitive module, and (b) is the sensor readout circuit.
[0039] For a 40mm The 40mm large-area infrared sensor no longer requires a matching ROIC of the same size; instead, it connects with four well-validated 20mm sensors on the lower layer. The 20mm standardized ROIC chip unit is integrated. The process flow is described below: First, passivation layer openings are made on the surface of the readout circuit ROIC wafer after the front-end process is completed to expose the top metal pads. Photoresist is spin-coated onto the wafer surface and exposed using deep ultraviolet light or a photolithography machine. The bonding window pattern of the ROIC cell region is precisely defined using a mask, and this pattern must strictly match the subsequent micro-bump array layout. After exposure, the photoresist in the window area is removed by developing, thus forming a photoresist mask pattern with precise dimensions and positions on the passivation layer. The alignment accuracy of this step must be better than ±0.5 µm, which is fundamental to ensuring the reliability of high-density interconnects. Using the photoresist pattern as a mask, reactive ion etching (RIE) or inductively coupled plasma (ICP) etching techniques are used to selectively remove the passivation layer (typically SiO2, Si3N4, or a composite layer thereof) in the window area until the surface of the underlying copper metal pads is fully exposed; subsequently, the photoresist is removed and cleaned to form a clean, steep pad opening structure. Secondly, to achieve surface coplanarity after splicing multiple ROIC chips and to provide a high-quality dielectric interface for subsequent hybrid bonding, dielectric filling and planarization are required. Plasma-enhanced chemical vapor deposition (PECVD) is used to deposit a low-dielectric-constant, low-stress organic-inorganic hybrid dielectric material across the entire ROIC wafer surface after the vias are opened. The deposited dielectric layer undergoes global chemical mechanical polishing to remove the dielectric material protruding above the copper pad surface, ensuring the dielectric layer surface and the copper pad surface are at the same height plane, thus achieving global planarization (requiring a surface roughness Ra < 0.5 nm). Finally, the dielectric material remains only in the gap regions between the ROIC chip units, serving as electrical isolation and mechanical support, while fully exposing the copper pads for electrical connections.
[0040] Then, high-density interconnects are constructed on the planarized surface. A copper redistribution layer is prepared using a semi-additive process (SAP). First, a Ti / Cu seed layer is sputtered, then the RDL pattern is defined by photolithography, followed by copper electroplating to form interconnects with a linewidth / spacing of 2-5 µm. Finally, the photoresist is removed and excess seed layer is etched away.
[0041] Next, the individual sensor wafers (such as IR sensors) undergo plasma activation treatment (commonly using N2 or Ar / O2 mixed gas) to remove surface organic contaminants and increase surface energy in a vacuum environment. Interconnect pad openings are then created at corresponding locations on the sensor wafer using photolithography and etching processes similar to those used for ROIC wafers. A high-precision flip-chip bonding machine is used to pre-align multiple standardized ROIC chips with the entire sensor wafer. Submicron-level precise alignment (typically within ±1µm) is achieved between the μbump array and the sensor pads using an infrared transmission alignment or optical micro-alignment system. Under vacuum or an inert atmosphere (such as N2), thermocompression bonding is performed at 250-350°C with a pressure of 1-10 MPa. During this process, the SnAg solder cap undergoes a eutectic reaction, forming a reliable metallurgical interconnect. Simultaneously, the planarized dielectric layer on the ROIC wafer and the silicon oxide layer on the sensor wafer surface achieve a strong dielectric-dielectric fusion bond under high temperature and pressure through van der Waals force enhancement and interatomic diffusion, thus forming a hybrid bonding interface that combines electrical interconnection and mechanical sealing. After bonding, a low-temperature annealing process is performed at 150-200°C for 2-4 hours to release interfacial thermal stress and stabilize and enhance bond strength. Using capillary underfill or molding underfill processes, epoxy resin is infused into the gap between the ROIC chip and the sensor wafer, followed by curing, effectively dispersing mechanical stress and improving the device's reliability against thermomechanical fatigue.
[0042] Finally, standard wafer-level packaging is performed, and solder balls are added to complete the electrical lead-out of the entire heterogeneous integrated device.
[0043] The entire process must be strictly controlled for thermal parameters to prevent irreversible degradation of the sensor's photosensitive elements due to high temperatures. Simultaneously, online inspection methods such as automated optical inspection (AOI) and X-ray inspection are necessary to monitor bonding alignment accuracy, interconnect integrity, and defects in real time, ensuring high yield and long-term reliability.
[0044] Based on the Poisson yield model, when wafer defects are randomly distributed, the area of a single chip shrinks to 1 / N of its original size, and its individual yield increases from... Upgraded to Where D is the defect density and A is the original chip area. For example, if a wafer has a fatal defect, a single 40mm×40mm wafer will result in 100% failure; however, if it is decomposed into four 20mm×20mm units, only one unit will fail, and the system's effective yield will increase to 75%.
[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for splicing and integrating modular and reusable sensor readout circuits, wherein the sensor includes an optical photosensitive element and multiple readout circuit sub-modules disposed below the optical photosensitive element, characterized in that: A method for fixing an optical photosensitive element to multiple readout circuit submodules includes the following steps: The passivation layer of the readout circuit submodule is made into a hole, exposing the top metal pad and the bottom metal pad in sequence, forming a pad hole structure. Global planarization is performed on the wafer surface of the readout circuit submodule after multiple openings, so that the surface of the dielectric layer and the surface of the copper pad are at the same height plane. High-density interconnection is performed on the readout circuit submodules after the surface is planarized; The interconnected readout circuit submodules are bonded to the optical photosensitive element wafer, and the bonded sensor as a whole is solidified. The sensor is packaged using standard wafer-level packaging and solder balls are added to complete the electrical lead-out.
2. The method for splicing and integrating a modular and reusable sensor readout circuit according to claim 1, characterized in that: The process of creating passivation layer openings on the wafer surface of the readout circuit submodule to sequentially expose the top and bottom metal pads and form a pad opening structure is as follows: Passivation layer openings are made on the wafer surface of the readout circuit submodule after the front-end process has been completed to expose the top metal pads. Photoresist is spin-coated onto the wafer surface and then exposed using deep ultraviolet light or a photolithography machine. Define the bonding window pattern of the readout circuit sub-unit region, expose it and then treat it with a developer to remove the photoresist in the window region, thereby forming a photoresist mask pattern on the passivation layer; Using a photoresist pattern as a mask, reactive ion etching or inductively coupled plasma etching methods are employed to remove the passivation layer in the window area until the surface of the underlying copper metal pads is fully exposed. The adhesive is then removed and cleaned to create the pad opening structure.
3. The method for splicing and integrating a modular and reusable sensor readout circuit according to claim 1, characterized in that: The process of performing high-density interconnection on the readout circuit submodules after planarization is as follows: A dielectric material is deposited over the entire wafer surface of the readout circuit submodule after the aperture is opened. Global chemical mechanical polishing is performed on the deposited dielectric layer to remove the dielectric material that protrudes above the surface of the copper pads and to make the surface of the dielectric layer and the surface of the copper pads reach the same height plane, thereby achieving global planarization. Ultimately, the dielectric material is only retained in the gap area of the readout circuit submodule.
4. The method for splicing and integrating a modular and reusable sensor readout circuit according to claim 3, characterized in that: The deposition of a medium material over the entire area is achieved using plasma-enhanced chemical vapor deposition.
5. The method for splicing and integrating a modular and reusable sensor readout circuit according to claim 3, characterized in that: The dielectric material is an organic-inorganic hybrid dielectric material with a dielectric constant between 2.5 and 3.5 and a film stress of less than 100 MPa.
6. The method for splicing and integrating a modular and reusable sensor readout circuit according to claim 3, characterized in that: The surface roughness Ra of the medium material is less than 0.5 nm.
7. The method for splicing and integrating a modular and reusable sensor readout circuit according to claim 1, characterized in that: The readout circuit submodule after planarization is subjected to high-density interconnection, and a copper redistribution layer is prepared using a semi-additive method, as detailed below: First, a titanium (Ti) or copper (Cu) seed layer is sputtered, and then the redistribution layer (RDL) pattern is defined by photolithography. Next, copper electroplating is performed to form interconnect traces; Finally, the photoresist is removed and the excess seed layer is etched away.
8. The method for splicing and integrating a modular and reusable sensor readout circuit according to claim 1, characterized in that: The process of bonding the interconnected readout circuit submodule to the optical photosensitive element wafer and then solidifying the bonded sensor assembly is as follows: The optical sensor wafer is subjected to plasma activation treatment, and surface organic contaminants are removed in a vacuum environment; Interconnect pad openings are fabricated at corresponding locations on the sensor wafer; Multiple standardized ROIC chips are pre-aligned with the entire sensor wafer; Then, by using infrared transmission alignment or optical microscopy alignment systems, submicron-level precise alignment of the μbump array and the sensor metal pad is achieved. Under vacuum or inert atmosphere protection, apply a pressure of 1-10 MPa and perform hot-press bonding at a temperature of 250-350℃; Subsequently, capillary underfill or molding underfill processes are used to inject epoxy resin into the gap between the readout circuit submodule and the optical sensor wafer, and then cure it.
9. A sensor, characterized in that: It includes an optical photosensitive element and multiple readout circuit sub-modules disposed below the optical photosensitive element. The fixed connection between the optical photosensitive element and the multiple readout circuit sub-modules is achieved by splicing and integrating a modular and reusable sensor readout circuit according to any one of claims 1-8.
10. A sensor according to claim 9, characterized in that: The number of readout circuit submodules is determined based on the surface area of the optical photosensitive element and the surface area of the readout circuit submodules.