Image sensor, arrangement and control method

Abstract

The application provides an image sensor, an arrangement structure and a control method, wherein the image sensor comprises a plurality of pixel units arranged in an array, and each pixel unit comprises: M light sensing modules coupled to a floating diffusion node, which convert a light signal into a first charge signal and a second charge signal, and store and transfer the first charge signal to the floating diffusion node; M overflow modules respectively coupled to the M light sensing modules, which store the second charge signal; M transfer modules coupled between the floating diffusion node and the M overflow modules, which transfer the second charge signal to the floating diffusion node; a reset module coupled to the floating diffusion node, which resets at least the floating diffusion node and each light sensing module; and a readout module coupled to the floating diffusion node, which quantitatively reads at least the first charge signal and the second charge signal. The application solves the problem that high resolution and high signal-to-noise ratio cannot be considered in the prior art.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and in particular relates to an image sensor, its arrangement structure, and a control method. Background Technology

[0002] With the development of portable devices such as smartphones, their photography / videography needs have placed higher performance demands on image sensors, among which higher resolution and higher signal-to-noise ratio (SNR) are two important indicators. Typically, higher resolution and higher SNR in image sensors correspond to smaller pixel size and higher full-well capacity; physically, as pixel size shrinks, device size also shrinks, making it impossible to simultaneously achieve a high full-well capacity. Therefore, how to achieve both high resolution and high SNR is a technical problem that those skilled in the art urgently want to solve.

[0003] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an image sensor, an arrangement structure, and a control method to solve the problem that the prior art cannot simultaneously achieve high resolution and high signal-to-noise ratio.

[0005] To achieve the above and other related objectives, the present invention provides an image sensor comprising a plurality of pixel units arranged in an array, wherein the pixel units include:

[0006] M photosensitive modules are coupled to a floating diffusion node for converting optical signals into a first charge signal and a second charge signal, and storing and transferring the first charge signal to the floating diffusion node.

[0007] M overflow modules are respectively coupled to M photosensitive modules for storing the second charge signal;

[0008] M transfer modules are coupled between the floating diffusion node and the M overflow modules, and are used to transfer the second charge signal to the floating diffusion node; where M is a natural number greater than or equal to 2;

[0009] A reset module, coupled to the floating diffusion node, is used to reset at least the floating diffusion node and each of the photosensitive modules;

[0010] The readout module, coupled to the floating diffusion node, is used to quantize and read out at least the first charge signal and the second charge signal.

[0011] The present invention also provides an image sensor arrangement structure as described in any one of the above claims, comprising:

[0012] The pixel unit has a first region defined in it, and each photosensitive module is arranged in the first region.

[0013] A second region is defined within the first region, and the floating diffusion nodes are arranged within the second region;

[0014] Each of the overflow modules and each of the transfer modules are arranged in the first region, and are respectively arranged on the outer periphery of each of the photosensitive modules;

[0015] The reset module and the readout module are arranged in the second region or on the periphery of the first region.

[0016] The present invention also provides a control method for an image sensor as described in any one of the above claims, comprising:

[0017] During the reset phase, the floating diffusion node, each of the photosensitive modules, and each of the overflow modules are reset.

[0018] During the exposure stage, the overflow modules are controlled to open and the transfer modules are controlled to close. Each photosensitive module generates a first charge signal and a second charge signal based on photoelectric conversion. The first charge signal is stored in each photosensitive module and the second charge signal is stored in each overflow module.

[0019] During the readout phase, each of the overflow modules is shut down to quantize and read out the first reset signal and the first charge signal based on the floating diffusion node;

[0020] The second reset signal is quantized and read out based on the floating diffusion node, and then each of the transfer modules is controlled to open, transferring the second charge signal to the floating diffusion node for quantization and readout; and / or, each of the transfer modules is controlled to open, transferring the second charge signal to the floating diffusion node for quantization and readout, and then the floating diffusion node is reset to quantize and read out the second reset signal.

[0021] As described above, the image sensor, arrangement structure, and control method of the present invention achieve a higher photosensitive area by sharing photosensitive elements and introduce additional overflow capacitors through lateral overflow technology to collect overflowed charge signals, thereby achieving a higher full-well capacity at a smaller pixel size (e.g., <2μm) and achieving a balance between high resolution and high signal-to-noise ratio. Attached Figure Description

[0022] Figure 1 The diagram shown is a circuit diagram of a pixel unit in an image sensor according to Embodiment 1 of the present invention.

[0023] Figure 2 The diagram shown is a circuit diagram of a pixel unit in an image sensor according to Embodiment 2 of the present invention.

[0024] Figure 3 This is a schematic diagram of another circuit of a pixel unit in an image sensor, as shown in Embodiment 2 of the present invention.

[0025] Figure 4 The diagram shown is another circuit schematic of a pixel unit in an image sensor according to Embodiment 2 of the present invention.

[0026] Figure 5 The diagram shown is another circuit schematic of a pixel unit in an image sensor according to Embodiment 2 of the present invention.

[0027] Figure 6 The diagram shown is a circuit diagram of a pixel unit in an image sensor according to Embodiment 3 of the present invention.

[0028] Figure 7 This is shown as another circuit diagram of a pixel unit in an image sensor according to Embodiment 3 of the present invention.

[0029] Figure 8 The diagram shown is another circuit diagram of a pixel unit in an image sensor as illustrated in Embodiment 3 of the present invention.

[0030] Figure 9 The diagram shown is a circuit diagram of a pixel unit in an image sensor according to Embodiment 4 of the present invention.

[0031] Figure 10 The diagram shown is another circuit schematic of a pixel unit in an image sensor according to Embodiment 4 of the present invention.

[0032] Figure 11 The diagram shown is another circuit schematic of a pixel unit in an image sensor as illustrated in Embodiment 4 of the present invention.

[0033] Figure 12 The diagram shown is a schematic representation of one arrangement of pixel units in the image sensor of this invention.

[0034] Figure 13 This diagram illustrates another arrangement of pixel units in the image sensor of the present invention.

[0035] Figure 14 The diagram shows the dynamic range of the image sensor of this invention at 50MP resolution.

[0036] Component designation explanation

[0037] 100 pixel unit

[0038] 110 photosensitive module

[0039] 120 Overflow Module

[0040] 130 transfer module

[0041] 140 Reset Module

[0042] 150 readout module

[0043] 160 gain module

[0044] 170 Fast Reset Module

[0045] 180 Shared Transfer Module Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] Please see Figures 1 to 14 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0048] Example 1

[0049] like Figure 1 As shown, this embodiment provides an image sensor, including a plurality of pixel units 100 arranged in an array; wherein, the pixel unit 100 includes a floating diffusion node FD, M photosensitive modules 110, M overflow modules 120, M transfer modules 130, a reset module 140, and a readout module 150. In this embodiment, M is a natural number greater than or equal to 2; in practical applications, M can be a natural number greater than or equal to 2 and less than or equal to 4, for example, M equals 4.

[0050] M photosensitive modules 110 are coupled to a floating diffusion node FD to convert optical signals into a first charge signal and a second charge signal, store the first charge signal, and transfer the first charge signal to the floating diffusion node FD. In one embodiment, each photosensitive module 110 has the same circuit structure, including a transmission transistor and a photosensitive element; wherein, the control terminal of the transmission transistor receives a transmission control signal, the first terminal of the transmission transistor is coupled to the floating diffusion node FD, and the second terminal of the transmission transistor is coupled to a fourth potential V4 via the photosensitive element. In this example implementation, the second terminal of the transmission transistor is also coupled to a corresponding overflow module 120. In this embodiment, to distinguish each photosensitive module 110, different labels are used to represent the transmission transistor, the photosensitive element, and the transmission control signal; taking M equal to 4 as an example, each transmission transistor is represented by M11 to M14, each photosensitive element is represented by PD1 to PD4, and each transmission control signal is represented by TX1 to TX4.

[0051] In practical applications, the first charge signal refers to the charge signal corresponding to the potential well portion, and the second charge signal refers to the charge signal corresponding to the overflow portion after the charge exceeds the potential well. When the charge sensed by the photosensitive module 110 has not reached the overflow state, the converted charge signal only includes the first charge signal and is stored in the photosensitive module 110. At this time, the second charge signal can be considered zero. When the charge sensed by the photosensitive module 110 reaches the overflow state, the converted charge signal includes both the first and second charge signals. The first charge signal is stored in the photosensitive module 110, while the second charge signal overflows from the photosensitive module 110 and is stored in the overflow module 120. Of course, in some other applications, the first charge signal can also be defined as the potential well charge signal, and the second charge signal can be defined as the overflow or overflow charge signal.

[0052] M overflow modules 120 are respectively coupled to M photosensitive modules 110 for storing the second charge signal. In one embodiment, each overflow module 120 has the same circuit structure, including an overflow transistor and an overflow capacitor; wherein, the control terminal of the overflow transistor receives an overflow control signal, the first terminal of the overflow transistor is coupled to the corresponding photosensitive module 110, and the second terminal of the overflow transistor is coupled to a third potential V3 via the overflow capacitor. In this embodiment, to distinguish each overflow module 120, different labels are used to represent the overflow transistor, overflow capacitor, and overflow control signal; taking M equal to 4 as an example, each overflow transistor is represented by M21 to M24, each overflow capacitor is represented by COF1 to COF4, and each overflow control signal is represented by OFG1 to OFG4.

[0053] M transfer modules 130 are coupled between the floating diffusion node FD and the M overflow modules 120, and are used to transfer the second charge signal to the floating diffusion node FD. In one embodiment, each transfer module 130 has the same circuit structure, including a transfer transistor; wherein, the control terminal of the transfer transistor receives a transfer control signal, the first terminal of the transfer transistor is coupled to the corresponding overflow module 120, and the second terminal of the transfer transistor is coupled to the floating diffusion node FD. In this embodiment, in order to distinguish each transfer module 130, different labels are used to represent the transfer transistor and the transfer control signal; taking M equal to 4 as an example, each transfer transistor is represented by M31 to M34, and each transfer control signal is represented by SW1 to SW4.

[0054] A reset module 140 is coupled to the floating diffusion node FD and is used to reset at least the floating diffusion node FD and each photosensitive module 110; in this embodiment, the reset module 140 also resets each overflow module 120. In one embodiment, the reset module 140 includes a reset transistor M4; the control terminal of the reset transistor M4 receives a reset control signal RST, the first terminal of the reset transistor M4 is coupled to a fifth potential V5, and the second terminal of the reset transistor M4 is coupled to the floating diffusion node FD.

[0055] The readout module 150 is coupled to the floating diffusion node FD and is used to quantize and read out at least the first charge signal and the second charge signal. In one embodiment, the readout module 150 includes a source follower transistor M5 and a select transistor M6; wherein, the control terminal of the source follower transistor M5 is coupled to the floating diffusion node FD, the first terminal of the source follower transistor M5 is coupled to a sixth potential V6, the second terminal of the source follower transistor M5 is coupled to the first terminal of the select transistor M6, the control terminal of the select transistor M6 receives a select control signal SEL, and the second terminal of the select transistor M6 is coupled to the column line BL. Furthermore, the source follower transistors M5 and the select transistors M6 are in a one-to-one correspondence, and their number can be designed according to actual needs to correspondingly read out signals.

[0056] In this embodiment, NMOS transistors are typically used for each transistor, and photodiodes are typically used for each photosensitive element. In this case, the control terminal refers to the gate terminal, the first terminal refers to the drain terminal, and the second terminal refers to the source terminal. Of course, it is also feasible to use PMOS transistors for each transistor and gratings or photoconductors for each photosensitive element. This has no substantial impact on the implementation of the scheme. In addition, each potential should be designed according to actual needs. For example, the third potential V3 is usually a variable potential, the fourth potential V4 is usually ground potential or negative potential, the fifth potential V5 is usually power supply potential, and the sixth potential V6 is usually a variable potential or power supply potential.

[0057] like Figure 12 and Figure 13As shown, this embodiment also provides an image sensor arrangement structure, wherein the image sensor is implemented using the structure described above in this embodiment, and the arrangement structure includes:

[0058] A first region is defined in the pixel unit 100, and each photosensitive module 110 is arranged in the first region;

[0059] The first region contains a second region, and floating diffusion nodes (FDs) are arranged in the second region.

[0060] Each overflow module 120 and each transfer module 130 are arranged in the first region, and are respectively arranged on the outer periphery of each photosensitive module 110;

[0061] The reset module 140 and the readout module 150 are arranged in the second region or on the periphery of the first region.

[0062] In one implementation, M is a natural number greater than or equal to 2 and less than or equal to 4. In the corresponding arrangement structure, based on the number of photosensitive modules 110, each photosensitive module 110 is arranged in a 2*1 or 2*2 form in the first area.

[0063] In one embodiment, each photosensitive module 110 includes a photosensitive element and a transmission transistor. Each transmission transistor is arranged in a first corner region facing each other. In addition, each photosensitive element can be arranged in a 2*1 or 2*2 configuration in the first region.

[0064] Specifically, when there are two photosensitive modules 110, each photosensitive element is arranged in a 2*1 configuration in the first region, that is, the two photosensitive elements are arranged in two adjacent rows of the same column. In this case, there are two sets of first corner regions facing each other. The same column is defined as the first column, and typically two transmission transistors are arranged on the first corner region facing the second column. When there are three photosensitive modules 110, each photosensitive element is arranged in a 2*2 configuration in the first region, that is, the first and second photosensitive elements are arranged in two adjacent columns of the same row, and the third and first photosensitive elements are arranged in two adjacent rows of the same column, or the third and second photosensitive elements are arranged in two adjacent rows of the same column. When there are four photosensitive modules 110, each photosensitive element is arranged in a 2*2 configuration in the first region, that is, the first and second photosensitive elements are arranged in two adjacent columns of the same row, the third and first photosensitive elements are arranged in two adjacent rows of the same column, and the fourth and second photosensitive elements are arranged in two adjacent rows of the same column, such as... Figure 12 and Figure 13 As shown.

[0065] A second region is defined within the first region based on each photosensitive module 110. Specifically, the second region is defined within the first region based on the outer edge of each transmission transistor, as shown by the dashed line in the figure. In this case, the floating diffusion node FD is arranged in the second region. In practical applications, the position of the floating diffusion node FD in the second region is related to the positions of the reset module 140 and the readout module 150; in one example, such as... Figure 12 As shown, if the reset module 140 and the readout module 150 are arranged in the second region, the floating diffusion node FD includes a first node region FD1 and a second node region FD2, which are symmetrically arranged between corresponding transmission transistors. For example, taking M equal to 4, the first node region FD1 is arranged between the first transmission transistor M11 and the third transmission transistor M13, and the second node region FD2 is arranged between the second transmission transistor M12 and the fourth transmission transistor M14; in another example, such as Figure 13 As shown, if the reset module 140 and the readout module 150 are arranged on the outer periphery of the first region, then floating diffusion nodes FD are arranged throughout the second region. It should be noted that the second region defined in the first region based on the outer edge of each transmission transistor is not a strict absolute region boundary including the outer edge, but can be relatively expanded and contracted. Here, the aim is to define the relative position of the second region including the floating diffusion nodes based on the outer edge contour of the transmission transistor.

[0066] Each overflow module 120 is arranged in the first region and is respectively arranged on the outer periphery of each photosensitive module 110. In one embodiment, each overflow module 120 includes an overflow transistor, wherein each overflow transistor is arranged on the outer side or periphery of each photosensitive element; further, each overflow transistor is arranged in any corner region of each photosensitive element other than the first corner region, in order to reduce the layout area. In one example, such as Figure 12 As shown, each overflow transistor is arranged in the second corner region of each photosensitive element, wherein the second corner region and the first corner region are arranged opposite each other. In another example, each overflow transistor is arranged in the third corner region of each photosensitive element, wherein the third corner region and the first corner region are arranged along a first direction, as shown. Figure 13 As shown, or, the third corner region and the first corner region are arranged along the second direction; in practical applications, the first direction refers to the horizontal direction, and the second direction refers to the vertical direction. It should be noted that each overflow module 120 also includes an overflow capacitor, but the overflow capacitor is arranged in other layers, such as in the metal layer above the device layer, and is electrically connected to the corresponding transistor in the device layer through a conductor; while the arrangement structure of this embodiment is mainly for each transistor in the device layer, so the arrangement of the overflow capacitor and other capacitors is not shown.

[0067] Each transfer module 130 is arranged in the first region and is respectively arranged on the outer periphery of each photosensitive module 110. In one embodiment, each transfer module 130 includes a transfer transistor, wherein each transfer transistor is arranged outside each photosensitive element; furthermore, each transfer transistor is arranged adjacent to each overflow transistor, and each transfer transistor is arranged outside each overflow transistor in a clockwise rotation manner to achieve the purpose of minimizing the area occupied by the photosensitive element and minimizing the loss of correlated double sample full-well capacity (CDSFWC). For example, OFG1 to OFG4 correspond to the first to fourth overflow transistors, and SW1 to SW4 correspond to the first to fourth transfer transistors, then: Figure 12 In this process, using each overflow transistor as a reference, the first transfer transistor is rotated clockwise in the order of first, third, fourth, and second to obtain the positions of the second to fourth transfer transistors. Figure 13 Taking the overflow transistors as an example, the positions of the second to fourth transfer transistors can be obtained by rotating the first transfer transistor clockwise in the order of first to fourth.

[0068] The reset module 140 and the readout module 150 are arranged in the same area, which is the outer periphery of either the second or first area. In practical applications, the reset module 140 and the readout module 150 are arranged according to the positions of the overflow transistors to reduce the layout area. In one example, such as... Figure 12 As shown, when the overflow transistors are arranged in the second corner region of each photosensitive element, the reset module 140 and the readout module 150 are arranged in the second region; in one embodiment, the reset module 140 includes a reset transistor, and the readout module 150 includes a source follower transistor and a select transistor, wherein the source follower transistor is arranged between two node regions (a first node region and a second node region), the reset transistor is arranged outside either node region, for example, outside the second node region, and the select transistor is arranged outside the source follower transistor away from the node region, for example, above the source follower transistor. In another example, as... Figure 13As shown, when each overflow transistor is arranged in the third triangular region of each photosensitive element, the reset module 140 and the readout module 150 are arranged on the outer side or periphery of the first region relative to the first and third corner regions. Furthermore, the arrangement direction of the reset module 140 and the readout module 150 is the same as the arrangement direction of the first and third corner regions. For example, if the first and third corner regions are arranged along a first direction, then the reset module 140 and the readout module 150 are arranged on the outer side or periphery of the first region and are also arranged along the first direction. If the first and third corner regions are arranged along a second direction, then the reset module 140 and the readout module 150 are arranged on the outer side or periphery of the first region. The left outer side or periphery of the domain and both are also arranged along the second direction; in one embodiment, the reset module 140 includes a reset transistor, and the readout module 150 includes a source follower transistor and a select transistor, wherein the source follower transistor is arranged corresponding to the floating diffusion node FD, for example, the center of the source follower transistor and the floating diffusion node FD is on the same vertical line, or the center of the source follower transistor and the floating diffusion node FD is on the same horizontal line, and the reset transistor and the select transistor are arranged on both sides of the source follower transistor, for example, the reset transistor is arranged on the left side of the source follower transistor, and the select transistor is arranged on the right side of the source follower transistor.

[0069] This embodiment also provides a control method for an image sensor, including a reset stage, an exposure stage, and a readout stage; wherein the image sensor is implemented using the structure described above in this embodiment.

[0070] During the reset phase, the floating diffusion node FD, each photosensitive module 110 and each overflow module 120 are reset. In fact, the reset module 140 is used to reset the floating diffusion node FD, each photosensitive module 110 and each overflow module 120.

[0071] For example, by controlling the reset transistor M4, each transmission transistor, and each transfer transistor to turn on, the floating diffusion node FD, each photosensitive element, and each overflow capacitor are cleared of charge, completing the reset operation; afterwards, the reset transistor M4, each transmission transistor, and each transfer transistor are turned off. As an optional solution, during the reset operation, each overflow transistor can also be turned on, which is beneficial for the execution of the reset operation of each overflow capacitor.

[0072] During the exposure stage, each overflow module 120 is controlled to open and each transfer module 130 is controlled to close. Each photosensitive module 110 generates a first charge signal and a second charge signal based on photoelectric conversion. The first charge signal is stored in each photosensitive module 110 and the second charge signal is stored in each overflow module 120.

[0073] For example, controlling the opening of each overflow transistor: if the overflow transistors were already opened during the reset phase, they do not need to be opened again in this phase; since the transfer transistors were already closed during the reset phase, they do not need to be closed again in this phase. When the amount of charge sensed by each photosensitive element has not reached the overflow state, the converted charge signal only includes the first charge signal, which is stored on each photosensitive element. At this time, although the overflow transistors are opened, no second charge signal is stored in the overflow capacitors via the overflow transistors, so the second charge signal can be considered zero. When the amount of charge sensed by each photosensitive element reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal. The first charge signal is stored on each photosensitive element, and the second charge signal is stored in the overflow capacitors via the overflow transistors. However, since the transfer transistors are already closed, the overflowed second charge signal will not affect the floating diffusion node. Finally, controlling the opening of each overflow transistor.

[0074] The readout phase includes correlation double sampling of the first charge signal, correlation double sampling of the second charge signal, and at least one of correlation double sampling of the second charge signal and non-true correlation double sampling of the second charge signal.

[0075] In one example, the readout phase includes correlation double sampling of a first charge signal and correlation double sampling of a second charge signal. Specifically, each overflow module 120 is controlled to be turned off to quantize and read out the first reset signal and the first charge signal based on the floating diffusion node FD, achieving correlation double sampling of the first charge signal. The second reset signal is quantized and read out based on the floating diffusion node FD, and then each transfer module 130 is controlled to be turned on to transfer the second charge signal to the floating diffusion node FD for quantization and readout, achieving correlation double sampling of the second charge signal; furthermore, the floating diffusion node FD is first reset, and then the second reset signal is quantized and read out based on the floating diffusion node FD.

[0076] For example, since the overflow transistors have been turned off during the exposure stage, they do not need to be turned off again in this stage. First, the selection transistor M6 is turned on to quantize and read out the first reset signal based on the floating diffusion node FD. Then, the transfer transistors are turned on and then off to transfer the first charge signal stored in each photosensitive element to the floating diffusion node FD and quantize and read out. In this way, the correlation double sampling of the first charge signal is completed. First, the reset transistor M4 is turned on and then off to reset the floating diffusion node FD and quantize and read out the second reset signal based on the floating diffusion node FD. Then, the transfer transistors are turned on and then off to transfer the second charge signal stored in each overflow capacitor to the floating diffusion node FD and quantize and read out. In this way, the correlation double sampling of the second charge signal is completed.

[0077] In another example, the readout phase includes correlated double sampling of the first charge signal and non-true correlated double sampling of the second charge signal. Specifically, each overflow module 120 is controlled to shut down to quantize and read out the first reset signal and the first charge signal based on the floating diffusion node FD, achieving correlated double sampling of the first charge signal. Each transfer module 130 is controlled to open to transfer the second charge signal to the floating diffusion node FD for quantization and readout, and then the floating diffusion node FD is reset to quantize and read out the second reset signal, achieving non-true correlated double sampling of the second charge signal.

[0078] For example, first, control each transfer transistor to turn on and then off, transferring the second charge signal stored in each overflow capacitor to the floating diffusion node FD and quantizing it for readout; then, control the reset transistor M4 to turn on and then off, resetting the floating diffusion node FD, and quantizing the second reset signal based on the floating diffusion node FD; thus, a non-true correlation double sampling of the second charge signal is completed. It should be noted that the method for correlation double sampling of the first charge signal is the same as in the previous example, and will not be repeated here.

[0079] In another example, the readout phase includes correlated double sampling of the first charge signal, correlated double sampling of the second charge signal, and non-true correlated double sampling of the second charge signal. It should be noted that the methods for correlated double sampling of the first charge signal, correlated double sampling of the second charge signal, and non-true correlated double sampling of the second charge signal are the same as in the previous example, and will not be repeated here.

[0080] In one example, the method for reading the second charge signal in each overflow module 120 includes: reading by combining the second charge signals from at least two overflow modules 120, or reading the second charge signal from each overflow module 120 separately. For example, in Figure 1In the example shown, one implementation involves simultaneously activating the corresponding transfer modules 130 in the four overflow modules, allowing the second charge signals from the four overflow modules to be read out in a merged manner. In this case, the correlated double sampling and non-true correlated double sampling of the merged signals can output a second reset signal equal to the number of merged second charge signals. When the four overflow modules merge, a second reset signal corresponding to the merged signal can be output. Another implementation involves reading the second charge signals from the four overflow modules separately, such as sequentially reading them in the order of the first to fourth overflow modules. In this case, the correlated double sampling process for the second charge signals can involve each overflow module sequentially reading out a second reset signal and its corresponding second charge signal. The non-true correlated double sampling process for the second charge signals can also involve each overflow module sequentially reading out a second charge signal and its corresponding second reset signal. Of course, in other examples, the signals and their order of reading can be selected according to actual needs.

[0081] Example 2

[0082] like Figures 2-5 As shown, this embodiment provides an image sensor, which differs from the first embodiment in that the pixel unit 100 further includes a gain module 160 for switching between different conversion gains.

[0083] In one example, such as Figure 2 and Figure 3 As shown, the gain module 160 is coupled between the reset module 140 and the floating diffusion node FD. In this case, the second terminal of the reset transistor M4 in the reset module 140 is changed from being coupled to the floating diffusion node FD to being coupled to the gain module 160. In one embodiment, the gain module 160 includes a gain transistor M7; wherein the control terminal of the gain transistor M7 receives a gain control signal DCG, and the first terminal of the gain transistor M7 is coupled to the reset module 140, for example, coupled to the second terminal of the reset transistor M4, and the second terminal of the gain transistor M7 is coupled to the floating diffusion node FD. In this example, the gain module 160 also forms a gain node, wherein the gain node is formed at the first terminal of the gain transistor M7, that is, the first terminal of the gain transistor M7 is used as the gain node. Specifically, this gain node corresponds to the parasitic capacitance of the transistor. Of course, in other implementations, a device capacitance can also be prepared corresponding to this point as the capacitance of the gain node.

[0084] In another example, such as Figure 4 and Figure 5As shown, gain module 160 is coupled to floating diffusion node FD. In one embodiment, gain module 170 includes gain transistor M7 and gain capacitor CCG; wherein, the control terminal of gain transistor M7 receives gain control signal DCG, the first terminal of gain transistor M7 is coupled to floating diffusion node FD, and the second terminal of gain transistor M7 is coupled to a first potential V1 via gain capacitor CCG. In this example, gain module 160 also forms a gain node, wherein the gain node is formed at the second terminal of gain transistor M7, that is, the second terminal of gain transistor M7 is used as the gain node. Gain capacitor CCG can be a device capacitor configured for the node, or it can be a parasitic capacitance of the node.

[0085] In practical applications, the floating diffusion node FD can be replaced by a gain node for electrical connection, so that at least one of the M transfer modules 130 is coupled between the gain node and the corresponding overflow module 120. In this case, the second terminal of the transfer transistor in the corresponding transfer module 130 is changed from being coupled to the floating diffusion node FD to being coupled to the gain node. That is, all M transfer modules 130 can be coupled between the floating diffusion node FD and the M overflow modules 120 (e.g., ...). Figure 2 and Figure 4 Alternatively, all of them can be coupled between the gain node and the M overflow modules 120 (e.g. Figure 3 and Figure 5 Alternatively, some modules can be coupled between the floating diffusion node FD and the corresponding overflow module 120, while others can be coupled between the gain node and the corresponding overflow module 120. However, considering storage capacity and control methods, typically all M transfer modules 130 are coupled between the gain node and the M overflow modules 120. In the example where the gain module 160 is coupled to the floating diffusion node FD, the external gain capacitor CCG can be omitted, such as... Figure 5 As shown, it is also feasible not to omit it, which has no substantial impact on the implementation of the plan.

[0086] In this embodiment, the gain transistor M7 is typically an NMOS transistor. Here, the control terminal refers to the gate terminal, the first terminal to the drain terminal, and the second terminal to the source terminal. Of course, using a PMOS transistor for the gain transistor M7 is also feasible and has no substantial impact on the implementation of the scheme. Furthermore, the first potential V1 is typically a variable potential.

[0087] As an example, when pixel unit 100 includes gain module 160, at least two pixel units have a connection structure between their gain modules to achieve sharing between connected gain modules based on the connection structure; wherein, the gain modules 160 of two adjacent rows of pixel units in the same column may be connected by the connection structure to achieve sharing between connected gain modules. Figure 3Taking the structure shown as an example, the drains of two gain modules can be connected. This allows signal readout from pixels in one row to utilize the low-gain node of the gain module in the other row (corresponding to the drain of the other row's gain module). In one implementation, the gain transistor DCG of the shared pixel unit can be in a turned-off state. The number and location of the pixel units sharing the gain module can be selected according to actual needs. Furthermore, the connection structure can be a metal interconnect fabricated in a metal layer. Of course, at least one switch can be placed on the shared connection path to control the path.

[0088] like Figure 12 and Figure 13 As shown, this embodiment also provides an image sensor layout structure, which differs from Embodiment 1 in that it includes a gain module 160. In this embodiment, the gain module 160, reset module 140, and readout module 150 are arranged in the same area; in one implementation, the gain module 160 includes a gain transistor M7. In one example, as... Figure 12 As shown, when the same region is the second region, the gain transistor M7 and the reset transistor M4 are arranged symmetrically. For example, the reset transistor M4 is arranged outside the first node region FD1, and the gain transistor M7 is arranged outside the second node region FD2. In another example, as... Figure 13 As shown, when the same region is the outer or peripheral side of the first region, the gain transistor M7 is arranged between the reset transistor M4 and the source follower transistor M5.

[0089] This embodiment also provides a control method for an image sensor, which differs from Embodiment 1 in that it includes a reset phase and a readout phase.

[0090] During the reset phase, in addition to resetting the floating diffusion node FD, each photosensitive module 110, and each overflow module 120, the gain module 160 is also reset. For example, during the reset operation, the gain transistor M7 is also turned on to facilitate the reset operation.

[0091] During the readout phase, regarding the first charge signal: The first charge signal is subjected to correlated double sampling under different conversion gains. Specifically, by controlling the gain module 160 to turn on and off, the first reset signal under different conversion gains is quantized and readout based on the floating diffusion node FD. Then, by controlling the gain module 160 to turn off and on again, the first charge signal under different conversion gains is quantized and readout based on the floating diffusion node FD. For example, since the gain transistor M7 is turned on during the reset phase, the image sensor operates at a low conversion gain and quantizes and reads the first reset signal under low conversion gain based on the floating diffusion node FD. Then, the gain transistor M7 is turned off, causing the image sensor to switch to a high conversion gain, and the first reset signal under high conversion gain is quantized and read out based on the floating diffusion node FD. Then, each transmission transistor is turned on and then off, transferring the first charge signal stored in each photosensitive element to the floating diffusion node FD, and quantizing and reading out the first charge signal under high conversion gain based on the floating diffusion node FD. Then, the gain transistor M7 is turned on again, causing the image sensor to switch back to low conversion gain, and quantizing and reading out the first charge signal under low conversion gain based on the floating diffusion node FD. In this way, the correlation double sampling of the first charge signal under different conversion gains is completed.

[0092] Regarding the second charge signal: When the conversion gain 160 is coupled between the reset module 140 and the floating diffusion node FD, the gain transistor M7 needs to be turned on when quantizing and reading the second charge signal. Additionally, the gain transistor M7 is also turned on during the corresponding second reset signal readout. When the conversion gain 160 is coupled to the floating diffusion node FD, the gain transistor M7 can be turned on or off when quantizing and reading the second charge signal, but it is usually turned on. Furthermore, during the corresponding second reset signal readout, the operation of the gain transistor M7 is the same as when the second charge signal is readout; that is, the second reset signal and the second charge signal are read out simultaneously when the gain transistor M7 is on, or simultaneously when the gain transistor M7 is off.

[0093] Example 3

[0094] like Figures 6 to 8As shown, this embodiment provides an image sensor, which differs from Embodiment 1 or Embodiment 2 in that: the pixel unit 100 includes a fast reset module 170, coupled to M overflow modules 120, for fast reset of each overflow module 120. In this case, the second terminal of the overflow transistor in the M overflow modules 120 is changed from being coupled to a third potential V3 via an overflow capacitor to being coupled to the fast reset module 170. In one embodiment, the fast reset module 170 includes a fast reset transistor M8; wherein the control terminal of the fast reset transistor M8 receives a fast reset signal OF_RST, the first terminal of the fast reset transistor M8 is coupled to a second potential V2, and the second terminal of the fast reset transistor M8 is coupled to each overflow module 120, for example, to the end of the overflow capacitor in each overflow module 120 furthest from the overflow transistor.

[0095] In this embodiment, the fast reset transistor M8 is typically an NMOS transistor. Here, the control terminal refers to the gate terminal, the first terminal to the drain terminal, and the second terminal to the source terminal. Of course, using a PMOS transistor for the fast reset transistor M8 is also feasible and has no substantial impact on the implementation of the solution. Furthermore, the second potential V2 and the fifth potential V5 are equal, and are typically the power supply potentials.

[0096] like Figure 12 and Figure 13 As shown, this embodiment also provides an image sensor arrangement structure, which differs from Embodiment 1 or Embodiment 2 in that it includes a fast reset module 170. In this embodiment, the fast reset module 170 is arranged in the same area as the reset module 140 and the readout module 150; in one implementation, the fast reset module 170 includes a fast reset transistor M8. In one example, as... Figure 12 As shown, when the same region is the second region, the fast reset transistor M8 and the select transistor M6 are arranged symmetrically. For example, the select transistor M6 is arranged above the source follower transistor M5, and the fast reset transistor M8 is arranged below the source follower transistor M5. In another example, as... Figure 13 As shown, when the same region is the outer side or periphery of the first region, the fast reset transistor M8 is arranged outside the reset transistor M4.

[0097] This embodiment also provides a control method for an image sensor, which differs from Embodiment 1 or Embodiment 2 in that it includes a reset phase. In one example, the difference from Embodiment 1 or Embodiment 2 may also lie in the readout phase.

[0098] During the reset phase, at least the fast reset module 170 performs a reset operation on each overflow module 120. In one example, the reset module 140 and the fast reset module 170 jointly perform a reset operation on each overflow module 120; for example, during the reset operation, the fast reset transistor M8 is also turned on to clear the charge of each overflow capacitor, completing the reset operation. Afterward, the fast reset transistor and each transfer transistor are turned off. In another example, only the fast reset module 170 performs a reset operation on each overflow module 120; for example, during the reset operation, the fast reset transistor M8 is turned on, but the transfer transistors and / or each overflow transistor are no longer turned on. The charge of each overflow capacitor is cleared, completing the reset operation. Afterward, the fast reset transistor is turned off.

[0099] In one example, during the readout phase, in the case of a non-true correlation sampling readout of the second charge signal, after the second charge signal is readout, a reset operation is performed on the floating diffusion node to quantize and read out the second reset signal. At this time, during the reset operation, the fast reset module can be further opened to quickly reset the overflow module.

[0100] Example 4

[0101] like Figures 9 to 11 As shown, this embodiment provides an image sensor, which differs from Embodiment 1, Embodiment 2 or Embodiment 3 in that: when at least two overflow capacitors in the pixel unit 100 are coupled to the same node (floating diffusion node FD and / or gain node) through the corresponding transfer module 130, the corresponding overflow capacitor can be replaced by a common overflow capacitor COF. At this time, the second terminal of the corresponding overflow transistor is coupled to the third potential V3 through the common overflow capacitor COF, thereby realizing that the corresponding overflow module 120 shares the overflow capacitor.

[0102] In the case of a shared overflow capacitor, the corresponding transfer module 130 should be replaced by a shared transfer module 180 to transfer the second charge signal stored in the overflow capacitor COF to the corresponding node. In one embodiment, the shared transfer module 180 includes a shared transfer transistor M3. The control terminal of the shared transfer transistor M3 receives a common-shift control signal SW. The first terminal of the shared transfer transistor M3 is coupled to the end of the overflow capacitor COF away from the third potential V3, and the second terminal of the shared transfer transistor M3 is coupled to the corresponding node.

[0103] In practical applications, each overflow capacitor is typically coupled to the same node, or a floating diffusion node FD, or a gain node via each transfer module 130. In this case, each overflow capacitor is replaced by a common overflow capacitor COF, and the second terminal of each overflow transistor is coupled to the third potential V3 via the common overflow capacitor COF, thus enabling each overflow module 120 to share the overflow capacitor. At the same time, each transfer module 130 is replaced by a shared transfer module 180; wherein, the shared transfer module 180 includes a shared transfer transistor M3, whose control terminal receives a common-shift control signal SW, whose first terminal is coupled to the end of the common overflow capacitor COF furthest from the third potential V3, and whose second terminal is coupled to the floating diffusion node FD or the gain node.

[0104] This embodiment also provides an image sensor arrangement structure, which differs from Embodiments 1, 2, or 3 in that it includes a shared transfer module 180; wherein at least two transfer modules 130 are replaced by the shared transfer module 180. In one embodiment, the shared transfer module 180 includes a shared transfer transistor M3, wherein the shared transfer transistor M3 is arranged at any of the replaced transfer transistors. In practical applications, typically all transfer modules 130 are replaced by the shared transfer module 180, in which case the shared transfer transistor M3 can be arranged at any of the transfer transistors.

[0105] This embodiment also provides a control method for an image sensor, which is the same as the method in Embodiment 1, Embodiment 2 or Embodiment 3, and will not be described again here.

[0106] In the image sensors of the above embodiments of the present invention, the overflow module 120 and the transfer module 130 are mainly for expanding the dynamic range. When the photosensitive modules 110 are designed in a shared manner, the original potential design can still be used. The design of the present invention brings more improvements to the performance of small-sized pixels and makes it easier to achieve high resolution and high signal-to-noise ratio; taking a 50MP image sensor as an example, the present invention expands the dynamic range at 50MP resolution, such as... Figure 14 As shown, of course, in the case of signal combining, such as at a resolution of 12.5MP, the present invention can also extend its dynamic range.

[0107] In summary, the image sensor, arrangement structure, and control method of the present invention achieve a higher photosensitive area by sharing photosensitive elements and introduces an additional overflow capacitor through lateral overflow technology to collect the overflowed charge signal. This enables higher full-well capacity at a smaller pixel size (e.g., <2μm), achieving a balance between high resolution and high signal-to-noise ratio. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0108] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that, It includes a plurality of pixel units arranged in an array, wherein the pixel units include: M photosensitive modules are coupled to a floating diffusion node for converting optical signals into a first charge signal and a second charge signal, and storing and transferring the first charge signal to the floating diffusion node. M overflow modules are respectively coupled to M photosensitive modules for storing the second charge signal; M transfer modules are coupled between the floating diffusion node and the M overflow modules for transferring the second charge signal to the floating diffusion node; where M is a natural number greater than or equal to 2; A reset module, coupled to the floating diffusion node, is used to reset at least the floating diffusion node and each of the photosensitive modules; The readout module, coupled to the floating diffusion node, is used to quantize and read out at least the first charge signal and the second charge signal.

2. The image sensor according to claim 1, characterized in that, The pixel unit further includes: A gain module, coupled between the reset module and the floating diffusion node, or coupled to the floating diffusion node, is used for switching between different conversion gains; and / or, A fast reset module is coupled to the M overflow modules and is used to quickly reset each of the overflow modules.

3. The image sensor according to claim 2, characterized in that, When the pixel unit includes a gain module and is coupled between the reset module and the floating diffusion node, the gain module includes a gain transistor, the control terminal of the gain transistor receives a gain control signal, the first terminal of the gain transistor is coupled to the reset module, and the second terminal of the gain transistor is coupled to the floating diffusion node. When the pixel unit includes a gain module and is coupled to the floating diffusion node, the gain module includes a gain transistor and a gain capacitor. The control terminal of the gain transistor receives a gain control signal, the first terminal of the gain transistor is coupled to the floating diffusion node, and the second terminal of the gain transistor is coupled to a first potential via the gain capacitor. When the pixel unit includes a fast reset module, the fast reset module includes a fast reset transistor. The control terminal of the fast reset transistor receives a fast reset signal, the first terminal of the fast reset transistor is coupled to a second potential, and the second terminal of the fast reset transistor is coupled to each of the overflow modules. And / or, when the pixel unit includes a gain module, at least two pixel units have a connection structure between the gain modules to enable sharing between the connected gain modules based on the connection structure.

4. The image sensor according to claim 3, characterized in that, When the pixel unit includes a gain module, the gain module also forms a gain node, and at least one of the M transfer modules is coupled between the gain node and the corresponding overflow module; wherein, when the gain module is coupled between the reset module and the floating diffusion node, the first end of the gain transistor serves as the gain node, and when the gain module is coupled to the floating diffusion node, the second end of the gain transistor serves as the gain node.

5. The image sensor according to any one of claims 1 to 4, characterized in that, The overflow module includes an overflow transistor and an overflow capacitor. The control terminal of the overflow transistor receives an overflow control signal. The first terminal of the overflow transistor is coupled to the corresponding photosensitive module, and the second terminal of the overflow transistor is coupled to a third potential via the overflow capacitor. When the pixel unit includes a fast reset module, the second terminal of the overflow transistor is changed from being coupled to the third potential via the overflow capacitor to being coupled to the fast reset module. And / or, the transfer module includes a transfer transistor, the control terminal of the transfer transistor receives a transfer control signal, the first terminal of the transfer transistor is coupled to a corresponding overflow module, and the second terminal of the transfer transistor is coupled to the floating diffusion node; wherein, when at least one of the M transfer modules is coupled between the gain node and the corresponding overflow module, the second terminal of the transfer transistor in the corresponding transfer module is also changed from being coupled to the floating diffusion node to being coupled to the gain node.

6. The image sensor according to claim 5, characterized in that, When the overflow module includes an overflow transistor and an overflow capacitor, and at least two of the overflow capacitors are coupled to the same node via corresponding transfer modules, the corresponding overflow capacitor is replaced by a common overflow capacitor. At this time, the second terminal of the corresponding overflow transistor is coupled to a third potential via the common overflow capacitor. Simultaneously, the corresponding transfer module is replaced by a shared transfer module, wherein the shared transfer module includes a shared transistor, the control terminal of the shared transistor receives a common shift control signal, the first terminal of the shared transistor is coupled to the corresponding common overflow capacitor, and the second terminal of the shared transistor is coupled to the corresponding node.

7. The image sensor according to any one of claims 1 to 4, characterized in that, The photosensitive module includes a transmission transistor and a photosensitive element. The control terminal of the transmission transistor receives a transmission control signal. The first terminal of the transmission transistor is coupled to the floating diffusion node. The second terminal of the transmission transistor is coupled to a fourth potential via the photosensitive element and coupled to the corresponding overflow module. And / or, the reset module includes a reset transistor, the control terminal of the reset transistor receives a reset control signal, the first terminal of the reset transistor is coupled to a fifth potential, and the second terminal of the reset transistor is coupled to the floating diffusion node; wherein, when the pixel unit includes a gain module and the gain module is coupled between the reset module and the floating diffusion node, the second terminal of the reset transistor is coupled to the gain module; And / or, the readout module includes a source follower transistor and a select transistor, the control terminal of the source follower transistor is coupled to the floating diffusion node, the first terminal of the source follower transistor is coupled to a sixth potential, the second terminal of the source follower transistor is coupled to the first terminal of the select transistor, the control terminal of the select transistor receives a select control signal, and the second terminal of the select transistor is coupled to a column line.

8. An image sensor arrangement structure as described in any one of claims 1 to 7, characterized in that, include: The pixel unit has a first region defined in it, and each photosensitive module is arranged in the first region. A second region is defined within the first region, and the floating diffusion nodes are arranged within the second region; Each of the overflow modules and each of the transfer modules are arranged in the first region, and are respectively arranged on the outer periphery of each of the photosensitive modules; The reset module and the readout module are arranged in the second region or on the periphery of the first region.

9. The image sensor arrangement structure according to claim 8, characterized in that, Based on the number of photosensitive modules, each photosensitive module is arranged in a 2*1 or 2*2 pattern in the first region, where M is a natural number greater than or equal to 2 and less than or equal to 4; a second region is defined in the first region based on each photosensitive module.

10. The image sensor arrangement structure according to claim 8, characterized in that, Each of the photosensitive modules includes a photosensitive element and a transmission transistor, with each transmission transistor arranged in a first corner region facing each of the photosensitive elements; wherein a second region is defined based on the outer edge of each transmission transistor; and / or, each of the overflow modules includes an overflow transistor, with each overflow transistor arranged on the outer side or periphery of each of the photosensitive elements; and / or, each of the transfer modules includes a transfer transistor, with each transfer transistor arranged on the outer side of each of the photosensitive elements.

11. The image sensor arrangement structure according to claim 10, characterized in that, When each of the transfer modules includes a transfer transistor, each of the transfer transistors is arranged adjacent to each of the overflow transistors, and each of the transfer transistors is arranged outside each of the overflow transistors in a clockwise rotation manner.

12. The image sensor arrangement structure according to claim 11, characterized in that, When a corresponding transfer module is replaced by a shared transfer module, the shared transfer module includes a shared transfer transistor, which is arranged at any of the transfer transistors being replaced.

13. The image sensor arrangement structure according to claim 10, characterized in that, Each of the overflow transistors is arranged in the second corner region of each of the photosensitive elements, wherein the second corner region and the first corner region are arranged opposite to each other; or, each of the overflow transistors is arranged in the third corner region of each of the photosensitive elements, wherein the third corner region and the first corner region are arranged along a first direction or along a second direction.

14. The image sensor arrangement structure according to claim 13, characterized in that, When each of the overflow transistors is arranged in the second corner region of each of the photosensitive elements, the reset module and the readout module are arranged in the second region; When each of the overflow transistors is arranged in the first triangular region of each of the photosensitive elements, the reset module and the readout module are arranged on the outer side or periphery of the first region relative to the first and third corner regions, wherein the arrangement direction of the reset module and the readout module is parallel to the arrangement direction of the first and third corner regions.

15. The image sensor arrangement structure according to claim 8 or 14, characterized in that, The reset module includes a reset transistor, and the readout module includes a source follower transistor and a select transistor. When the reset module and the readout module are arranged in the second region, the floating diffusion node includes a first node region and a second node region, which are symmetrically arranged between corresponding transmission transistors. The source follower transistor is arranged between the two node regions. The reset transistor is arranged outside any node region. The selection transistor is arranged outside the source follower transistor away from the node region. When the reset module and the readout module are arranged on the outside or periphery of the first region relative to the first corner region and the third corner region, the source follower transistor is arranged corresponding to the floating diffusion node, and the reset transistor and the select transistor are arranged on both sides of the source follower transistor.

16. The image sensor arrangement structure according to any one of claims 8 to 14, characterized in that, The pixel unit further includes a gain module and / or a fast reset module, which are arranged in the same area as the reset module and the readout module; The gain module includes a gain transistor, and the fast reset module includes a fast reset transistor.

17. The image sensor arrangement structure according to claim 16, characterized in that, When the same region is the second region, the gain transistor in the gain module and the reset transistor in the reset module are arranged symmetrically, and the fast reset transistor in the fast reset module and the selection transistor in the readout module are arranged symmetrically. When the same region is the outer side or periphery of the first region, the gain transistor in the gain module is arranged between the reset transistor in the reset module and the source follower transistor in the readout module, and the fast reset transistor in the fast reset module is arranged outside the reset transistor in the reset module.

18. A control method for an image sensor as described in any one of claims 1 to 7, characterized in that, include: During the reset phase, the floating diffusion node, each of the photosensitive modules, and each of the overflow modules are reset. During the exposure stage, the overflow modules are controlled to open and the transfer modules are controlled to close. Each photosensitive module generates a first charge signal and a second charge signal based on photoelectric conversion. The first charge signal is stored in each photosensitive module and the second charge signal is stored in each overflow module. During the readout phase, each of the overflow modules is shut down to quantize and read out the first reset signal and the first charge signal based on the floating diffusion node; The second reset signal is quantized and read out based on the floating diffusion node, and then each of the transfer modules is controlled to open, transferring the second charge signal to the floating diffusion node for quantization and readout; and / or, each of the transfer modules is controlled to open, transferring the second charge signal to the floating diffusion node for quantization and readout, and then the floating diffusion node is reset to quantize and read out the second reset signal.

19. The control method for an image sensor according to claim 18, characterized in that, During the readout phase, when the second reset signal is quantized and readout before the second charge signal, the floating diffusion node is reset first, and then the second reset signal is quantized and readout based on the floating diffusion node. And / or, the method of reading the second charge signal in each of the overflow modules includes: reading by combining the second charge signals in at least two of the overflow modules, or reading the second charge signal in each of the overflow modules separately.

20. The control method for an image sensor according to claim 18 or 19, characterized in that, When the pixel unit includes a gain module, the method for quantizing and reading out the first reset signal and the first charge signal based on the floating diffusion node includes: controlling the gain module to open and then close to quantize and read out the first reset signal under different conversion gains based on the floating diffusion node, and then controlling the gain module to close and then open to quantize and read out the first charge signal under different conversion gains based on the floating diffusion node. And / or, when the pixel unit includes a gain module, the method for quantizing and reading out the second reset signal and the second charge signal based on the floating diffusion node includes: when the gain module is coupled between the reset module and the floating diffusion node, controlling the gain module to be turned on when quantizing and reading out the second reset signal and the second charge signal; when the gain module is coupled to the floating diffusion node, controlling the corresponding gain module to be turned on or off when quantizing and reading out the second reset signal and the second charge signal. And / or, when the pixel unit includes a fast reset module, in at least one of the reset phase and the readout phase of the non-true correlated double sampling of the second charge signal, each of the overflow modules is reset by the fast reset module.

Images