An IBC cell and a method of manufacturing the same

Abstract

The application discloses an IBC battery and a preparation method thereof. The method comprises the following steps: providing a P-type silicon substrate; preparing a first tunneling oxide layer and a first doped layer in a first region; printing a second doped paste in a second region and performing high-temperature propulsion to form a second doped layer in part of the P-type silicon substrate; removing the second doped paste in the second region; performing texturing on the front surface to form a textured structure; preparing a protective layer on the surface of the textured structure by using a preset deposition process; preparing a first passivation layer on the surface of the first doped layer and the second doped layer away from the P-type silicon substrate, and preparing a second passivation layer on the surface of the protective layer away from the P-type silicon substrate; performing screen printing and high-temperature sintering on the first region and the second region to form a first electrode in contact with the first doped layer in the first region and a second electrode in contact with the second doped layer in the second region, thereby obtaining the IBC battery. The method improves the ultraviolet resistance of the IBC battery.

Description

Technical Field

[0001] This invention relates to the technical field of photovoltaic cells, and more particularly to an IBC cell and its preparation method. Background Technology

[0002] The core technology of interdigitated back contact (IBC) solar cells lies in fabricating high-quality, interdigitated p-regions and n-regions on the back of the solar cell. Without the obstruction of metal electrodes on the front, they exhibit higher short-circuit current. Furthermore, the back side allows for wider metal grid lines to reduce series resistance, thereby improving the fill factor. Combined with the open-circuit voltage gain resulting from the surface field on the front of the solar cell and good passivation, this type of unobstructed solar cell not only boasts high conversion efficiency but also a more aesthetically pleasing appearance. Additionally, the fully back-electrode design makes the assembly of the module easier.

[0003] Current methods for fabricating IBC cells typically involve simply creating high-quality, interdigitated P- and N-regions on the back of the solar cell, without any metal electrodes on the front to enhance short-circuit current. However, with the increasing demands for UV degradation resistance in IBC cells, this approach only achieves 5% UV degradation resistance in the first year at UV30, severely impacting the first-year degradation performance and leading to a significant reduction in power generation. Summary of the Invention

[0004] This invention provides an IBC battery and its preparation method, which utilizes preset deposition conditions to prepare a protective layer of a certain thickness on the front side, greatly reducing the UV degradation resistance of the IBC battery, improving the UV resistance of the IBC battery, and thus improving the power generation and conversion efficiency of the IBC battery.

[0005] In a first aspect, the present invention provides a method for preparing an IBC battery, comprising:

[0006] A P-type silicon substrate is provided; the P-type silicon substrate includes a front side and a back side facing away from each other, the back side including a first region and a second region arranged in an interdigitated space;

[0007] A first tunneling oxide layer and a first doped layer are prepared in the first region;

[0008] A second doped paste is printed in the second region and advanced at high temperature to form a second doped layer within a portion of the P-type silicon substrate; the second doped paste in the second region is then removed.

[0009] The front side is napped to create a napped surface structure;

[0010] A protective layer is prepared on the surface of the textured structure using a pre-defined deposition process;

[0011] A first passivation layer is prepared on the side of the first doped layer and the second doped layer facing away from the P-type silicon substrate, and a second passivation layer is prepared on the side of the protective layer facing away from the P-type silicon substrate.

[0012] The first region and the second region are screen printed and sintered at high temperature to form a first electrode in the first region that contacts the first doped layer, and a second electrode in the second region that contacts the second doped layer, thereby obtaining an IBC cell.

[0013] Optionally, a protective layer is prepared on the surface of the textured structure using a pre-defined deposition process, including:

[0014] By introducing water at a flow rate of 18 sccm-23 sccm and trimethylaluminum gas at a flow rate of 12 sccm-17 sccm into the reaction chamber of the preset deposition process, and under preset high temperature conditions of 270℃-320℃, the reaction time is 30s-35s, thus forming a protective layer on the surface of the textured structure.

[0015] Optionally, the thickness of the protective layer can range from 5nm to 6nm.

[0016] Optionally, the first passivation layer includes a first silicon nitride layer;

[0017] A first passivation layer is prepared on the surface of the first doped layer and the second doped layer on the side facing away from the P-type silicon substrate, including:

[0018] A first silicon nitride layer is formed on the side of the first doped layer and the second doped layer away from the P-type silicon substrate using a second deposition process.

[0019] Optionally, the thickness of the first silicon nitride layer is in the range of 80nm-85nm; the refractive index of the first silicon nitride layer is in the range of 2.09-2.12.

[0020] Optionally, the second passivation layer includes a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a silicon oxynitride layer, and a silicon dioxide layer;

[0021] A second passivation layer is prepared on the side of the protective layer facing away from the P-type silicon substrate, including:

[0022] Using a third deposition process, a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a silicon oxynitride layer, and a silicon dioxide layer are sequentially formed on the side of the protective layer facing away from the P-type silicon substrate.

[0023] Optionally, the thickness of the second silicon nitride layer is 8nm-10nm; the thickness of the third silicon nitride layer is 10nm-15nm; the thickness of the fourth silicon nitride layer is 12nm-15nm; the thickness of the silicon oxynitride layer is 8nm-10nm; and the thickness of the silicon dioxide layer is 20nm-25nm.

[0024] Optionally, the refractive index of the second silicon nitride layer is in the range of 2.25-2.3; the refractive index of the third silicon nitride layer is in the range of 2.2-2.25; the refractive index of the fourth silicon nitride layer is in the range of 2.18-2.22; the refractive index of the silicon oxynitride layer is in the range of 2.18-2.2; and the refractive index of the silicon dioxide layer is in the range of 2.12-2.15.

[0025] Optionally, the refractive index of the second passivation layer is in the range of 2.17-2.2, and the thickness of the second passivation layer is in the range of 69nm-72nm.

[0026] Secondly, the present invention provides an IBC battery, which is prepared by the above-described method for preparing an IBC battery.

[0027] The technical solution of this invention involves providing a P-type silicon substrate; the P-type silicon substrate includes a front side and a back side that are opposite to each other, and the back side includes a first region and a second region arranged in an interdigitated pattern; a first tunneling oxide layer and a first doped layer are prepared in the first region; a second doped paste is printed in the second region and subjected to high-temperature propulsion to form a second doped layer in a portion of the P-type silicon substrate; the second doped paste in the second region is removed; a texturing process is performed on the front side to form a textured structure; a protective layer is prepared on the surface of the textured structure using a preset deposition process; a first passivation layer is prepared on the side of the first and second doped layers opposite to the P-type silicon substrate, and a second passivation layer is prepared on the side of the protective layer opposite to the P-type silicon substrate; the first and second regions are screen-printed and sintered at high temperature to form a first electrode in contact with the first doped layer in the first region and a second electrode in contact with the second doped layer in the second region, thereby obtaining an IBC cell. Through the above method, a protective layer of a certain thickness is prepared on the front side using preset deposition conditions, which greatly reduces the UV degradation resistance of the IBC cell, improves the UV resistance of the IBC cell, and thus improves the power generation and conversion efficiency of the IBC cell.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1A flowchart illustrating a method for preparing an IBC battery according to an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the structure of an IBC battery provided in an embodiment of the present invention;

[0032] Figure 3 A flowchart illustrating a second method for preparing an IBC battery according to an embodiment of the present invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, preparation method, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] In one embodiment, Figure 1 This is a flowchart illustrating a method for preparing an IBC battery according to an embodiment of the present invention. Figure 2 This is a schematic diagram of an IBC battery provided in an embodiment of the present invention. This embodiment can be applied to situations where the UV resistance of the IBC battery is improved, such as... Figure 1 and Figure 2 As shown, the method includes:

[0036] S110 provides a P-type silicon substrate.

[0037] The P-type silicon substrate 1 includes a front side and a back side that are opposite to each other. The back side includes a first region and a second region arranged in an interdigitated pattern. Typically, the first region can be an n-region or a p-region, and correspondingly, the second region can be a p-region or an n-region. In this embodiment, the first region can be an n-region, and the second region can be a p-region.

[0038] S120, Prepare a first tunneling oxide layer and a first doped layer in the first region.

[0039] The first tunneling oxide layer 21 allows majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thereby achieving selective carrier collection, reducing surface recombination, improving the open-circuit voltage and fill factor of the battery, and ultimately enhancing the photoelectric conversion efficiency of the IBC battery. In this embodiment, the first tunneling oxide layer 21 can be an ultrathin silicon dioxide layer. The first doped layer 22 is a phosphorus-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with phosphorus.

[0040] Specifically, using a deposition process, a first tunneling oxide layer 21 and a first intrinsic silicon layer are sequentially deposited in the first region. After the formation of the first intrinsic silicon layer, it needs to be elementally doped to form a first doped layer 22. The methods for depositing the first tunneling oxide layer 21 and the first intrinsic silicon layer include, but are not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition, etc., and the specific method can be determined according to the actual situation, without limitation. In this embodiment, the sheet resistance of the formed first doped layer 22 is 45 Ω / sq, and the junction depth of the first doped layer 22 is 0.98 μm.

[0041] S130: Print the second doped paste in the second region and perform high-temperature propulsion to form a second doped layer in a portion of the P-type silicon substrate; remove the second doped paste in the second region.

[0042] The second doped layer 3 is a boron-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with boron. The second doping paste is a mixture formed by doping elements such as boron and silicon. In this embodiment, the second doping paste includes at least a boron-silicon paste.

[0043] Specifically, a second doping paste is printed in the second region to form a second doping paste of a certain thickness on the second region. After printing, the second doping paste is dried, and then subjected to high-temperature propulsion under a preset high-temperature condition, which can be 980℃-1150℃. The high-temperature propulsion equipment can include, but is not limited to, a tube diffusion furnace. After the dried second doping paste is propulsed at high temperature, boron can be propulsed into the P-type silicon substrate 1. The structure formed in the P-type silicon substrate 1 at this time is the high-concentration second doped layer 3. In this embodiment, the concentration of the formed second doped layer 3 is 9.2×10¹⁸ atoms / cm³. 3The sheet resistance of the second doped layer 3 is 220 Ω / sq. After the formation of the second doped layer 3, since the second doped paste will not be completely pushed into the P-type silicon substrate 1 during the high-temperature propagation process, residual second doped paste will still be generated in the second region. Therefore, it is necessary to remove the residual second doped paste. The removal methods may include, but are not limited to, laser etching or chain acid washing, or laser etching and chain acid washing can be used together for removal.

[0044] S140. The front side is velvetted to form a velvet structure.

[0045] Among them, front texturing refers to the special treatment of the front surface of the P-type silicon substrate 1 of the IBC battery during the production process of the IBC battery, forming a rough, textured structure.

[0046] Specifically, using a texturing process, a concentrated sodium hydroxide solution, texturing additive, and water in a volume ratio of 25:8:460 are added to the reaction chamber of the texturing process. Texturing is performed on the front side of the P-type silicon substrate 1 at a texturing temperature of 72°C to form a front-side texturized structure. The texturing time can be 480 seconds.

[0047] S150. A protective layer is prepared on the surface of the velvety structure using a preset deposition process.

[0048] The preset deposition process may include, but is not limited to, ALD deposition. The protective layer may be an alumina layer; the thicker the protective layer, the stronger its UV resistance.

[0049] Specifically, after the textured surface structure is formed on the front side, a protective layer 4 can be deposited on the surface of the textured surface within a preset reaction time using a pre-defined deposition process. This process involves setting specific reaction conditions within the reaction chamber of the pre-defined deposition process. The thickness of the protective layer 4 can range from 5nm to 6nm. For example, the thickness of the protective layer 4 can be 5nm, 5.5nm, or 6nm, and the specific thickness can be determined according to the actual situation. This thickness of protective layer 4 can significantly improve the UV resistance of the IBC battery and greatly reduce its UV degradation value.

[0050] S160. A first passivation layer is prepared on the side of the first doped layer and the second doped layer facing away from the P-type silicon substrate, and a second passivation layer is prepared on the side of the protective layer facing away from the P-type silicon substrate.

[0051] The first passivation layer 5 and the second passivation layer 6 are used to reduce the reflection of sunlight, increase the absorption of sunlight, improve the conversion efficiency of IBC cells, reduce surface recombination, increase the mobility of charge carriers, and improve the overall performance of IBC cells. The second passivation layer 6 can also improve the UV resistance of IBC cells.

[0052] Specifically, using a deposition process, a first passivation layer 5 of a certain thickness is deposited on the surface of the first doped layer 22 and the second doped layer 3 on the side facing away from the P-type silicon substrate 1. After the first passivation layer 5 is formed, a second passivation layer 6 of a certain thickness is deposited on the surface of the protective layer 4 on the side facing away from the P-type silicon substrate 1.

[0053] S170. Screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doped layer in the first region and a second electrode in contact with the second doped layer in the second region, thereby obtaining an IBC cell.

[0054] Screen printing is one of the core processes in IBC battery manufacturing, primarily used for electrode forming. This process utilizes the principle that the paste passes through the mesh openings of the screen in the patterned areas, while the paste does not pass through the non-patterned areas. During printing, the paste is precisely extruded through the mesh openings of the screen onto the P-type silicon substrate 1, forming the desired electrode pattern. Typically, the paste used for screen printing can include, but is not limited to, silver paste. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed onto the surface of the cell at high temperatures, ensuring good ohmic contact between the metal grid lines and the P-type silicon substrate 1.

[0055] Specifically, after forming the first passivation layer 5 on the back side, electrodes need to be formed on the back side to convert photogenerated carriers generated by solar energy into current that flows to the external circuit. In this embodiment, screen printing is performed on the first and second regions on the back side to form metal grid lines on the surfaces of the first and second regions. After forming the metal grid lines, the formed metal grid lines need to be sintered at high temperature so that the sintered metal grid lines can contact the first doped layer 22 and the second doped layer 3 to form an ohmic contact. Specifically, after high-temperature sintering, a first electrode 7 in contact with the first doped layer 22 is formed in the first region, and a second electrode 8 in contact with the second doped layer 3 is formed in the second region, thereby fabricating an IBC battery. In addition, the first electrode 7 and the second electrode 8 have opposite polarities. When the first electrode 7 is a positive electrode, the corresponding second electrode 8 is a negative electrode; when the first electrode 7 is a negative electrode, the corresponding second electrode 8 is a positive electrode. In this embodiment, the first region is an n-region, the second region is a p-region, and the first electrode 7 formed in the p-region is a negative electrode, while the second electrode 8 formed in the n-region is a positive electrode.

[0056] It should be noted that after forming the first electrode 7 and the second electrode 8, the IBC cell undergoes light injection in this embodiment. The temperature of the light injection heating zone is set to 528°C, and the light intensity is 19000 W / m². This adjusts the migration rate and concentration of hydrogen atoms released from the protective layer 4 and the passivation layer. Simultaneously, the IBC cell absorbs photons from sunlight, generating a large number of non-equilibrium charge carriers. These carriers further regulate the charge state of the permeated hydrogen, ultimately leading to the hydrogen atoms combining with internal defects to complete the passivation process. After light injection, the formed IBC cell is laser-induced. The laser power can be set to 16W, and a voltage of 16V is applied across the first electrode 7 and the second electrode 8 of the IBC cell to test its conversion efficiency. The test results show that the conversion efficiency of the IBC cell prepared in this embodiment is 0.62% higher than that prepared by existing methods. In addition, after the conversion efficiency test of the IBC battery is completed, the UV resistance of the IBC battery also needs to be tested. In this embodiment, the UV resistance of the IBC battery is tested under an irradiance of 180W / m2. The test result is that the cumulative irradiance decay value of the IBC battery formed in this embodiment under UV30 is 0.65%, which greatly reduces the UV decay of the IBC battery and improves the UV resistance of the IBC battery.

[0057] The technical solution of this invention involves providing a P-type silicon substrate; the P-type silicon substrate includes a front side and a back side that are opposite to each other, and the back side includes a first region and a second region arranged in an interdigitated pattern; a first tunneling oxide layer and a first doped layer are prepared in the first region; a second doped paste is printed in the second region and subjected to high-temperature propagation to form a second doped layer in a portion of the P-type silicon substrate; the second doped paste in the second region is removed; a texturing process is performed on the front side to form a textured structure; a protective layer is prepared on the surface of the textured structure using a preset deposition process; a first passivation layer is prepared on the side of the first doped layer and the second doped layer opposite to the P-type silicon substrate, and a second passivation layer is prepared on the side of the protective layer opposite to the P-type silicon substrate; screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doped layer and a second electrode in contact with the second doped layer, thereby obtaining an IBC cell. By using the above method, a protective layer of a certain thickness is prepared on the front side using preset deposition conditions, which greatly reduces the UV degradation resistance of IBC cells and improves the UV resistance of IBC cells, thereby improving the power generation and conversion efficiency of IBC cells.

[0058] Figure 3This is a flowchart illustrating a second method for preparing an IBC battery according to an embodiment of the present invention. This embodiment refines the IBC battery preparation method described in the previous embodiments. For details not covered in this embodiment, please refer to the previous embodiments; further elaboration is not required here. Figure 2 and Figure 3 As shown, the method includes:

[0059] S210 provides a P-type silicon substrate.

[0060] S220, Prepare a first tunneling oxide layer and a first doped layer in the first region.

[0061] S230: Print the second doped paste in the second region and perform high-temperature propulsion to form a second doped layer in a portion of the P-type silicon substrate; remove the second doped paste in the second region.

[0062] S240, The front side is velvetted to form a velvet structure.

[0063] S250. By introducing water at a flow rate of 18 sccm-23 sccm and trimethylaluminum gas at a flow rate of 12 sccm-17 sccm into the reaction chamber of the preset deposition process, and under the preset high temperature conditions of 270℃-320℃, the reaction time is 30s-35s, and a protective layer is formed on the surface of the textured structure.

[0064] Specifically, when preparing the protective layer 4 on the textured surface, the ALD's preset deposition process can be used. Water with a flow rate of 18-23 sccm and trimethylaluminum gas with a flow rate of 12-17 sccm are introduced into its reaction chamber. Under the preset high temperature conditions of 270℃-320℃, the water is evaporated to produce water vapor. The oxygen atoms in the water vapor react chemically with the trimethylaluminum gas for 30-35 seconds. By repeating this process 36-41 times, a protective layer 4 with a thickness of 5nm-6nm can be deposited on the textured surface to improve the oxidation resistance of the IBC battery.

[0065] S260. Using a second deposition process, a first silicon nitride layer is formed on the side of the first doped layer and the second doped layer that is away from the P-type silicon substrate.

[0066] The second deposition process includes low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, etc. The specific process can be determined according to the circumstances and is not limited here.

[0067] Specifically, using a second deposition process, such as low-pressure chemical vapor deposition, a first silicon nitride layer is deposited on the surface of the first doped layer 22 and the second doped layer 3 on the side opposite to the P-type silicon substrate 1 by introducing SiH4 gas at a flow rate of 2500 sccm-3200 sccm and ammonia gas at a flow rate of 10000 sccm-15000 sccm into the reaction chamber of the second deposition process, and setting the deposition conditions as follows: deposition pressure of 240N-300N, deposition power of 2400W, deposition temperature of 485℃-500℃, and deposition time of 450s-500s. The thickness of the first silicon nitride layer ranges from 80nm to 85nm. For example, the thickness of the first silicon nitride layer can be 80nm, 82nm, or 85nm, etc., and can be determined according to the actual situation, without limitation here. In addition, the refractive index of the first silicon nitride layer is in the range of 2.09-2.12. For example, the refractive index of the first silicon nitride layer can be 2.09, 2.10, 2.11 or 2.12, etc., which can be determined according to the actual situation and are not limited here.

[0068] S270. Using the third deposition process, a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a silicon oxynitride layer, and a silicon dioxide layer are sequentially formed on the side of the protective layer away from the P-type silicon substrate.

[0069] The third deposition process includes low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, etc. The specific process can be determined according to the circumstances and is not limited here.

[0070] Specifically, using a third deposition process, such as low-pressure chemical vapor deposition, a five-layer passivation structure is formed on the side of the protective layer 4 facing away from the P-type silicon substrate 1. This structure consists of a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a silicon oxynitride layer, and a silicon dioxide layer. The flow rate of SiH4 gas is 2200 sccm-2500 sccm, and the flow rate of ammonia gas is 10000 sccm-15000 sccm. The deposition conditions are set as follows: deposition pressure 1500 N-2000 N, deposition power 2400 W-2700 W, deposition temperature 485℃-520℃, and deposition time 480 s-530 s. The passivation structure comprises five layers: a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a silicon oxynitride layer, and a silicon dioxide layer. The thickness of the second silicon nitride layer ranges from 8 nm to 10 nm. For example, the thickness of the second silicon nitride layer can be 8 nm, 9 nm, or 10 nm, etc., and can be determined according to the actual situation. No limitation is imposed here. The thickness of the formed third silicon nitride layer ranges from 10nm to 15nm. For example, the thickness of the third silicon nitride layer can be 10nm, 12nm, 13nm, or 15nm, etc., and can be determined according to the actual situation, without limitation. The thickness of the formed fourth silicon nitride layer ranges from 12nm to 15nm. For example, the thickness of the fourth silicon nitride layer can be 12nm, 13nm, or 15nm, etc., and can be determined according to the actual situation, without limitation. The thickness of the formed silicon oxynitride layer ranges from 8nm to 10nm. For example, the thickness of the silicon oxynitride layer can be 8nm, 9nm, or 10nm, etc., and can be determined according to the actual situation, without limitation. The thickness of the formed silicon dioxide layer ranges from 20nm to 25nm. For example, the thickness of the silicon dioxide layer can be 20nm, 22nm, 23nm, or 25nm, etc., and can be determined according to the actual situation, without limitation.

[0071] Furthermore, the refractive index of the formed second silicon nitride layer ranges from 2.25 to 2.3. For example, the refractive index of the second silicon nitride layer can be 2.25, 2.26, 2.27, 2.28, 2.29, or 2.3, etc., and can be determined according to the actual situation without limitation. The refractive index of the formed third silicon nitride layer ranges from 2.2 to 2.25. For example, the refractive index of the third silicon nitride layer can be 2.2, 2.21, 2.22, 2.23, 2.24, or 2.25, etc., and can be determined according to the actual situation without limitation. The refractive index of the formed fourth silicon nitride layer ranges from 2.18 to 2.22. For example, the refractive index of the fourth silicon nitride layer can be 2.18, 2.19, 2.2, 2.21, or 2.22, etc., and can be determined according to the actual situation without limitation. The refractive index of the formed silicon oxynitride layer ranges from 2.18 to 2.2. For example, the refractive index of the silicon oxynitride layer can be 2.18, 2.19, or 2.2, etc., and can be determined according to the actual situation without limitation. The refractive index of the formed silicon dioxide layer ranges from 2.12 to 2.15. For example, the refractive index of the silicon dioxide layer can be 2.12, 2.13, 2.14, or 2.15, etc., and can be determined according to the actual situation without limitation. Furthermore, in actual production, the refractive indices of the second, third, and fourth silicon oxynitride layers are usually set to decrease sequentially. That is, the second silicon oxynitride layer has the highest refractive index, and the fourth silicon oxynitride layer has the lowest refractive index. This improves the light utilization rate of the IBC cell, thereby increasing the conversion efficiency of the IBC cell.

[0072] It should also be noted that the overall refractive index range of the formed second silicon nitride layer, third silicon nitride layer, fourth silicon nitride layer, silicon oxynitride layer, and silicon dioxide layer, i.e., the refractive index range of the second passivation layer, is 2.17-2.2. For example, the refractive index of the second passivation layer can be 2.17, 2.18, 2.19, or 2.2, etc., and can be determined according to the actual situation; no limitation is imposed here. The thickness range of the formed second passivation layer is 69nm-72nm. For example, the thickness of the second passivation layer can be 69nm, 70nm, 71nm, or 72nm, etc., and can be determined according to the actual situation; no limitation is imposed here. At this thickness and refractive index, the UV resistance of the IBC cell can be significantly improved, and the conversion efficiency of the IBC cell can be increased.

[0073] S280. Screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doped layer in the first region and a second electrode in contact with the second doped layer in the second region, thereby obtaining an IBC cell.

[0074] The technical solution of this invention involves introducing water at a flow rate of 18-23 sccm and trimethylaluminum gas at a flow rate of 12-17 sccm into the reaction chamber of a preset deposition process. Under preset high-temperature conditions of 270℃-320℃ and a reaction time of 30-35 seconds, a protective layer is formed on the textured surface. A second deposition process is then used to form a first silicon nitride layer on the side of the first and second doped layers facing away from the P-type silicon substrate. Finally, a third deposition process is used to sequentially form a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a silicon oxynitride layer, and a silicon dioxide layer on the side of the protective layer facing away from the P-type silicon substrate. This method significantly reduces UV degradation in IBC batteries, improves their UV resistance, and thus increases their power generation and conversion efficiency.

[0075] In another optional embodiment, this embodiment also provides a process flow for preparing a TBC battery, the specific process including:

[0076] S1. A P-type silicon substrate with dimensions of 182.2mm * 210mm is selected. Before fabricating the IBC battery, the P-type silicon substrate needs to be polished on both sides. In this embodiment, 38L of concentrated sodium hydroxide solution and 12L of alkaline polishing additive are introduced into the reaction chamber of the polishing process, along with 420L of pure water. The P-type silicon substrate is then alkaline polished at a polishing temperature of 70℃-75℃ for a polishing time of 300s-350s to remove mechanical damage layers, dirt, and oil stains from both the front and back sides, ensuring the flatness and cleanliness of the P-type silicon substrate surface. After alkaline polishing, the cube size of the P-type silicon substrate morphology measured under a microscope is 8µm-10µm.

[0077] S2. The P-type silicon substrate after alkali polishing is subjected to low-pressure chemical vapor deposition in a double-intercalation manner, that is, an ultra-thin silicon dioxide layer is deposited on the back side of the P-type silicon substrate, and then a thin intrinsic silicon layer is deposited on the silicon dioxide away from the P-type silicon substrate.

[0078] S3. Phosphorus diffusion is performed on the intrinsic silicon layer to form the first doped layer. The silicon dioxide layer and the first doped layer together form a passivation contact structure, effectively reducing surface recombination and metal-to-metal recombination. Simultaneously with the formation of the first doped layer, a first mask layer, namely a phosphorosilicate glass (PSG) layer, is formed on the surface of the first doped layer away from the P-type silicon substrate. The sheet resistance of the formed first doped layer is 45 Ω / sq, and the junction depth (ECV), i.e., the thickness of the first doped layer, is 0.98 μm.

[0079] S4. The phosphorus-dilated P-type silicon substrate is laser-grooved under preset laser conditions. Based on the preset interdigitated alternating n-regions and p-regions, the first mask layer, first doped layer, and silicon dioxide layer of the p-region are removed, thereby exposing the surface of the P-type silicon substrate in the p-region. The exposed P-type silicon substrate has a width of 34 μm and a depth of 1.3 μm. The preset laser conditions can be: laser marking speed of 3200 mm / s-3700 mm / s, laser power of 16 W-20 W, and laser frequency of 800 Hz-1200 Hz.

[0080] S5. Take the laser-grooved P-type silicon substrate and perform chain-type acid washing on the first mask layer on the n-region surface to remove it. The chain-type acid washing conditions can be an acidic solution formed by mixing 1.0%-1.5% hydrochloric acid and 0.8%-1.2% hydrofluoric acid. After removing the first mask layer in the n-region, perform trench texturing on the front side of the P-type silicon substrate to form a textured surface. The trench texturing conditions are: 25L of concentrated sodium hydroxide solution, 8L of texturing additive, and 460L of water; the texturing temperature is 72℃; and the texturing time is 480s.

[0081] S6. After texturing the P-type silicon substrate using a slotted method, borosilicate paste is printed on the p-region of the laser-exposed P-type silicon substrate surface in the laser-opened area. After printing, the P-type silicon substrate with the printed borosilicate paste is dried. After drying, the borosilicate paste is propelled at high temperature using a tubular diffusion device, causing boron in the borosilicate paste to diffuse into the P-type silicon substrate, thereby forming a highly concentrated second doped layer within the P-type silicon substrate. The diffusion temperature of the tubular diffusion device is 980℃~1150℃, and the concentration of the second doped layer formed at this temperature is 9.2×10¹⁸ atoms / cm³, with a sheet resistance of 220Ω / sq.

[0082] S6. Take the boron-expanded P-type silicon substrate, use a low-power laser to remove a portion of the excess borosilicate paste in the p-region, and use a 1.0%-1.5% hydrochloric acid solution to completely remove the remaining borosilicate paste in the p-region.

[0083] S7. Perform ALD process on the front side of the acid-washed P-type silicon substrate to deposit an aluminum oxide film layer with a thickness of 6nm on the textured surface to improve the UV resistance of the IBC cell.

[0084] S8. Take the P-type silicon substrate after ALD process, and deposit a silicon nitride layer on the side of the first doped layer and the second doped layer away from the P-type silicon substrate to improve the passivation effect of the IBC cell.

[0085] S9. A front-side deposition is performed on the alumina film layer of the P-type silicon substrate to sequentially deposit a bottom three-layer silicon nitride layer-silicon oxynitride layer-silicon dioxide layer on the surface of the alumina film layer away from the P-type silicon substrate. The overall refractive index of the bottom three-layer silicon nitride layer-silicon oxynitride layer-silicon dioxide layer is 2.2 to improve the UV resistance of the IBC cell.

[0086] S10. Screen printing is performed on the n-region and p-region of the P-type silicon substrate. The printing includes printing the main gate lines and the fine gate lines. In this embodiment, the printing material is silver paste to improve the passivation effect.

[0087] S11. The screen-printed P-type silicon substrate is sintered at high temperature to form the first and second electrodes. The maximum sintering temperature can be 748℃. After high-temperature sintering, light injection is performed at a light injection temperature of 528℃ and a light injection intensity of 19000W / m2 to form an IBC cell. After light injection, the IBC cell is laser-induced by applying a 16V directional voltage to the first and second electrodes at a laser power of 16W to test the conversion efficiency of the IBC cell. The final test results show that the conversion efficiency of the IBC cell is improved by about 0.62% compared with the existing IBC cell.

[0088] S12. The IBC battery was subjected to irradiance at 180W / m2 to test its UV resistance. The test showed that the cumulative irradiance UV30 attenuation value was 0.65%, which is 4.4% lower than the existing UV30 attenuation value. This greatly reduced the UV attenuation and improved the light utilization rate of the IBC battery.

[0089] Based on the same inventive concept, this invention also provides an IBC battery, which is prepared by the above-described method for preparing an IBC battery and has the corresponding functional modules and beneficial effects of the method.

[0090] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0091] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing an IBC battery, characterized in that, include: Provides P-type silicon substrates; The P-type silicon substrate includes a front side and a back side that are opposite to each other, and the back side includes a first region and a second region arranged in an interdigitated pattern. A first tunneling oxide layer and a first doped layer are prepared in the first region; A second doped paste is printed in the second region and advanced at high temperature to form a second doped layer within a portion of the P-type silicon substrate; Remove the second doped slurry from the second region; The front surface is napped to form a napped structure. A protective layer is prepared on the surface of the velvety structure using a pre-defined deposition process; A first passivation layer is formed on the surface of the first doped layer and the second doped layer facing away from the P-type silicon substrate, and a second passivation layer is formed on the surface of the protective layer facing away from the P-type silicon substrate. The first region and the second region are screen printed and sintered at high temperature to form a first electrode in the first region that contacts the first doped layer, and a second electrode in the second region that contacts the second doped layer, thereby obtaining the IBC battery.

2. The preparation method according to claim 1, characterized in that, A protective layer is prepared on the surface of the textured structure using a pre-defined deposition process, including: By introducing water at a flow rate of 18 sccm-23 sccm and trimethylaluminum gas at a flow rate of 12 sccm-17 sccm into the reaction chamber of the preset deposition process, and under preset high temperature conditions of 270℃-320℃, the reaction time is 30s-35s, thus forming the protective layer on the surface of the textured structure.

3. The preparation method according to claim 2, characterized in that, The thickness of the protective layer ranges from 5nm to 6nm.

4. The preparation method according to claim 1, characterized in that, The first passivation layer includes a first silicon nitride layer; A first passivation layer is formed on the surface of the first doped layer and the second doped layer on the side facing away from the P-type silicon substrate, including: The first silicon nitride layer is formed on the side of the first doped layer and the second doped layer opposite to the P-type silicon substrate using a second deposition process.

5. The preparation method according to claim 4, characterized in that, The thickness of the first silicon nitride layer ranges from 80 nm to 85 nm; the refractive index of the first silicon nitride layer ranges from 2.09 to 2.

12.

6. The preparation method according to claim 1, characterized in that, The second passivation layer includes a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a silicon oxynitride layer, and a silicon dioxide layer; A second passivation layer is prepared on the surface of the protective layer facing away from the P-type silicon substrate, comprising: Using a third deposition process, the second silicon nitride layer, the third silicon nitride layer, the fourth silicon nitride layer, the silicon oxynitride layer, and the silicon dioxide layer are sequentially formed on the side of the protective layer opposite to the P-type silicon substrate.

7. The preparation method according to claim 6, characterized in that, The thickness of the second silicon nitride layer ranges from 8 nm to 10 nm; the thickness of the third silicon nitride layer ranges from 10 nm to 15 nm; the thickness of the fourth silicon nitride layer ranges from 12 nm to 15 nm; the thickness of the silicon oxynitride layer ranges from 8 nm to 10 nm; and the thickness of the silicon dioxide layer ranges from 20 nm to 25 nm.

8. The preparation method according to claim 6, characterized in that, The refractive index of the second silicon nitride layer is in the range of 2.25-2.3; the refractive index of the third silicon nitride layer is in the range of 2.2-2.25; the refractive index of the fourth silicon nitride layer is in the range of 2.18-2.22; the refractive index of the silicon oxynitride layer is in the range of 2.18-2.2; and the refractive index of the silicon dioxide layer is in the range of 2.12-2.

15.

9. The preparation method according to claim 6, characterized in that, The refractive index of the second passivation layer ranges from 2.17 to 2.2, and the thickness of the second passivation layer ranges from 69 nm to 72 nm.

10. An IBC battery, characterized in that, The IBC battery is prepared using the method described in any one of claims 1-9.

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